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[PATCH] aic7xxx_osm build fix
[cris-mirror.git] / drivers / parport / parport_pc.c
blobe7f3bcb790006417c5567712cca71930274fa26d
1 /* Low-level parallel-port routines for 8255-based PC-style hardware.
2 *
3 * Authors: Phil Blundell <philb@gnu.org>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
6 * David Campbell <campbell@torque.net>
7 * Andrea Arcangeli
8 *
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
10 *
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
15 * Various hacks, Fred Barnes, 04/2001
16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
17 */
18
19 /* This driver should work with any hardware that is broadly compatible
20 * with that in the IBM PC. This applies to the majority of integrated
21 * I/O chipsets that are commonly available. The expected register
22 * layout is:
23 *
24 * base+0 data
25 * base+1 status
26 * base+2 control
27 *
28 * In addition, there are some optional registers:
29 *
30 * base+3 EPP address
31 * base+4 EPP data
32 * base+0x400 ECP config A
33 * base+0x401 ECP config B
34 * base+0x402 ECP control
35 *
36 * All registers are 8 bits wide and read/write. If your hardware differs
37 * only in register addresses (eg because your registers are on 32-bit
38 * word boundaries) then you can alter the constants in parport_pc.h to
39 * accommodate this.
40 *
41 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
42 * but rather will start at port->base_hi.
43 */
44
45 #include <linux/config.h>
46 #include <linux/module.h>
47 #include <linux/init.h>
48 #include <linux/sched.h>
49 #include <linux/delay.h>
50 #include <linux/errno.h>
51 #include <linux/interrupt.h>
52 #include <linux/ioport.h>
53 #include <linux/kernel.h>
54 #include <linux/slab.h>
55 #include <linux/pci.h>
56 #include <linux/pnp.h>
57 #include <linux/sysctl.h>
58
59 #include <asm/io.h>
60 #include <asm/dma.h>
61 #include <asm/uaccess.h>
62
63 #include <linux/parport.h>
64 #include <linux/parport_pc.h>
65 #include <linux/via.h>
66 #include <asm/parport.h>
67
68 #define PARPORT_PC_MAX_PORTS PARPORT_MAX
69
70 #ifdef CONFIG_ISA_DMA_API
71 #define HAS_DMA
72 #endif
73
74 /* ECR modes */
75 #define ECR_SPP 00
76 #define ECR_PS2 01
77 #define ECR_PPF 02
78 #define ECR_ECP 03
79 #define ECR_EPP 04
80 #define ECR_VND 05
81 #define ECR_TST 06
82 #define ECR_CNF 07
83 #define ECR_MODE_MASK 0xe0
84 #define ECR_WRITE(p,v) frob_econtrol((p),0xff,(v))
85
86 #undef DEBUG
87
88 #ifdef DEBUG
89 #define DPRINTK printk
90 #else
91 #define DPRINTK(stuff...)
92 #endif
93
94
95 #define NR_SUPERIOS 3
96 static struct superio_struct { /* For Super-IO chips autodetection */
97 int io;
98 int irq;
99 int dma;
100 } superios[NR_SUPERIOS] __devinitdata = { {0,},};
101
102 static int user_specified;
103 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
104 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
105 static int verbose_probing;
106 #endif
107 static int pci_registered_parport;
108 static int pnp_registered_parport;
109
110 /* frob_control, but for ECR */
111 static void frob_econtrol (struct parport *pb, unsigned char m,
112 unsigned char v)
113 {
114 unsigned char ectr = 0;
115
116 if (m != 0xff)
117 ectr = inb (ECONTROL (pb));
118
119 DPRINTK (KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
120 m, v, ectr, (ectr & ~m) ^ v);
121
122 outb ((ectr & ~m) ^ v, ECONTROL (pb));
123 }
124
125 static __inline__ void frob_set_mode (struct parport *p, int mode)
126 {
127 frob_econtrol (p, ECR_MODE_MASK, mode << 5);
128 }
129
130 #ifdef CONFIG_PARPORT_PC_FIFO
131 /* Safely change the mode bits in the ECR
132 Returns:
133 0 : Success
134 -EBUSY: Could not drain FIFO in some finite amount of time,
135 mode not changed!
136 */
137 static int change_mode(struct parport *p, int m)
138 {
139 const struct parport_pc_private *priv = p->physport->private_data;
140 unsigned char oecr;
141 int mode;
142
143 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n",m);
144
145 if (!priv->ecr) {
146 printk (KERN_DEBUG "change_mode: but there's no ECR!\n");
147 return 0;
148 }
149
150 /* Bits <7:5> contain the mode. */
151 oecr = inb (ECONTROL (p));
152 mode = (oecr >> 5) & 0x7;
153 if (mode == m) return 0;
154
155 if (mode >= 2 && !(priv->ctr & 0x20)) {
156 /* This mode resets the FIFO, so we may
157 * have to wait for it to drain first. */
158 unsigned long expire = jiffies + p->physport->cad->timeout;
159 int counter;
160 switch (mode) {
161 case ECR_PPF: /* Parallel Port FIFO mode */
162 case ECR_ECP: /* ECP Parallel Port mode */
163 /* Busy wait for 200us */
164 for (counter = 0; counter < 40; counter++) {
165 if (inb (ECONTROL (p)) & 0x01)
166 break;
167 if (signal_pending (current)) break;
168 udelay (5);
169 }
170
171 /* Poll slowly. */
172 while (!(inb (ECONTROL (p)) & 0x01)) {
173 if (time_after_eq (jiffies, expire))
174 /* The FIFO is stuck. */
175 return -EBUSY;
176 __set_current_state (TASK_INTERRUPTIBLE);
177 schedule_timeout ((HZ + 99) / 100);
178 if (signal_pending (current))
179 break;
180 }
181 }
182 }
183
184 if (mode >= 2 && m >= 2) {
185 /* We have to go through mode 001 */
186 oecr &= ~(7 << 5);
187 oecr |= ECR_PS2 << 5;
188 ECR_WRITE (p, oecr);
189 }
190
191 /* Set the mode. */
192 oecr &= ~(7 << 5);
193 oecr |= m << 5;
194 ECR_WRITE (p, oecr);
195 return 0;
196 }
197
198 #ifdef CONFIG_PARPORT_1284
199 /* Find FIFO lossage; FIFO is reset */
200 #if 0
201 static int get_fifo_residue (struct parport *p)
202 {
203 int residue;
204 int cnfga;
205 const struct parport_pc_private *priv = p->physport->private_data;
206
207 /* Adjust for the contents of the FIFO. */
208 for (residue = priv->fifo_depth; ; residue--) {
209 if (inb (ECONTROL (p)) & 0x2)
210 /* Full up. */
211 break;
212
213 outb (0, FIFO (p));
214 }
215
216 printk (KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name,
217 residue);
218
219 /* Reset the FIFO. */
220 frob_set_mode (p, ECR_PS2);
221
222 /* Now change to config mode and clean up. FIXME */
223 frob_set_mode (p, ECR_CNF);
224 cnfga = inb (CONFIGA (p));
225 printk (KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga);
226
227 if (!(cnfga & (1<<2))) {
228 printk (KERN_DEBUG "%s: Accounting for extra byte\n", p->name);
229 residue++;
230 }
231
232 /* Don't care about partial PWords until support is added for
233 * PWord != 1 byte. */
234
235 /* Back to PS2 mode. */
236 frob_set_mode (p, ECR_PS2);
237
238 DPRINTK (KERN_DEBUG "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n", inb (ECONTROL (p)));
239 return residue;
240 }
241 #endif /* 0 */
242 #endif /* IEEE 1284 support */
243 #endif /* FIFO support */
244
245 /*
246 * Clear TIMEOUT BIT in EPP MODE
247 *
248 * This is also used in SPP detection.
249 */
250 static int clear_epp_timeout(struct parport *pb)
251 {
252 unsigned char r;
253
254 if (!(parport_pc_read_status(pb) & 0x01))
255 return 1;
256
257 /* To clear timeout some chips require double read */
258 parport_pc_read_status(pb);
259 r = parport_pc_read_status(pb);
260 outb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */
261 outb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */
262 r = parport_pc_read_status(pb);
263
264 return !(r & 0x01);
265 }
266
267 /*
268 * Access functions.
269 *
270 * Most of these aren't static because they may be used by the
271 * parport_xxx_yyy macros. extern __inline__ versions of several
272 * of these are in parport_pc.h.
273 */
274
275 static irqreturn_t parport_pc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
276 {
277 parport_generic_irq(irq, (struct parport *) dev_id, regs);
278 /* FIXME! Was it really ours? */
279 return IRQ_HANDLED;
280 }
281
282 static void parport_pc_init_state(struct pardevice *dev, struct parport_state *s)
283 {
284 s->u.pc.ctr = 0xc;
285 if (dev->irq_func &&
286 dev->port->irq != PARPORT_IRQ_NONE)
287 /* Set ackIntEn */
288 s->u.pc.ctr |= 0x10;
289
290 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
291 * D.Gruszka VScom */
292 }
293
294 static void parport_pc_save_state(struct parport *p, struct parport_state *s)
295 {
296 const struct parport_pc_private *priv = p->physport->private_data;
297 s->u.pc.ctr = priv->ctr;
298 if (priv->ecr)
299 s->u.pc.ecr = inb (ECONTROL (p));
300 }
301
302 static void parport_pc_restore_state(struct parport *p, struct parport_state *s)
303 {
304 struct parport_pc_private *priv = p->physport->private_data;
305 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
306 outb (c, CONTROL (p));
307 priv->ctr = c;
308 if (priv->ecr)
309 ECR_WRITE (p, s->u.pc.ecr);
310 }
311
312 #ifdef CONFIG_PARPORT_1284
313 static size_t parport_pc_epp_read_data (struct parport *port, void *buf,
314 size_t length, int flags)
315 {
316 size_t got = 0;
317
318 if (flags & PARPORT_W91284PIC) {
319 unsigned char status;
320 size_t left = length;
321
322 /* use knowledge about data lines..:
323 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
324 * pError is 1 if there are 16 bytes in the Warp's FIFO
325 */
326 status = inb (STATUS (port));
327
328 while (!(status & 0x08) && (got < length)) {
329 if ((left >= 16) && (status & 0x20) && !(status & 0x08)) {
330 /* can grab 16 bytes from warp fifo */
331 if (!((long)buf & 0x03)) {
332 insl (EPPDATA (port), buf, 4);
333 } else {
334 insb (EPPDATA (port), buf, 16);
335 }
336 buf += 16;
337 got += 16;
338 left -= 16;
339 } else {
340 /* grab single byte from the warp fifo */
341 *((char *)buf) = inb (EPPDATA (port));
342 buf++;
343 got++;
344 left--;
345 }
346 status = inb (STATUS (port));
347 if (status & 0x01) {
348 /* EPP timeout should never occur... */
349 printk (KERN_DEBUG "%s: EPP timeout occurred while talking to "
350 "w91284pic (should not have done)\n", port->name);
351 clear_epp_timeout (port);
352 }
353 }
354 return got;
355 }
356 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
357 if (!(((long)buf | length) & 0x03)) {
358 insl (EPPDATA (port), buf, (length >> 2));
359 } else {
360 insb (EPPDATA (port), buf, length);
361 }
362 if (inb (STATUS (port)) & 0x01) {
363 clear_epp_timeout (port);
364 return -EIO;
365 }
366 return length;
367 }
368 for (; got < length; got++) {
369 *((char*)buf) = inb (EPPDATA(port));
370 buf++;
371 if (inb (STATUS (port)) & 0x01) {
372 /* EPP timeout */
373 clear_epp_timeout (port);
374 break;
375 }
376 }
377
378 return got;
379 }
380
381 static size_t parport_pc_epp_write_data (struct parport *port, const void *buf,
382 size_t length, int flags)
383 {
384 size_t written = 0;
385
386 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
387 if (!(((long)buf | length) & 0x03)) {
388 outsl (EPPDATA (port), buf, (length >> 2));
389 } else {
390 outsb (EPPDATA (port), buf, length);
391 }
392 if (inb (STATUS (port)) & 0x01) {
393 clear_epp_timeout (port);
394 return -EIO;
395 }
396 return length;
397 }
398 for (; written < length; written++) {
399 outb (*((char*)buf), EPPDATA(port));
400 buf++;
401 if (inb (STATUS(port)) & 0x01) {
402 clear_epp_timeout (port);
403 break;
404 }
405 }
406
407 return written;
408 }
409
410 static size_t parport_pc_epp_read_addr (struct parport *port, void *buf,
411 size_t length, int flags)
412 {
413 size_t got = 0;
414
415 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
416 insb (EPPADDR (port), buf, length);
417 if (inb (STATUS (port)) & 0x01) {
418 clear_epp_timeout (port);
419 return -EIO;
420 }
421 return length;
422 }
423 for (; got < length; got++) {
424 *((char*)buf) = inb (EPPADDR (port));
425 buf++;
426 if (inb (STATUS (port)) & 0x01) {
427 clear_epp_timeout (port);
428 break;
429 }
430 }
431
432 return got;
433 }
434
435 static size_t parport_pc_epp_write_addr (struct parport *port,
436 const void *buf, size_t length,
437 int flags)
438 {
439 size_t written = 0;
440
441 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
442 outsb (EPPADDR (port), buf, length);
443 if (inb (STATUS (port)) & 0x01) {
444 clear_epp_timeout (port);
445 return -EIO;
446 }
447 return length;
448 }
449 for (; written < length; written++) {
450 outb (*((char*)buf), EPPADDR (port));
451 buf++;
452 if (inb (STATUS (port)) & 0x01) {
453 clear_epp_timeout (port);
454 break;
455 }
456 }
457
458 return written;
459 }
460
461 static size_t parport_pc_ecpepp_read_data (struct parport *port, void *buf,
462 size_t length, int flags)
463 {
464 size_t got;
465
466 frob_set_mode (port, ECR_EPP);
467 parport_pc_data_reverse (port);
468 parport_pc_write_control (port, 0x4);
469 got = parport_pc_epp_read_data (port, buf, length, flags);
470 frob_set_mode (port, ECR_PS2);
471
472 return got;
473 }
474
475 static size_t parport_pc_ecpepp_write_data (struct parport *port,
476 const void *buf, size_t length,
477 int flags)
478 {
479 size_t written;
480
481 frob_set_mode (port, ECR_EPP);
482 parport_pc_write_control (port, 0x4);
483 parport_pc_data_forward (port);
484 written = parport_pc_epp_write_data (port, buf, length, flags);
485 frob_set_mode (port, ECR_PS2);
486
487 return written;
488 }
489
490 static size_t parport_pc_ecpepp_read_addr (struct parport *port, void *buf,
491 size_t length, int flags)
492 {
493 size_t got;
494
495 frob_set_mode (port, ECR_EPP);
496 parport_pc_data_reverse (port);
497 parport_pc_write_control (port, 0x4);
498 got = parport_pc_epp_read_addr (port, buf, length, flags);
499 frob_set_mode (port, ECR_PS2);
500
501 return got;
502 }
503
504 static size_t parport_pc_ecpepp_write_addr (struct parport *port,
505 const void *buf, size_t length,
506 int flags)
507 {
508 size_t written;
509
510 frob_set_mode (port, ECR_EPP);
511 parport_pc_write_control (port, 0x4);
512 parport_pc_data_forward (port);
513 written = parport_pc_epp_write_addr (port, buf, length, flags);
514 frob_set_mode (port, ECR_PS2);
515
516 return written;
517 }
518 #endif /* IEEE 1284 support */
519
520 #ifdef CONFIG_PARPORT_PC_FIFO
521 static size_t parport_pc_fifo_write_block_pio (struct parport *port,
522 const void *buf, size_t length)
523 {
524 int ret = 0;
525 const unsigned char *bufp = buf;
526 size_t left = length;
527 unsigned long expire = jiffies + port->physport->cad->timeout;
528 const int fifo = FIFO (port);
529 int poll_for = 8; /* 80 usecs */
530 const struct parport_pc_private *priv = port->physport->private_data;
531 const int fifo_depth = priv->fifo_depth;
532
533 port = port->physport;
534
535 /* We don't want to be interrupted every character. */
536 parport_pc_disable_irq (port);
537 /* set nErrIntrEn and serviceIntr */
538 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
539
540 /* Forward mode. */
541 parport_pc_data_forward (port); /* Must be in PS2 mode */
542
543 while (left) {
544 unsigned char byte;
545 unsigned char ecrval = inb (ECONTROL (port));
546 int i = 0;
547
548 if (need_resched() && time_before (jiffies, expire))
549 /* Can't yield the port. */
550 schedule ();
551
552 /* Anyone else waiting for the port? */
553 if (port->waithead) {
554 printk (KERN_DEBUG "Somebody wants the port\n");
555 break;
556 }
557
558 if (ecrval & 0x02) {
559 /* FIFO is full. Wait for interrupt. */
560
561 /* Clear serviceIntr */
562 ECR_WRITE (port, ecrval & ~(1<<2));
563 false_alarm:
564 ret = parport_wait_event (port, HZ);
565 if (ret < 0) break;
566 ret = 0;
567 if (!time_before (jiffies, expire)) {
568 /* Timed out. */
569 printk (KERN_DEBUG "FIFO write timed out\n");
570 break;
571 }
572 ecrval = inb (ECONTROL (port));
573 if (!(ecrval & (1<<2))) {
574 if (need_resched() &&
575 time_before (jiffies, expire))
576 schedule ();
577
578 goto false_alarm;
579 }
580
581 continue;
582 }
583
584 /* Can't fail now. */
585 expire = jiffies + port->cad->timeout;
586
587 poll:
588 if (signal_pending (current))
589 break;
590
591 if (ecrval & 0x01) {
592 /* FIFO is empty. Blast it full. */
593 const int n = left < fifo_depth ? left : fifo_depth;
594 outsb (fifo, bufp, n);
595 bufp += n;
596 left -= n;
597
598 /* Adjust the poll time. */
599 if (i < (poll_for - 2)) poll_for--;
600 continue;
601 } else if (i++ < poll_for) {
602 udelay (10);
603 ecrval = inb (ECONTROL (port));
604 goto poll;
605 }
606
607 /* Half-full (call me an optimist) */
608 byte = *bufp++;
609 outb (byte, fifo);
610 left--;
611 }
612
613 dump_parport_state ("leave fifo_write_block_pio", port);
614 return length - left;
615 }
616
617 #ifdef HAS_DMA
618 static size_t parport_pc_fifo_write_block_dma (struct parport *port,
619 const void *buf, size_t length)
620 {
621 int ret = 0;
622 unsigned long dmaflag;
623 size_t left = length;
624 const struct parport_pc_private *priv = port->physport->private_data;
625 dma_addr_t dma_addr, dma_handle;
626 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
627 unsigned long start = (unsigned long) buf;
628 unsigned long end = (unsigned long) buf + length - 1;
629
630 dump_parport_state ("enter fifo_write_block_dma", port);
631 if (end < MAX_DMA_ADDRESS) {
632 /* If it would cross a 64k boundary, cap it at the end. */
633 if ((start ^ end) & ~0xffffUL)
634 maxlen = 0x10000 - (start & 0xffff);
635
636 dma_addr = dma_handle = pci_map_single(priv->dev, (void *)buf, length,
637 PCI_DMA_TODEVICE);
638 } else {
639 /* above 16 MB we use a bounce buffer as ISA-DMA is not possible */
640 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
641 dma_addr = priv->dma_handle;
642 dma_handle = 0;
643 }
644
645 port = port->physport;
646
647 /* We don't want to be interrupted every character. */
648 parport_pc_disable_irq (port);
649 /* set nErrIntrEn and serviceIntr */
650 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
651
652 /* Forward mode. */
653 parport_pc_data_forward (port); /* Must be in PS2 mode */
654
655 while (left) {
656 unsigned long expire = jiffies + port->physport->cad->timeout;
657
658 size_t count = left;
659
660 if (count > maxlen)
661 count = maxlen;
662
663 if (!dma_handle) /* bounce buffer ! */
664 memcpy(priv->dma_buf, buf, count);
665
666 dmaflag = claim_dma_lock();
667 disable_dma(port->dma);
668 clear_dma_ff(port->dma);
669 set_dma_mode(port->dma, DMA_MODE_WRITE);
670 set_dma_addr(port->dma, dma_addr);
671 set_dma_count(port->dma, count);
672
673 /* Set DMA mode */
674 frob_econtrol (port, 1<<3, 1<<3);
675
676 /* Clear serviceIntr */
677 frob_econtrol (port, 1<<2, 0);
678
679 enable_dma(port->dma);
680 release_dma_lock(dmaflag);
681
682 /* assume DMA will be successful */
683 left -= count;
684 buf += count;
685 if (dma_handle) dma_addr += count;
686
687 /* Wait for interrupt. */
688 false_alarm:
689 ret = parport_wait_event (port, HZ);
690 if (ret < 0) break;
691 ret = 0;
692 if (!time_before (jiffies, expire)) {
693 /* Timed out. */
694 printk (KERN_DEBUG "DMA write timed out\n");
695 break;
696 }
697 /* Is serviceIntr set? */
698 if (!(inb (ECONTROL (port)) & (1<<2))) {
699 cond_resched();
700
701 goto false_alarm;
702 }
703
704 dmaflag = claim_dma_lock();
705 disable_dma(port->dma);
706 clear_dma_ff(port->dma);
707 count = get_dma_residue(port->dma);
708 release_dma_lock(dmaflag);
709
710 cond_resched(); /* Can't yield the port. */
711
712 /* Anyone else waiting for the port? */
713 if (port->waithead) {
714 printk (KERN_DEBUG "Somebody wants the port\n");
715 break;
716 }
717
718 /* update for possible DMA residue ! */
719 buf -= count;
720 left += count;
721 if (dma_handle) dma_addr -= count;
722 }
723
724 /* Maybe got here through break, so adjust for DMA residue! */
725 dmaflag = claim_dma_lock();
726 disable_dma(port->dma);
727 clear_dma_ff(port->dma);
728 left += get_dma_residue(port->dma);
729 release_dma_lock(dmaflag);
730
731 /* Turn off DMA mode */
732 frob_econtrol (port, 1<<3, 0);
733
734 if (dma_handle)
735 pci_unmap_single(priv->dev, dma_handle, length, PCI_DMA_TODEVICE);
736
737 dump_parport_state ("leave fifo_write_block_dma", port);
738 return length - left;
739 }
740 #endif
741
742 static inline size_t parport_pc_fifo_write_block(struct parport *port,
743 const void *buf, size_t length)
744 {
745 #ifdef HAS_DMA
746 if (port->dma != PARPORT_DMA_NONE)
747 return parport_pc_fifo_write_block_dma (port, buf, length);
748 #endif
749 return parport_pc_fifo_write_block_pio (port, buf, length);
750 }
751
752 /* Parallel Port FIFO mode (ECP chipsets) */
753 static size_t parport_pc_compat_write_block_pio (struct parport *port,
754 const void *buf, size_t length,
755 int flags)
756 {
757 size_t written;
758 int r;
759 unsigned long expire;
760 const struct parport_pc_private *priv = port->physport->private_data;
761
762 /* Special case: a timeout of zero means we cannot call schedule().
763 * Also if O_NONBLOCK is set then use the default implementation. */
764 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
765 return parport_ieee1284_write_compat (port, buf,
766 length, flags);
767
768 /* Set up parallel port FIFO mode.*/
769 parport_pc_data_forward (port); /* Must be in PS2 mode */
770 parport_pc_frob_control (port, PARPORT_CONTROL_STROBE, 0);
771 r = change_mode (port, ECR_PPF); /* Parallel port FIFO */
772 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", port->name);
773
774 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
775
776 /* Write the data to the FIFO. */
777 written = parport_pc_fifo_write_block(port, buf, length);
778
779 /* Finish up. */
780 /* For some hardware we don't want to touch the mode until
781 * the FIFO is empty, so allow 4 seconds for each position
782 * in the fifo.
783 */
784 expire = jiffies + (priv->fifo_depth * HZ * 4);
785 do {
786 /* Wait for the FIFO to empty */
787 r = change_mode (port, ECR_PS2);
788 if (r != -EBUSY) {
789 break;
790 }
791 } while (time_before (jiffies, expire));
792 if (r == -EBUSY) {
793
794 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
795
796 /* Prevent further data transfer. */
797 frob_set_mode (port, ECR_TST);
798
799 /* Adjust for the contents of the FIFO. */
800 for (written -= priv->fifo_depth; ; written++) {
801 if (inb (ECONTROL (port)) & 0x2) {
802 /* Full up. */
803 break;
804 }
805 outb (0, FIFO (port));
806 }
807
808 /* Reset the FIFO and return to PS2 mode. */
809 frob_set_mode (port, ECR_PS2);
810 }
811
812 r = parport_wait_peripheral (port,
813 PARPORT_STATUS_BUSY,
814 PARPORT_STATUS_BUSY);
815 if (r)
816 printk (KERN_DEBUG
817 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
818 port->name, r);
819
820 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
821
822 return written;
823 }
824
825 /* ECP */
826 #ifdef CONFIG_PARPORT_1284
827 static size_t parport_pc_ecp_write_block_pio (struct parport *port,
828 const void *buf, size_t length,
829 int flags)
830 {
831 size_t written;
832 int r;
833 unsigned long expire;
834 const struct parport_pc_private *priv = port->physport->private_data;
835
836 /* Special case: a timeout of zero means we cannot call schedule().
837 * Also if O_NONBLOCK is set then use the default implementation. */
838 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
839 return parport_ieee1284_ecp_write_data (port, buf,
840 length, flags);
841
842 /* Switch to forward mode if necessary. */
843 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
844 /* Event 47: Set nInit high. */
845 parport_frob_control (port,
846 PARPORT_CONTROL_INIT
847 | PARPORT_CONTROL_AUTOFD,
848 PARPORT_CONTROL_INIT
849 | PARPORT_CONTROL_AUTOFD);
850
851 /* Event 49: PError goes high. */
852 r = parport_wait_peripheral (port,
853 PARPORT_STATUS_PAPEROUT,
854 PARPORT_STATUS_PAPEROUT);
855 if (r) {
856 printk (KERN_DEBUG "%s: PError timeout (%d) "
857 "in ecp_write_block_pio\n", port->name, r);
858 }
859 }
860
861 /* Set up ECP parallel port mode.*/
862 parport_pc_data_forward (port); /* Must be in PS2 mode */
863 parport_pc_frob_control (port,
864 PARPORT_CONTROL_STROBE |
865 PARPORT_CONTROL_AUTOFD,
866 0);
867 r = change_mode (port, ECR_ECP); /* ECP FIFO */
868 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
869 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
870
871 /* Write the data to the FIFO. */
872 written = parport_pc_fifo_write_block(port, buf, length);
873
874 /* Finish up. */
875 /* For some hardware we don't want to touch the mode until
876 * the FIFO is empty, so allow 4 seconds for each position
877 * in the fifo.
878 */
879 expire = jiffies + (priv->fifo_depth * (HZ * 4));
880 do {
881 /* Wait for the FIFO to empty */
882 r = change_mode (port, ECR_PS2);
883 if (r != -EBUSY) {
884 break;
885 }
886 } while (time_before (jiffies, expire));
887 if (r == -EBUSY) {
888
889 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
890
891 /* Prevent further data transfer. */
892 frob_set_mode (port, ECR_TST);
893
894 /* Adjust for the contents of the FIFO. */
895 for (written -= priv->fifo_depth; ; written++) {
896 if (inb (ECONTROL (port)) & 0x2) {
897 /* Full up. */
898 break;
899 }
900 outb (0, FIFO (port));
901 }
902
903 /* Reset the FIFO and return to PS2 mode. */
904 frob_set_mode (port, ECR_PS2);
905
906 /* Host transfer recovery. */
907 parport_pc_data_reverse (port); /* Must be in PS2 mode */
908 udelay (5);
909 parport_frob_control (port, PARPORT_CONTROL_INIT, 0);
910 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
911 if (r)
912 printk (KERN_DEBUG "%s: PE,1 timeout (%d) "
913 "in ecp_write_block_pio\n", port->name, r);
914
915 parport_frob_control (port,
916 PARPORT_CONTROL_INIT,
917 PARPORT_CONTROL_INIT);
918 r = parport_wait_peripheral (port,
919 PARPORT_STATUS_PAPEROUT,
920 PARPORT_STATUS_PAPEROUT);
921 if (r)
922 printk (KERN_DEBUG "%s: PE,2 timeout (%d) "
923 "in ecp_write_block_pio\n", port->name, r);
924 }
925
926 r = parport_wait_peripheral (port,
927 PARPORT_STATUS_BUSY,
928 PARPORT_STATUS_BUSY);
929 if(r)
930 printk (KERN_DEBUG
931 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
932 port->name, r);
933
934 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
935
936 return written;
937 }
938
939 #if 0
940 static size_t parport_pc_ecp_read_block_pio (struct parport *port,
941 void *buf, size_t length,
942 int flags)
943 {
944 size_t left = length;
945 size_t fifofull;
946 int r;
947 const int fifo = FIFO(port);
948 const struct parport_pc_private *priv = port->physport->private_data;
949 const int fifo_depth = priv->fifo_depth;
950 char *bufp = buf;
951
952 port = port->physport;
953 DPRINTK (KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n");
954 dump_parport_state ("enter fcn", port);
955
956 /* Special case: a timeout of zero means we cannot call schedule().
957 * Also if O_NONBLOCK is set then use the default implementation. */
958 if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
959 return parport_ieee1284_ecp_read_data (port, buf,
960 length, flags);
961
962 if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) {
963 /* If the peripheral is allowed to send RLE compressed
964 * data, it is possible for a byte to expand to 128
965 * bytes in the FIFO. */
966 fifofull = 128;
967 } else {
968 fifofull = fifo_depth;
969 }
970
971 /* If the caller wants less than a full FIFO's worth of data,
972 * go through software emulation. Otherwise we may have to throw
973 * away data. */
974 if (length < fifofull)
975 return parport_ieee1284_ecp_read_data (port, buf,
976 length, flags);
977
978 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) {
979 /* change to reverse-idle phase (must be in forward-idle) */
980
981 /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */
982 parport_frob_control (port,
983 PARPORT_CONTROL_AUTOFD
984 | PARPORT_CONTROL_STROBE,
985 PARPORT_CONTROL_AUTOFD);
986 parport_pc_data_reverse (port); /* Must be in PS2 mode */
987 udelay (5);
988 /* Event 39: Set nInit low to initiate bus reversal */
989 parport_frob_control (port,
990 PARPORT_CONTROL_INIT,
991 0);
992 /* Event 40: Wait for nAckReverse (PError) to go low */
993 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
994 if (r) {
995 printk (KERN_DEBUG "%s: PE timeout Event 40 (%d) "
996 "in ecp_read_block_pio\n", port->name, r);
997 return 0;
998 }
999 }
1000
1001 /* Set up ECP FIFO mode.*/
1002 /* parport_pc_frob_control (port,
1003 PARPORT_CONTROL_STROBE |
1004 PARPORT_CONTROL_AUTOFD,
1005 PARPORT_CONTROL_AUTOFD); */
1006 r = change_mode (port, ECR_ECP); /* ECP FIFO */
1007 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
1008
1009 port->ieee1284.phase = IEEE1284_PH_REV_DATA;
1010
1011 /* the first byte must be collected manually */
1012 dump_parport_state ("pre 43", port);
1013 /* Event 43: Wait for nAck to go low */
1014 r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0);
1015 if (r) {
1016 /* timed out while reading -- no data */
1017 printk (KERN_DEBUG "PIO read timed out (initial byte)\n");
1018 goto out_no_data;
1019 }
1020 /* read byte */
1021 *bufp++ = inb (DATA (port));
1022 left--;
1023 dump_parport_state ("43-44", port);
1024 /* Event 44: nAutoFd (HostAck) goes high to acknowledge */
1025 parport_pc_frob_control (port,
1026 PARPORT_CONTROL_AUTOFD,
1027 0);
1028 dump_parport_state ("pre 45", port);
1029 /* Event 45: Wait for nAck to go high */
1030 /* r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); */
1031 dump_parport_state ("post 45", port);
1032 r = 0;
1033 if (r) {
1034 /* timed out while waiting for peripheral to respond to ack */
1035 printk (KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n");
1036
1037 /* keep hold of the byte we've got already */
1038 goto out_no_data;
1039 }
1040 /* Event 46: nAutoFd (HostAck) goes low to accept more data */
1041 parport_pc_frob_control (port,
1042 PARPORT_CONTROL_AUTOFD,
1043 PARPORT_CONTROL_AUTOFD);
1044
1045
1046 dump_parport_state ("rev idle", port);
1047 /* Do the transfer. */
1048 while (left > fifofull) {
1049 int ret;
1050 unsigned long expire = jiffies + port->cad->timeout;
1051 unsigned char ecrval = inb (ECONTROL (port));
1052
1053 if (need_resched() && time_before (jiffies, expire))
1054 /* Can't yield the port. */
1055 schedule ();
1056
1057 /* At this point, the FIFO may already be full. In
1058 * that case ECP is already holding back the
1059 * peripheral (assuming proper design) with a delayed
1060 * handshake. Work fast to avoid a peripheral
1061 * timeout. */
1062
1063 if (ecrval & 0x01) {
1064 /* FIFO is empty. Wait for interrupt. */
1065 dump_parport_state ("FIFO empty", port);
1066
1067 /* Anyone else waiting for the port? */
1068 if (port->waithead) {
1069 printk (KERN_DEBUG "Somebody wants the port\n");
1070 break;
1071 }
1072
1073 /* Clear serviceIntr */
1074 ECR_WRITE (port, ecrval & ~(1<<2));
1075 false_alarm:
1076 dump_parport_state ("waiting", port);
1077 ret = parport_wait_event (port, HZ);
1078 DPRINTK (KERN_DEBUG "parport_wait_event returned %d\n", ret);
1079 if (ret < 0)
1080 break;
1081 ret = 0;
1082 if (!time_before (jiffies, expire)) {
1083 /* Timed out. */
1084 dump_parport_state ("timeout", port);
1085 printk (KERN_DEBUG "PIO read timed out\n");
1086 break;
1087 }
1088 ecrval = inb (ECONTROL (port));
1089 if (!(ecrval & (1<<2))) {
1090 if (need_resched() &&
1091 time_before (jiffies, expire)) {
1092 schedule ();
1093 }
1094 goto false_alarm;
1095 }
1096
1097 /* Depending on how the FIFO threshold was
1098 * set, how long interrupt service took, and
1099 * how fast the peripheral is, we might be
1100 * lucky and have a just filled FIFO. */
1101 continue;
1102 }
1103
1104 if (ecrval & 0x02) {
1105 /* FIFO is full. */
1106 dump_parport_state ("FIFO full", port);
1107 insb (fifo, bufp, fifo_depth);
1108 bufp += fifo_depth;
1109 left -= fifo_depth;
1110 continue;
1111 }
1112
1113 DPRINTK (KERN_DEBUG "*** ecp_read_block_pio: reading one byte from the FIFO\n");
1114
1115 /* FIFO not filled. We will cycle this loop for a while
1116 * and either the peripheral will fill it faster,
1117 * tripping a fast empty with insb, or we empty it. */
1118 *bufp++ = inb (fifo);
1119 left--;
1120 }
1121
1122 /* scoop up anything left in the FIFO */
1123 while (left && !(inb (ECONTROL (port) & 0x01))) {
1124 *bufp++ = inb (fifo);
1125 left--;
1126 }
1127
1128 port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
1129 dump_parport_state ("rev idle2", port);
1130
1131 out_no_data:
1132
1133 /* Go to forward idle mode to shut the peripheral up (event 47). */
1134 parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT);
1135
1136 /* event 49: PError goes high */
1137 r = parport_wait_peripheral (port,
1138 PARPORT_STATUS_PAPEROUT,
1139 PARPORT_STATUS_PAPEROUT);
1140 if (r) {
1141 printk (KERN_DEBUG
1142 "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n",
1143 port->name, r);
1144 }
1145
1146 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1147
1148 /* Finish up. */
1149 {
1150 int lost = get_fifo_residue (port);
1151 if (lost)
1152 /* Shouldn't happen with compliant peripherals. */
1153 printk (KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n",
1154 port->name, lost);
1155 }
1156
1157 dump_parport_state ("fwd idle", port);
1158 return length - left;
1159 }
1160 #endif /* 0 */
1161 #endif /* IEEE 1284 support */
1162 #endif /* Allowed to use FIFO/DMA */
1163
1164
1165 /*
1166 * ******************************************
1167 * INITIALISATION AND MODULE STUFF BELOW HERE
1168 * ******************************************
1169 */
1170
1171 /* GCC is not inlining extern inline function later overwriten to non-inline,
1172 so we use outlined_ variants here. */
1173 static struct parport_operations parport_pc_ops =
1174 {
1175 .write_data = parport_pc_write_data,
1176 .read_data = parport_pc_read_data,
1177
1178 .write_control = parport_pc_write_control,
1179 .read_control = parport_pc_read_control,
1180 .frob_control = parport_pc_frob_control,
1181
1182 .read_status = parport_pc_read_status,
1183
1184 .enable_irq = parport_pc_enable_irq,
1185 .disable_irq = parport_pc_disable_irq,
1186
1187 .data_forward = parport_pc_data_forward,
1188 .data_reverse = parport_pc_data_reverse,
1189
1190 .init_state = parport_pc_init_state,
1191 .save_state = parport_pc_save_state,
1192 .restore_state = parport_pc_restore_state,
1193
1194 .epp_write_data = parport_ieee1284_epp_write_data,
1195 .epp_read_data = parport_ieee1284_epp_read_data,
1196 .epp_write_addr = parport_ieee1284_epp_write_addr,
1197 .epp_read_addr = parport_ieee1284_epp_read_addr,
1198
1199 .ecp_write_data = parport_ieee1284_ecp_write_data,
1200 .ecp_read_data = parport_ieee1284_ecp_read_data,
1201 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
1202
1203 .compat_write_data = parport_ieee1284_write_compat,
1204 .nibble_read_data = parport_ieee1284_read_nibble,
1205 .byte_read_data = parport_ieee1284_read_byte,
1206
1207 .owner = THIS_MODULE,
1208 };
1209
1210 #ifdef CONFIG_PARPORT_PC_SUPERIO
1211 /* Super-IO chipset detection, Winbond, SMSC */
1212 static void __devinit show_parconfig_smsc37c669(int io, int key)
1213 {
1214 int cr1,cr4,cra,cr23,cr26,cr27,i=0;
1215 static const char *modes[]={ "SPP and Bidirectional (PS/2)",
1216 "EPP and SPP",
1217 "ECP",
1218 "ECP and EPP" };
1219
1220 outb(key,io);
1221 outb(key,io);
1222 outb(1,io);
1223 cr1=inb(io+1);
1224 outb(4,io);
1225 cr4=inb(io+1);
1226 outb(0x0a,io);
1227 cra=inb(io+1);
1228 outb(0x23,io);
1229 cr23=inb(io+1);
1230 outb(0x26,io);
1231 cr26=inb(io+1);
1232 outb(0x27,io);
1233 cr27=inb(io+1);
1234 outb(0xaa,io);
1235
1236 if (verbose_probing) {
1237 printk (KERN_INFO "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
1238 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
1239 cr1,cr4,cra,cr23,cr26,cr27);
1240
1241 /* The documentation calls DMA and IRQ-Lines by letters, so
1242 the board maker can/will wire them
1243 appropriately/randomly... G=reserved H=IDE-irq, */
1244 printk (KERN_INFO "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, "
1245 "fifo threshold=%d\n", cr23*4,
1246 (cr27 &0x0f) ? 'A'-1+(cr27 &0x0f): '-',
1247 (cr26 &0x0f) ? 'A'-1+(cr26 &0x0f): '-', cra & 0x0f);
1248 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
1249 (cr23*4 >=0x100) ?"yes":"no", (cr1 & 4) ? "yes" : "no");
1250 printk(KERN_INFO "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1251 (cr1 & 0x08 ) ? "Standard mode only (SPP)" : modes[cr4 & 0x03],
1252 (cr4 & 0x40) ? "1.7" : "1.9");
1253 }
1254
1255 /* Heuristics ! BIOS setup for this mainboard device limits
1256 the choices to standard settings, i.e. io-address and IRQ
1257 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1258 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1259 if(cr23*4 >=0x100) { /* if active */
1260 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1261 i++;
1262 if(i==NR_SUPERIOS)
1263 printk(KERN_INFO "Super-IO: too many chips!\n");
1264 else {
1265 int d;
1266 switch (cr23*4) {
1267 case 0x3bc:
1268 superios[i].io = 0x3bc;
1269 superios[i].irq = 7;
1270 break;
1271 case 0x378:
1272 superios[i].io = 0x378;
1273 superios[i].irq = 7;
1274 break;
1275 case 0x278:
1276 superios[i].io = 0x278;
1277 superios[i].irq = 5;
1278 }
1279 d=(cr26 &0x0f);
1280 if((d==1) || (d==3))
1281 superios[i].dma= d;
1282 else
1283 superios[i].dma= PARPORT_DMA_NONE;
1284 }
1285 }
1286 }
1287
1288
1289 static void __devinit show_parconfig_winbond(int io, int key)
1290 {
1291 int cr30,cr60,cr61,cr70,cr74,crf0,i=0;
1292 static const char *modes[] = {
1293 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1294 "EPP-1.9 and SPP",
1295 "ECP",
1296 "ECP and EPP-1.9",
1297 "Standard (SPP)",
1298 "EPP-1.7 and SPP", /* 5 */
1299 "undefined!",
1300 "ECP and EPP-1.7" };
1301 static char *irqtypes[] = { "pulsed low, high-Z", "follows nACK" };
1302
1303 /* The registers are called compatible-PnP because the
1304 register layout is modelled after ISA-PnP, the access
1305 method is just another ... */
1306 outb(key,io);
1307 outb(key,io);
1308 outb(0x07,io); /* Register 7: Select Logical Device */
1309 outb(0x01,io+1); /* LD1 is Parallel Port */
1310 outb(0x30,io);
1311 cr30=inb(io+1);
1312 outb(0x60,io);
1313 cr60=inb(io+1);
1314 outb(0x61,io);
1315 cr61=inb(io+1);
1316 outb(0x70,io);
1317 cr70=inb(io+1);
1318 outb(0x74,io);
1319 cr74=inb(io+1);
1320 outb(0xf0,io);
1321 crf0=inb(io+1);
1322 outb(0xaa,io);
1323
1324 if (verbose_probing) {
1325 printk(KERN_INFO "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x "
1326 "70=%02x 74=%02x, f0=%02x\n", cr30,cr60,cr61,cr70,cr74,crf0);
1327 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1328 (cr30 & 0x01) ? "yes":"no", cr60,cr61,cr70&0x0f );
1329 if ((cr74 & 0x07) > 3)
1330 printk("dma=none\n");
1331 else
1332 printk("dma=%d\n",cr74 & 0x07);
1333 printk(KERN_INFO "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1334 irqtypes[crf0>>7], (crf0>>3)&0x0f);
1335 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", modes[crf0 & 0x07]);
1336 }
1337
1338 if(cr30 & 0x01) { /* the settings can be interrogated later ... */
1339 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1340 i++;
1341 if(i==NR_SUPERIOS)
1342 printk(KERN_INFO "Super-IO: too many chips!\n");
1343 else {
1344 superios[i].io = (cr60<<8)|cr61;
1345 superios[i].irq = cr70&0x0f;
1346 superios[i].dma = (((cr74 & 0x07) > 3) ?
1347 PARPORT_DMA_NONE : (cr74 & 0x07));
1348 }
1349 }
1350 }
1351
1352 static void __devinit decode_winbond(int efer, int key, int devid, int devrev, int oldid)
1353 {
1354 const char *type = "unknown";
1355 int id,progif=2;
1356
1357 if (devid == devrev)
1358 /* simple heuristics, we happened to read some
1359 non-winbond register */
1360 return;
1361
1362 id=(devid<<8) | devrev;
1363
1364 /* Values are from public data sheets pdf files, I can just
1365 confirm 83977TF is correct :-) */
1366 if (id == 0x9771) type="83977F/AF";
1367 else if (id == 0x9773) type="83977TF / SMSC 97w33x/97w34x";
1368 else if (id == 0x9774) type="83977ATF";
1369 else if ((id & ~0x0f) == 0x5270) type="83977CTF / SMSC 97w36x";
1370 else if ((id & ~0x0f) == 0x52f0) type="83977EF / SMSC 97w35x";
1371 else if ((id & ~0x0f) == 0x5210) type="83627";
1372 else if ((id & ~0x0f) == 0x6010) type="83697HF";
1373 else if ((oldid &0x0f ) == 0x0a) { type="83877F"; progif=1;}
1374 else if ((oldid &0x0f ) == 0x0b) { type="83877AF"; progif=1;}
1375 else if ((oldid &0x0f ) == 0x0c) { type="83877TF"; progif=1;}
1376 else if ((oldid &0x0f ) == 0x0d) { type="83877ATF"; progif=1;}
1377 else progif=0;
1378
1379 if (verbose_probing)
1380 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
1381 "devid=%02x devrev=%02x oldid=%02x type=%s\n",
1382 efer, key, devid, devrev, oldid, type);
1383
1384 if (progif == 2)
1385 show_parconfig_winbond(efer,key);
1386 }
1387
1388 static void __devinit decode_smsc(int efer, int key, int devid, int devrev)
1389 {
1390 const char *type = "unknown";
1391 void (*func)(int io, int key);
1392 int id;
1393
1394 if (devid == devrev)
1395 /* simple heuristics, we happened to read some
1396 non-smsc register */
1397 return;
1398
1399 func=NULL;
1400 id=(devid<<8) | devrev;
1401
1402 if (id==0x0302) {type="37c669"; func=show_parconfig_smsc37c669;}
1403 else if (id==0x6582) type="37c665IR";
1404 else if (devid==0x65) type="37c665GT";
1405 else if (devid==0x66) type="37c666GT";
1406
1407 if (verbose_probing)
1408 printk(KERN_INFO "SMSC chip at EFER=0x%x "
1409 "key=0x%02x devid=%02x devrev=%02x type=%s\n",
1410 efer, key, devid, devrev, type);
1411
1412 if (func)
1413 func(efer,key);
1414 }
1415
1416
1417 static void __devinit winbond_check(int io, int key)
1418 {
1419 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1420
1421 if (!request_region(io, 3, __FUNCTION__))
1422 return;
1423
1424 /* First probe without key */
1425 outb(0x20,io);
1426 x_devid=inb(io+1);
1427 outb(0x21,io);
1428 x_devrev=inb(io+1);
1429 outb(0x09,io);
1430 x_oldid=inb(io+1);
1431
1432 outb(key,io);
1433 outb(key,io); /* Write Magic Sequence to EFER, extended
1434 funtion enable register */
1435 outb(0x20,io); /* Write EFIR, extended function index register */
1436 devid=inb(io+1); /* Read EFDR, extended function data register */
1437 outb(0x21,io);
1438 devrev=inb(io+1);
1439 outb(0x09,io);
1440 oldid=inb(io+1);
1441 outb(0xaa,io); /* Magic Seal */
1442
1443 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1444 goto out; /* protection against false positives */
1445
1446 decode_winbond(io,key,devid,devrev,oldid);
1447 out:
1448 release_region(io, 3);
1449 }
1450
1451 static void __devinit winbond_check2(int io,int key)
1452 {
1453 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1454
1455 if (!request_region(io, 3, __FUNCTION__))
1456 return;
1457
1458 /* First probe without the key */
1459 outb(0x20,io+2);
1460 x_devid=inb(io+2);
1461 outb(0x21,io+1);
1462 x_devrev=inb(io+2);
1463 outb(0x09,io+1);
1464 x_oldid=inb(io+2);
1465
1466 outb(key,io); /* Write Magic Byte to EFER, extended
1467 funtion enable register */
1468 outb(0x20,io+2); /* Write EFIR, extended function index register */
1469 devid=inb(io+2); /* Read EFDR, extended function data register */
1470 outb(0x21,io+1);
1471 devrev=inb(io+2);
1472 outb(0x09,io+1);
1473 oldid=inb(io+2);
1474 outb(0xaa,io); /* Magic Seal */
1475
1476 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1477 goto out; /* protection against false positives */
1478
1479 decode_winbond(io,key,devid,devrev,oldid);
1480 out:
1481 release_region(io, 3);
1482 }
1483
1484 static void __devinit smsc_check(int io, int key)
1485 {
1486 int id,rev,oldid,oldrev,x_id,x_rev,x_oldid,x_oldrev;
1487
1488 if (!request_region(io, 3, __FUNCTION__))
1489 return;
1490
1491 /* First probe without the key */
1492 outb(0x0d,io);
1493 x_oldid=inb(io+1);
1494 outb(0x0e,io);
1495 x_oldrev=inb(io+1);
1496 outb(0x20,io);
1497 x_id=inb(io+1);
1498 outb(0x21,io);
1499 x_rev=inb(io+1);
1500
1501 outb(key,io);
1502 outb(key,io); /* Write Magic Sequence to EFER, extended
1503 funtion enable register */
1504 outb(0x0d,io); /* Write EFIR, extended function index register */
1505 oldid=inb(io+1); /* Read EFDR, extended function data register */
1506 outb(0x0e,io);
1507 oldrev=inb(io+1);
1508 outb(0x20,io);
1509 id=inb(io+1);
1510 outb(0x21,io);
1511 rev=inb(io+1);
1512 outb(0xaa,io); /* Magic Seal */
1513
1514 if ((x_id == id) && (x_oldrev == oldrev) &&
1515 (x_oldid == oldid) && (x_rev == rev))
1516 goto out; /* protection against false positives */
1517
1518 decode_smsc(io,key,oldid,oldrev);
1519 out:
1520 release_region(io, 3);
1521 }
1522
1523
1524 static void __devinit detect_and_report_winbond (void)
1525 {
1526 if (verbose_probing)
1527 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1528 winbond_check(0x3f0,0x87);
1529 winbond_check(0x370,0x87);
1530 winbond_check(0x2e ,0x87);
1531 winbond_check(0x4e ,0x87);
1532 winbond_check(0x3f0,0x86);
1533 winbond_check2(0x250,0x88);
1534 winbond_check2(0x250,0x89);
1535 }
1536
1537 static void __devinit detect_and_report_smsc (void)
1538 {
1539 if (verbose_probing)
1540 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1541 smsc_check(0x3f0,0x55);
1542 smsc_check(0x370,0x55);
1543 smsc_check(0x3f0,0x44);
1544 smsc_check(0x370,0x44);
1545 }
1546 #endif /* CONFIG_PARPORT_PC_SUPERIO */
1547
1548 static int __devinit get_superio_dma (struct parport *p)
1549 {
1550 int i=0;
1551 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1552 i++;
1553 if (i!=NR_SUPERIOS)
1554 return superios[i].dma;
1555 return PARPORT_DMA_NONE;
1556 }
1557
1558 static int __devinit get_superio_irq (struct parport *p)
1559 {
1560 int i=0;
1561 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1562 i++;
1563 if (i!=NR_SUPERIOS)
1564 return superios[i].irq;
1565 return PARPORT_IRQ_NONE;
1566 }
1567
1568
1569 /* --- Mode detection ------------------------------------- */
1570
1571 /*
1572 * Checks for port existence, all ports support SPP MODE
1573 * Returns:
1574 * 0 : No parallel port at this address
1575 * PARPORT_MODE_PCSPP : SPP port detected
1576 * (if the user specified an ioport himself,
1577 * this shall always be the case!)
1578 *
1579 */
1580 static int __devinit parport_SPP_supported(struct parport *pb)
1581 {
1582 unsigned char r, w;
1583
1584 /*
1585 * first clear an eventually pending EPP timeout
1586 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1587 * that does not even respond to SPP cycles if an EPP
1588 * timeout is pending
1589 */
1590 clear_epp_timeout(pb);
1591
1592 /* Do a simple read-write test to make sure the port exists. */
1593 w = 0xc;
1594 outb (w, CONTROL (pb));
1595
1596 /* Is there a control register that we can read from? Some
1597 * ports don't allow reads, so read_control just returns a
1598 * software copy. Some ports _do_ allow reads, so bypass the
1599 * software copy here. In addition, some bits aren't
1600 * writable. */
1601 r = inb (CONTROL (pb));
1602 if ((r & 0xf) == w) {
1603 w = 0xe;
1604 outb (w, CONTROL (pb));
1605 r = inb (CONTROL (pb));
1606 outb (0xc, CONTROL (pb));
1607 if ((r & 0xf) == w)
1608 return PARPORT_MODE_PCSPP;
1609 }
1610
1611 if (user_specified)
1612 /* That didn't work, but the user thinks there's a
1613 * port here. */
1614 printk (KERN_INFO "parport 0x%lx (WARNING): CTR: "
1615 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1616
1617 /* Try the data register. The data lines aren't tri-stated at
1618 * this stage, so we expect back what we wrote. */
1619 w = 0xaa;
1620 parport_pc_write_data (pb, w);
1621 r = parport_pc_read_data (pb);
1622 if (r == w) {
1623 w = 0x55;
1624 parport_pc_write_data (pb, w);
1625 r = parport_pc_read_data (pb);
1626 if (r == w)
1627 return PARPORT_MODE_PCSPP;
1628 }
1629
1630 if (user_specified) {
1631 /* Didn't work, but the user is convinced this is the
1632 * place. */
1633 printk (KERN_INFO "parport 0x%lx (WARNING): DATA: "
1634 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1635 printk (KERN_INFO "parport 0x%lx: You gave this address, "
1636 "but there is probably no parallel port there!\n",
1637 pb->base);
1638 }
1639
1640 /* It's possible that we can't read the control register or
1641 * the data register. In that case just believe the user. */
1642 if (user_specified)
1643 return PARPORT_MODE_PCSPP;
1644
1645 return 0;
1646 }
1647
1648 /* Check for ECR
1649 *
1650 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1651 * on these cards actually accesses the CTR.
1652 *
1653 * Modern cards don't do this but reading from ECR will return 0xff
1654 * regardless of what is written here if the card does NOT support
1655 * ECP.
1656 *
1657 * We first check to see if ECR is the same as CTR. If not, the low
1658 * two bits of ECR aren't writable, so we check by writing ECR and
1659 * reading it back to see if it's what we expect.
1660 */
1661 static int __devinit parport_ECR_present(struct parport *pb)
1662 {
1663 struct parport_pc_private *priv = pb->private_data;
1664 unsigned char r = 0xc;
1665
1666 outb (r, CONTROL (pb));
1667 if ((inb (ECONTROL (pb)) & 0x3) == (r & 0x3)) {
1668 outb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */
1669
1670 r = inb (CONTROL (pb));
1671 if ((inb (ECONTROL (pb)) & 0x2) == (r & 0x2))
1672 goto no_reg; /* Sure that no ECR register exists */
1673 }
1674
1675 if ((inb (ECONTROL (pb)) & 0x3 ) != 0x1)
1676 goto no_reg;
1677
1678 ECR_WRITE (pb, 0x34);
1679 if (inb (ECONTROL (pb)) != 0x35)
1680 goto no_reg;
1681
1682 priv->ecr = 1;
1683 outb (0xc, CONTROL (pb));
1684
1685 /* Go to mode 000 */
1686 frob_set_mode (pb, ECR_SPP);
1687
1688 return 1;
1689
1690 no_reg:
1691 outb (0xc, CONTROL (pb));
1692 return 0;
1693 }
1694
1695 #ifdef CONFIG_PARPORT_1284
1696 /* Detect PS/2 support.
1697 *
1698 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1699 * allows us to read data from the data lines. In theory we would get back
1700 * 0xff but any peripheral attached to the port may drag some or all of the
1701 * lines down to zero. So if we get back anything that isn't the contents
1702 * of the data register we deem PS/2 support to be present.
1703 *
1704 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1705 * drivers, but an external peripheral with sufficiently beefy drivers of
1706 * its own can overpower them and assert its own levels onto the bus, from
1707 * where they can then be read back as normal. Ports with this property
1708 * and the right type of device attached are likely to fail the SPP test,
1709 * (as they will appear to have stuck bits) and so the fact that they might
1710 * be misdetected here is rather academic.
1711 */
1712
1713 static int __devinit parport_PS2_supported(struct parport *pb)
1714 {
1715 int ok = 0;
1716
1717 clear_epp_timeout(pb);
1718
1719 /* try to tri-state the buffer */
1720 parport_pc_data_reverse (pb);
1721
1722 parport_pc_write_data(pb, 0x55);
1723 if (parport_pc_read_data(pb) != 0x55) ok++;
1724
1725 parport_pc_write_data(pb, 0xaa);
1726 if (parport_pc_read_data(pb) != 0xaa) ok++;
1727
1728 /* cancel input mode */
1729 parport_pc_data_forward (pb);
1730
1731 if (ok) {
1732 pb->modes |= PARPORT_MODE_TRISTATE;
1733 } else {
1734 struct parport_pc_private *priv = pb->private_data;
1735 priv->ctr_writable &= ~0x20;
1736 }
1737
1738 return ok;
1739 }
1740
1741 #ifdef CONFIG_PARPORT_PC_FIFO
1742 static int __devinit parport_ECP_supported(struct parport *pb)
1743 {
1744 int i;
1745 int config, configb;
1746 int pword;
1747 struct parport_pc_private *priv = pb->private_data;
1748 /* Translate ECP intrLine to ISA irq value */
1749 static const int intrline[]= { 0, 7, 9, 10, 11, 14, 15, 5 };
1750
1751 /* If there is no ECR, we have no hope of supporting ECP. */
1752 if (!priv->ecr)
1753 return 0;
1754
1755 /* Find out FIFO depth */
1756 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1757 ECR_WRITE (pb, ECR_TST << 5); /* TEST FIFO */
1758 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02); i++)
1759 outb (0xaa, FIFO (pb));
1760
1761 /*
1762 * Using LGS chipset it uses ECR register, but
1763 * it doesn't support ECP or FIFO MODE
1764 */
1765 if (i == 1024) {
1766 ECR_WRITE (pb, ECR_SPP << 5);
1767 return 0;
1768 }
1769
1770 priv->fifo_depth = i;
1771 if (verbose_probing)
1772 printk (KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1773
1774 /* Find out writeIntrThreshold */
1775 frob_econtrol (pb, 1<<2, 1<<2);
1776 frob_econtrol (pb, 1<<2, 0);
1777 for (i = 1; i <= priv->fifo_depth; i++) {
1778 inb (FIFO (pb));
1779 udelay (50);
1780 if (inb (ECONTROL (pb)) & (1<<2))
1781 break;
1782 }
1783
1784 if (i <= priv->fifo_depth) {
1785 if (verbose_probing)
1786 printk (KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1787 pb->base, i);
1788 } else
1789 /* Number of bytes we know we can write if we get an
1790 interrupt. */
1791 i = 0;
1792
1793 priv->writeIntrThreshold = i;
1794
1795 /* Find out readIntrThreshold */
1796 frob_set_mode (pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1797 parport_pc_data_reverse (pb); /* Must be in PS2 mode */
1798 frob_set_mode (pb, ECR_TST); /* Test FIFO */
1799 frob_econtrol (pb, 1<<2, 1<<2);
1800 frob_econtrol (pb, 1<<2, 0);
1801 for (i = 1; i <= priv->fifo_depth; i++) {
1802 outb (0xaa, FIFO (pb));
1803 if (inb (ECONTROL (pb)) & (1<<2))
1804 break;
1805 }
1806
1807 if (i <= priv->fifo_depth) {
1808 if (verbose_probing)
1809 printk (KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1810 pb->base, i);
1811 } else
1812 /* Number of bytes we can read if we get an interrupt. */
1813 i = 0;
1814
1815 priv->readIntrThreshold = i;
1816
1817 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1818 ECR_WRITE (pb, 0xf4); /* Configuration mode */
1819 config = inb (CONFIGA (pb));
1820 pword = (config >> 4) & 0x7;
1821 switch (pword) {
1822 case 0:
1823 pword = 2;
1824 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1825 pb->base);
1826 break;
1827 case 2:
1828 pword = 4;
1829 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1830 pb->base);
1831 break;
1832 default:
1833 printk (KERN_WARNING "0x%lx: Unknown implementation ID\n",
1834 pb->base);
1835 /* Assume 1 */
1836 case 1:
1837 pword = 1;
1838 }
1839 priv->pword = pword;
1840
1841 if (verbose_probing) {
1842 printk (KERN_DEBUG "0x%lx: PWord is %d bits\n", pb->base, 8 * pword);
1843
1844 printk (KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1845 config & 0x80 ? "Level" : "Pulses");
1846
1847 configb = inb (CONFIGB (pb));
1848 printk (KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1849 pb->base, config, configb);
1850 printk (KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1851 if ((configb >>3) & 0x07)
1852 printk("%d",intrline[(configb >>3) & 0x07]);
1853 else
1854 printk("<none or set by other means>");
1855 printk (" dma=");
1856 if( (configb & 0x03 ) == 0x00)
1857 printk("<none or set by other means>\n");
1858 else
1859 printk("%d\n",configb & 0x07);
1860 }
1861
1862 /* Go back to mode 000 */
1863 frob_set_mode (pb, ECR_SPP);
1864
1865 return 1;
1866 }
1867 #endif
1868
1869 static int __devinit parport_ECPPS2_supported(struct parport *pb)
1870 {
1871 const struct parport_pc_private *priv = pb->private_data;
1872 int result;
1873 unsigned char oecr;
1874
1875 if (!priv->ecr)
1876 return 0;
1877
1878 oecr = inb (ECONTROL (pb));
1879 ECR_WRITE (pb, ECR_PS2 << 5);
1880 result = parport_PS2_supported(pb);
1881 ECR_WRITE (pb, oecr);
1882 return result;
1883 }
1884
1885 /* EPP mode detection */
1886
1887 static int __devinit parport_EPP_supported(struct parport *pb)
1888 {
1889 const struct parport_pc_private *priv = pb->private_data;
1890
1891 /*
1892 * Theory:
1893 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1894 * when EPP is possible and is set high when an EPP timeout
1895 * occurs (EPP uses the HALT line to stop the CPU while it does
1896 * the byte transfer, an EPP timeout occurs if the attached
1897 * device fails to respond after 10 micro seconds).
1898 *
1899 * This bit is cleared by either reading it (National Semi)
1900 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1901 * This bit is always high in non EPP modes.
1902 */
1903
1904 /* If EPP timeout bit clear then EPP available */
1905 if (!clear_epp_timeout(pb)) {
1906 return 0; /* No way to clear timeout */
1907 }
1908
1909 /* Check for Intel bug. */
1910 if (priv->ecr) {
1911 unsigned char i;
1912 for (i = 0x00; i < 0x80; i += 0x20) {
1913 ECR_WRITE (pb, i);
1914 if (clear_epp_timeout (pb)) {
1915 /* Phony EPP in ECP. */
1916 return 0;
1917 }
1918 }
1919 }
1920
1921 pb->modes |= PARPORT_MODE_EPP;
1922
1923 /* Set up access functions to use EPP hardware. */
1924 pb->ops->epp_read_data = parport_pc_epp_read_data;
1925 pb->ops->epp_write_data = parport_pc_epp_write_data;
1926 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1927 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1928
1929 return 1;
1930 }
1931
1932 static int __devinit parport_ECPEPP_supported(struct parport *pb)
1933 {
1934 struct parport_pc_private *priv = pb->private_data;
1935 int result;
1936 unsigned char oecr;
1937
1938 if (!priv->ecr) {
1939 return 0;
1940 }
1941
1942 oecr = inb (ECONTROL (pb));
1943 /* Search for SMC style EPP+ECP mode */
1944 ECR_WRITE (pb, 0x80);
1945 outb (0x04, CONTROL (pb));
1946 result = parport_EPP_supported(pb);
1947
1948 ECR_WRITE (pb, oecr);
1949
1950 if (result) {
1951 /* Set up access functions to use ECP+EPP hardware. */
1952 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
1953 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
1954 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
1955 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
1956 }
1957
1958 return result;
1959 }
1960
1961 #else /* No IEEE 1284 support */
1962
1963 /* Don't bother probing for modes we know we won't use. */
1964 static int __devinit parport_PS2_supported(struct parport *pb) { return 0; }
1965 #ifdef CONFIG_PARPORT_PC_FIFO
1966 static int __devinit parport_ECP_supported(struct parport *pb) { return 0; }
1967 #endif
1968 static int __devinit parport_EPP_supported(struct parport *pb) { return 0; }
1969 static int __devinit parport_ECPEPP_supported(struct parport *pb){return 0;}
1970 static int __devinit parport_ECPPS2_supported(struct parport *pb){return 0;}
1971
1972 #endif /* No IEEE 1284 support */
1973
1974 /* --- IRQ detection -------------------------------------- */
1975
1976 /* Only if supports ECP mode */
1977 static int __devinit programmable_irq_support(struct parport *pb)
1978 {
1979 int irq, intrLine;
1980 unsigned char oecr = inb (ECONTROL (pb));
1981 static const int lookup[8] = {
1982 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
1983 };
1984
1985 ECR_WRITE (pb, ECR_CNF << 5); /* Configuration MODE */
1986
1987 intrLine = (inb (CONFIGB (pb)) >> 3) & 0x07;
1988 irq = lookup[intrLine];
1989
1990 ECR_WRITE (pb, oecr);
1991 return irq;
1992 }
1993
1994 static int __devinit irq_probe_ECP(struct parport *pb)
1995 {
1996 int i;
1997 unsigned long irqs;
1998
1999 irqs = probe_irq_on();
2000
2001 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
2002 ECR_WRITE (pb, (ECR_TST << 5) | 0x04);
2003 ECR_WRITE (pb, ECR_TST << 5);
2004
2005 /* If Full FIFO sure that writeIntrThreshold is generated */
2006 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02) ; i++)
2007 outb (0xaa, FIFO (pb));
2008
2009 pb->irq = probe_irq_off(irqs);
2010 ECR_WRITE (pb, ECR_SPP << 5);
2011
2012 if (pb->irq <= 0)
2013 pb->irq = PARPORT_IRQ_NONE;
2014
2015 return pb->irq;
2016 }
2017
2018 /*
2019 * This detection seems that only works in National Semiconductors
2020 * This doesn't work in SMC, LGS, and Winbond
2021 */
2022 static int __devinit irq_probe_EPP(struct parport *pb)
2023 {
2024 #ifndef ADVANCED_DETECT
2025 return PARPORT_IRQ_NONE;
2026 #else
2027 int irqs;
2028 unsigned char oecr;
2029
2030 if (pb->modes & PARPORT_MODE_PCECR)
2031 oecr = inb (ECONTROL (pb));
2032
2033 irqs = probe_irq_on();
2034
2035 if (pb->modes & PARPORT_MODE_PCECR)
2036 frob_econtrol (pb, 0x10, 0x10);
2037
2038 clear_epp_timeout(pb);
2039 parport_pc_frob_control (pb, 0x20, 0x20);
2040 parport_pc_frob_control (pb, 0x10, 0x10);
2041 clear_epp_timeout(pb);
2042
2043 /* Device isn't expecting an EPP read
2044 * and generates an IRQ.
2045 */
2046 parport_pc_read_epp(pb);
2047 udelay(20);
2048
2049 pb->irq = probe_irq_off (irqs);
2050 if (pb->modes & PARPORT_MODE_PCECR)
2051 ECR_WRITE (pb, oecr);
2052 parport_pc_write_control(pb, 0xc);
2053
2054 if (pb->irq <= 0)
2055 pb->irq = PARPORT_IRQ_NONE;
2056
2057 return pb->irq;
2058 #endif /* Advanced detection */
2059 }
2060
2061 static int __devinit irq_probe_SPP(struct parport *pb)
2062 {
2063 /* Don't even try to do this. */
2064 return PARPORT_IRQ_NONE;
2065 }
2066
2067 /* We will attempt to share interrupt requests since other devices
2068 * such as sound cards and network cards seem to like using the
2069 * printer IRQs.
2070 *
2071 * When ECP is available we can autoprobe for IRQs.
2072 * NOTE: If we can autoprobe it, we can register the IRQ.
2073 */
2074 static int __devinit parport_irq_probe(struct parport *pb)
2075 {
2076 struct parport_pc_private *priv = pb->private_data;
2077
2078 if (priv->ecr) {
2079 pb->irq = programmable_irq_support(pb);
2080
2081 if (pb->irq == PARPORT_IRQ_NONE)
2082 pb->irq = irq_probe_ECP(pb);
2083 }
2084
2085 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
2086 (pb->modes & PARPORT_MODE_EPP))
2087 pb->irq = irq_probe_EPP(pb);
2088
2089 clear_epp_timeout(pb);
2090
2091 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
2092 pb->irq = irq_probe_EPP(pb);
2093
2094 clear_epp_timeout(pb);
2095
2096 if (pb->irq == PARPORT_IRQ_NONE)
2097 pb->irq = irq_probe_SPP(pb);
2098
2099 if (pb->irq == PARPORT_IRQ_NONE)
2100 pb->irq = get_superio_irq(pb);
2101
2102 return pb->irq;
2103 }
2104
2105 /* --- DMA detection -------------------------------------- */
2106
2107 /* Only if chipset conforms to ECP ISA Interface Standard */
2108 static int __devinit programmable_dma_support (struct parport *p)
2109 {
2110 unsigned char oecr = inb (ECONTROL (p));
2111 int dma;
2112
2113 frob_set_mode (p, ECR_CNF);
2114
2115 dma = inb (CONFIGB(p)) & 0x07;
2116 /* 000: Indicates jumpered 8-bit DMA if read-only.
2117 100: Indicates jumpered 16-bit DMA if read-only. */
2118 if ((dma & 0x03) == 0)
2119 dma = PARPORT_DMA_NONE;
2120
2121 ECR_WRITE (p, oecr);
2122 return dma;
2123 }
2124
2125 static int __devinit parport_dma_probe (struct parport *p)
2126 {
2127 const struct parport_pc_private *priv = p->private_data;
2128 if (priv->ecr)
2129 p->dma = programmable_dma_support(p); /* ask ECP chipset first */
2130 if (p->dma == PARPORT_DMA_NONE) {
2131 /* ask known Super-IO chips proper, although these
2132 claim ECP compatible, some don't report their DMA
2133 conforming to ECP standards */
2134 p->dma = get_superio_dma(p);
2135 }
2136
2137 return p->dma;
2138 }
2139
2140 /* --- Initialisation code -------------------------------- */
2141
2142 static LIST_HEAD(ports_list);
2143 static DEFINE_SPINLOCK(ports_lock);
2144
2145 struct parport *parport_pc_probe_port (unsigned long int base,
2146 unsigned long int base_hi,
2147 int irq, int dma,
2148 struct pci_dev *dev)
2149 {
2150 struct parport_pc_private *priv;
2151 struct parport_operations *ops;
2152 struct parport *p;
2153 int probedirq = PARPORT_IRQ_NONE;
2154 struct resource *base_res;
2155 struct resource *ECR_res = NULL;
2156 struct resource *EPP_res = NULL;
2157
2158 ops = kmalloc(sizeof (struct parport_operations), GFP_KERNEL);
2159 if (!ops)
2160 goto out1;
2161
2162 priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
2163 if (!priv)
2164 goto out2;
2165
2166 /* a misnomer, actually - it's allocate and reserve parport number */
2167 p = parport_register_port(base, irq, dma, ops);
2168 if (!p)
2169 goto out3;
2170
2171 base_res = request_region(base, 3, p->name);
2172 if (!base_res)
2173 goto out4;
2174
2175 memcpy(ops, &parport_pc_ops, sizeof (struct parport_operations));
2176 priv->ctr = 0xc;
2177 priv->ctr_writable = ~0x10;
2178 priv->ecr = 0;
2179 priv->fifo_depth = 0;
2180 priv->dma_buf = NULL;
2181 priv->dma_handle = 0;
2182 priv->dev = dev;
2183 INIT_LIST_HEAD(&priv->list);
2184 priv->port = p;
2185 p->base_hi = base_hi;
2186 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2187 p->private_data = priv;
2188
2189 if (base_hi) {
2190 ECR_res = request_region(base_hi, 3, p->name);
2191 if (ECR_res)
2192 parport_ECR_present(p);
2193 }
2194
2195 if (base != 0x3bc) {
2196 EPP_res = request_region(base+0x3, 5, p->name);
2197 if (EPP_res)
2198 if (!parport_EPP_supported(p))
2199 parport_ECPEPP_supported(p);
2200 }
2201 if (!parport_SPP_supported (p))
2202 /* No port. */
2203 goto out5;
2204 if (priv->ecr)
2205 parport_ECPPS2_supported(p);
2206 else
2207 parport_PS2_supported(p);
2208
2209 p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
2210
2211 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2212 if (p->base_hi && priv->ecr)
2213 printk(" (0x%lx)", p->base_hi);
2214 if (p->irq == PARPORT_IRQ_AUTO) {
2215 p->irq = PARPORT_IRQ_NONE;
2216 parport_irq_probe(p);
2217 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2218 p->irq = PARPORT_IRQ_NONE;
2219 parport_irq_probe(p);
2220 probedirq = p->irq;
2221 p->irq = PARPORT_IRQ_NONE;
2222 }
2223 if (p->irq != PARPORT_IRQ_NONE) {
2224 printk(", irq %d", p->irq);
2225 priv->ctr_writable |= 0x10;
2226
2227 if (p->dma == PARPORT_DMA_AUTO) {
2228 p->dma = PARPORT_DMA_NONE;
2229 parport_dma_probe(p);
2230 }
2231 }
2232 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2233 is mandatory (see above) */
2234 p->dma = PARPORT_DMA_NONE;
2235
2236 #ifdef CONFIG_PARPORT_PC_FIFO
2237 if (parport_ECP_supported(p) &&
2238 p->dma != PARPORT_DMA_NOFIFO &&
2239 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2240 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2241 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2242 #ifdef CONFIG_PARPORT_1284
2243 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2244 /* currently broken, but working on it.. (FB) */
2245 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2246 #endif /* IEEE 1284 support */
2247 if (p->dma != PARPORT_DMA_NONE) {
2248 printk(", dma %d", p->dma);
2249 p->modes |= PARPORT_MODE_DMA;
2250 }
2251 else printk(", using FIFO");
2252 }
2253 else
2254 /* We can't use the DMA channel after all. */
2255 p->dma = PARPORT_DMA_NONE;
2256 #endif /* Allowed to use FIFO/DMA */
2257
2258 printk(" [");
2259 #define printmode(x) {if(p->modes&PARPORT_MODE_##x){printk("%s%s",f?",":"",#x);f++;}}
2260 {
2261 int f = 0;
2262 printmode(PCSPP);
2263 printmode(TRISTATE);
2264 printmode(COMPAT)
2265 printmode(EPP);
2266 printmode(ECP);
2267 printmode(DMA);
2268 }
2269 #undef printmode
2270 #ifndef CONFIG_PARPORT_1284
2271 printk ("(,...)");
2272 #endif /* CONFIG_PARPORT_1284 */
2273 printk("]\n");
2274 if (probedirq != PARPORT_IRQ_NONE)
2275 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2276
2277 /* If No ECP release the ports grabbed above. */
2278 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2279 release_region(base_hi, 3);
2280 ECR_res = NULL;
2281 }
2282 /* Likewise for EEP ports */
2283 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2284 release_region(base+3, 5);
2285 EPP_res = NULL;
2286 }
2287 if (p->irq != PARPORT_IRQ_NONE) {
2288 if (request_irq (p->irq, parport_pc_interrupt,
2289 0, p->name, p)) {
2290 printk (KERN_WARNING "%s: irq %d in use, "
2291 "resorting to polled operation\n",
2292 p->name, p->irq);
2293 p->irq = PARPORT_IRQ_NONE;
2294 p->dma = PARPORT_DMA_NONE;
2295 }
2296
2297 #ifdef CONFIG_PARPORT_PC_FIFO
2298 #ifdef HAS_DMA
2299 if (p->dma != PARPORT_DMA_NONE) {
2300 if (request_dma (p->dma, p->name)) {
2301 printk (KERN_WARNING "%s: dma %d in use, "
2302 "resorting to PIO operation\n",
2303 p->name, p->dma);
2304 p->dma = PARPORT_DMA_NONE;
2305 } else {
2306 priv->dma_buf =
2307 pci_alloc_consistent(priv->dev,
2308 PAGE_SIZE,
2309 &priv->dma_handle);
2310 if (! priv->dma_buf) {
2311 printk (KERN_WARNING "%s: "
2312 "cannot get buffer for DMA, "
2313 "resorting to PIO operation\n",
2314 p->name);
2315 free_dma(p->dma);
2316 p->dma = PARPORT_DMA_NONE;
2317 }
2318 }
2319 }
2320 #endif
2321 #endif
2322 }
2323
2324 /* Done probing. Now put the port into a sensible start-up state. */
2325 if (priv->ecr)
2326 /*
2327 * Put the ECP detected port in PS2 mode.
2328 * Do this also for ports that have ECR but don't do ECP.
2329 */
2330 ECR_WRITE (p, 0x34);
2331
2332 parport_pc_write_data(p, 0);
2333 parport_pc_data_forward (p);
2334
2335 /* Now that we've told the sharing engine about the port, and
2336 found out its characteristics, let the high-level drivers
2337 know about it. */
2338 spin_lock(&ports_lock);
2339 list_add(&priv->list, &ports_list);
2340 spin_unlock(&ports_lock);
2341 parport_announce_port (p);
2342
2343 return p;
2344
2345 out5:
2346 if (ECR_res)
2347 release_region(base_hi, 3);
2348 if (EPP_res)
2349 release_region(base+0x3, 5);
2350 release_region(base, 3);
2351 out4:
2352 parport_put_port(p);
2353 out3:
2354 kfree (priv);
2355 out2:
2356 kfree (ops);
2357 out1:
2358 return NULL;
2359 }
2360
2361 EXPORT_SYMBOL (parport_pc_probe_port);
2362
2363 void parport_pc_unregister_port (struct parport *p)
2364 {
2365 struct parport_pc_private *priv = p->private_data;
2366 struct parport_operations *ops = p->ops;
2367
2368 parport_remove_port(p);
2369 spin_lock(&ports_lock);
2370 list_del_init(&priv->list);
2371 spin_unlock(&ports_lock);
2372 if (p->dma != PARPORT_DMA_NONE)
2373 free_dma(p->dma);
2374 if (p->irq != PARPORT_IRQ_NONE)
2375 free_irq(p->irq, p);
2376 release_region(p->base, 3);
2377 if (p->size > 3)
2378 release_region(p->base + 3, p->size - 3);
2379 if (p->modes & PARPORT_MODE_ECP)
2380 release_region(p->base_hi, 3);
2381 #ifdef CONFIG_PARPORT_PC_FIFO
2382 #ifdef HAS_DMA
2383 if (priv->dma_buf)
2384 pci_free_consistent(priv->dev, PAGE_SIZE,
2385 priv->dma_buf,
2386 priv->dma_handle);
2387 #endif
2388 #endif
2389 kfree (p->private_data);
2390 parport_put_port(p);
2391 kfree (ops); /* hope no-one cached it */
2392 }
2393
2394 EXPORT_SYMBOL (parport_pc_unregister_port);
2395
2396 #ifdef CONFIG_PCI
2397
2398 /* ITE support maintained by Rich Liu <richliu@poorman.org> */
2399 static int __devinit sio_ite_8872_probe (struct pci_dev *pdev, int autoirq,
2400 int autodma, struct parport_pc_via_data *via)
2401 {
2402 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2403 struct resource *base_res;
2404 u32 ite8872set;
2405 u32 ite8872_lpt, ite8872_lpthi;
2406 u8 ite8872_irq, type;
2407 char *fake_name = "parport probe";
2408 int irq;
2409 int i;
2410
2411 DPRINTK (KERN_DEBUG "sio_ite_8872_probe()\n");
2412
2413 // make sure which one chip
2414 for(i = 0; i < 5; i++) {
2415 base_res = request_region(inta_addr[i], 0x8, fake_name);
2416 if (base_res) {
2417 int test;
2418 pci_write_config_dword (pdev, 0x60,
2419 0xe7000000 | inta_addr[i]);
2420 pci_write_config_dword (pdev, 0x78,
2421 0x00000000 | inta_addr[i]);
2422 test = inb (inta_addr[i]);
2423 if (test != 0xff) break;
2424 release_region(inta_addr[i], 0x8);
2425 }
2426 }
2427 if(i >= 5) {
2428 printk (KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
2429 return 0;
2430 }
2431
2432 type = inb (inta_addr[i] + 0x18);
2433 type &= 0x0f;
2434
2435 switch (type) {
2436 case 0x2:
2437 printk (KERN_INFO "parport_pc: ITE8871 found (1P)\n");
2438 ite8872set = 0x64200000;
2439 break;
2440 case 0xa:
2441 printk (KERN_INFO "parport_pc: ITE8875 found (1P)\n");
2442 ite8872set = 0x64200000;
2443 break;
2444 case 0xe:
2445 printk (KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
2446 ite8872set = 0x64e00000;
2447 break;
2448 case 0x6:
2449 printk (KERN_INFO "parport_pc: ITE8873 found (1S)\n");
2450 return 0;
2451 case 0x8:
2452 DPRINTK (KERN_DEBUG "parport_pc: ITE8874 found (2S)\n");
2453 return 0;
2454 default:
2455 printk (KERN_INFO "parport_pc: unknown ITE887x\n");
2456 printk (KERN_INFO "parport_pc: please mail 'lspci -nvv' "
2457 "output to Rich.Liu@ite.com.tw\n");
2458 return 0;
2459 }
2460
2461 pci_read_config_byte (pdev, 0x3c, &ite8872_irq);
2462 pci_read_config_dword (pdev, 0x1c, &ite8872_lpt);
2463 ite8872_lpt &= 0x0000ff00;
2464 pci_read_config_dword (pdev, 0x20, &ite8872_lpthi);
2465 ite8872_lpthi &= 0x0000ff00;
2466 pci_write_config_dword (pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2467 pci_write_config_dword (pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2468 pci_write_config_dword (pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2469 // SET SPP&EPP , Parallel Port NO DMA , Enable All Function
2470 // SET Parallel IRQ
2471 pci_write_config_dword (pdev, 0x9c,
2472 ite8872set | (ite8872_irq * 0x11111));
2473
2474 DPRINTK (KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
2475 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
2476 ite8872_lpt);
2477 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
2478 ite8872_lpthi);
2479
2480 /* Let the user (or defaults) steer us away from interrupts */
2481 irq = ite8872_irq;
2482 if (autoirq != PARPORT_IRQ_AUTO)
2483 irq = PARPORT_IRQ_NONE;
2484
2485 /*
2486 * Release the resource so that parport_pc_probe_port can get it.
2487 */
2488 release_resource(base_res);
2489 if (parport_pc_probe_port (ite8872_lpt, ite8872_lpthi,
2490 irq, PARPORT_DMA_NONE, NULL)) {
2491 printk (KERN_INFO
2492 "parport_pc: ITE 8872 parallel port: io=0x%X",
2493 ite8872_lpt);
2494 if (irq != PARPORT_IRQ_NONE)
2495 printk (", irq=%d", irq);
2496 printk ("\n");
2497 return 1;
2498 }
2499
2500 return 0;
2501 }
2502
2503 /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2504 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
2505 static int __devinitdata parport_init_mode = 0;
2506
2507 /* Data for two known VIA chips */
2508 static struct parport_pc_via_data via_686a_data __devinitdata = {
2509 0x51,
2510 0x50,
2511 0x85,
2512 0x02,
2513 0xE2,
2514 0xF0,
2515 0xE6
2516 };
2517 static struct parport_pc_via_data via_8231_data __devinitdata = {
2518 0x45,
2519 0x44,
2520 0x50,
2521 0x04,
2522 0xF2,
2523 0xFA,
2524 0xF6
2525 };
2526
2527 static int __devinit sio_via_probe (struct pci_dev *pdev, int autoirq,
2528 int autodma, struct parport_pc_via_data *via)
2529 {
2530 u8 tmp, tmp2, siofunc;
2531 u8 ppcontrol = 0;
2532 int dma, irq;
2533 unsigned port1, port2;
2534 unsigned have_epp = 0;
2535
2536 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
2537
2538 switch(parport_init_mode)
2539 {
2540 case 1:
2541 printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
2542 siofunc = VIA_FUNCTION_PARPORT_SPP;
2543 break;
2544 case 2:
2545 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
2546 siofunc = VIA_FUNCTION_PARPORT_SPP;
2547 ppcontrol = VIA_PARPORT_BIDIR;
2548 break;
2549 case 3:
2550 printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
2551 siofunc = VIA_FUNCTION_PARPORT_EPP;
2552 ppcontrol = VIA_PARPORT_BIDIR;
2553 have_epp = 1;
2554 break;
2555 case 4:
2556 printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
2557 siofunc = VIA_FUNCTION_PARPORT_ECP;
2558 ppcontrol = VIA_PARPORT_BIDIR;
2559 break;
2560 case 5:
2561 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
2562 siofunc = VIA_FUNCTION_PARPORT_ECP;
2563 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
2564 have_epp = 1;
2565 break;
2566 default:
2567 printk(KERN_DEBUG "parport_pc: probing current configuration\n");
2568 siofunc = VIA_FUNCTION_PROBE;
2569 break;
2570 }
2571 /*
2572 * unlock super i/o configuration
2573 */
2574 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2575 tmp |= via->via_pci_superio_config_data;
2576 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2577
2578 /* Bits 1-0: Parallel Port Mode / Enable */
2579 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2580 tmp = inb (VIA_CONFIG_DATA);
2581 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2582 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2583 tmp2 = inb (VIA_CONFIG_DATA);
2584 if (siofunc == VIA_FUNCTION_PROBE)
2585 {
2586 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
2587 ppcontrol = tmp2;
2588 }
2589 else
2590 {
2591 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
2592 tmp |= siofunc;
2593 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2594 outb(tmp, VIA_CONFIG_DATA);
2595 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
2596 tmp2 |= ppcontrol;
2597 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2598 outb(tmp2, VIA_CONFIG_DATA);
2599 }
2600
2601 /* Parallel Port I/O Base Address, bits 9-2 */
2602 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2603 port1 = inb(VIA_CONFIG_DATA) << 2;
2604
2605 printk (KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",port1);
2606 if ((port1 == 0x3BC) && have_epp)
2607 {
2608 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2609 outb((0x378 >> 2), VIA_CONFIG_DATA);
2610 printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n");
2611 port1 = 0x378;
2612 }
2613
2614 /*
2615 * lock super i/o configuration
2616 */
2617 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2618 tmp &= ~via->via_pci_superio_config_data;
2619 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2620
2621 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
2622 printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n");
2623 return 0;
2624 }
2625
2626 /* Bits 7-4: PnP Routing for Parallel Port IRQ */
2627 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
2628 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
2629
2630 if (siofunc == VIA_FUNCTION_PARPORT_ECP)
2631 {
2632 /* Bits 3-2: PnP Routing for Parallel Port DMA */
2633 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
2634 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
2635 }
2636 else
2637 /* if ECP not enabled, DMA is not enabled, assumed bogus 'dma' value */
2638 dma = PARPORT_DMA_NONE;
2639
2640 /* Let the user (or defaults) steer us away from interrupts and DMA */
2641 if (autoirq == PARPORT_IRQ_NONE) {
2642 irq = PARPORT_IRQ_NONE;
2643 dma = PARPORT_DMA_NONE;
2644 }
2645 if (autodma == PARPORT_DMA_NONE)
2646 dma = PARPORT_DMA_NONE;
2647
2648 switch (port1) {
2649 case 0x3bc: port2 = 0x7bc; break;
2650 case 0x378: port2 = 0x778; break;
2651 case 0x278: port2 = 0x678; break;
2652 default:
2653 printk(KERN_INFO "parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2654 port1);
2655 return 0;
2656 }
2657
2658 /* filter bogus IRQs */
2659 switch (irq) {
2660 case 0:
2661 case 2:
2662 case 8:
2663 case 13:
2664 irq = PARPORT_IRQ_NONE;
2665 break;
2666
2667 default: /* do nothing */
2668 break;
2669 }
2670
2671 /* finally, do the probe with values obtained */
2672 if (parport_pc_probe_port (port1, port2, irq, dma, NULL)) {
2673 printk (KERN_INFO
2674 "parport_pc: VIA parallel port: io=0x%X", port1);
2675 if (irq != PARPORT_IRQ_NONE)
2676 printk (", irq=%d", irq);
2677 if (dma != PARPORT_DMA_NONE)
2678 printk (", dma=%d", dma);
2679 printk ("\n");
2680 return 1;
2681 }
2682
2683 printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2684 port1, irq, dma);
2685 return 0;
2686 }
2687
2688
2689 enum parport_pc_sio_types {
2690 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2691 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
2692 sio_ite_8872,
2693 last_sio
2694 };
2695
2696 /* each element directly indexed from enum list, above */
2697 static struct parport_pc_superio {
2698 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma, struct parport_pc_via_data *via);
2699 struct parport_pc_via_data *via;
2700 } parport_pc_superio_info[] __devinitdata = {
2701 { sio_via_probe, &via_686a_data, },
2702 { sio_via_probe, &via_8231_data, },
2703 { sio_ite_8872_probe, NULL, },
2704 };
2705
2706 enum parport_pc_pci_cards {
2707 siig_1p_10x = last_sio,
2708 siig_2p_10x,
2709 siig_1p_20x,
2710 siig_2p_20x,
2711 lava_parallel,
2712 lava_parallel_dual_a,
2713 lava_parallel_dual_b,
2714 boca_ioppar,
2715 plx_9050,
2716 timedia_4078a,
2717 timedia_4079h,
2718 timedia_4085h,
2719 timedia_4088a,
2720 timedia_4089a,
2721 timedia_4095a,
2722 timedia_4096a,
2723 timedia_4078u,
2724 timedia_4079a,
2725 timedia_4085u,
2726 timedia_4079r,
2727 timedia_4079s,
2728 timedia_4079d,
2729 timedia_4079e,
2730 timedia_4079f,
2731 timedia_9079a,
2732 timedia_9079b,
2733 timedia_9079c,
2734 timedia_4006a,
2735 timedia_4014,
2736 timedia_4008a,
2737 timedia_4018,
2738 timedia_9018a,
2739 syba_2p_epp,
2740 syba_1p_ecp,
2741 titan_010l,
2742 titan_1284p2,
2743 avlab_1p,
2744 avlab_2p,
2745 oxsemi_954,
2746 oxsemi_840,
2747 aks_0100,
2748 mobility_pp,
2749 netmos_9705,
2750 netmos_9715,
2751 netmos_9755,
2752 netmos_9805,
2753 netmos_9815,
2754 netmos_9855,
2755 };
2756
2757
2758 /* each element directly indexed from enum list, above
2759 * (but offset by last_sio) */
2760 static struct parport_pc_pci {
2761 int numports;
2762 struct { /* BAR (base address registers) numbers in the config
2763 space header */
2764 int lo;
2765 int hi; /* -1 if not there, >6 for offset-method (max
2766 BAR is 6) */
2767 } addr[4];
2768
2769 /* If set, this is called immediately after pci_enable_device.
2770 * If it returns non-zero, no probing will take place and the
2771 * ports will not be used. */
2772 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2773
2774 /* If set, this is called after probing for ports. If 'failed'
2775 * is non-zero we couldn't use any of the ports. */
2776 void (*postinit_hook) (struct pci_dev *pdev, int failed);
2777 } cards[] __devinitdata = {
2778 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2779 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2780 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2781 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2782 /* lava_parallel */ { 1, { { 0, -1 }, } },
2783 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2784 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2785 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2786 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2787 /* timedia_4078a */ { 1, { { 2, -1 }, } },
2788 /* timedia_4079h */ { 1, { { 2, 3 }, } },
2789 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
2790 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2791 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2792 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2793 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2794 /* timedia_4078u */ { 1, { { 2, -1 }, } },
2795 /* timedia_4079a */ { 1, { { 2, 3 }, } },
2796 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
2797 /* timedia_4079r */ { 1, { { 2, 3 }, } },
2798 /* timedia_4079s */ { 1, { { 2, 3 }, } },
2799 /* timedia_4079d */ { 1, { { 2, 3 }, } },
2800 /* timedia_4079e */ { 1, { { 2, 3 }, } },
2801 /* timedia_4079f */ { 1, { { 2, 3 }, } },
2802 /* timedia_9079a */ { 1, { { 2, 3 }, } },
2803 /* timedia_9079b */ { 1, { { 2, 3 }, } },
2804 /* timedia_9079c */ { 1, { { 2, 3 }, } },
2805 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2806 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2807 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2808 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2809 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2810 /* SYBA uses fixed offsets in
2811 a 1K io window */
2812 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2813 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2814 /* titan_010l */ { 1, { { 3, -1 }, } },
2815 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2816 /* avlab_1p */ { 1, { { 0, 1}, } },
2817 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2818 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2819 * and 840 locks up if you write 1 to bit 2! */
2820 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
2821 /* oxsemi_840 */ { 1, { { 0, -1 }, } },
2822 /* aks_0100 */ { 1, { { 0, -1 }, } },
2823 /* mobility_pp */ { 1, { { 0, 1 }, } },
2824 /* netmos_9705 */ { 1, { { 0, -1 }, } }, /* untested */
2825 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */
2826 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */
2827 /* netmos_9805 */ { 1, { { 0, -1 }, } }, /* untested */
2828 /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } }, /* untested */
2829 /* netmos_9855 */ { 2, { { 0, -1 }, { 2, -1 }, } }, /* untested */
2830 };
2831
2832 static struct pci_device_id parport_pc_pci_tbl[] = {
2833 /* Super-IO onboard chips */
2834 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2835 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2836 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2837 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2838
2839 /* PCI cards */
2840 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2841 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2842 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2843 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2844 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2845 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2846 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2847 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2848 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2849 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2850 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2851 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2852 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2853 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2854 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2855 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2856 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2857 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0,0, plx_9050 },
2858 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2859 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
2860 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
2861 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
2862 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
2863 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
2864 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
2865 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
2866 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
2867 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
2868 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
2869 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
2870 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
2871 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
2872 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
2873 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
2874 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
2875 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
2876 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
2877 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2878 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2879 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2880 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2881 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2882 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2883 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2884 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2885 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2886 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2887 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2888 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2889 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 },
2890 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
2891 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, /* AFAVLAB_TK9902 */
2892 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2893 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2894 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2895 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2896 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2897 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2898 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2899 /* NetMos communication controllers */
2900 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
2901 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
2902 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
2903 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
2904 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
2905 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
2906 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
2907 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
2908 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
2909 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
2910 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
2911 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9855 },
2912 { 0, } /* terminate list */
2913 };
2914 MODULE_DEVICE_TABLE(pci,parport_pc_pci_tbl);
2915
2916 struct pci_parport_data {
2917 int num;
2918 struct parport *ports[2];
2919 };
2920
2921 static int parport_pc_pci_probe (struct pci_dev *dev,
2922 const struct pci_device_id *id)
2923 {
2924 int err, count, n, i = id->driver_data;
2925 struct pci_parport_data *data;
2926
2927 if (i < last_sio)
2928 /* This is an onboard Super-IO and has already been probed */
2929 return 0;
2930
2931 /* This is a PCI card */
2932 i -= last_sio;
2933 count = 0;
2934 if ((err = pci_enable_device (dev)) != 0)
2935 return err;
2936
2937 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
2938 if (!data)
2939 return -ENOMEM;
2940
2941 if (cards[i].preinit_hook &&
2942 cards[i].preinit_hook (dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
2943 kfree(data);
2944 return -ENODEV;
2945 }
2946
2947 for (n = 0; n < cards[i].numports; n++) {
2948 int lo = cards[i].addr[n].lo;
2949 int hi = cards[i].addr[n].hi;
2950 unsigned long io_lo, io_hi;
2951 io_lo = pci_resource_start (dev, lo);
2952 io_hi = 0;
2953 if ((hi >= 0) && (hi <= 6))
2954 io_hi = pci_resource_start (dev, hi);
2955 else if (hi > 6)
2956 io_lo += hi; /* Reinterpret the meaning of
2957 "hi" as an offset (see SYBA
2958 def.) */
2959 /* TODO: test if sharing interrupts works */
2960 printk (KERN_DEBUG "PCI parallel port detected: %04x:%04x, "
2961 "I/O at %#lx(%#lx)\n",
2962 parport_pc_pci_tbl[i + last_sio].vendor,
2963 parport_pc_pci_tbl[i + last_sio].device, io_lo, io_hi);
2964 data->ports[count] =
2965 parport_pc_probe_port (io_lo, io_hi, PARPORT_IRQ_NONE,
2966 PARPORT_DMA_NONE, dev);
2967 if (data->ports[count])
2968 count++;
2969 }
2970
2971 data->num = count;
2972
2973 if (cards[i].postinit_hook)
2974 cards[i].postinit_hook (dev, count == 0);
2975
2976 if (count) {
2977 pci_set_drvdata(dev, data);
2978 return 0;
2979 }
2980
2981 kfree(data);
2982
2983 return -ENODEV;
2984 }
2985
2986 static void __devexit parport_pc_pci_remove(struct pci_dev *dev)
2987 {
2988 struct pci_parport_data *data = pci_get_drvdata(dev);
2989 int i;
2990
2991 pci_set_drvdata(dev, NULL);
2992
2993 if (data) {
2994 for (i = data->num - 1; i >= 0; i--)
2995 parport_pc_unregister_port(data->ports[i]);
2996
2997 kfree(data);
2998 }
2999 }
3000
3001 static struct pci_driver parport_pc_pci_driver = {
3002 .name = "parport_pc",
3003 .id_table = parport_pc_pci_tbl,
3004 .probe = parport_pc_pci_probe,
3005 .remove = __devexit_p(parport_pc_pci_remove),
3006 };
3007
3008 static int __init parport_pc_init_superio (int autoirq, int autodma)
3009 {
3010 const struct pci_device_id *id;
3011 struct pci_dev *pdev = NULL;
3012 int ret = 0;
3013
3014 while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev)) != NULL) {
3015 id = pci_match_device (parport_pc_pci_tbl, pdev);
3016 if (id == NULL || id->driver_data >= last_sio)
3017 continue;
3018
3019 if (parport_pc_superio_info[id->driver_data].probe
3020 (pdev, autoirq, autodma,parport_pc_superio_info[id->driver_data].via)) {
3021 ret++;
3022 }
3023 }
3024
3025 return ret; /* number of devices found */
3026 }
3027 #else
3028 static struct pci_driver parport_pc_pci_driver;
3029 static int __init parport_pc_init_superio(int autoirq, int autodma) {return 0;}
3030 #endif /* CONFIG_PCI */
3031
3032
3033 static const struct pnp_device_id parport_pc_pnp_tbl[] = {
3034 /* Standard LPT Printer Port */
3035 {.id = "PNP0400", .driver_data = 0},
3036 /* ECP Printer Port */
3037 {.id = "PNP0401", .driver_data = 0},
3038 { }
3039 };
3040
3041 MODULE_DEVICE_TABLE(pnp,parport_pc_pnp_tbl);
3042
3043 static int parport_pc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id)
3044 {
3045 struct parport *pdata;
3046 unsigned long io_lo, io_hi;
3047 int dma, irq;
3048
3049 if (pnp_port_valid(dev,0) &&
3050 !(pnp_port_flags(dev,0) & IORESOURCE_DISABLED)) {
3051 io_lo = pnp_port_start(dev,0);
3052 } else
3053 return -EINVAL;
3054
3055 if (pnp_port_valid(dev,1) &&
3056 !(pnp_port_flags(dev,1) & IORESOURCE_DISABLED)) {
3057 io_hi = pnp_port_start(dev,1);
3058 } else
3059 io_hi = 0;
3060
3061 if (pnp_irq_valid(dev,0) &&
3062 !(pnp_irq_flags(dev,0) & IORESOURCE_DISABLED)) {
3063 irq = pnp_irq(dev,0);
3064 } else
3065 irq = PARPORT_IRQ_NONE;
3066
3067 if (pnp_dma_valid(dev,0) &&
3068 !(pnp_dma_flags(dev,0) & IORESOURCE_DISABLED)) {
3069 dma = pnp_dma(dev,0);
3070 } else
3071 dma = PARPORT_DMA_NONE;
3072
3073 printk(KERN_INFO "parport: PnPBIOS parport detected.\n");
3074 if (!(pdata = parport_pc_probe_port (io_lo, io_hi, irq, dma, NULL)))
3075 return -ENODEV;
3076
3077 pnp_set_drvdata(dev,pdata);
3078 return 0;
3079 }
3080
3081 static void parport_pc_pnp_remove(struct pnp_dev *dev)
3082 {
3083 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
3084 if (!pdata)
3085 return;
3086
3087 parport_pc_unregister_port(pdata);
3088 }
3089
3090 /* we only need the pnp layer to activate the device, at least for now */
3091 static struct pnp_driver parport_pc_pnp_driver = {
3092 .name = "parport_pc",
3093 .id_table = parport_pc_pnp_tbl,
3094 .probe = parport_pc_pnp_probe,
3095 .remove = parport_pc_pnp_remove,
3096 };
3097
3098
3099 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
3100 static int __devinit __attribute__((unused))
3101 parport_pc_find_isa_ports (int autoirq, int autodma)
3102 {
3103 int count = 0;
3104
3105 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL))
3106 count++;
3107 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL))
3108 count++;
3109 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL))
3110 count++;
3111
3112 return count;
3113 }
3114
3115 /* This function is called by parport_pc_init if the user didn't
3116 * specify any ports to probe. Its job is to find some ports. Order
3117 * is important here -- we want ISA ports to be registered first,
3118 * followed by PCI cards (for least surprise), but before that we want
3119 * to do chipset-specific tests for some onboard ports that we know
3120 * about.
3121 *
3122 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3123 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3124 */
3125 static int __init parport_pc_find_ports (int autoirq, int autodma)
3126 {
3127 int count = 0, r;
3128
3129 #ifdef CONFIG_PARPORT_PC_SUPERIO
3130 detect_and_report_winbond ();
3131 detect_and_report_smsc ();
3132 #endif
3133
3134 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3135 count += parport_pc_init_superio (autoirq, autodma);
3136
3137 /* PnP ports, skip detection if SuperIO already found them */
3138 if (!count) {
3139 r = pnp_register_driver (&parport_pc_pnp_driver);
3140 if (r >= 0) {
3141 pnp_registered_parport = 1;
3142 count += r;
3143 }
3144 }
3145
3146 /* ISA ports and whatever (see asm/parport.h). */
3147 count += parport_pc_find_nonpci_ports (autoirq, autodma);
3148
3149 r = pci_register_driver (&parport_pc_pci_driver);
3150 if (r)
3151 return r;
3152 pci_registered_parport = 1;
3153 count += 1;
3154
3155 return count;
3156 }
3157
3158 /*
3159 * Piles of crap below pretend to be a parser for module and kernel
3160 * parameters. Say "thank you" to whoever had come up with that
3161 * syntax and keep in mind that code below is a cleaned up version.
3162 */
3163
3164 static int __initdata io[PARPORT_PC_MAX_PORTS+1] = { [0 ... PARPORT_PC_MAX_PORTS] = 0 };
3165 static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] =
3166 { [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO };
3167 static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE };
3168 static int __initdata irqval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY };
3169
3170 static int __init parport_parse_param(const char *s, int *val,
3171 int automatic, int none, int nofifo)
3172 {
3173 if (!s)
3174 return 0;
3175 if (!strncmp(s, "auto", 4))
3176 *val = automatic;
3177 else if (!strncmp(s, "none", 4))
3178 *val = none;
3179 else if (nofifo && !strncmp(s, "nofifo", 4))
3180 *val = nofifo;
3181 else {
3182 char *ep;
3183 unsigned long r = simple_strtoul(s, &ep, 0);
3184 if (ep != s)
3185 *val = r;
3186 else {
3187 printk(KERN_ERR "parport: bad specifier `%s'\n", s);
3188 return -1;
3189 }
3190 }
3191 return 0;
3192 }
3193
3194 static int __init parport_parse_irq(const char *irqstr, int *val)
3195 {
3196 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3197 PARPORT_IRQ_NONE, 0);
3198 }
3199
3200 static int __init parport_parse_dma(const char *dmastr, int *val)
3201 {
3202 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3203 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3204 }
3205
3206 #ifdef CONFIG_PCI
3207 static int __init parport_init_mode_setup(char *str)
3208 {
3209 printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n", str);
3210
3211 if (!strcmp (str, "spp"))
3212 parport_init_mode=1;
3213 if (!strcmp (str, "ps2"))
3214 parport_init_mode=2;
3215 if (!strcmp (str, "epp"))
3216 parport_init_mode=3;
3217 if (!strcmp (str, "ecp"))
3218 parport_init_mode=4;
3219 if (!strcmp (str, "ecpepp"))
3220 parport_init_mode=5;
3221 return 1;
3222 }
3223 #endif
3224
3225 #ifdef MODULE
3226 static const char *irq[PARPORT_PC_MAX_PORTS];
3227 static const char *dma[PARPORT_PC_MAX_PORTS];
3228
3229 MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3230 module_param_array(io, int, NULL, 0);
3231 MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3232 module_param_array(io_hi, int, NULL, 0);
3233 MODULE_PARM_DESC(irq, "IRQ line");
3234 module_param_array(irq, charp, NULL, 0);
3235 MODULE_PARM_DESC(dma, "DMA channel");
3236 module_param_array(dma, charp, NULL, 0);
3237 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3238 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3239 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3240 module_param(verbose_probing, int, 0644);
3241 #endif
3242 #ifdef CONFIG_PCI
3243 static char *init_mode;
3244 MODULE_PARM_DESC(init_mode, "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3245 module_param(init_mode, charp, 0);
3246 #endif
3247
3248 static int __init parse_parport_params(void)
3249 {
3250 unsigned int i;
3251 int val;
3252
3253 #ifdef CONFIG_PCI
3254 if (init_mode)
3255 parport_init_mode_setup(init_mode);
3256 #endif
3257
3258 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3259 if (parport_parse_irq(irq[i], &val))
3260 return 1;
3261 irqval[i] = val;
3262 if (parport_parse_dma(dma[i], &val))
3263 return 1;
3264 dmaval[i] = val;
3265 }
3266 if (!io[0]) {
3267 /* The user can make us use any IRQs or DMAs we find. */
3268 if (irq[0] && !parport_parse_irq(irq[0], &val))
3269 switch (val) {
3270 case PARPORT_IRQ_NONE:
3271 case PARPORT_IRQ_AUTO:
3272 irqval[0] = val;
3273 break;
3274 default:
3275 printk (KERN_WARNING
3276 "parport_pc: irq specified "
3277 "without base address. Use 'io=' "
3278 "to specify one\n");
3279 }
3280
3281 if (dma[0] && !parport_parse_dma(dma[0], &val))
3282 switch (val) {
3283 case PARPORT_DMA_NONE:
3284 case PARPORT_DMA_AUTO:
3285 dmaval[0] = val;
3286 break;
3287 default:
3288 printk (KERN_WARNING
3289 "parport_pc: dma specified "
3290 "without base address. Use 'io=' "
3291 "to specify one\n");
3292 }
3293 }
3294 return 0;
3295 }
3296
3297 #else
3298
3299 static int parport_setup_ptr __initdata = 0;
3300
3301 /*
3302 * Acceptable parameters:
3303 *
3304 * parport=0
3305 * parport=auto
3306 * parport=0xBASE[,IRQ[,DMA]]
3307 *
3308 * IRQ/DMA may be numeric or 'auto' or 'none'
3309 */
3310 static int __init parport_setup (char *str)
3311 {
3312 char *endptr;
3313 char *sep;
3314 int val;
3315
3316 if (!str || !*str || (*str == '0' && !*(str+1))) {
3317 /* Disable parport if "parport=0" in cmdline */
3318 io[0] = PARPORT_DISABLE;
3319 return 1;
3320 }
3321
3322 if (!strncmp (str, "auto", 4)) {
3323 irqval[0] = PARPORT_IRQ_AUTO;
3324 dmaval[0] = PARPORT_DMA_AUTO;
3325 return 1;
3326 }
3327
3328 val = simple_strtoul (str, &endptr, 0);
3329 if (endptr == str) {
3330 printk (KERN_WARNING "parport=%s not understood\n", str);
3331 return 1;
3332 }
3333
3334 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3335 printk(KERN_ERR "parport=%s ignored, too many ports\n", str);
3336 return 1;
3337 }
3338
3339 io[parport_setup_ptr] = val;
3340 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3341 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3342
3343 sep = strchr(str, ',');
3344 if (sep++) {
3345 if (parport_parse_irq(sep, &val))
3346 return 1;
3347 irqval[parport_setup_ptr] = val;
3348 sep = strchr(sep, ',');
3349 if (sep++) {
3350 if (parport_parse_dma(sep, &val))
3351 return 1;
3352 dmaval[parport_setup_ptr] = val;
3353 }
3354 }
3355 parport_setup_ptr++;
3356 return 1;
3357 }
3358
3359 static int __init parse_parport_params(void)
3360 {
3361 return io[0] == PARPORT_DISABLE;
3362 }
3363
3364 __setup ("parport=", parport_setup);
3365
3366 /*
3367 * Acceptable parameters:
3368 *
3369 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
3370 */
3371 #ifdef CONFIG_PCI
3372 __setup("parport_init_mode=",parport_init_mode_setup);
3373 #endif
3374 #endif
3375
3376 /* "Parser" ends here */
3377
3378 static int __init parport_pc_init(void)
3379 {
3380 int count = 0;
3381
3382 if (parse_parport_params())
3383 return -EINVAL;
3384
3385 if (io[0]) {
3386 int i;
3387 /* Only probe the ports we were given. */
3388 user_specified = 1;
3389 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3390 if (!io[i])
3391 break;
3392 if ((io_hi[i]) == PARPORT_IOHI_AUTO)
3393 io_hi[i] = 0x400 + io[i];
3394 if (parport_pc_probe_port(io[i], io_hi[i],
3395 irqval[i], dmaval[i], NULL))
3396 count++;
3397 }
3398 } else
3399 count += parport_pc_find_ports (irqval[0], dmaval[0]);
3400
3401 return 0;
3402 }
3403
3404 static void __exit parport_pc_exit(void)
3405 {
3406 if (pci_registered_parport)
3407 pci_unregister_driver (&parport_pc_pci_driver);
3408 if (pnp_registered_parport)
3409 pnp_unregister_driver (&parport_pc_pnp_driver);
3410
3411 spin_lock(&ports_lock);
3412 while (!list_empty(&ports_list)) {
3413 struct parport_pc_private *priv;
3414 struct parport *port;
3415 priv = list_entry(ports_list.next,
3416 struct parport_pc_private, list);
3417 port = priv->port;
3418 spin_unlock(&ports_lock);
3419 parport_pc_unregister_port(port);
3420 spin_lock(&ports_lock);
3421 }
3422 spin_unlock(&ports_lock);
3423 }
3424
3425 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3426 MODULE_DESCRIPTION("PC-style parallel port driver");
3427 MODULE_LICENSE("GPL");
3428 module_init(parport_pc_init)
3429 module_exit(parport_pc_exit)
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