include/asm-m32r/m32r.h

   1 #ifndef _ASM_M32R_M32R_H_
   2 #define _ASM_M32R_M32R_H_
   3
   4 /*
   5  * Renesas M32R processor
   6  *
   7  * Copyright (C) 2003, 2004  Renesas Technology Corp.
   8  */
   9
  10 #include <linux/config.h>
  11
  12 /* Chip type */
  13 #if defined(CONFIG_CHIP_XNUX_MP) || defined(CONFIG_CHIP_XNUX2_MP)
  14 #include <asm/m32r_mp_fpga.h>
  15 #elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
  16         || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
  17         || defined(CONFIG_CHIP_OPSP)
  18 #include <asm/m32102.h>
  19 #include <asm/m32102peri.h>
  20 #endif
  21
  22 /* Platform type */
  23 #if defined(CONFIG_PLAT_M32700UT)
  24 #include <asm/m32700ut/m32700ut_pld.h>
  25 #include <asm/m32700ut/m32700ut_lan.h>
  26 #include <asm/m32700ut/m32700ut_lcd.h>
  27 #endif  /* CONFIG_PLAT_M32700UT */
  28
  29 #if defined(CONFIG_PLAT_OPSPUT)
  30 #include <asm/opsput/opsput_pld.h>
  31 #include <asm/opsput/opsput_lan.h>
  32 #include <asm/opsput/opsput_lcd.h>
  33 #endif  /* CONFIG_PLAT_OPSPUT */
  34
  35 #if defined(CONFIG_PLAT_MAPPI2)
  36 #include <asm/mappi2/mappi2_pld.h>
  37 #endif  /* CONFIG_PLAT_MAPPI2 */
  38
  39 #if defined(CONFIG_PLAT_USRV)
  40 #include <asm/m32700ut/m32700ut_pld.h>
  41 #endif
  42
  43 /*
  44  * M32R Register
  45  */
  46
  47 /*
  48  * MMU Register
  49  */
  50
  51 #define MMU_REG_BASE    (0xffff0000)
  52 #define ITLB_BASE       (0xfe000000)
  53 #define DTLB_BASE       (0xfe000800)
  54
  55 #define NR_TLB_ENTRIES  CONFIG_TLB_ENTRIES
  56
  57 #define MATM    MMU_REG_BASE            /* MMU Address Translation Mode
  58                                            Register */
  59 #define MPSZ    (0x04 + MMU_REG_BASE)   /* MMU Page Size Designation Register */
  60 #define MASID   (0x08 + MMU_REG_BASE)   /* MMU Address Space ID Register */
  61 #define MESTS   (0x0c + MMU_REG_BASE)   /* MMU Exception Status Register */
  62 #define MDEVA   (0x10 + MMU_REG_BASE)   /* MMU Operand Exception Virtual
  63                                            Address Register */
  64 #define MDEVP   (0x14 + MMU_REG_BASE)   /* MMU Operand Exception Virtual Page
  65                                            Number Register */
  66 #define MPTB    (0x18 + MMU_REG_BASE)   /* MMU Page Table Base Register */
  67 #define MSVA    (0x20 + MMU_REG_BASE)   /* MMU Search Virtual Address
  68                                            Register */
  69 #define MTOP    (0x24 + MMU_REG_BASE)   /* MMU TLB Operation Register */
  70 #define MIDXI   (0x28 + MMU_REG_BASE)   /* MMU Index Register for
  71                                            Instruciton */
  72 #define MIDXD   (0x2c + MMU_REG_BASE)   /* MMU Index Register for Operand */
  73
  74 #define MATM_offset     (MATM - MMU_REG_BASE)
  75 #define MPSZ_offset     (MPSZ - MMU_REG_BASE)
  76 #define MASID_offset    (MASID - MMU_REG_BASE)
  77 #define MESTS_offset    (MESTS - MMU_REG_BASE)
  78 #define MDEVA_offset    (MDEVA - MMU_REG_BASE)
  79 #define MDEVP_offset    (MDEVP - MMU_REG_BASE)
  80 #define MPTB_offset     (MPTB - MMU_REG_BASE)
  81 #define MSVA_offset     (MSVA - MMU_REG_BASE)
  82 #define MTOP_offset     (MTOP - MMU_REG_BASE)
  83 #define MIDXI_offset    (MIDXI - MMU_REG_BASE)
  84 #define MIDXD_offset    (MIDXD - MMU_REG_BASE)
  85
  86 #define MESTS_IT        (1 << 0)        /* Instruction TLB miss */
  87 #define MESTS_IA        (1 << 1)        /* Instruction Access Exception */
  88 #define MESTS_DT        (1 << 4)        /* Operand TLB miss */
  89 #define MESTS_DA        (1 << 5)        /* Operand Access Exception */
  90 #define MESTS_DRW       (1 << 6)        /* Operand Write Exception Flag */
  91
  92 /*
  93  * PSW (Processor Status Word)
  94  */
  95
  96 /* PSW bit */
  97 #define M32R_PSW_BIT_SM   (7)    /* Stack Mode */
  98 #define M32R_PSW_BIT_IE   (6)    /* Interrupt Enable */
  99 #define M32R_PSW_BIT_PM   (3)    /* Processor Mode [0:Supervisor,1:User] */
 100 #define M32R_PSW_BIT_C    (0)    /* Condition */
 101 #define M32R_PSW_BIT_BSM  (7+8)  /* Backup Stack Mode */
 102 #define M32R_PSW_BIT_BIE  (6+8)  /* Backup Interrupt Enable */
 103 #define M32R_PSW_BIT_BPM  (3+8)  /* Backup Processor Mode */
 104 #define M32R_PSW_BIT_BC   (0+8)  /* Backup Condition */
 105
 106 /* PSW bit map */
 107 #define M32R_PSW_SM   (1UL<< M32R_PSW_BIT_SM)   /* Stack Mode */
 108 #define M32R_PSW_IE   (1UL<< M32R_PSW_BIT_IE)   /* Interrupt Enable */
 109 #define M32R_PSW_PM   (1UL<< M32R_PSW_BIT_PM)   /* Processor Mode */
 110 #define M32R_PSW_C    (1UL<< M32R_PSW_BIT_C)    /* Condition */
 111 #define M32R_PSW_BSM  (1UL<< M32R_PSW_BIT_BSM)  /* Backup Stack Mode */
 112 #define M32R_PSW_BIE  (1UL<< M32R_PSW_BIT_BIE)  /* Backup Interrupt Enable */
 113 #define M32R_PSW_BPM  (1UL<< M32R_PSW_BIT_BPM)  /* Backup Processor Mode */
 114 #define M32R_PSW_BC   (1UL<< M32R_PSW_BIT_BC)   /* Backup Condition */
 115
 116 /*
 117  * Direct address to SFR
 118  */
 119
 120 #include <asm/page.h>
 121 #ifdef CONFIG_MMU
 122 #define NONCACHE_OFFSET  __PAGE_OFFSET+0x20000000
 123 #else
 124 #define NONCACHE_OFFSET  __PAGE_OFFSET
 125 #endif /* CONFIG_MMU */
 126
 127 #define M32R_ICU_ISTS_ADDR  M32R_ICU_ISTS_PORTL+NONCACHE_OFFSET
 128 #define M32R_ICU_IPICR_ADDR  M32R_ICU_IPICR0_PORTL+NONCACHE_OFFSET
 129 #define M32R_ICU_IMASK_ADDR  M32R_ICU_IMASK_PORTL+NONCACHE_OFFSET
 130 #define M32R_FPGA_CPU_NAME_ADDR  M32R_FPGA_CPU_NAME0_PORTL+NONCACHE_OFFSET
 131 #define M32R_FPGA_MODEL_ID_ADDR  M32R_FPGA_MODEL_ID0_PORTL+NONCACHE_OFFSET
 132 #define M32R_FPGA_VERSION_ADDR   M32R_FPGA_VERSION0_PORTL+NONCACHE_OFFSET
 133
 134 #endif /* _ASM_M32R_M32R_H_ */