6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/types.h>
13 #include <linux/slab.h>
14 #include <linux/string.h>
15 #include <linux/dma-mapping.h>
17 #include <asm/machdep.h>
18 #include <asm/scatterlist.h>
22 #include <asm-generic/pci-dma-compat.h>
24 #define PCIBIOS_MIN_IO 0x1000
25 #define PCIBIOS_MIN_MEM 0x10000000
29 #ifdef CONFIG_PPC_ISERIES
30 #define pcibios_scan_all_fns(a, b) 0
32 extern int pcibios_scan_all_fns(struct pci_bus
*bus
, int devfn
);
35 static inline void pcibios_set_master(struct pci_dev
*dev
)
37 /* No special bus mastering setup handling */
40 static inline void pcibios_penalize_isa_irq(int irq
)
42 /* We don't do dynamic PCI IRQ allocation */
45 #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
46 static inline int pci_get_legacy_ide_irq(struct pci_dev
*dev
, int channel
)
48 if (ppc_md
.pci_get_legacy_ide_irq
)
49 return ppc_md
.pci_get_legacy_ide_irq(dev
, channel
);
50 return channel
? 15 : 14;
53 #define HAVE_ARCH_PCI_MWI 1
54 static inline int pcibios_prep_mwi(struct pci_dev
*dev
)
57 * We would like to avoid touching the cacheline size or MWI bit
58 * but we cant do that with the current pcibios_prep_mwi
59 * interface. pSeries firmware sets the cacheline size (which is not
60 * the cpu cacheline size in all cases) and hardware treats MWI
61 * the same as memory write. So we dont touch the cacheline size
62 * here and allow the generic code to set the MWI bit.
67 extern unsigned int pcibios_assign_all_busses(void);
69 extern struct dma_mapping_ops pci_dma_ops
;
71 /* For DAC DMA, we currently don't support it by default, but
72 * we let the platform override this
74 static inline int pci_dac_dma_supported(struct pci_dev
*hwdev
,u64 mask
)
76 if (pci_dma_ops
.dac_dma_supported
)
77 return pci_dma_ops
.dac_dma_supported(&hwdev
->dev
, mask
);
81 extern int pci_domain_nr(struct pci_bus
*bus
);
83 /* Decide whether to display the domain number in /proc */
84 extern int pci_proc_domain(struct pci_bus
*bus
);
86 struct vm_area_struct
;
87 /* Map a range of PCI memory or I/O space for a device into user space */
88 int pci_mmap_page_range(struct pci_dev
*pdev
, struct vm_area_struct
*vma
,
89 enum pci_mmap_state mmap_state
, int write_combine
);
91 /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
92 #define HAVE_PCI_MMAP 1
94 /* pci_unmap_{single,page} is not a nop, thus... */
95 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
97 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
99 #define pci_unmap_addr(PTR, ADDR_NAME) \
101 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
102 (((PTR)->ADDR_NAME) = (VAL))
103 #define pci_unmap_len(PTR, LEN_NAME) \
105 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
106 (((PTR)->LEN_NAME) = (VAL))
108 /* The PCI address space does equal the physical memory
109 * address space. The networking and block device layers use
110 * this boolean for bounce buffer decisions.
112 #define PCI_DMA_BUS_IS_PHYS (0)
115 pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
116 struct resource
*res
);
119 unmap_bus_range(struct pci_bus
*bus
);
122 remap_bus_range(struct pci_bus
*bus
);
125 pcibios_fixup_device_resources(struct pci_dev
*dev
, struct pci_bus
*bus
);
127 extern struct pci_controller
*init_phb_dynamic(struct device_node
*dn
);
129 extern int pci_read_irq_line(struct pci_dev
*dev
);
131 extern void pcibios_add_platform_entries(struct pci_dev
*dev
);
134 extern pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
135 unsigned long offset
,
140 #endif /* __KERNEL__ */
142 #endif /* __PPC64_PCI_H */