include/asm-x86_64/smp.h

   1 #ifndef __ASM_SMP_H
   2 #define __ASM_SMP_H
   3
   4 /*
   5  * We need the APIC definitions automatically as part of 'smp.h'
   6  */
   7 #ifndef __ASSEMBLY__
   8 #include <linux/config.h>
   9 #include <linux/threads.h>
  10 #include <linux/cpumask.h>
  11 #include <linux/bitops.h>
  12 extern int disable_apic;
  13 #endif
  14
  15 #ifdef CONFIG_X86_LOCAL_APIC
  16 #ifndef __ASSEMBLY__
  17 #include <asm/fixmap.h>
  18 #include <asm/mpspec.h>
  19 #ifdef CONFIG_X86_IO_APIC
  20 #include <asm/io_apic.h>
  21 #endif
  22 #include <asm/apic.h>
  23 #include <asm/thread_info.h>
  24 #endif
  25 #endif
  26
  27 #ifdef CONFIG_SMP
  28 #ifndef ASSEMBLY
  29
  30 #include <asm/pda.h>
  31
  32 struct pt_regs;
  33
  34 extern cpumask_t cpu_present_mask;
  35 extern cpumask_t cpu_possible_map;
  36 extern cpumask_t cpu_online_map;
  37 extern cpumask_t cpu_callout_map;
  38
  39 /*
  40  * Private routines/data
  41  */
  42
  43 extern void smp_alloc_memory(void);
  44 extern volatile unsigned long smp_invalidate_needed;
  45 extern int pic_mode;
  46 extern int smp_num_siblings;
  47 extern void smp_flush_tlb(void);
  48 extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs);
  49 extern void smp_send_reschedule(int cpu);
  50 extern void smp_invalidate_rcv(void);           /* Process an NMI */
  51 extern void zap_low_mappings(void);
  52 void smp_stop_cpu(void);
  53 extern cpumask_t cpu_sibling_map[NR_CPUS];
  54 extern cpumask_t cpu_core_map[NR_CPUS];
  55 extern u8 phys_proc_id[NR_CPUS];
  56 extern u8 cpu_core_id[NR_CPUS];
  57
  58 #define SMP_TRAMPOLINE_BASE 0x6000
  59
  60 /*
  61  * On x86 all CPUs are mapped 1:1 to the APIC space.
  62  * This simplifies scheduling and IPI sending and
  63  * compresses data structures.
  64  */
  65
  66 static inline int num_booting_cpus(void)
  67 {
  68         return cpus_weight(cpu_callout_map);
  69 }
  70
  71 #define __smp_processor_id() read_pda(cpunumber)
  72
  73 extern __inline int hard_smp_processor_id(void)
  74 {
  75         /* we don't want to mark this access volatile - bad code generation */
  76         return GET_APIC_ID(*(unsigned int *)(APIC_BASE+APIC_ID));
  77 }
  78
  79 extern int safe_smp_processor_id(void);
  80
  81 #endif /* !ASSEMBLY */
  82
  83 #define NO_PROC_ID              0xFF            /* No processor magic marker */
  84
  85 #endif
  86
  87 #ifndef ASSEMBLY
  88 /*
  89  * Some lowlevel functions might want to know about
  90  * the real APIC ID <-> CPU # mapping.
  91  */
  92 extern u8 x86_cpu_to_apicid[NR_CPUS];   /* physical ID */
  93 extern u8 x86_cpu_to_log_apicid[NR_CPUS];
  94 extern u8 bios_cpu_apicid[];
  95
  96 static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
  97 {
  98         return cpus_addr(cpumask)[0];
  99 }
 100
 101 static inline int cpu_present_to_apicid(int mps_cpu)
 102 {
 103         if (mps_cpu < NR_CPUS)
 104                 return (int)bios_cpu_apicid[mps_cpu];
 105         else
 106                 return BAD_APICID;
 107 }
 108
 109 #endif /* !ASSEMBLY */
 110
 111 #ifndef CONFIG_SMP
 112 #define stack_smp_processor_id() 0
 113 #define safe_smp_processor_id() 0
 114 #define cpu_logical_map(x) (x)
 115 #else
 116 #include <asm/thread_info.h>
 117 #define stack_smp_processor_id() \
 118 ({                                                              \
 119         struct thread_info *ti;                                 \
 120         __asm__("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK));      \
 121         ti->cpu;                                                \
 122 })
 123 #endif
 124
 125 #ifndef __ASSEMBLY__
 126 static __inline int logical_smp_processor_id(void)
 127 {
 128         /* we don't want to mark this access volatile - bad code generation */
 129         return GET_APIC_LOGICAL_ID(*(unsigned long *)(APIC_BASE+APIC_LDR));
 130 }
 131 #endif
 132
 133 #endif
 134