1 <!-- Root element for a DriverGen module description file -->
3 <!-- Module definition: Future version may have more than one module defined per xml-file -->
5 <!-- Block configuration, multiple entries allowed -->
6 <block id="0"> <!-- entry tag with unique block id -->
7 <base>1</base> <!-- base of block -->
8 <offset>0</offset> <!-- offset of block -->
10 <!-- Register configuration, multiple entries allowed -->
11 <register name="control"> <!-- entry tag with unique name -->
12 <block>0</block> <!-- block number of register -->
13 <offset>0x00000000</offset> <!-- offset of register -->
14 <depth>0</depth> <!-- depth of register: scalar (0) fifo (-1) or any number > 0 (array) -->
15 <mode>rw</mode> <!-- access mode rwce -->
16 <size>long</size> <!-- size: char (1) short (2) or long (4) -->
17 <timeloop>0</timeloop> <!-- time loop -->
18 <comment>test reg.</comment> <!-- comment -->
20 <!-- PCI board information (one entry only) -->
22 <vendor>0x00000000</vendor> <!-- vendor id -->
23 <device>0x00000000</device> <!-- device id -->
25 <!-- VME board information (one entry only) -->
27 <address base="0x03000000"> <!-- address space information table with base address (multiple entries) -->
28 <range>0x00001000</range> <!-- range -->
29 <increment>4</increment> <!-- increment -->
30 <am>ST</am> <!-- address modifier: SH, ST, SE or CR -->
31 <size>32</size> <!-- dataport size: short (16) or long (32) -->
33 <type>0</type> <!-- module type number -->
34 <channels>0</channels> <!-- module channels -->
35 <irq>0</irq> <!-- interrupt level -->
36 <irqVector>0</irqVector> <!-- interrupt vector -->
37 <irgVectorInc>0</irgVectorInc> <!-- interrupt vector increment -->