drm/modes: Fix drm_mode_vrefres() docs
[drm/drm-misc.git] / arch / x86 / events / intel / uncore_discovery.h
blob0e94aa7db8e7d7d34c9670637c246d6ecdf5d8e1
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /* Generic device ID of a discovery table device */
4 #define UNCORE_DISCOVERY_TABLE_DEVICE 0x09a7
5 /* Capability ID for a discovery table device */
6 #define UNCORE_EXT_CAP_ID_DISCOVERY 0x23
7 /* First DVSEC offset */
8 #define UNCORE_DISCOVERY_DVSEC_OFFSET 0x8
9 /* Mask of the supported discovery entry type */
10 #define UNCORE_DISCOVERY_DVSEC_ID_MASK 0xffff
11 /* PMON discovery entry type ID */
12 #define UNCORE_DISCOVERY_DVSEC_ID_PMON 0x1
13 /* Second DVSEC offset */
14 #define UNCORE_DISCOVERY_DVSEC2_OFFSET 0xc
15 /* Mask of the discovery table BAR offset */
16 #define UNCORE_DISCOVERY_DVSEC2_BIR_MASK 0x7
17 /* Discovery table BAR base offset */
18 #define UNCORE_DISCOVERY_BIR_BASE 0x10
19 /* Discovery table BAR step */
20 #define UNCORE_DISCOVERY_BIR_STEP 0x4
21 /* Global discovery table size */
22 #define UNCORE_DISCOVERY_GLOBAL_MAP_SIZE 0x20
24 #define UNCORE_DISCOVERY_PCI_DOMAIN_OFFSET 28
25 #define UNCORE_DISCOVERY_PCI_DOMAIN(data) \
26 ((data >> UNCORE_DISCOVERY_PCI_DOMAIN_OFFSET) & 0x7)
27 #define UNCORE_DISCOVERY_PCI_BUS_OFFSET 20
28 #define UNCORE_DISCOVERY_PCI_BUS(data) \
29 ((data >> UNCORE_DISCOVERY_PCI_BUS_OFFSET) & 0xff)
30 #define UNCORE_DISCOVERY_PCI_DEVFN_OFFSET 12
31 #define UNCORE_DISCOVERY_PCI_DEVFN(data) \
32 ((data >> UNCORE_DISCOVERY_PCI_DEVFN_OFFSET) & 0xff)
33 #define UNCORE_DISCOVERY_PCI_BOX_CTRL(data) (data & 0xfff)
36 #define uncore_discovery_invalid_unit(unit) \
37 (!unit.table1 || !unit.ctl || \
38 unit.table1 == -1ULL || unit.ctl == -1ULL || \
39 unit.table3 == -1ULL)
41 #define GENERIC_PMON_CTL_EV_SEL_MASK 0x000000ff
42 #define GENERIC_PMON_CTL_UMASK_MASK 0x0000ff00
43 #define GENERIC_PMON_CTL_EDGE_DET (1 << 18)
44 #define GENERIC_PMON_CTL_INVERT (1 << 23)
45 #define GENERIC_PMON_CTL_TRESH_MASK 0xff000000
46 #define GENERIC_PMON_RAW_EVENT_MASK (GENERIC_PMON_CTL_EV_SEL_MASK | \
47 GENERIC_PMON_CTL_UMASK_MASK | \
48 GENERIC_PMON_CTL_EDGE_DET | \
49 GENERIC_PMON_CTL_INVERT | \
50 GENERIC_PMON_CTL_TRESH_MASK)
52 #define GENERIC_PMON_BOX_CTL_FRZ (1 << 0)
53 #define GENERIC_PMON_BOX_CTL_RST_CTRL (1 << 8)
54 #define GENERIC_PMON_BOX_CTL_RST_CTRS (1 << 9)
55 #define GENERIC_PMON_BOX_CTL_INT (GENERIC_PMON_BOX_CTL_RST_CTRL | \
56 GENERIC_PMON_BOX_CTL_RST_CTRS)
58 enum uncore_access_type {
59 UNCORE_ACCESS_MSR = 0,
60 UNCORE_ACCESS_MMIO,
61 UNCORE_ACCESS_PCI,
63 UNCORE_ACCESS_MAX,
66 struct uncore_global_discovery {
67 union {
68 u64 table1;
69 struct {
70 u64 type : 8,
71 stride : 8,
72 max_units : 10,
73 __reserved_1 : 36,
74 access_type : 2;
78 u64 ctl; /* Global Control Address */
80 union {
81 u64 table3;
82 struct {
83 u64 status_offset : 8,
84 num_status : 16,
85 __reserved_2 : 40;
90 struct uncore_unit_discovery {
91 union {
92 u64 table1;
93 struct {
94 u64 num_regs : 8,
95 ctl_offset : 8,
96 bit_width : 8,
97 ctr_offset : 8,
98 status_offset : 8,
99 __reserved_1 : 22,
100 access_type : 2;
104 u64 ctl; /* Unit Control Address */
106 union {
107 u64 table3;
108 struct {
109 u64 box_type : 16,
110 box_id : 16,
111 __reserved_2 : 32;
116 struct intel_uncore_discovery_unit {
117 struct rb_node node;
118 unsigned int pmu_idx; /* The idx of the corresponding PMU */
119 unsigned int id; /* Unit ID */
120 unsigned int die; /* Die ID */
121 u64 addr; /* Unit Control Address */
124 struct intel_uncore_discovery_type {
125 struct rb_node node;
126 enum uncore_access_type access_type;
127 struct rb_root units; /* Unit ctrl addr for all units */
128 u16 type; /* Type ID of the uncore block */
129 u8 num_counters;
130 u8 counter_width;
131 u8 ctl_offset; /* Counter Control 0 offset */
132 u8 ctr_offset; /* Counter 0 offset */
133 u16 num_units; /* number of units */
136 bool intel_uncore_has_discovery_tables(int *ignore);
137 void intel_uncore_clear_discovery_tables(void);
138 void intel_uncore_generic_uncore_cpu_init(void);
139 int intel_uncore_generic_uncore_pci_init(void);
140 void intel_uncore_generic_uncore_mmio_init(void);
142 void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box);
143 void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box);
144 void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box);
146 void intel_generic_uncore_mmio_init_box(struct intel_uncore_box *box);
147 void intel_generic_uncore_mmio_disable_box(struct intel_uncore_box *box);
148 void intel_generic_uncore_mmio_enable_box(struct intel_uncore_box *box);
149 void intel_generic_uncore_mmio_disable_event(struct intel_uncore_box *box,
150 struct perf_event *event);
151 void intel_generic_uncore_mmio_enable_event(struct intel_uncore_box *box,
152 struct perf_event *event);
154 void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box);
155 void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box);
156 void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box);
157 void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box,
158 struct perf_event *event);
159 u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box,
160 struct perf_event *event);
162 struct intel_uncore_type **
163 intel_uncore_generic_init_uncores(enum uncore_access_type type_id, int num_extra);
165 int intel_uncore_find_discovery_unit_id(struct rb_root *units, int die,
166 unsigned int pmu_idx);
167 bool intel_generic_uncore_assign_hw_event(struct perf_event *event,
168 struct intel_uncore_box *box);
169 void uncore_find_add_unit(struct intel_uncore_discovery_unit *node,
170 struct rb_root *root, u16 *num_units);