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drm/panel: simple: add Multi-Inno Technology MI0700A2T-30
[drm/drm-misc.git] / drivers / iio / accel / msa311.c
blobe7fb860f32337ca9bc82547fbf2133b8a07da5ce
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MEMSensing digital 3-Axis accelerometer
4 *
5 * MSA311 is a tri-axial, low-g accelerometer with I2C digital output for
6 * sensitivity consumer applications. It has dynamic user-selectable full
7 * scales range of +-2g/+-4g/+-8g/+-16g and allows acceleration measurements
8 * with output data rates from 1Hz to 1000Hz.
9 *
10 * MSA311 is available in an ultra small (2mm x 2mm, height 0.95mm) LGA package
11 * and is guaranteed to operate over -40C to +85C.
12 *
13 * This driver supports following MSA311 features:
14 * - IIO interface
15 * - Different power modes: NORMAL, SUSPEND
16 * - ODR (Output Data Rate) selection
17 * - Scale selection
18 * - IIO triggered buffer
19 * - NEW_DATA interrupt + trigger
20 *
21 * Below features to be done:
22 * - Motion Events: ACTIVE, TAP, ORIENT, FREEFALL
23 * - Low Power mode
24 *
25 * Copyright (c) 2022, SberDevices. All Rights Reserved.
26 *
27 * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
28 */
29
30 #include <linux/i2c.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/module.h>
33 #include <linux/pm.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/regmap.h>
36 #include <linux/string_choices.h>
37 #include <linux/types.h>
38 #include <linux/units.h>
39
40 #include <linux/iio/buffer.h>
41 #include <linux/iio/iio.h>
42 #include <linux/iio/sysfs.h>
43 #include <linux/iio/trigger.h>
44 #include <linux/iio/trigger_consumer.h>
45 #include <linux/iio/triggered_buffer.h>
46
47 #define MSA311_SOFT_RESET_REG 0x00
48 #define MSA311_PARTID_REG 0x01
49 #define MSA311_ACC_X_REG 0x02
50 #define MSA311_ACC_Y_REG 0x04
51 #define MSA311_ACC_Z_REG 0x06
52 #define MSA311_MOTION_INT_REG 0x09
53 #define MSA311_DATA_INT_REG 0x0A
54 #define MSA311_TAP_ACTIVE_STS_REG 0x0B
55 #define MSA311_ORIENT_STS_REG 0x0C
56 #define MSA311_RANGE_REG 0x0F
57 #define MSA311_ODR_REG 0x10
58 #define MSA311_PWR_MODE_REG 0x11
59 #define MSA311_SWAP_POLARITY_REG 0x12
60 #define MSA311_INT_SET_0_REG 0x16
61 #define MSA311_INT_SET_1_REG 0x17
62 #define MSA311_INT_MAP_0_REG 0x19
63 #define MSA311_INT_MAP_1_REG 0x1A
64 #define MSA311_INT_CONFIG_REG 0x20
65 #define MSA311_INT_LATCH_REG 0x21
66 #define MSA311_FREEFALL_DUR_REG 0x22
67 #define MSA311_FREEFALL_TH_REG 0x23
68 #define MSA311_FREEFALL_HY_REG 0x24
69 #define MSA311_ACTIVE_DUR_REG 0x27
70 #define MSA311_ACTIVE_TH_REG 0x28
71 #define MSA311_TAP_DUR_REG 0x2A
72 #define MSA311_TAP_TH_REG 0x2B
73 #define MSA311_ORIENT_HY_REG 0x2C
74 #define MSA311_Z_BLOCK_REG 0x2D
75 #define MSA311_OFFSET_X_REG 0x38
76 #define MSA311_OFFSET_Y_REG 0x39
77 #define MSA311_OFFSET_Z_REG 0x3A
78
79 enum msa311_fields {
80 /* Soft_Reset */
81 F_SOFT_RESET_I2C, F_SOFT_RESET_SPI,
82 /* Motion_Interrupt */
83 F_ORIENT_INT, F_S_TAP_INT, F_D_TAP_INT, F_ACTIVE_INT, F_FREEFALL_INT,
84 /* Data_Interrupt */
85 F_NEW_DATA_INT,
86 /* Tap_Active_Status */
87 F_TAP_SIGN, F_TAP_FIRST_X, F_TAP_FIRST_Y, F_TAP_FIRST_Z, F_ACTV_SIGN,
88 F_ACTV_FIRST_X, F_ACTV_FIRST_Y, F_ACTV_FIRST_Z,
89 /* Orientation_Status */
90 F_ORIENT_Z, F_ORIENT_X_Y,
91 /* Range */
92 F_FS,
93 /* ODR */
94 F_X_AXIS_DIS, F_Y_AXIS_DIS, F_Z_AXIS_DIS, F_ODR,
95 /* Power Mode/Bandwidth */
96 F_PWR_MODE, F_LOW_POWER_BW,
97 /* Swap_Polarity */
98 F_X_POLARITY, F_Y_POLARITY, F_Z_POLARITY, F_X_Y_SWAP,
99 /* Int_Set_0 */
100 F_ORIENT_INT_EN, F_S_TAP_INT_EN, F_D_TAP_INT_EN, F_ACTIVE_INT_EN_Z,
101 F_ACTIVE_INT_EN_Y, F_ACTIVE_INT_EN_X,
102 /* Int_Set_1 */
103 F_NEW_DATA_INT_EN, F_FREEFALL_INT_EN,
104 /* Int_Map_0 */
105 F_INT1_ORIENT, F_INT1_S_TAP, F_INT1_D_TAP, F_INT1_ACTIVE,
106 F_INT1_FREEFALL,
107 /* Int_Map_1 */
108 F_INT1_NEW_DATA,
109 /* Int_Config */
110 F_INT1_OD, F_INT1_LVL,
111 /* Int_Latch */
112 F_RESET_INT, F_LATCH_INT,
113 /* Freefall_Hy */
114 F_FREEFALL_MODE, F_FREEFALL_HY,
115 /* Active_Dur */
116 F_ACTIVE_DUR,
117 /* Tap_Dur */
118 F_TAP_QUIET, F_TAP_SHOCK, F_TAP_DUR,
119 /* Tap_Th */
120 F_TAP_TH,
121 /* Orient_Hy */
122 F_ORIENT_HYST, F_ORIENT_BLOCKING, F_ORIENT_MODE,
123 /* Z_Block */
124 F_Z_BLOCKING,
125 /* End of register map */
126 F_MAX_FIELDS,
127 };
128
129 static const struct reg_field msa311_reg_fields[] = {
130 /* Soft_Reset */
131 [F_SOFT_RESET_I2C] = REG_FIELD(MSA311_SOFT_RESET_REG, 2, 2),
132 [F_SOFT_RESET_SPI] = REG_FIELD(MSA311_SOFT_RESET_REG, 5, 5),
133 /* Motion_Interrupt */
134 [F_ORIENT_INT] = REG_FIELD(MSA311_MOTION_INT_REG, 6, 6),
135 [F_S_TAP_INT] = REG_FIELD(MSA311_MOTION_INT_REG, 5, 5),
136 [F_D_TAP_INT] = REG_FIELD(MSA311_MOTION_INT_REG, 4, 4),
137 [F_ACTIVE_INT] = REG_FIELD(MSA311_MOTION_INT_REG, 2, 2),
138 [F_FREEFALL_INT] = REG_FIELD(MSA311_MOTION_INT_REG, 0, 0),
139 /* Data_Interrupt */
140 [F_NEW_DATA_INT] = REG_FIELD(MSA311_DATA_INT_REG, 0, 0),
141 /* Tap_Active_Status */
142 [F_TAP_SIGN] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 7, 7),
143 [F_TAP_FIRST_X] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 6, 6),
144 [F_TAP_FIRST_Y] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 5, 5),
145 [F_TAP_FIRST_Z] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 4, 4),
146 [F_ACTV_SIGN] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 3, 3),
147 [F_ACTV_FIRST_X] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 2, 2),
148 [F_ACTV_FIRST_Y] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 1, 1),
149 [F_ACTV_FIRST_Z] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 0, 0),
150 /* Orientation_Status */
151 [F_ORIENT_Z] = REG_FIELD(MSA311_ORIENT_STS_REG, 6, 6),
152 [F_ORIENT_X_Y] = REG_FIELD(MSA311_ORIENT_STS_REG, 4, 5),
153 /* Range */
154 [F_FS] = REG_FIELD(MSA311_RANGE_REG, 0, 1),
155 /* ODR */
156 [F_X_AXIS_DIS] = REG_FIELD(MSA311_ODR_REG, 7, 7),
157 [F_Y_AXIS_DIS] = REG_FIELD(MSA311_ODR_REG, 6, 6),
158 [F_Z_AXIS_DIS] = REG_FIELD(MSA311_ODR_REG, 5, 5),
159 [F_ODR] = REG_FIELD(MSA311_ODR_REG, 0, 3),
160 /* Power Mode/Bandwidth */
161 [F_PWR_MODE] = REG_FIELD(MSA311_PWR_MODE_REG, 6, 7),
162 [F_LOW_POWER_BW] = REG_FIELD(MSA311_PWR_MODE_REG, 1, 4),
163 /* Swap_Polarity */
164 [F_X_POLARITY] = REG_FIELD(MSA311_SWAP_POLARITY_REG, 3, 3),
165 [F_Y_POLARITY] = REG_FIELD(MSA311_SWAP_POLARITY_REG, 2, 2),
166 [F_Z_POLARITY] = REG_FIELD(MSA311_SWAP_POLARITY_REG, 1, 1),
167 [F_X_Y_SWAP] = REG_FIELD(MSA311_SWAP_POLARITY_REG, 0, 0),
168 /* Int_Set_0 */
169 [F_ORIENT_INT_EN] = REG_FIELD(MSA311_INT_SET_0_REG, 6, 6),
170 [F_S_TAP_INT_EN] = REG_FIELD(MSA311_INT_SET_0_REG, 5, 5),
171 [F_D_TAP_INT_EN] = REG_FIELD(MSA311_INT_SET_0_REG, 4, 4),
172 [F_ACTIVE_INT_EN_Z] = REG_FIELD(MSA311_INT_SET_0_REG, 2, 2),
173 [F_ACTIVE_INT_EN_Y] = REG_FIELD(MSA311_INT_SET_0_REG, 1, 1),
174 [F_ACTIVE_INT_EN_X] = REG_FIELD(MSA311_INT_SET_0_REG, 0, 0),
175 /* Int_Set_1 */
176 [F_NEW_DATA_INT_EN] = REG_FIELD(MSA311_INT_SET_1_REG, 4, 4),
177 [F_FREEFALL_INT_EN] = REG_FIELD(MSA311_INT_SET_1_REG, 3, 3),
178 /* Int_Map_0 */
179 [F_INT1_ORIENT] = REG_FIELD(MSA311_INT_MAP_0_REG, 6, 6),
180 [F_INT1_S_TAP] = REG_FIELD(MSA311_INT_MAP_0_REG, 5, 5),
181 [F_INT1_D_TAP] = REG_FIELD(MSA311_INT_MAP_0_REG, 4, 4),
182 [F_INT1_ACTIVE] = REG_FIELD(MSA311_INT_MAP_0_REG, 2, 2),
183 [F_INT1_FREEFALL] = REG_FIELD(MSA311_INT_MAP_0_REG, 0, 0),
184 /* Int_Map_1 */
185 [F_INT1_NEW_DATA] = REG_FIELD(MSA311_INT_MAP_1_REG, 0, 0),
186 /* Int_Config */
187 [F_INT1_OD] = REG_FIELD(MSA311_INT_CONFIG_REG, 1, 1),
188 [F_INT1_LVL] = REG_FIELD(MSA311_INT_CONFIG_REG, 0, 0),
189 /* Int_Latch */
190 [F_RESET_INT] = REG_FIELD(MSA311_INT_LATCH_REG, 7, 7),
191 [F_LATCH_INT] = REG_FIELD(MSA311_INT_LATCH_REG, 0, 3),
192 /* Freefall_Hy */
193 [F_FREEFALL_MODE] = REG_FIELD(MSA311_FREEFALL_HY_REG, 2, 2),
194 [F_FREEFALL_HY] = REG_FIELD(MSA311_FREEFALL_HY_REG, 0, 1),
195 /* Active_Dur */
196 [F_ACTIVE_DUR] = REG_FIELD(MSA311_ACTIVE_DUR_REG, 0, 1),
197 /* Tap_Dur */
198 [F_TAP_QUIET] = REG_FIELD(MSA311_TAP_DUR_REG, 7, 7),
199 [F_TAP_SHOCK] = REG_FIELD(MSA311_TAP_DUR_REG, 6, 6),
200 [F_TAP_DUR] = REG_FIELD(MSA311_TAP_DUR_REG, 0, 2),
201 /* Tap_Th */
202 [F_TAP_TH] = REG_FIELD(MSA311_TAP_TH_REG, 0, 4),
203 /* Orient_Hy */
204 [F_ORIENT_HYST] = REG_FIELD(MSA311_ORIENT_HY_REG, 4, 6),
205 [F_ORIENT_BLOCKING] = REG_FIELD(MSA311_ORIENT_HY_REG, 2, 3),
206 [F_ORIENT_MODE] = REG_FIELD(MSA311_ORIENT_HY_REG, 0, 1),
207 /* Z_Block */
208 [F_Z_BLOCKING] = REG_FIELD(MSA311_Z_BLOCK_REG, 0, 3),
209 };
210
211 #define MSA311_WHO_AM_I 0x13
212
213 /*
214 * Possible Full Scale ranges
215 *
216 * Axis data is 12-bit signed value, so
217 *
218 * fs0 = (2 + 2) * 9.81 / (2^11) = 0.009580
219 * fs1 = (4 + 4) * 9.81 / (2^11) = 0.019160
220 * fs2 = (8 + 8) * 9.81 / (2^11) = 0.038320
221 * fs3 = (16 + 16) * 9.81 / (2^11) = 0.076641
222 */
223 enum {
224 MSA311_FS_2G,
225 MSA311_FS_4G,
226 MSA311_FS_8G,
227 MSA311_FS_16G,
228 };
229
230 struct iio_decimal_fract {
231 int integral;
232 int microfract;
233 };
234
235 static const struct iio_decimal_fract msa311_fs_table[] = {
236 {0, 9580}, {0, 19160}, {0, 38320}, {0, 76641},
237 };
238
239 /* Possible Output Data Rate values */
240 enum {
241 MSA311_ODR_1_HZ,
242 MSA311_ODR_1_95_HZ,
243 MSA311_ODR_3_9_HZ,
244 MSA311_ODR_7_81_HZ,
245 MSA311_ODR_15_63_HZ,
246 MSA311_ODR_31_25_HZ,
247 MSA311_ODR_62_5_HZ,
248 MSA311_ODR_125_HZ,
249 MSA311_ODR_250_HZ,
250 MSA311_ODR_500_HZ,
251 MSA311_ODR_1000_HZ,
252 };
253
254 static const struct iio_decimal_fract msa311_odr_table[] = {
255 {1, 0}, {1, 950000}, {3, 900000}, {7, 810000}, {15, 630000},
256 {31, 250000}, {62, 500000}, {125, 0}, {250, 0}, {500, 0}, {1000, 0},
257 };
258
259 /* All supported power modes */
260 #define MSA311_PWR_MODE_NORMAL 0b00
261 #define MSA311_PWR_MODE_LOW 0b01
262 #define MSA311_PWR_MODE_UNKNOWN 0b10
263 #define MSA311_PWR_MODE_SUSPEND 0b11
264 static const char * const msa311_pwr_modes[] = {
265 [MSA311_PWR_MODE_NORMAL] = "normal",
266 [MSA311_PWR_MODE_LOW] = "low",
267 [MSA311_PWR_MODE_UNKNOWN] = "unknown",
268 [MSA311_PWR_MODE_SUSPEND] = "suspend",
269 };
270
271 /* Autosuspend delay */
272 #define MSA311_PWR_SLEEP_DELAY_MS 2000
273
274 /* Possible INT1 types and levels */
275 enum {
276 MSA311_INT1_OD_PUSH_PULL,
277 MSA311_INT1_OD_OPEN_DRAIN,
278 };
279
280 enum {
281 MSA311_INT1_LVL_LOW,
282 MSA311_INT1_LVL_HIGH,
283 };
284
285 /* Latch INT modes */
286 #define MSA311_LATCH_INT_NOT_LATCHED 0b0000
287 #define MSA311_LATCH_INT_250MS 0b0001
288 #define MSA311_LATCH_INT_500MS 0b0010
289 #define MSA311_LATCH_INT_1S 0b0011
290 #define MSA311_LATCH_INT_2S 0b0100
291 #define MSA311_LATCH_INT_4S 0b0101
292 #define MSA311_LATCH_INT_8S 0b0110
293 #define MSA311_LATCH_INT_1MS 0b1010
294 #define MSA311_LATCH_INT_2MS 0b1011
295 #define MSA311_LATCH_INT_25MS 0b1100
296 #define MSA311_LATCH_INT_50MS 0b1101
297 #define MSA311_LATCH_INT_100MS 0b1110
298 #define MSA311_LATCH_INT_LATCHED 0b0111
299
300 static const struct regmap_range msa311_readonly_registers[] = {
301 regmap_reg_range(MSA311_PARTID_REG, MSA311_ORIENT_STS_REG),
302 };
303
304 static const struct regmap_access_table msa311_writeable_table = {
305 .no_ranges = msa311_readonly_registers,
306 .n_no_ranges = ARRAY_SIZE(msa311_readonly_registers),
307 };
308
309 static const struct regmap_range msa311_writeonly_registers[] = {
310 regmap_reg_range(MSA311_SOFT_RESET_REG, MSA311_SOFT_RESET_REG),
311 };
312
313 static const struct regmap_access_table msa311_readable_table = {
314 .no_ranges = msa311_writeonly_registers,
315 .n_no_ranges = ARRAY_SIZE(msa311_writeonly_registers),
316 };
317
318 static const struct regmap_range msa311_volatile_registers[] = {
319 regmap_reg_range(MSA311_ACC_X_REG, MSA311_ORIENT_STS_REG),
320 };
321
322 static const struct regmap_access_table msa311_volatile_table = {
323 .yes_ranges = msa311_volatile_registers,
324 .n_yes_ranges = ARRAY_SIZE(msa311_volatile_registers),
325 };
326
327 static const struct regmap_config msa311_regmap_config = {
328 .name = "msa311",
329 .reg_bits = 8,
330 .val_bits = 8,
331 .max_register = MSA311_OFFSET_Z_REG,
332 .wr_table = &msa311_writeable_table,
333 .rd_table = &msa311_readable_table,
334 .volatile_table = &msa311_volatile_table,
335 .cache_type = REGCACHE_RBTREE,
336 };
337
338 #define MSA311_GENMASK(field) ({ \
339 typeof(&(msa311_reg_fields)[0]) _field; \
340 _field = &msa311_reg_fields[(field)]; \
341 GENMASK(_field->msb, _field->lsb); \
342 })
343
344 /**
345 * struct msa311_priv - MSA311 internal private state
346 * @regs: Underlying I2C bus adapter used to abstract slave
347 * register accesses
348 * @fields: Abstract objects for each registers fields access
349 * @dev: Device handler associated with appropriate bus client
350 * @lock: Protects msa311 device state between setup and data access routines
351 * (power transitions, samp_freq/scale tune, retrieving axes data, etc)
352 * @chip_name: Chip name in the format "msa311-%02x" % partid
353 * @new_data_trig: Optional NEW_DATA interrupt driven trigger used
354 * to notify external consumers a new sample is ready
355 */
356 struct msa311_priv {
357 struct regmap *regs;
358 struct regmap_field *fields[F_MAX_FIELDS];
359
360 struct device *dev;
361 struct mutex lock;
362 char *chip_name;
363
364 struct iio_trigger *new_data_trig;
365 };
366
367 enum msa311_si {
368 MSA311_SI_X,
369 MSA311_SI_Y,
370 MSA311_SI_Z,
371 MSA311_SI_TIMESTAMP,
372 };
373
374 #define MSA311_ACCEL_CHANNEL(axis) { \
375 .type = IIO_ACCEL, \
376 .modified = 1, \
377 .channel2 = IIO_MOD_##axis, \
378 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
379 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
380 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
381 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) | \
382 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
383 .scan_index = MSA311_SI_##axis, \
384 .scan_type = { \
385 .sign = 's', \
386 .realbits = 12, \
387 .storagebits = 16, \
388 .shift = 4, \
389 .endianness = IIO_LE, \
390 }, \
391 .datasheet_name = "ACC_"#axis, \
392 }
393
394 static const struct iio_chan_spec msa311_channels[] = {
395 MSA311_ACCEL_CHANNEL(X),
396 MSA311_ACCEL_CHANNEL(Y),
397 MSA311_ACCEL_CHANNEL(Z),
398 IIO_CHAN_SOFT_TIMESTAMP(MSA311_SI_TIMESTAMP),
399 };
400
401 /**
402 * msa311_get_odr() - Read Output Data Rate (ODR) value from MSA311 accel
403 * @msa311: MSA311 internal private state
404 * @odr: output ODR value
405 *
406 * This function should be called under msa311->lock.
407 *
408 * Return: 0 on success, -ERRNO in other failures
409 */
410 static int msa311_get_odr(struct msa311_priv *msa311, unsigned int *odr)
411 {
412 int err;
413
414 err = regmap_field_read(msa311->fields[F_ODR], odr);
415 if (err)
416 return err;
417
418 /*
419 * Filter the same 1000Hz ODR register values based on datasheet info.
420 * ODR can be equal to 1010-1111 for 1000Hz, but function returns 1010
421 * all the time.
422 */
423 if (*odr > MSA311_ODR_1000_HZ)
424 *odr = MSA311_ODR_1000_HZ;
425
426 return 0;
427 }
428
429 /**
430 * msa311_set_odr() - Setup Output Data Rate (ODR) value for MSA311 accel
431 * @msa311: MSA311 internal private state
432 * @odr: requested ODR value
433 *
434 * This function should be called under msa311->lock. Possible ODR values:
435 * - 1Hz (not available in normal mode)
436 * - 1.95Hz (not available in normal mode)
437 * - 3.9Hz
438 * - 7.81Hz
439 * - 15.63Hz
440 * - 31.25Hz
441 * - 62.5Hz
442 * - 125Hz
443 * - 250Hz
444 * - 500Hz
445 * - 1000Hz
446 *
447 * Return: 0 on success, -EINVAL for bad ODR value in the certain power mode,
448 * -ERRNO in other failures
449 */
450 static int msa311_set_odr(struct msa311_priv *msa311, unsigned int odr)
451 {
452 struct device *dev = msa311->dev;
453 unsigned int pwr_mode;
454 bool good_odr;
455 int err;
456
457 err = regmap_field_read(msa311->fields[F_PWR_MODE], &pwr_mode);
458 if (err)
459 return err;
460
461 /* Filter bad ODR values */
462 if (pwr_mode == MSA311_PWR_MODE_NORMAL)
463 good_odr = (odr > MSA311_ODR_1_95_HZ);
464 else
465 good_odr = false;
466
467 if (!good_odr) {
468 dev_err(dev,
469 "can't set odr %u.%06uHz, not available in %s mode\n",
470 msa311_odr_table[odr].integral,
471 msa311_odr_table[odr].microfract,
472 msa311_pwr_modes[pwr_mode]);
473 return -EINVAL;
474 }
475
476 return regmap_field_write(msa311->fields[F_ODR], odr);
477 }
478
479 /**
480 * msa311_wait_for_next_data() - Wait next accel data available after resume
481 * @msa311: MSA311 internal private state
482 *
483 * Return: 0 on success, -EINTR if msleep() was interrupted,
484 * -ERRNO in other failures
485 */
486 static int msa311_wait_for_next_data(struct msa311_priv *msa311)
487 {
488 static const unsigned int unintr_thresh_ms = 20;
489 struct device *dev = msa311->dev;
490 unsigned long freq_uhz;
491 unsigned long wait_ms;
492 unsigned int odr;
493 int err;
494
495 err = msa311_get_odr(msa311, &odr);
496 if (err) {
497 dev_err(dev, "can't get actual frequency (%pe)\n",
498 ERR_PTR(err));
499 return err;
500 }
501
502 /*
503 * After msa311 resuming is done, we need to wait for data
504 * to be refreshed by accel logic.
505 * A certain timeout is calculated based on the current ODR value.
506 * If requested timeout isn't so long (let's assume 20ms),
507 * we can wait for next data in uninterruptible sleep.
508 */
509 freq_uhz = msa311_odr_table[odr].integral * MICROHZ_PER_HZ +
510 msa311_odr_table[odr].microfract;
511 wait_ms = (MICROHZ_PER_HZ / freq_uhz) * MSEC_PER_SEC;
512
513 if (wait_ms < unintr_thresh_ms)
514 usleep_range(wait_ms * USEC_PER_MSEC,
515 unintr_thresh_ms * USEC_PER_MSEC);
516 else if (msleep_interruptible(wait_ms))
517 return -EINTR;
518
519 return 0;
520 }
521
522 /**
523 * msa311_set_pwr_mode() - Install certain MSA311 power mode
524 * @msa311: MSA311 internal private state
525 * @mode: Power mode can be equal to NORMAL or SUSPEND
526 *
527 * This function should be called under msa311->lock.
528 *
529 * Return: 0 on success, -ERRNO on failure
530 */
531 static int msa311_set_pwr_mode(struct msa311_priv *msa311, unsigned int mode)
532 {
533 struct device *dev = msa311->dev;
534 unsigned int prev_mode;
535 int err;
536
537 if (mode >= ARRAY_SIZE(msa311_pwr_modes))
538 return -EINVAL;
539
540 dev_dbg(dev, "transition to %s mode\n", msa311_pwr_modes[mode]);
541
542 err = regmap_field_read(msa311->fields[F_PWR_MODE], &prev_mode);
543 if (err)
544 return err;
545
546 err = regmap_field_write(msa311->fields[F_PWR_MODE], mode);
547 if (err)
548 return err;
549
550 /* Wait actual data if we wake up */
551 if (prev_mode == MSA311_PWR_MODE_SUSPEND &&
552 mode == MSA311_PWR_MODE_NORMAL)
553 return msa311_wait_for_next_data(msa311);
554
555 return 0;
556 }
557
558 /**
559 * msa311_get_axis() - Read MSA311 accel data for certain IIO channel axis spec
560 * @msa311: MSA311 internal private state
561 * @chan: IIO channel specification
562 * @axis: Output accel axis data for requested IIO channel spec
563 *
564 * This function should be called under msa311->lock.
565 *
566 * Return: 0 on success, -EINVAL for unknown IIO channel specification,
567 * -ERRNO in other failures
568 */
569 static int msa311_get_axis(struct msa311_priv *msa311,
570 const struct iio_chan_spec * const chan,
571 __le16 *axis)
572 {
573 struct device *dev = msa311->dev;
574 unsigned int axis_reg;
575
576 if (chan->scan_index < MSA311_SI_X || chan->scan_index > MSA311_SI_Z) {
577 dev_err(dev, "invalid scan_index value [%d]\n",
578 chan->scan_index);
579 return -EINVAL;
580 }
581
582 /* Axes data layout has 2 byte gap for each axis starting from X axis */
583 axis_reg = MSA311_ACC_X_REG + (chan->scan_index << 1);
584
585 return regmap_bulk_read(msa311->regs, axis_reg, axis, sizeof(*axis));
586 }
587
588 static int msa311_read_raw_data(struct iio_dev *indio_dev,
589 struct iio_chan_spec const *chan,
590 int *val, int *val2)
591 {
592 struct msa311_priv *msa311 = iio_priv(indio_dev);
593 struct device *dev = msa311->dev;
594 __le16 axis;
595 int err;
596
597 err = pm_runtime_resume_and_get(dev);
598 if (err)
599 return err;
600
601 err = iio_device_claim_direct_mode(indio_dev);
602 if (err)
603 return err;
604
605 mutex_lock(&msa311->lock);
606 err = msa311_get_axis(msa311, chan, &axis);
607 mutex_unlock(&msa311->lock);
608
609 iio_device_release_direct_mode(indio_dev);
610
611 pm_runtime_mark_last_busy(dev);
612 pm_runtime_put_autosuspend(dev);
613
614 if (err) {
615 dev_err(dev, "can't get axis %s (%pe)\n",
616 chan->datasheet_name, ERR_PTR(err));
617 return err;
618 }
619
620 /*
621 * Axis data format is:
622 * ACC_X = (ACC_X_MSB[7:0] << 4) | ACC_X_LSB[7:4]
623 */
624 *val = sign_extend32(le16_to_cpu(axis) >> chan->scan_type.shift,
625 chan->scan_type.realbits - 1);
626
627 return IIO_VAL_INT;
628 }
629
630 static int msa311_read_scale(struct iio_dev *indio_dev, int *val, int *val2)
631 {
632 struct msa311_priv *msa311 = iio_priv(indio_dev);
633 struct device *dev = msa311->dev;
634 unsigned int fs;
635 int err;
636
637 mutex_lock(&msa311->lock);
638 err = regmap_field_read(msa311->fields[F_FS], &fs);
639 mutex_unlock(&msa311->lock);
640 if (err) {
641 dev_err(dev, "can't get actual scale (%pe)\n", ERR_PTR(err));
642 return err;
643 }
644
645 *val = msa311_fs_table[fs].integral;
646 *val2 = msa311_fs_table[fs].microfract;
647
648 return IIO_VAL_INT_PLUS_MICRO;
649 }
650
651 static int msa311_read_samp_freq(struct iio_dev *indio_dev,
652 int *val, int *val2)
653 {
654 struct msa311_priv *msa311 = iio_priv(indio_dev);
655 struct device *dev = msa311->dev;
656 unsigned int odr;
657 int err;
658
659 mutex_lock(&msa311->lock);
660 err = msa311_get_odr(msa311, &odr);
661 mutex_unlock(&msa311->lock);
662 if (err) {
663 dev_err(dev, "can't get actual frequency (%pe)\n",
664 ERR_PTR(err));
665 return err;
666 }
667
668 *val = msa311_odr_table[odr].integral;
669 *val2 = msa311_odr_table[odr].microfract;
670
671 return IIO_VAL_INT_PLUS_MICRO;
672 }
673
674 static int msa311_read_raw(struct iio_dev *indio_dev,
675 struct iio_chan_spec const *chan,
676 int *val, int *val2, long mask)
677 {
678 switch (mask) {
679 case IIO_CHAN_INFO_RAW:
680 return msa311_read_raw_data(indio_dev, chan, val, val2);
681
682 case IIO_CHAN_INFO_SCALE:
683 return msa311_read_scale(indio_dev, val, val2);
684
685 case IIO_CHAN_INFO_SAMP_FREQ:
686 return msa311_read_samp_freq(indio_dev, val, val2);
687
688 default:
689 return -EINVAL;
690 }
691 }
692
693 static int msa311_read_avail(struct iio_dev *indio_dev,
694 struct iio_chan_spec const *chan,
695 const int **vals, int *type,
696 int *length, long mask)
697 {
698 switch (mask) {
699 case IIO_CHAN_INFO_SAMP_FREQ:
700 *vals = (int *)msa311_odr_table;
701 *type = IIO_VAL_INT_PLUS_MICRO;
702 /* ODR value has 2 ints (integer and fractional parts) */
703 *length = ARRAY_SIZE(msa311_odr_table) * 2;
704 return IIO_AVAIL_LIST;
705
706 case IIO_CHAN_INFO_SCALE:
707 *vals = (int *)msa311_fs_table;
708 *type = IIO_VAL_INT_PLUS_MICRO;
709 /* FS value has 2 ints (integer and fractional parts) */
710 *length = ARRAY_SIZE(msa311_fs_table) * 2;
711 return IIO_AVAIL_LIST;
712
713 default:
714 return -EINVAL;
715 }
716 }
717
718 static int msa311_write_scale(struct iio_dev *indio_dev, int val, int val2)
719 {
720 struct msa311_priv *msa311 = iio_priv(indio_dev);
721 struct device *dev = msa311->dev;
722 unsigned int fs;
723 int err;
724
725 /* We do not have fs >= 1, so skip such values */
726 if (val)
727 return 0;
728
729 err = pm_runtime_resume_and_get(dev);
730 if (err)
731 return err;
732
733 err = -EINVAL;
734 for (fs = 0; fs < ARRAY_SIZE(msa311_fs_table); fs++)
735 /* Do not check msa311_fs_table[fs].integral, it's always 0 */
736 if (val2 == msa311_fs_table[fs].microfract) {
737 mutex_lock(&msa311->lock);
738 err = regmap_field_write(msa311->fields[F_FS], fs);
739 mutex_unlock(&msa311->lock);
740 break;
741 }
742
743 pm_runtime_mark_last_busy(dev);
744 pm_runtime_put_autosuspend(dev);
745
746 if (err)
747 dev_err(dev, "can't update scale (%pe)\n", ERR_PTR(err));
748
749 return err;
750 }
751
752 static int msa311_write_samp_freq(struct iio_dev *indio_dev, int val, int val2)
753 {
754 struct msa311_priv *msa311 = iio_priv(indio_dev);
755 struct device *dev = msa311->dev;
756 unsigned int odr;
757 int err;
758
759 err = pm_runtime_resume_and_get(dev);
760 if (err)
761 return err;
762
763 /*
764 * Sampling frequency changing is prohibited when buffer mode is
765 * enabled, because sometimes MSA311 chip returns outliers during
766 * frequency values growing up in the read operation moment.
767 */
768 err = iio_device_claim_direct_mode(indio_dev);
769 if (err)
770 return err;
771
772 err = -EINVAL;
773 for (odr = 0; odr < ARRAY_SIZE(msa311_odr_table); odr++)
774 if (val == msa311_odr_table[odr].integral &&
775 val2 == msa311_odr_table[odr].microfract) {
776 mutex_lock(&msa311->lock);
777 err = msa311_set_odr(msa311, odr);
778 mutex_unlock(&msa311->lock);
779 break;
780 }
781
782 iio_device_release_direct_mode(indio_dev);
783
784 pm_runtime_mark_last_busy(dev);
785 pm_runtime_put_autosuspend(dev);
786
787 if (err)
788 dev_err(dev, "can't update frequency (%pe)\n", ERR_PTR(err));
789
790 return err;
791 }
792
793 static int msa311_write_raw(struct iio_dev *indio_dev,
794 struct iio_chan_spec const *chan,
795 int val, int val2, long mask)
796 {
797 switch (mask) {
798 case IIO_CHAN_INFO_SCALE:
799 return msa311_write_scale(indio_dev, val, val2);
800
801 case IIO_CHAN_INFO_SAMP_FREQ:
802 return msa311_write_samp_freq(indio_dev, val, val2);
803
804 default:
805 return -EINVAL;
806 }
807 }
808
809 static int msa311_debugfs_reg_access(struct iio_dev *indio_dev,
810 unsigned int reg, unsigned int writeval,
811 unsigned int *readval)
812 {
813 struct msa311_priv *msa311 = iio_priv(indio_dev);
814 struct device *dev = msa311->dev;
815 int err;
816
817 if (reg > regmap_get_max_register(msa311->regs))
818 return -EINVAL;
819
820 err = pm_runtime_resume_and_get(dev);
821 if (err)
822 return err;
823
824 mutex_lock(&msa311->lock);
825
826 if (readval)
827 err = regmap_read(msa311->regs, reg, readval);
828 else
829 err = regmap_write(msa311->regs, reg, writeval);
830
831 mutex_unlock(&msa311->lock);
832
833 pm_runtime_mark_last_busy(dev);
834 pm_runtime_put_autosuspend(dev);
835
836 if (err)
837 dev_err(dev, "can't %s register %u from debugfs (%pe)\n",
838 str_read_write(readval), reg, ERR_PTR(err));
839
840 return err;
841 }
842
843 static int msa311_buffer_preenable(struct iio_dev *indio_dev)
844 {
845 struct msa311_priv *msa311 = iio_priv(indio_dev);
846 struct device *dev = msa311->dev;
847
848 return pm_runtime_resume_and_get(dev);
849 }
850
851 static int msa311_buffer_postdisable(struct iio_dev *indio_dev)
852 {
853 struct msa311_priv *msa311 = iio_priv(indio_dev);
854 struct device *dev = msa311->dev;
855
856 pm_runtime_mark_last_busy(dev);
857 pm_runtime_put_autosuspend(dev);
858
859 return 0;
860 }
861
862 static int msa311_set_new_data_trig_state(struct iio_trigger *trig, bool state)
863 {
864 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
865 struct msa311_priv *msa311 = iio_priv(indio_dev);
866 struct device *dev = msa311->dev;
867 int err;
868
869 mutex_lock(&msa311->lock);
870 err = regmap_field_write(msa311->fields[F_NEW_DATA_INT_EN], state);
871 mutex_unlock(&msa311->lock);
872 if (err)
873 dev_err(dev,
874 "can't %s buffer due to new_data_int failure (%pe)\n",
875 str_enable_disable(state), ERR_PTR(err));
876
877 return err;
878 }
879
880 static int msa311_validate_device(struct iio_trigger *trig,
881 struct iio_dev *indio_dev)
882 {
883 return iio_trigger_get_drvdata(trig) == indio_dev ? 0 : -EINVAL;
884 }
885
886 static irqreturn_t msa311_buffer_thread(int irq, void *p)
887 {
888 struct iio_poll_func *pf = p;
889 struct msa311_priv *msa311 = iio_priv(pf->indio_dev);
890 struct iio_dev *indio_dev = pf->indio_dev;
891 const struct iio_chan_spec *chan;
892 struct device *dev = msa311->dev;
893 int bit, err, i = 0;
894 __le16 axis;
895 struct {
896 __le16 channels[MSA311_SI_Z + 1];
897 aligned_s64 ts;
898 } buf;
899
900 memset(&buf, 0, sizeof(buf));
901
902 mutex_lock(&msa311->lock);
903
904 iio_for_each_active_channel(indio_dev, bit) {
905 chan = &msa311_channels[bit];
906
907 err = msa311_get_axis(msa311, chan, &axis);
908 if (err) {
909 mutex_unlock(&msa311->lock);
910 dev_err(dev, "can't get axis %s (%pe)\n",
911 chan->datasheet_name, ERR_PTR(err));
912 goto notify_done;
913 }
914
915 buf.channels[i++] = axis;
916 }
917
918 mutex_unlock(&msa311->lock);
919
920 iio_push_to_buffers_with_timestamp(indio_dev, &buf,
921 iio_get_time_ns(indio_dev));
922
923 notify_done:
924 iio_trigger_notify_done(indio_dev->trig);
925
926 return IRQ_HANDLED;
927 }
928
929 static irqreturn_t msa311_irq_thread(int irq, void *p)
930 {
931 struct msa311_priv *msa311 = iio_priv(p);
932 unsigned int new_data_int_enabled;
933 struct device *dev = msa311->dev;
934 int err;
935
936 mutex_lock(&msa311->lock);
937
938 /*
939 * We do not check NEW_DATA int status, because based on the
940 * specification it's cleared automatically after a fixed time.
941 * So just check that is enabled by driver logic.
942 */
943 err = regmap_field_read(msa311->fields[F_NEW_DATA_INT_EN],
944 &new_data_int_enabled);
945
946 mutex_unlock(&msa311->lock);
947 if (err) {
948 dev_err(dev, "can't read new_data interrupt state (%pe)\n",
949 ERR_PTR(err));
950 return IRQ_NONE;
951 }
952
953 if (new_data_int_enabled)
954 iio_trigger_poll_nested(msa311->new_data_trig);
955
956 return IRQ_HANDLED;
957 }
958
959 static const struct iio_info msa311_info = {
960 .read_raw = msa311_read_raw,
961 .read_avail = msa311_read_avail,
962 .write_raw = msa311_write_raw,
963 .debugfs_reg_access = msa311_debugfs_reg_access,
964 };
965
966 static const struct iio_buffer_setup_ops msa311_buffer_setup_ops = {
967 .preenable = msa311_buffer_preenable,
968 .postdisable = msa311_buffer_postdisable,
969 };
970
971 static const struct iio_trigger_ops msa311_new_data_trig_ops = {
972 .set_trigger_state = msa311_set_new_data_trig_state,
973 .validate_device = msa311_validate_device,
974 };
975
976 static int msa311_check_partid(struct msa311_priv *msa311)
977 {
978 struct device *dev = msa311->dev;
979 unsigned int partid;
980 int err;
981
982 err = regmap_read(msa311->regs, MSA311_PARTID_REG, &partid);
983 if (err)
984 return dev_err_probe(dev, err, "failed to read partid\n");
985
986 if (partid != MSA311_WHO_AM_I)
987 dev_warn(dev, "invalid partid (%#x), expected (%#x)\n",
988 partid, MSA311_WHO_AM_I);
989
990 msa311->chip_name = devm_kasprintf(dev, GFP_KERNEL,
991 "msa311-%02x", partid);
992 if (!msa311->chip_name)
993 return dev_err_probe(dev, -ENOMEM, "can't alloc chip name\n");
994
995 return 0;
996 }
997
998 static int msa311_soft_reset(struct msa311_priv *msa311)
999 {
1000 struct device *dev = msa311->dev;
1001 int err;
1002
1003 err = regmap_write(msa311->regs, MSA311_SOFT_RESET_REG,
1004 MSA311_GENMASK(F_SOFT_RESET_I2C) |
1005 MSA311_GENMASK(F_SOFT_RESET_SPI));
1006 if (err)
1007 return dev_err_probe(dev, err, "can't soft reset all logic\n");
1008
1009 return 0;
1010 }
1011
1012 static int msa311_chip_init(struct msa311_priv *msa311)
1013 {
1014 struct device *dev = msa311->dev;
1015 const char zero_bulk[2] = { };
1016 int err;
1017
1018 err = regmap_write(msa311->regs, MSA311_RANGE_REG, MSA311_FS_16G);
1019 if (err)
1020 return dev_err_probe(dev, err, "failed to setup accel range\n");
1021
1022 /* Disable all interrupts by default */
1023 err = regmap_bulk_write(msa311->regs, MSA311_INT_SET_0_REG,
1024 zero_bulk, sizeof(zero_bulk));
1025 if (err)
1026 return dev_err_probe(dev, err,
1027 "can't disable set0/set1 interrupts\n");
1028
1029 /* Unmap all INT1 interrupts by default */
1030 err = regmap_bulk_write(msa311->regs, MSA311_INT_MAP_0_REG,
1031 zero_bulk, sizeof(zero_bulk));
1032 if (err)
1033 return dev_err_probe(dev, err,
1034 "failed to unmap map0/map1 interrupts\n");
1035
1036 /* Disable all axes by default */
1037 err = regmap_clear_bits(msa311->regs, MSA311_ODR_REG,
1038 MSA311_GENMASK(F_X_AXIS_DIS) |
1039 MSA311_GENMASK(F_Y_AXIS_DIS) |
1040 MSA311_GENMASK(F_Z_AXIS_DIS));
1041 if (err)
1042 return dev_err_probe(dev, err, "can't enable all axes\n");
1043
1044 err = msa311_set_odr(msa311, MSA311_ODR_125_HZ);
1045 if (err)
1046 return dev_err_probe(dev, err,
1047 "failed to set accel frequency\n");
1048
1049 return 0;
1050 }
1051
1052 static int msa311_setup_interrupts(struct msa311_priv *msa311)
1053 {
1054 struct device *dev = msa311->dev;
1055 struct i2c_client *i2c = to_i2c_client(dev);
1056 struct iio_dev *indio_dev = i2c_get_clientdata(i2c);
1057 struct iio_trigger *trig;
1058 int err;
1059
1060 /* Keep going without interrupts if no initialized I2C IRQ */
1061 if (i2c->irq <= 0)
1062 return 0;
1063
1064 err = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
1065 msa311_irq_thread, IRQF_ONESHOT,
1066 msa311->chip_name, indio_dev);
1067 if (err)
1068 return dev_err_probe(dev, err, "failed to request IRQ\n");
1069
1070 trig = devm_iio_trigger_alloc(dev, "%s-new-data", msa311->chip_name);
1071 if (!trig)
1072 return dev_err_probe(dev, -ENOMEM,
1073 "can't allocate newdata trigger\n");
1074
1075 msa311->new_data_trig = trig;
1076 msa311->new_data_trig->ops = &msa311_new_data_trig_ops;
1077 iio_trigger_set_drvdata(msa311->new_data_trig, indio_dev);
1078
1079 err = devm_iio_trigger_register(dev, msa311->new_data_trig);
1080 if (err)
1081 return dev_err_probe(dev, err,
1082 "can't register newdata trigger\n");
1083
1084 err = regmap_field_write(msa311->fields[F_INT1_OD],
1085 MSA311_INT1_OD_PUSH_PULL);
1086 if (err)
1087 return dev_err_probe(dev, err,
1088 "can't enable push-pull interrupt\n");
1089
1090 err = regmap_field_write(msa311->fields[F_INT1_LVL],
1091 MSA311_INT1_LVL_HIGH);
1092 if (err)
1093 return dev_err_probe(dev, err,
1094 "can't set active interrupt level\n");
1095
1096 err = regmap_field_write(msa311->fields[F_LATCH_INT],
1097 MSA311_LATCH_INT_LATCHED);
1098 if (err)
1099 return dev_err_probe(dev, err,
1100 "can't latch interrupt\n");
1101
1102 err = regmap_field_write(msa311->fields[F_RESET_INT], 1);
1103 if (err)
1104 return dev_err_probe(dev, err,
1105 "can't reset interrupt\n");
1106
1107 err = regmap_field_write(msa311->fields[F_INT1_NEW_DATA], 1);
1108 if (err)
1109 return dev_err_probe(dev, err,
1110 "can't map new data interrupt\n");
1111
1112 return 0;
1113 }
1114
1115 static int msa311_regmap_init(struct msa311_priv *msa311)
1116 {
1117 struct regmap_field **fields = msa311->fields;
1118 struct device *dev = msa311->dev;
1119 struct i2c_client *i2c = to_i2c_client(dev);
1120 struct regmap *regmap;
1121 int i;
1122
1123 regmap = devm_regmap_init_i2c(i2c, &msa311_regmap_config);
1124 if (IS_ERR(regmap))
1125 return dev_err_probe(dev, PTR_ERR(regmap),
1126 "failed to register i2c regmap\n");
1127
1128 msa311->regs = regmap;
1129
1130 for (i = 0; i < F_MAX_FIELDS; i++) {
1131 fields[i] = devm_regmap_field_alloc(dev,
1132 msa311->regs,
1133 msa311_reg_fields[i]);
1134 if (IS_ERR(msa311->fields[i]))
1135 return dev_err_probe(dev, PTR_ERR(msa311->fields[i]),
1136 "can't alloc field[%d]\n", i);
1137 }
1138
1139 return 0;
1140 }
1141
1142 static void msa311_powerdown(void *msa311)
1143 {
1144 msa311_set_pwr_mode(msa311, MSA311_PWR_MODE_SUSPEND);
1145 }
1146
1147 static int msa311_probe(struct i2c_client *i2c)
1148 {
1149 struct device *dev = &i2c->dev;
1150 struct msa311_priv *msa311;
1151 struct iio_dev *indio_dev;
1152 int err;
1153
1154 indio_dev = devm_iio_device_alloc(dev, sizeof(*msa311));
1155 if (!indio_dev)
1156 return dev_err_probe(dev, -ENOMEM,
1157 "IIO device allocation failed\n");
1158
1159 msa311 = iio_priv(indio_dev);
1160 msa311->dev = dev;
1161 i2c_set_clientdata(i2c, indio_dev);
1162
1163 err = msa311_regmap_init(msa311);
1164 if (err)
1165 return err;
1166
1167 mutex_init(&msa311->lock);
1168
1169 err = devm_regulator_get_enable(dev, "vdd");
1170 if (err)
1171 return dev_err_probe(dev, err, "can't get vdd supply\n");
1172
1173 err = msa311_check_partid(msa311);
1174 if (err)
1175 return err;
1176
1177 err = msa311_soft_reset(msa311);
1178 if (err)
1179 return err;
1180
1181 err = msa311_set_pwr_mode(msa311, MSA311_PWR_MODE_NORMAL);
1182 if (err)
1183 return dev_err_probe(dev, err, "failed to power on device\n");
1184
1185 /*
1186 * Register powerdown deferred callback which suspends the chip
1187 * after module unloaded.
1188 *
1189 * MSA311 should be in SUSPEND mode in the two cases:
1190 * 1) When driver is loaded, but we do not have any data or
1191 * configuration requests to it (we are solving it using
1192 * autosuspend feature).
1193 * 2) When driver is unloaded and device is not used (devm action is
1194 * used in this case).
1195 */
1196 err = devm_add_action_or_reset(dev, msa311_powerdown, msa311);
1197 if (err)
1198 return dev_err_probe(dev, err, "can't add powerdown action\n");
1199
1200 err = pm_runtime_set_active(dev);
1201 if (err)
1202 return err;
1203
1204 err = devm_pm_runtime_enable(dev);
1205 if (err)
1206 return err;
1207
1208 pm_runtime_get_noresume(dev);
1209 pm_runtime_set_autosuspend_delay(dev, MSA311_PWR_SLEEP_DELAY_MS);
1210 pm_runtime_use_autosuspend(dev);
1211
1212 err = msa311_chip_init(msa311);
1213 if (err)
1214 return err;
1215
1216 indio_dev->modes = INDIO_DIRECT_MODE;
1217 indio_dev->channels = msa311_channels;
1218 indio_dev->num_channels = ARRAY_SIZE(msa311_channels);
1219 indio_dev->name = msa311->chip_name;
1220 indio_dev->info = &msa311_info;
1221
1222 err = devm_iio_triggered_buffer_setup(dev, indio_dev,
1223 iio_pollfunc_store_time,
1224 msa311_buffer_thread,
1225 &msa311_buffer_setup_ops);
1226 if (err)
1227 return dev_err_probe(dev, err,
1228 "can't setup IIO trigger buffer\n");
1229
1230 err = msa311_setup_interrupts(msa311);
1231 if (err)
1232 return err;
1233
1234 pm_runtime_mark_last_busy(dev);
1235 pm_runtime_put_autosuspend(dev);
1236
1237 err = devm_iio_device_register(dev, indio_dev);
1238 if (err)
1239 return dev_err_probe(dev, err, "IIO device register failed\n");
1240
1241 return 0;
1242 }
1243
1244 static int msa311_runtime_suspend(struct device *dev)
1245 {
1246 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1247 struct msa311_priv *msa311 = iio_priv(indio_dev);
1248 int err;
1249
1250 mutex_lock(&msa311->lock);
1251 err = msa311_set_pwr_mode(msa311, MSA311_PWR_MODE_SUSPEND);
1252 mutex_unlock(&msa311->lock);
1253 if (err)
1254 dev_err(dev, "failed to power off device (%pe)\n",
1255 ERR_PTR(err));
1256
1257 return err;
1258 }
1259
1260 static int msa311_runtime_resume(struct device *dev)
1261 {
1262 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1263 struct msa311_priv *msa311 = iio_priv(indio_dev);
1264 int err;
1265
1266 mutex_lock(&msa311->lock);
1267 err = msa311_set_pwr_mode(msa311, MSA311_PWR_MODE_NORMAL);
1268 mutex_unlock(&msa311->lock);
1269 if (err)
1270 dev_err(dev, "failed to power on device (%pe)\n",
1271 ERR_PTR(err));
1272
1273 return err;
1274 }
1275
1276 static DEFINE_RUNTIME_DEV_PM_OPS(msa311_pm_ops, msa311_runtime_suspend,
1277 msa311_runtime_resume, NULL);
1278
1279 static const struct i2c_device_id msa311_i2c_id[] = {
1280 { .name = "msa311" },
1281 { }
1282 };
1283 MODULE_DEVICE_TABLE(i2c, msa311_i2c_id);
1284
1285 static const struct of_device_id msa311_of_match[] = {
1286 { .compatible = "memsensing,msa311" },
1287 { }
1288 };
1289 MODULE_DEVICE_TABLE(of, msa311_of_match);
1290
1291 static struct i2c_driver msa311_driver = {
1292 .driver = {
1293 .name = "msa311",
1294 .of_match_table = msa311_of_match,
1295 .pm = pm_ptr(&msa311_pm_ops),
1296 },
1297 .probe = msa311_probe,
1298 .id_table = msa311_i2c_id,
1299 };
1300 module_i2c_driver(msa311_driver);
1301
1302 MODULE_AUTHOR("Dmitry Rokosov <ddrokosov@sberdevices.ru>");
1303 MODULE_DESCRIPTION("MEMSensing MSA311 3-axis accelerometer driver");
1304 MODULE_LICENSE("GPL");
Kernel DRM miscellaneous fixes and cross-tree changes