drivers/iio/adc/xilinx-xadc-core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Xilinx XADC driver
   4  *
   5  * Copyright 2013-2014 Analog Devices Inc.
   6  *  Author: Lars-Peter Clausen <lars@metafoo.de>
   7  *
   8  * Documentation for the parts can be found at:
   9  *  - XADC hardmacro: Xilinx UG480
  10  *  - ZYNQ XADC interface: Xilinx UG585
  11  *  - AXI XADC interface: Xilinx PG019
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/device.h>
  16 #include <linux/err.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mod_devicetable.h>
  21 #include <linux/module.h>
  22 #include <linux/overflow.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/property.h>
  25 #include <linux/slab.h>
  26 #include <linux/sysfs.h>
  27
  28 #include <linux/iio/buffer.h>
  29 #include <linux/iio/events.h>
  30 #include <linux/iio/iio.h>
  31 #include <linux/iio/sysfs.h>
  32 #include <linux/iio/trigger.h>
  33 #include <linux/iio/trigger_consumer.h>
  34 #include <linux/iio/triggered_buffer.h>
  35
  36 #include "xilinx-xadc.h"
  37
  38 static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
  39
  40 /* ZYNQ register definitions */
  41 #define XADC_ZYNQ_REG_CFG       0x00
  42 #define XADC_ZYNQ_REG_INTSTS    0x04
  43 #define XADC_ZYNQ_REG_INTMSK    0x08
  44 #define XADC_ZYNQ_REG_STATUS    0x0c
  45 #define XADC_ZYNQ_REG_CFIFO     0x10
  46 #define XADC_ZYNQ_REG_DFIFO     0x14
  47 #define XADC_ZYNQ_REG_CTL               0x18
  48
  49 #define XADC_ZYNQ_CFG_ENABLE            BIT(31)
  50 #define XADC_ZYNQ_CFG_CFIFOTH_MASK      (0xf << 20)
  51 #define XADC_ZYNQ_CFG_CFIFOTH_OFFSET    20
  52 #define XADC_ZYNQ_CFG_DFIFOTH_MASK      (0xf << 16)
  53 #define XADC_ZYNQ_CFG_DFIFOTH_OFFSET    16
  54 #define XADC_ZYNQ_CFG_WEDGE             BIT(13)
  55 #define XADC_ZYNQ_CFG_REDGE             BIT(12)
  56 #define XADC_ZYNQ_CFG_TCKRATE_MASK      (0x3 << 8)
  57 #define XADC_ZYNQ_CFG_TCKRATE_DIV2      (0x0 << 8)
  58 #define XADC_ZYNQ_CFG_TCKRATE_DIV4      (0x1 << 8)
  59 #define XADC_ZYNQ_CFG_TCKRATE_DIV8      (0x2 << 8)
  60 #define XADC_ZYNQ_CFG_TCKRATE_DIV16     (0x3 << 8)
  61 #define XADC_ZYNQ_CFG_IGAP_MASK         0x1f
  62 #define XADC_ZYNQ_CFG_IGAP(x)           (x)
  63
  64 #define XADC_ZYNQ_INT_CFIFO_LTH         BIT(9)
  65 #define XADC_ZYNQ_INT_DFIFO_GTH         BIT(8)
  66 #define XADC_ZYNQ_INT_ALARM_MASK        0xff
  67 #define XADC_ZYNQ_INT_ALARM_OFFSET      0
  68
  69 #define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK (0xf << 16)
  70 #define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET       16
  71 #define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK (0xf << 12)
  72 #define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET       12
  73 #define XADC_ZYNQ_STATUS_CFIFOF         BIT(11)
  74 #define XADC_ZYNQ_STATUS_CFIFOE         BIT(10)
  75 #define XADC_ZYNQ_STATUS_DFIFOF         BIT(9)
  76 #define XADC_ZYNQ_STATUS_DFIFOE         BIT(8)
  77 #define XADC_ZYNQ_STATUS_OT             BIT(7)
  78 #define XADC_ZYNQ_STATUS_ALM(x)         BIT(x)
  79
  80 #define XADC_ZYNQ_CTL_RESET             BIT(4)
  81
  82 #define XADC_ZYNQ_CMD_NOP               0x00
  83 #define XADC_ZYNQ_CMD_READ              0x01
  84 #define XADC_ZYNQ_CMD_WRITE             0x02
  85
  86 #define XADC_ZYNQ_CMD(cmd, addr, data) (((cmd) << 26) | ((addr) << 16) | (data))
  87
  88 /* AXI register definitions */
  89 #define XADC_AXI_REG_RESET              0x00
  90 #define XADC_AXI_REG_STATUS             0x04
  91 #define XADC_AXI_REG_ALARM_STATUS       0x08
  92 #define XADC_AXI_REG_CONVST             0x0c
  93 #define XADC_AXI_REG_XADC_RESET         0x10
  94 #define XADC_AXI_REG_GIER               0x5c
  95 #define XADC_AXI_REG_IPISR              0x60
  96 #define XADC_AXI_REG_IPIER              0x68
  97
  98 /* 7 Series */
  99 #define XADC_7S_AXI_ADC_REG_OFFSET      0x200
 100
 101 /* UltraScale */
 102 #define XADC_US_AXI_ADC_REG_OFFSET      0x400
 103
 104 #define XADC_AXI_RESET_MAGIC            0xa
 105 #define XADC_AXI_GIER_ENABLE            BIT(31)
 106
 107 #define XADC_AXI_INT_EOS                BIT(4)
 108 #define XADC_AXI_INT_ALARM_MASK         0x3c0f
 109
 110 #define XADC_FLAGS_BUFFERED BIT(0)
 111 #define XADC_FLAGS_IRQ_OPTIONAL BIT(1)
 112
 113 /*
 114  * The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does
 115  * not have a hardware FIFO. Which means an interrupt is generated for each
 116  * conversion sequence. At 1MSPS sample rate the CPU in ZYNQ7000 is completely
 117  * overloaded by the interrupts that it soft-lockups. For this reason the driver
 118  * limits the maximum samplerate 150kSPS. At this rate the CPU is fairly busy,
 119  * but still responsive.
 120  */
 121 #define XADC_MAX_SAMPLERATE 150000
 122
 123 static void xadc_write_reg(struct xadc *xadc, unsigned int reg,
 124         uint32_t val)
 125 {
 126         writel(val, xadc->base + reg);
 127 }
 128
 129 static void xadc_read_reg(struct xadc *xadc, unsigned int reg,
 130         uint32_t *val)
 131 {
 132         *val = readl(xadc->base + reg);
 133 }
 134
 135 /*
 136  * The ZYNQ interface uses two asynchronous FIFOs for communication with the
 137  * XADC. Reads and writes to the XADC register are performed by submitting a
 138  * request to the command FIFO (CFIFO), once the request has been completed the
 139  * result can be read from the data FIFO (DFIFO). The method currently used in
 140  * this driver is to submit the request for a read/write operation, then go to
 141  * sleep and wait for an interrupt that signals that a response is available in
 142  * the data FIFO.
 143  */
 144
 145 static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,
 146         unsigned int n)
 147 {
 148         unsigned int i;
 149
 150         for (i = 0; i < n; i++)
 151                 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);
 152 }
 153
 154 static void xadc_zynq_drain_fifo(struct xadc *xadc)
 155 {
 156         uint32_t status, tmp;
 157
 158         xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
 159
 160         while (!(status & XADC_ZYNQ_STATUS_DFIFOE)) {
 161                 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
 162                 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
 163         }
 164 }
 165
 166 static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,
 167         unsigned int val)
 168 {
 169         xadc->zynq_intmask &= ~mask;
 170         xadc->zynq_intmask |= val;
 171
 172         xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,
 173                 xadc->zynq_intmask | xadc->zynq_masked_alarm);
 174 }
 175
 176 static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,
 177         uint16_t val)
 178 {
 179         uint32_t cmd[1];
 180         uint32_t tmp;
 181         int ret;
 182
 183         spin_lock_irq(&xadc->lock);
 184         xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
 185                         XADC_ZYNQ_INT_DFIFO_GTH);
 186
 187         reinit_completion(&xadc->completion);
 188
 189         cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
 190         xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
 191         xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
 192         tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
 193         tmp |= 0 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
 194         xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
 195
 196         xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
 197         spin_unlock_irq(&xadc->lock);
 198
 199         ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
 200         if (ret == 0)
 201                 ret = -EIO;
 202         else
 203                 ret = 0;
 204
 205         xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
 206
 207         return ret;
 208 }
 209
 210 static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,
 211         uint16_t *val)
 212 {
 213         uint32_t cmd[2];
 214         uint32_t resp, tmp;
 215         int ret;
 216
 217         cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0);
 218         cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0);
 219
 220         spin_lock_irq(&xadc->lock);
 221         xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
 222                         XADC_ZYNQ_INT_DFIFO_GTH);
 223         xadc_zynq_drain_fifo(xadc);
 224         reinit_completion(&xadc->completion);
 225
 226         xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
 227         xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
 228         tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
 229         tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
 230         xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
 231
 232         xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
 233         spin_unlock_irq(&xadc->lock);
 234         ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
 235         if (ret == 0)
 236                 ret = -EIO;
 237         if (ret < 0)
 238                 return ret;
 239
 240         xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
 241         xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
 242
 243         *val = resp & 0xffff;
 244
 245         return 0;
 246 }
 247
 248 static unsigned int xadc_zynq_transform_alarm(unsigned int alarm)
 249 {
 250         return ((alarm & 0x80) >> 4) |
 251                 ((alarm & 0x78) << 1) |
 252                 (alarm & 0x07);
 253 }
 254
 255 /*
 256  * The ZYNQ threshold interrupts are level sensitive. Since we can't make the
 257  * threshold condition go way from within the interrupt handler, this means as
 258  * soon as a threshold condition is present we would enter the interrupt handler
 259  * again and again. To work around this we mask all active thresholds interrupts
 260  * in the interrupt handler and start a timer. In this timer we poll the
 261  * interrupt status and only if the interrupt is inactive we unmask it again.
 262  */
 263 static void xadc_zynq_unmask_worker(struct work_struct *work)
 264 {
 265         struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work);
 266         unsigned int misc_sts, unmask;
 267
 268         xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts);
 269
 270         misc_sts &= XADC_ZYNQ_INT_ALARM_MASK;
 271
 272         spin_lock_irq(&xadc->lock);
 273
 274         /* Clear those bits which are not active anymore */
 275         unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
 276         xadc->zynq_masked_alarm &= misc_sts;
 277
 278         /* Also clear those which are masked out anyway */
 279         xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
 280
 281         /* Clear the interrupts before we unmask them */
 282         xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
 283
 284         xadc_zynq_update_intmsk(xadc, 0, 0);
 285
 286         spin_unlock_irq(&xadc->lock);
 287
 288         /* if still pending some alarm re-trigger the timer */
 289         if (xadc->zynq_masked_alarm) {
 290                 schedule_delayed_work(&xadc->zynq_unmask_work,
 291                                 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
 292         }
 293
 294 }
 295
 296 static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
 297 {
 298         struct iio_dev *indio_dev = devid;
 299         struct xadc *xadc = iio_priv(indio_dev);
 300         uint32_t status;
 301
 302         xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
 303
 304         status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);
 305
 306         if (!status)
 307                 return IRQ_NONE;
 308
 309         spin_lock(&xadc->lock);
 310
 311         xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);
 312
 313         if (status & XADC_ZYNQ_INT_DFIFO_GTH) {
 314                 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
 315                         XADC_ZYNQ_INT_DFIFO_GTH);
 316                 complete(&xadc->completion);
 317         }
 318
 319         status &= XADC_ZYNQ_INT_ALARM_MASK;
 320         if (status) {
 321                 xadc->zynq_masked_alarm |= status;
 322                 /*
 323                  * mask the current event interrupt,
 324                  * unmask it when the interrupt is no more active.
 325                  */
 326                 xadc_zynq_update_intmsk(xadc, 0, 0);
 327
 328                 xadc_handle_events(indio_dev,
 329                                 xadc_zynq_transform_alarm(status));
 330
 331                 /* unmask the required interrupts in timer. */
 332                 schedule_delayed_work(&xadc->zynq_unmask_work,
 333                                 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
 334         }
 335         spin_unlock(&xadc->lock);
 336
 337         return IRQ_HANDLED;
 338 }
 339
 340 #define XADC_ZYNQ_TCK_RATE_MAX 50000000
 341 #define XADC_ZYNQ_IGAP_DEFAULT 20
 342 #define XADC_ZYNQ_PCAP_RATE_MAX 200000000
 343
 344 static int xadc_zynq_setup(struct platform_device *pdev,
 345         struct iio_dev *indio_dev, int irq)
 346 {
 347         struct xadc *xadc = iio_priv(indio_dev);
 348         unsigned long pcap_rate;
 349         unsigned int tck_div;
 350         unsigned int div;
 351         unsigned int igap;
 352         unsigned int tck_rate;
 353         int ret;
 354
 355         /* TODO: Figure out how to make igap and tck_rate configurable */
 356         igap = XADC_ZYNQ_IGAP_DEFAULT;
 357         tck_rate = XADC_ZYNQ_TCK_RATE_MAX;
 358
 359         xadc->zynq_intmask = ~0;
 360
 361         pcap_rate = clk_get_rate(xadc->clk);
 362         if (!pcap_rate)
 363                 return -EINVAL;
 364
 365         if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
 366                 ret = clk_set_rate(xadc->clk,
 367                                    (unsigned long)XADC_ZYNQ_PCAP_RATE_MAX);
 368                 if (ret)
 369                         return ret;
 370         }
 371
 372         if (tck_rate > pcap_rate / 2) {
 373                 div = 2;
 374         } else {
 375                 div = pcap_rate / tck_rate;
 376                 if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX)
 377                         div++;
 378         }
 379
 380         if (div <= 3)
 381                 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV2;
 382         else if (div <= 7)
 383                 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV4;
 384         else if (div <= 15)
 385                 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV8;
 386         else
 387                 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV16;
 388
 389         xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET);
 390         xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);
 391         xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
 392         xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
 393         xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |
 394                         XADC_ZYNQ_CFG_REDGE | XADC_ZYNQ_CFG_WEDGE |
 395                         tck_div | XADC_ZYNQ_CFG_IGAP(igap));
 396
 397         if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
 398                 ret = clk_set_rate(xadc->clk, pcap_rate);
 399                 if (ret)
 400                         return ret;
 401         }
 402
 403         return 0;
 404 }
 405
 406 static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
 407 {
 408         unsigned int div;
 409         uint32_t val;
 410
 411         xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);
 412
 413         switch (val & XADC_ZYNQ_CFG_TCKRATE_MASK) {
 414         case XADC_ZYNQ_CFG_TCKRATE_DIV4:
 415                 div = 4;
 416                 break;
 417         case XADC_ZYNQ_CFG_TCKRATE_DIV8:
 418                 div = 8;
 419                 break;
 420         case XADC_ZYNQ_CFG_TCKRATE_DIV16:
 421                 div = 16;
 422                 break;
 423         default:
 424                 div = 2;
 425                 break;
 426         }
 427
 428         return clk_get_rate(xadc->clk) / div;
 429 }
 430
 431 static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)
 432 {
 433         unsigned long flags;
 434         uint32_t status;
 435
 436         /* Move OT to bit 7 */
 437         alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07);
 438
 439         spin_lock_irqsave(&xadc->lock, flags);
 440
 441         /* Clear previous interrupts if any. */
 442         xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
 443         xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);
 444
 445         xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,
 446                 ~alarm & XADC_ZYNQ_INT_ALARM_MASK);
 447
 448         spin_unlock_irqrestore(&xadc->lock, flags);
 449 }
 450
 451 static const struct xadc_ops xadc_zynq_ops = {
 452         .read = xadc_zynq_read_adc_reg,
 453         .write = xadc_zynq_write_adc_reg,
 454         .setup = xadc_zynq_setup,
 455         .get_dclk_rate = xadc_zynq_get_dclk_rate,
 456         .interrupt_handler = xadc_zynq_interrupt_handler,
 457         .update_alarm = xadc_zynq_update_alarm,
 458         .type = XADC_TYPE_S7,
 459         /* Temp in C = (val * 503.975) / 2**bits - 273.15 */
 460         .temp_scale = 503975,
 461         .temp_offset = 273150,
 462 };
 463
 464 static const unsigned int xadc_axi_reg_offsets[] = {
 465         [XADC_TYPE_S7] = XADC_7S_AXI_ADC_REG_OFFSET,
 466         [XADC_TYPE_US] = XADC_US_AXI_ADC_REG_OFFSET,
 467 };
 468
 469 static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,
 470         uint16_t *val)
 471 {
 472         uint32_t val32;
 473
 474         xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
 475                 &val32);
 476         *val = val32 & 0xffff;
 477
 478         return 0;
 479 }
 480
 481 static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,
 482         uint16_t val)
 483 {
 484         xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
 485                 val);
 486
 487         return 0;
 488 }
 489
 490 static int xadc_axi_setup(struct platform_device *pdev,
 491         struct iio_dev *indio_dev, int irq)
 492 {
 493         struct xadc *xadc = iio_priv(indio_dev);
 494
 495         xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC);
 496         xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE);
 497
 498         return 0;
 499 }
 500
 501 static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid)
 502 {
 503         struct iio_dev *indio_dev = devid;
 504         struct xadc *xadc = iio_priv(indio_dev);
 505         uint32_t status, mask;
 506         unsigned int events;
 507
 508         xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);
 509         xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask);
 510         status &= mask;
 511
 512         if (!status)
 513                 return IRQ_NONE;
 514
 515         if ((status & XADC_AXI_INT_EOS) && xadc->trigger)
 516                 iio_trigger_poll(xadc->trigger);
 517
 518         if (status & XADC_AXI_INT_ALARM_MASK) {
 519                 /*
 520                  * The order of the bits in the AXI-XADC status register does
 521                  * not match the order of the bits in the XADC alarm enable
 522                  * register. xadc_handle_events() expects the events to be in
 523                  * the same order as the XADC alarm enable register.
 524                  */
 525                 events = (status & 0x000e) >> 1;
 526                 events |= (status & 0x0001) << 3;
 527                 events |= (status & 0x3c00) >> 6;
 528                 xadc_handle_events(indio_dev, events);
 529         }
 530
 531         xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status);
 532
 533         return IRQ_HANDLED;
 534 }
 535
 536 static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
 537 {
 538         uint32_t val;
 539         unsigned long flags;
 540
 541         /*
 542          * The order of the bits in the AXI-XADC status register does not match
 543          * the order of the bits in the XADC alarm enable register. We get
 544          * passed the alarm mask in the same order as in the XADC alarm enable
 545          * register.
 546          */
 547         alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) |
 548                         ((alarm & 0xf0) << 6);
 549
 550         spin_lock_irqsave(&xadc->lock, flags);
 551         xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
 552         val &= ~XADC_AXI_INT_ALARM_MASK;
 553         val |= alarm;
 554         xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
 555         spin_unlock_irqrestore(&xadc->lock, flags);
 556 }
 557
 558 static unsigned long xadc_axi_get_dclk(struct xadc *xadc)
 559 {
 560         return clk_get_rate(xadc->clk);
 561 }
 562
 563 static const struct xadc_ops xadc_7s_axi_ops = {
 564         .read = xadc_axi_read_adc_reg,
 565         .write = xadc_axi_write_adc_reg,
 566         .setup = xadc_axi_setup,
 567         .get_dclk_rate = xadc_axi_get_dclk,
 568         .update_alarm = xadc_axi_update_alarm,
 569         .interrupt_handler = xadc_axi_interrupt_handler,
 570         .flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
 571         .type = XADC_TYPE_S7,
 572         /* Temp in C = (val * 503.975) / 2**bits - 273.15 */
 573         .temp_scale = 503975,
 574         .temp_offset = 273150,
 575 };
 576
 577 static const struct xadc_ops xadc_us_axi_ops = {
 578         .read = xadc_axi_read_adc_reg,
 579         .write = xadc_axi_write_adc_reg,
 580         .setup = xadc_axi_setup,
 581         .get_dclk_rate = xadc_axi_get_dclk,
 582         .update_alarm = xadc_axi_update_alarm,
 583         .interrupt_handler = xadc_axi_interrupt_handler,
 584         .flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
 585         .type = XADC_TYPE_US,
 586         /**
 587          * Values below are for UltraScale+ (SYSMONE4) using internal reference.
 588          * See https://docs.xilinx.com/v/u/en-US/ug580-ultrascale-sysmon
 589          */
 590         .temp_scale = 509314,
 591         .temp_offset = 280231,
 592 };
 593
 594 static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
 595         uint16_t mask, uint16_t val)
 596 {
 597         uint16_t tmp;
 598         int ret;
 599
 600         ret = _xadc_read_adc_reg(xadc, reg, &tmp);
 601         if (ret)
 602                 return ret;
 603
 604         return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);
 605 }
 606
 607 static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
 608         uint16_t mask, uint16_t val)
 609 {
 610         int ret;
 611
 612         mutex_lock(&xadc->mutex);
 613         ret = _xadc_update_adc_reg(xadc, reg, mask, val);
 614         mutex_unlock(&xadc->mutex);
 615
 616         return ret;
 617 }
 618
 619 static unsigned long xadc_get_dclk_rate(struct xadc *xadc)
 620 {
 621         return xadc->ops->get_dclk_rate(xadc);
 622 }
 623
 624 static int xadc_update_scan_mode(struct iio_dev *indio_dev,
 625         const unsigned long *mask)
 626 {
 627         struct xadc *xadc = iio_priv(indio_dev);
 628         size_t n;
 629         void *data;
 630
 631         n = bitmap_weight(mask, iio_get_masklength(indio_dev));
 632
 633         data = devm_krealloc_array(indio_dev->dev.parent, xadc->data,
 634                                    n, sizeof(*xadc->data), GFP_KERNEL);
 635         if (!data)
 636                 return -ENOMEM;
 637
 638         memset(data, 0, n * sizeof(*xadc->data));
 639         xadc->data = data;
 640
 641         return 0;
 642 }
 643
 644 static unsigned int xadc_scan_index_to_channel(unsigned int scan_index)
 645 {
 646         switch (scan_index) {
 647         case 5:
 648                 return XADC_REG_VCCPINT;
 649         case 6:
 650                 return XADC_REG_VCCPAUX;
 651         case 7:
 652                 return XADC_REG_VCCO_DDR;
 653         case 8:
 654                 return XADC_REG_TEMP;
 655         case 9:
 656                 return XADC_REG_VCCINT;
 657         case 10:
 658                 return XADC_REG_VCCAUX;
 659         case 11:
 660                 return XADC_REG_VPVN;
 661         case 12:
 662                 return XADC_REG_VREFP;
 663         case 13:
 664                 return XADC_REG_VREFN;
 665         case 14:
 666                 return XADC_REG_VCCBRAM;
 667         default:
 668                 return XADC_REG_VAUX(scan_index - 16);
 669         }
 670 }
 671
 672 static irqreturn_t xadc_trigger_handler(int irq, void *p)
 673 {
 674         struct iio_poll_func *pf = p;
 675         struct iio_dev *indio_dev = pf->indio_dev;
 676         struct xadc *xadc = iio_priv(indio_dev);
 677         unsigned int chan;
 678         int i, j;
 679
 680         if (!xadc->data)
 681                 goto out;
 682
 683         j = 0;
 684         iio_for_each_active_channel(indio_dev, i) {
 685                 chan = xadc_scan_index_to_channel(i);
 686                 xadc_read_adc_reg(xadc, chan, &xadc->data[j]);
 687                 j++;
 688         }
 689
 690         iio_push_to_buffers(indio_dev, xadc->data);
 691
 692 out:
 693         iio_trigger_notify_done(indio_dev->trig);
 694
 695         return IRQ_HANDLED;
 696 }
 697
 698 static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
 699 {
 700         struct xadc *xadc = iio_trigger_get_drvdata(trigger);
 701         unsigned long flags;
 702         unsigned int convst;
 703         unsigned int val;
 704         int ret = 0;
 705
 706         mutex_lock(&xadc->mutex);
 707
 708         if (state) {
 709                 /* Only one of the two triggers can be active at a time. */
 710                 if (xadc->trigger != NULL) {
 711                         ret = -EBUSY;
 712                         goto err_out;
 713                 } else {
 714                         xadc->trigger = trigger;
 715                         if (trigger == xadc->convst_trigger)
 716                                 convst = XADC_CONF0_EC;
 717                         else
 718                                 convst = 0;
 719                 }
 720                 ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,
 721                                         convst);
 722                 if (ret)
 723                         goto err_out;
 724         } else {
 725                 xadc->trigger = NULL;
 726         }
 727
 728         spin_lock_irqsave(&xadc->lock, flags);
 729         xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
 730         xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
 731         if (state)
 732                 val |= XADC_AXI_INT_EOS;
 733         else
 734                 val &= ~XADC_AXI_INT_EOS;
 735         xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
 736         spin_unlock_irqrestore(&xadc->lock, flags);
 737
 738 err_out:
 739         mutex_unlock(&xadc->mutex);
 740
 741         return ret;
 742 }
 743
 744 static const struct iio_trigger_ops xadc_trigger_ops = {
 745         .set_trigger_state = &xadc_trigger_set_state,
 746 };
 747
 748 static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev,
 749         const char *name)
 750 {
 751         struct device *dev = indio_dev->dev.parent;
 752         struct iio_trigger *trig;
 753         int ret;
 754
 755         trig = devm_iio_trigger_alloc(dev, "%s%d-%s", indio_dev->name,
 756                                       iio_device_id(indio_dev), name);
 757         if (trig == NULL)
 758                 return ERR_PTR(-ENOMEM);
 759
 760         trig->ops = &xadc_trigger_ops;
 761         iio_trigger_set_drvdata(trig, iio_priv(indio_dev));
 762
 763         ret = devm_iio_trigger_register(dev, trig);
 764         if (ret)
 765                 return ERR_PTR(ret);
 766
 767         return trig;
 768 }
 769
 770 static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
 771 {
 772         uint16_t val;
 773
 774         /*
 775          * As per datasheet the power-down bits are don't care in the
 776          * UltraScale, but as per reality setting the power-down bit for the
 777          * non-existing ADC-B powers down the main ADC, so just return and don't
 778          * do anything.
 779          */
 780         if (xadc->ops->type == XADC_TYPE_US)
 781                 return 0;
 782
 783         /* Powerdown the ADC-B when it is not needed. */
 784         switch (seq_mode) {
 785         case XADC_CONF1_SEQ_SIMULTANEOUS:
 786         case XADC_CONF1_SEQ_INDEPENDENT:
 787                 val = 0;
 788                 break;
 789         default:
 790                 val = XADC_CONF2_PD_ADC_B;
 791                 break;
 792         }
 793
 794         return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,
 795                 val);
 796 }
 797
 798 static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
 799 {
 800         unsigned int aux_scan_mode = scan_mode >> 16;
 801
 802         /* UltraScale has only one ADC and supports only continuous mode */
 803         if (xadc->ops->type == XADC_TYPE_US)
 804                 return XADC_CONF1_SEQ_CONTINUOUS;
 805
 806         if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)
 807                 return XADC_CONF1_SEQ_SIMULTANEOUS;
 808
 809         if ((aux_scan_mode & 0xff00) == 0 ||
 810                 (aux_scan_mode & 0x00ff) == 0)
 811                 return XADC_CONF1_SEQ_CONTINUOUS;
 812
 813         return XADC_CONF1_SEQ_SIMULTANEOUS;
 814 }
 815
 816 static int xadc_postdisable(struct iio_dev *indio_dev)
 817 {
 818         struct xadc *xadc = iio_priv(indio_dev);
 819         unsigned long scan_mask;
 820         int ret;
 821         int i;
 822
 823         scan_mask = 1; /* Run calibration as part of the sequence */
 824         for (i = 0; i < indio_dev->num_channels; i++)
 825                 scan_mask |= BIT(indio_dev->channels[i].scan_index);
 826
 827         /* Enable all channels and calibration */
 828         ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
 829         if (ret)
 830                 return ret;
 831
 832         ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
 833         if (ret)
 834                 return ret;
 835
 836         ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
 837                 XADC_CONF1_SEQ_CONTINUOUS);
 838         if (ret)
 839                 return ret;
 840
 841         return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS);
 842 }
 843
 844 static int xadc_preenable(struct iio_dev *indio_dev)
 845 {
 846         struct xadc *xadc = iio_priv(indio_dev);
 847         unsigned long scan_mask;
 848         int seq_mode;
 849         int ret;
 850
 851         ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
 852                 XADC_CONF1_SEQ_DEFAULT);
 853         if (ret)
 854                 goto err;
 855
 856         scan_mask = *indio_dev->active_scan_mask;
 857         seq_mode = xadc_get_seq_mode(xadc, scan_mask);
 858
 859         ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
 860         if (ret)
 861                 goto err;
 862
 863         /*
 864          * In simultaneous mode the upper and lower aux channels are samples at
 865          * the same time. In this mode the upper 8 bits in the sequencer
 866          * register are don't care and the lower 8 bits control two channels
 867          * each. As such we must set the bit if either the channel in the lower
 868          * group or the upper group is enabled.
 869          */
 870         if (seq_mode == XADC_CONF1_SEQ_SIMULTANEOUS)
 871                 scan_mask = ((scan_mask >> 8) | scan_mask) & 0xff0000;
 872
 873         ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
 874         if (ret)
 875                 goto err;
 876
 877         ret = xadc_power_adc_b(xadc, seq_mode);
 878         if (ret)
 879                 goto err;
 880
 881         ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
 882                 seq_mode);
 883         if (ret)
 884                 goto err;
 885
 886         return 0;
 887 err:
 888         xadc_postdisable(indio_dev);
 889         return ret;
 890 }
 891
 892 static const struct iio_buffer_setup_ops xadc_buffer_ops = {
 893         .preenable = &xadc_preenable,
 894         .postdisable = &xadc_postdisable,
 895 };
 896
 897 static int xadc_read_samplerate(struct xadc *xadc)
 898 {
 899         unsigned int div;
 900         uint16_t val16;
 901         int ret;
 902
 903         ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);
 904         if (ret)
 905                 return ret;
 906
 907         div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET;
 908         if (div < 2)
 909                 div = 2;
 910
 911         return xadc_get_dclk_rate(xadc) / div / 26;
 912 }
 913
 914 static int xadc_read_raw(struct iio_dev *indio_dev,
 915         struct iio_chan_spec const *chan, int *val, int *val2, long info)
 916 {
 917         struct xadc *xadc = iio_priv(indio_dev);
 918         unsigned int bits = chan->scan_type.realbits;
 919         uint16_t val16;
 920         int ret;
 921
 922         switch (info) {
 923         case IIO_CHAN_INFO_RAW:
 924                 if (iio_buffer_enabled(indio_dev))
 925                         return -EBUSY;
 926                 ret = xadc_read_adc_reg(xadc, chan->address, &val16);
 927                 if (ret < 0)
 928                         return ret;
 929
 930                 val16 >>= chan->scan_type.shift;
 931                 if (chan->scan_type.sign == 'u')
 932                         *val = val16;
 933                 else
 934                         *val = sign_extend32(val16, bits - 1);
 935
 936                 return IIO_VAL_INT;
 937         case IIO_CHAN_INFO_SCALE:
 938                 switch (chan->type) {
 939                 case IIO_VOLTAGE:
 940                         /* V = (val * 3.0) / 2**bits */
 941                         switch (chan->address) {
 942                         case XADC_REG_VCCINT:
 943                         case XADC_REG_VCCAUX:
 944                         case XADC_REG_VREFP:
 945                         case XADC_REG_VREFN:
 946                         case XADC_REG_VCCBRAM:
 947                         case XADC_REG_VCCPINT:
 948                         case XADC_REG_VCCPAUX:
 949                         case XADC_REG_VCCO_DDR:
 950                                 *val = 3000;
 951                                 break;
 952                         default:
 953                                 *val = 1000;
 954                                 break;
 955                         }
 956                         *val2 = bits;
 957                         return IIO_VAL_FRACTIONAL_LOG2;
 958                 case IIO_TEMP:
 959                         *val = xadc->ops->temp_scale;
 960                         *val2 = bits;
 961                         return IIO_VAL_FRACTIONAL_LOG2;
 962                 default:
 963                         return -EINVAL;
 964                 }
 965         case IIO_CHAN_INFO_OFFSET:
 966                 /* Only the temperature channel has an offset */
 967                 *val = -((xadc->ops->temp_offset << bits) / xadc->ops->temp_scale);
 968                 return IIO_VAL_INT;
 969         case IIO_CHAN_INFO_SAMP_FREQ:
 970                 ret = xadc_read_samplerate(xadc);
 971                 if (ret < 0)
 972                         return ret;
 973
 974                 *val = ret;
 975                 return IIO_VAL_INT;
 976         default:
 977                 return -EINVAL;
 978         }
 979 }
 980
 981 static int xadc_write_samplerate(struct xadc *xadc, int val)
 982 {
 983         unsigned long clk_rate = xadc_get_dclk_rate(xadc);
 984         unsigned int div;
 985
 986         if (!clk_rate)
 987                 return -EINVAL;
 988
 989         if (val <= 0)
 990                 return -EINVAL;
 991
 992         /* Max. 150 kSPS */
 993         if (val > XADC_MAX_SAMPLERATE)
 994                 val = XADC_MAX_SAMPLERATE;
 995
 996         val *= 26;
 997
 998         /* Min 1MHz */
 999         if (val < 1000000)
1000                 val = 1000000;
1001
1002         /*
1003          * We want to round down, but only if we do not exceed the 150 kSPS
1004          * limit.
1005          */
1006         div = clk_rate / val;
1007         if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE)
1008                 div++;
1009         if (div < 2)
1010                 div = 2;
1011         else if (div > 0xff)
1012                 div = 0xff;
1013
1014         return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,
1015                 div << XADC_CONF2_DIV_OFFSET);
1016 }
1017
1018 static int xadc_write_raw(struct iio_dev *indio_dev,
1019         struct iio_chan_spec const *chan, int val, int val2, long info)
1020 {
1021         struct xadc *xadc = iio_priv(indio_dev);
1022
1023         if (info != IIO_CHAN_INFO_SAMP_FREQ)
1024                 return -EINVAL;
1025
1026         return xadc_write_samplerate(xadc, val);
1027 }
1028
1029 static const struct iio_event_spec xadc_temp_events[] = {
1030         {
1031                 .type = IIO_EV_TYPE_THRESH,
1032                 .dir = IIO_EV_DIR_RISING,
1033                 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
1034                                 BIT(IIO_EV_INFO_VALUE) |
1035                                 BIT(IIO_EV_INFO_HYSTERESIS),
1036         },
1037 };
1038
1039 /* Separate values for upper and lower thresholds, but only a shared enabled */
1040 static const struct iio_event_spec xadc_voltage_events[] = {
1041         {
1042                 .type = IIO_EV_TYPE_THRESH,
1043                 .dir = IIO_EV_DIR_RISING,
1044                 .mask_separate = BIT(IIO_EV_INFO_VALUE),
1045         }, {
1046                 .type = IIO_EV_TYPE_THRESH,
1047                 .dir = IIO_EV_DIR_FALLING,
1048                 .mask_separate = BIT(IIO_EV_INFO_VALUE),
1049         }, {
1050                 .type = IIO_EV_TYPE_THRESH,
1051                 .dir = IIO_EV_DIR_EITHER,
1052                 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1053         },
1054 };
1055
1056 #define XADC_CHAN_TEMP(_chan, _scan_index, _addr, _bits) { \
1057         .type = IIO_TEMP, \
1058         .indexed = 1, \
1059         .channel = (_chan), \
1060         .address = (_addr), \
1061         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1062                 BIT(IIO_CHAN_INFO_SCALE) | \
1063                 BIT(IIO_CHAN_INFO_OFFSET), \
1064         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1065         .event_spec = xadc_temp_events, \
1066         .num_event_specs = ARRAY_SIZE(xadc_temp_events), \
1067         .scan_index = (_scan_index), \
1068         .scan_type = { \
1069                 .sign = 'u', \
1070                 .realbits = (_bits), \
1071                 .storagebits = 16, \
1072                 .shift = 16 - (_bits), \
1073                 .endianness = IIO_CPU, \
1074         }, \
1075 }
1076
1077 #define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _bits, _ext, _alarm) { \
1078         .type = IIO_VOLTAGE, \
1079         .indexed = 1, \
1080         .channel = (_chan), \
1081         .address = (_addr), \
1082         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1083                 BIT(IIO_CHAN_INFO_SCALE), \
1084         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1085         .event_spec = (_alarm) ? xadc_voltage_events : NULL, \
1086         .num_event_specs = (_alarm) ? ARRAY_SIZE(xadc_voltage_events) : 0, \
1087         .scan_index = (_scan_index), \
1088         .scan_type = { \
1089                 .sign = ((_addr) == XADC_REG_VREFN) ? 's' : 'u', \
1090                 .realbits = (_bits), \
1091                 .storagebits = 16, \
1092                 .shift = 16 - (_bits), \
1093                 .endianness = IIO_CPU, \
1094         }, \
1095         .extend_name = _ext, \
1096 }
1097
1098 /* 7 Series */
1099 #define XADC_7S_CHAN_TEMP(_chan, _scan_index, _addr) \
1100         XADC_CHAN_TEMP(_chan, _scan_index, _addr, 12)
1101 #define XADC_7S_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
1102         XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 12, _ext, _alarm)
1103
1104 static const struct iio_chan_spec xadc_7s_channels[] = {
1105         XADC_7S_CHAN_TEMP(0, 8, XADC_REG_TEMP),
1106         XADC_7S_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
1107         XADC_7S_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
1108         XADC_7S_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
1109         XADC_7S_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true),
1110         XADC_7S_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true),
1111         XADC_7S_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true),
1112         XADC_7S_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
1113         XADC_7S_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
1114         XADC_7S_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
1115         XADC_7S_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
1116         XADC_7S_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
1117         XADC_7S_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
1118         XADC_7S_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
1119         XADC_7S_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
1120         XADC_7S_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
1121         XADC_7S_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
1122         XADC_7S_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
1123         XADC_7S_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
1124         XADC_7S_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
1125         XADC_7S_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
1126         XADC_7S_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
1127         XADC_7S_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
1128         XADC_7S_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
1129         XADC_7S_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
1130         XADC_7S_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
1131 };
1132
1133 /* UltraScale */
1134 #define XADC_US_CHAN_TEMP(_chan, _scan_index, _addr) \
1135         XADC_CHAN_TEMP(_chan, _scan_index, _addr, 10)
1136 #define XADC_US_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
1137         XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 10, _ext, _alarm)
1138
1139 static const struct iio_chan_spec xadc_us_channels[] = {
1140         XADC_US_CHAN_TEMP(0, 8, XADC_REG_TEMP),
1141         XADC_US_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
1142         XADC_US_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
1143         XADC_US_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
1144         XADC_US_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpsintlp", true),
1145         XADC_US_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpsintfp", true),
1146         XADC_US_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccpsaux", true),
1147         XADC_US_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
1148         XADC_US_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
1149         XADC_US_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
1150         XADC_US_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
1151         XADC_US_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
1152         XADC_US_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
1153         XADC_US_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
1154         XADC_US_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
1155         XADC_US_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
1156         XADC_US_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
1157         XADC_US_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
1158         XADC_US_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
1159         XADC_US_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
1160         XADC_US_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
1161         XADC_US_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
1162         XADC_US_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
1163         XADC_US_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
1164         XADC_US_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
1165         XADC_US_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
1166 };
1167
1168 static const struct iio_info xadc_info = {
1169         .read_raw = &xadc_read_raw,
1170         .write_raw = &xadc_write_raw,
1171         .read_event_config = &xadc_read_event_config,
1172         .write_event_config = &xadc_write_event_config,
1173         .read_event_value = &xadc_read_event_value,
1174         .write_event_value = &xadc_write_event_value,
1175         .update_scan_mode = &xadc_update_scan_mode,
1176 };
1177
1178 static const struct of_device_id xadc_of_match_table[] = {
1179         {
1180                 .compatible = "xlnx,zynq-xadc-1.00.a",
1181                 .data = &xadc_zynq_ops
1182         }, {
1183                 .compatible = "xlnx,axi-xadc-1.00.a",
1184                 .data = &xadc_7s_axi_ops
1185         }, {
1186                 .compatible = "xlnx,system-management-wiz-1.3",
1187                 .data = &xadc_us_axi_ops
1188         },
1189         { },
1190 };
1191 MODULE_DEVICE_TABLE(of, xadc_of_match_table);
1192
1193 static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
1194 {
1195         struct device *dev = indio_dev->dev.parent;
1196         struct xadc *xadc = iio_priv(indio_dev);
1197         const struct iio_chan_spec *channel_templates;
1198         struct iio_chan_spec *channels, *chan;
1199         struct fwnode_handle *chan_node, *child;
1200         unsigned int max_channels;
1201         unsigned int num_channels;
1202         const char *external_mux;
1203         u32 ext_mux_chan;
1204         u32 reg;
1205         int ret;
1206         int i;
1207
1208         *conf = 0;
1209
1210         ret = device_property_read_string(dev, "xlnx,external-mux", &external_mux);
1211         if (ret < 0 || strcasecmp(external_mux, "none") == 0)
1212                 xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;
1213         else if (strcasecmp(external_mux, "single") == 0)
1214                 xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;
1215         else if (strcasecmp(external_mux, "dual") == 0)
1216                 xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;
1217         else
1218                 return -EINVAL;
1219
1220         if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {
1221                 ret = device_property_read_u32(dev, "xlnx,external-mux-channel", &ext_mux_chan);
1222                 if (ret < 0)
1223                         return ret;
1224
1225                 if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {
1226                         if (ext_mux_chan == 0)
1227                                 ext_mux_chan = XADC_REG_VPVN;
1228                         else if (ext_mux_chan <= 16)
1229                                 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1230                         else
1231                                 return -EINVAL;
1232                 } else {
1233                         if (ext_mux_chan > 0 && ext_mux_chan <= 8)
1234                                 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1235                         else
1236                                 return -EINVAL;
1237                 }
1238
1239                 *conf |= XADC_CONF0_MUX | XADC_CONF0_CHAN(ext_mux_chan);
1240         }
1241         if (xadc->ops->type == XADC_TYPE_S7) {
1242                 channel_templates = xadc_7s_channels;
1243                 max_channels = ARRAY_SIZE(xadc_7s_channels);
1244         } else {
1245                 channel_templates = xadc_us_channels;
1246                 max_channels = ARRAY_SIZE(xadc_us_channels);
1247         }
1248         channels = devm_kmemdup(dev, channel_templates,
1249                                 sizeof(channels[0]) * max_channels, GFP_KERNEL);
1250         if (!channels)
1251                 return -ENOMEM;
1252
1253         num_channels = 9;
1254         chan = &channels[9];
1255
1256         chan_node = device_get_named_child_node(dev, "xlnx,channels");
1257         fwnode_for_each_child_node(chan_node, child) {
1258                 if (num_channels >= max_channels) {
1259                         fwnode_handle_put(child);
1260                         break;
1261                 }
1262
1263                 ret = fwnode_property_read_u32(child, "reg", &reg);
1264                 if (ret || reg > 16)
1265                         continue;
1266
1267                 if (fwnode_property_read_bool(child, "xlnx,bipolar"))
1268                         chan->scan_type.sign = 's';
1269
1270                 if (reg == 0) {
1271                         chan->scan_index = 11;
1272                         chan->address = XADC_REG_VPVN;
1273                 } else {
1274                         chan->scan_index = 15 + reg;
1275                         chan->address = XADC_REG_VAUX(reg - 1);
1276                 }
1277                 num_channels++;
1278                 chan++;
1279         }
1280         fwnode_handle_put(chan_node);
1281
1282         /* No IRQ => no events */
1283         if (irq <= 0) {
1284                 for (i = 0; i < num_channels; i++) {
1285                         channels[i].event_spec = NULL;
1286                         channels[i].num_event_specs = 0;
1287                 }
1288         }
1289
1290         indio_dev->num_channels = num_channels;
1291         indio_dev->channels = devm_krealloc_array(dev, channels,
1292                                                   num_channels, sizeof(*channels),
1293                                                   GFP_KERNEL);
1294         /* If we can't resize the channels array, just use the original */
1295         if (!indio_dev->channels)
1296                 indio_dev->channels = channels;
1297
1298         return 0;
1299 }
1300
1301 static const char * const xadc_type_names[] = {
1302         [XADC_TYPE_S7] = "xadc",
1303         [XADC_TYPE_US] = "xilinx-system-monitor",
1304 };
1305
1306 static void xadc_cancel_delayed_work(void *data)
1307 {
1308         struct delayed_work *work = data;
1309
1310         cancel_delayed_work_sync(work);
1311 }
1312
1313 static int xadc_probe(struct platform_device *pdev)
1314 {
1315         struct device *dev = &pdev->dev;
1316         const struct xadc_ops *ops;
1317         struct iio_dev *indio_dev;
1318         unsigned int bipolar_mask;
1319         unsigned int conf0;
1320         struct xadc *xadc;
1321         int ret;
1322         int irq;
1323         int i;
1324
1325         ops = device_get_match_data(dev);
1326         if (!ops)
1327                 return -EINVAL;
1328
1329         irq = platform_get_irq_optional(pdev, 0);
1330         if (irq < 0 &&
1331             (irq != -ENXIO || !(ops->flags & XADC_FLAGS_IRQ_OPTIONAL)))
1332                 return irq;
1333
1334         indio_dev = devm_iio_device_alloc(dev, sizeof(*xadc));
1335         if (!indio_dev)
1336                 return -ENOMEM;
1337
1338         xadc = iio_priv(indio_dev);
1339         xadc->ops = ops;
1340         init_completion(&xadc->completion);
1341         mutex_init(&xadc->mutex);
1342         spin_lock_init(&xadc->lock);
1343         INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);
1344
1345         xadc->base = devm_platform_ioremap_resource(pdev, 0);
1346         if (IS_ERR(xadc->base))
1347                 return PTR_ERR(xadc->base);
1348
1349         indio_dev->name = xadc_type_names[xadc->ops->type];
1350         indio_dev->modes = INDIO_DIRECT_MODE;
1351         indio_dev->info = &xadc_info;
1352
1353         ret = xadc_parse_dt(indio_dev, &conf0, irq);
1354         if (ret)
1355                 return ret;
1356
1357         if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1358                 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
1359                                                       &iio_pollfunc_store_time,
1360                                                       &xadc_trigger_handler,
1361                                                       &xadc_buffer_ops);
1362                 if (ret)
1363                         return ret;
1364
1365                 if (irq > 0) {
1366                         xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");
1367                         if (IS_ERR(xadc->convst_trigger))
1368                                 return PTR_ERR(xadc->convst_trigger);
1369
1370                         xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,
1371                                 "samplerate");
1372                         if (IS_ERR(xadc->samplerate_trigger))
1373                                 return PTR_ERR(xadc->samplerate_trigger);
1374                 }
1375         }
1376
1377         xadc->clk = devm_clk_get_enabled(dev, NULL);
1378         if (IS_ERR(xadc->clk))
1379                 return PTR_ERR(xadc->clk);
1380
1381         /*
1382          * Make sure not to exceed the maximum samplerate since otherwise the
1383          * resulting interrupt storm will soft-lock the system.
1384          */
1385         if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1386                 ret = xadc_read_samplerate(xadc);
1387                 if (ret < 0)
1388                         return ret;
1389
1390                 if (ret > XADC_MAX_SAMPLERATE) {
1391                         ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE);
1392                         if (ret < 0)
1393                                 return ret;
1394                 }
1395         }
1396
1397         if (irq > 0) {
1398                 ret = devm_request_irq(dev, irq, xadc->ops->interrupt_handler,
1399                                        0, dev_name(dev), indio_dev);
1400                 if (ret)
1401                         return ret;
1402
1403                 ret = devm_add_action_or_reset(dev, xadc_cancel_delayed_work,
1404                                                &xadc->zynq_unmask_work);
1405                 if (ret)
1406                         return ret;
1407         }
1408
1409         ret = xadc->ops->setup(pdev, indio_dev, irq);
1410         if (ret)
1411                 return ret;
1412
1413         for (i = 0; i < 16; i++)
1414                 xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),
1415                         &xadc->threshold[i]);
1416
1417         ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);
1418         if (ret)
1419                 return ret;
1420
1421         bipolar_mask = 0;
1422         for (i = 0; i < indio_dev->num_channels; i++) {
1423                 if (indio_dev->channels[i].scan_type.sign == 's')
1424                         bipolar_mask |= BIT(indio_dev->channels[i].scan_index);
1425         }
1426
1427         ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask);
1428         if (ret)
1429                 return ret;
1430
1431         ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),
1432                 bipolar_mask >> 16);
1433         if (ret)
1434                 return ret;
1435
1436         /* Go to non-buffered mode */
1437         xadc_postdisable(indio_dev);
1438
1439         return devm_iio_device_register(dev, indio_dev);
1440 }
1441
1442 static struct platform_driver xadc_driver = {
1443         .probe = xadc_probe,
1444         .driver = {
1445                 .name = "xadc",
1446                 .of_match_table = xadc_of_match_table,
1447         },
1448 };
1449 module_platform_driver(xadc_driver);
1450
1451 MODULE_LICENSE("GPL v2");
1452 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1453 MODULE_DESCRIPTION("Xilinx XADC IIO driver");