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drm/log: select CONFIG_FONT_SUPPORT
[drm/drm-misc.git] / drivers / scsi / advansys.c
blobfd4fcb37863dc2eeefb8332fdbb409d35dfcb631
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
4 *
5 * Copyright (c) 1995-2000 Advanced System Products, Inc.
6 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
7 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
8 * Copyright (c) 2014 Hannes Reinecke <hare@suse.de>
9 * All Rights Reserved.
10 */
11
12 /*
13 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
14 * changed its name to ConnectCom Solutions, Inc.
15 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
16 */
17
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/kernel.h>
21 #include <linux/types.h>
22 #include <linux/ioport.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/slab.h>
26 #include <linux/mm.h>
27 #include <linux/proc_fs.h>
28 #include <linux/init.h>
29 #include <linux/blkdev.h>
30 #include <linux/isa.h>
31 #include <linux/eisa.h>
32 #include <linux/pci.h>
33 #include <linux/spinlock.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/firmware.h>
36 #include <linux/dmapool.h>
37
38 #include <asm/io.h>
39 #include <asm/dma.h>
40
41 #include <scsi/scsi_cmnd.h>
42 #include <scsi/scsi_device.h>
43 #include <scsi/scsi_tcq.h>
44 #include <scsi/scsi.h>
45 #include <scsi/scsi_host.h>
46
47 #define DRV_NAME "advansys"
48 #define ASC_VERSION "3.5" /* AdvanSys Driver Version */
49
50 /* FIXME:
51 *
52 * 1. Use scsi_transport_spi
53 * 2. advansys_info is not safe against multiple simultaneous callers
54 * 3. Add module_param to override ISA/VLB ioport array
55 */
56
57 /* Enable driver /proc statistics. */
58 #define ADVANSYS_STATS
59
60 /* Enable driver tracing. */
61 #undef ADVANSYS_DEBUG
62
63 typedef unsigned char uchar;
64
65 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
66
67 #define PCI_VENDOR_ID_ASP 0x10cd
68 #define PCI_DEVICE_ID_ASP_1200A 0x1100
69 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
70 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
71 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
72 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
73 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
74
75 #define PortAddr unsigned int /* port address size */
76 #define inp(port) inb(port)
77 #define outp(port, byte) outb((byte), (port))
78
79 #define inpw(port) inw(port)
80 #define outpw(port, word) outw((word), (port))
81
82 #define ASC_MAX_SG_QUEUE 7
83 #define ASC_MAX_SG_LIST 255
84
85 #define ASC_CS_TYPE unsigned short
86
87 #define ASC_IS_EISA (0x0002)
88 #define ASC_IS_PCI (0x0004)
89 #define ASC_IS_PCI_ULTRA (0x0104)
90 #define ASC_IS_PCMCIA (0x0008)
91 #define ASC_IS_MCA (0x0020)
92 #define ASC_IS_VL (0x0040)
93 #define ASC_IS_WIDESCSI_16 (0x0100)
94 #define ASC_IS_WIDESCSI_32 (0x0200)
95 #define ASC_IS_BIG_ENDIAN (0x8000)
96
97 #define ASC_CHIP_MIN_VER_VL (0x01)
98 #define ASC_CHIP_MAX_VER_VL (0x07)
99 #define ASC_CHIP_MIN_VER_PCI (0x09)
100 #define ASC_CHIP_MAX_VER_PCI (0x0F)
101 #define ASC_CHIP_VER_PCI_BIT (0x08)
102 #define ASC_CHIP_VER_ASYN_BUG (0x21)
103 #define ASC_CHIP_VER_PCI 0x08
104 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
105 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
106 #define ASC_CHIP_MIN_VER_EISA (0x41)
107 #define ASC_CHIP_MAX_VER_EISA (0x47)
108 #define ASC_CHIP_VER_EISA_BIT (0x40)
109 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
110 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
111 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
112
113 #define ASC_SCSI_ID_BITS 3
114 #define ASC_SCSI_TIX_TYPE uchar
115 #define ASC_ALL_DEVICE_BIT_SET 0xFF
116 #define ASC_SCSI_BIT_ID_TYPE uchar
117 #define ASC_MAX_TID 7
118 #define ASC_MAX_LUN 7
119 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
120 #define ASC_MAX_SENSE_LEN 32
121 #define ASC_MIN_SENSE_LEN 14
122 #define ASC_SCSI_RESET_HOLD_TIME_US 60
123
124 /*
125 * Narrow boards only support 12-byte commands, while wide boards
126 * extend to 16-byte commands.
127 */
128 #define ASC_MAX_CDB_LEN 12
129 #define ADV_MAX_CDB_LEN 16
130
131 #define MS_SDTR_LEN 0x03
132 #define MS_WDTR_LEN 0x02
133
134 #define ASC_SG_LIST_PER_Q 7
135 #define QS_FREE 0x00
136 #define QS_READY 0x01
137 #define QS_DISC1 0x02
138 #define QS_DISC2 0x04
139 #define QS_BUSY 0x08
140 #define QS_ABORTED 0x40
141 #define QS_DONE 0x80
142 #define QC_NO_CALLBACK 0x01
143 #define QC_SG_SWAP_QUEUE 0x02
144 #define QC_SG_HEAD 0x04
145 #define QC_DATA_IN 0x08
146 #define QC_DATA_OUT 0x10
147 #define QC_URGENT 0x20
148 #define QC_MSG_OUT 0x40
149 #define QC_REQ_SENSE 0x80
150 #define QCSG_SG_XFER_LIST 0x02
151 #define QCSG_SG_XFER_MORE 0x04
152 #define QCSG_SG_XFER_END 0x08
153 #define QD_IN_PROGRESS 0x00
154 #define QD_NO_ERROR 0x01
155 #define QD_ABORTED_BY_HOST 0x02
156 #define QD_WITH_ERROR 0x04
157 #define QD_INVALID_REQUEST 0x80
158 #define QD_INVALID_HOST_NUM 0x81
159 #define QD_INVALID_DEVICE 0x82
160 #define QD_ERR_INTERNAL 0xFF
161 #define QHSTA_NO_ERROR 0x00
162 #define QHSTA_M_SEL_TIMEOUT 0x11
163 #define QHSTA_M_DATA_OVER_RUN 0x12
164 #define QHSTA_M_DATA_UNDER_RUN 0x12
165 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
166 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
167 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
168 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
169 #define QHSTA_D_HOST_ABORT_FAILED 0x23
170 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
171 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
172 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
173 #define QHSTA_M_WTM_TIMEOUT 0x41
174 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
175 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
176 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
177 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
178 #define QHSTA_M_BAD_TAG_CODE 0x46
179 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
180 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
181 #define QHSTA_D_LRAM_CMP_ERROR 0x81
182 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
183 #define ASC_FLAG_SCSIQ_REQ 0x01
184 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
185 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
186 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
187 #define ASC_FLAG_WIN16 0x10
188 #define ASC_FLAG_WIN32 0x20
189 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
190 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
191 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
192 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
193 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
194 #define ASC_SCSIQ_CPY_BEG 4
195 #define ASC_SCSIQ_SGHD_CPY_BEG 2
196 #define ASC_SCSIQ_B_FWD 0
197 #define ASC_SCSIQ_B_BWD 1
198 #define ASC_SCSIQ_B_STATUS 2
199 #define ASC_SCSIQ_B_QNO 3
200 #define ASC_SCSIQ_B_CNTL 4
201 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
202 #define ASC_SCSIQ_D_DATA_ADDR 8
203 #define ASC_SCSIQ_D_DATA_CNT 12
204 #define ASC_SCSIQ_B_SENSE_LEN 20
205 #define ASC_SCSIQ_DONE_INFO_BEG 22
206 #define ASC_SCSIQ_D_SRBPTR 22
207 #define ASC_SCSIQ_B_TARGET_IX 26
208 #define ASC_SCSIQ_B_CDB_LEN 28
209 #define ASC_SCSIQ_B_TAG_CODE 29
210 #define ASC_SCSIQ_W_VM_ID 30
211 #define ASC_SCSIQ_DONE_STATUS 32
212 #define ASC_SCSIQ_HOST_STATUS 33
213 #define ASC_SCSIQ_SCSI_STATUS 34
214 #define ASC_SCSIQ_CDB_BEG 36
215 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
216 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
217 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
218 #define ASC_SCSIQ_B_SG_WK_QP 49
219 #define ASC_SCSIQ_B_SG_WK_IX 50
220 #define ASC_SCSIQ_W_ALT_DC1 52
221 #define ASC_SCSIQ_B_LIST_CNT 6
222 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
223 #define ASC_SGQ_B_SG_CNTL 4
224 #define ASC_SGQ_B_SG_HEAD_QP 5
225 #define ASC_SGQ_B_SG_LIST_CNT 6
226 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
227 #define ASC_SGQ_LIST_BEG 8
228 #define ASC_DEF_SCSI1_QNG 4
229 #define ASC_MAX_SCSI1_QNG 4
230 #define ASC_DEF_SCSI2_QNG 16
231 #define ASC_MAX_SCSI2_QNG 32
232 #define ASC_TAG_CODE_MASK 0x23
233 #define ASC_STOP_REQ_RISC_STOP 0x01
234 #define ASC_STOP_ACK_RISC_STOP 0x03
235 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
236 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
237 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
238 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
239 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
240 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
241 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
242 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
243 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
244 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
245
246 typedef struct asc_scsiq_1 {
247 uchar status;
248 uchar q_no;
249 uchar cntl;
250 uchar sg_queue_cnt;
251 uchar target_id;
252 uchar target_lun;
253 __le32 data_addr;
254 __le32 data_cnt;
255 __le32 sense_addr;
256 uchar sense_len;
257 uchar extra_bytes;
258 } ASC_SCSIQ_1;
259
260 typedef struct asc_scsiq_2 {
261 u32 srb_tag;
262 uchar target_ix;
263 uchar flag;
264 uchar cdb_len;
265 uchar tag_code;
266 ushort vm_id;
267 } ASC_SCSIQ_2;
268
269 typedef struct asc_scsiq_3 {
270 uchar done_stat;
271 uchar host_stat;
272 uchar scsi_stat;
273 uchar scsi_msg;
274 } ASC_SCSIQ_3;
275
276 typedef struct asc_scsiq_4 {
277 uchar cdb[ASC_MAX_CDB_LEN];
278 uchar y_first_sg_list_qp;
279 uchar y_working_sg_qp;
280 uchar y_working_sg_ix;
281 uchar y_res;
282 ushort x_req_count;
283 ushort x_reconnect_rtn;
284 __le32 x_saved_data_addr;
285 __le32 x_saved_data_cnt;
286 } ASC_SCSIQ_4;
287
288 typedef struct asc_q_done_info {
289 ASC_SCSIQ_2 d2;
290 ASC_SCSIQ_3 d3;
291 uchar q_status;
292 uchar q_no;
293 uchar cntl;
294 uchar sense_len;
295 uchar extra_bytes;
296 uchar res;
297 u32 remain_bytes;
298 } ASC_QDONE_INFO;
299
300 typedef struct asc_sg_list {
301 __le32 addr;
302 __le32 bytes;
303 } ASC_SG_LIST;
304
305 typedef struct asc_sg_head {
306 ushort entry_cnt;
307 ushort queue_cnt;
308 ushort entry_to_copy;
309 ushort res;
310 ASC_SG_LIST sg_list[];
311 } ASC_SG_HEAD;
312
313 typedef struct asc_scsi_q {
314 ASC_SCSIQ_1 q1;
315 ASC_SCSIQ_2 q2;
316 uchar *cdbptr;
317 ASC_SG_HEAD *sg_head;
318 ushort remain_sg_entry_cnt;
319 ushort next_sg_index;
320 } ASC_SCSI_Q;
321
322 typedef struct asc_scsi_bios_req_q {
323 ASC_SCSIQ_1 r1;
324 ASC_SCSIQ_2 r2;
325 uchar *cdbptr;
326 ASC_SG_HEAD *sg_head;
327 uchar *sense_ptr;
328 ASC_SCSIQ_3 r3;
329 uchar cdb[ASC_MAX_CDB_LEN];
330 uchar sense[ASC_MIN_SENSE_LEN];
331 } ASC_SCSI_BIOS_REQ_Q;
332
333 typedef struct asc_risc_q {
334 uchar fwd;
335 uchar bwd;
336 ASC_SCSIQ_1 i1;
337 ASC_SCSIQ_2 i2;
338 ASC_SCSIQ_3 i3;
339 ASC_SCSIQ_4 i4;
340 } ASC_RISC_Q;
341
342 typedef struct asc_sg_list_q {
343 uchar seq_no;
344 uchar q_no;
345 uchar cntl;
346 uchar sg_head_qp;
347 uchar sg_list_cnt;
348 uchar sg_cur_list_cnt;
349 } ASC_SG_LIST_Q;
350
351 typedef struct asc_risc_sg_list_q {
352 uchar fwd;
353 uchar bwd;
354 ASC_SG_LIST_Q sg;
355 ASC_SG_LIST sg_list[7];
356 } ASC_RISC_SG_LIST_Q;
357
358 #define ASCQ_ERR_Q_STATUS 0x0D
359 #define ASCQ_ERR_CUR_QNG 0x17
360 #define ASCQ_ERR_SG_Q_LINKS 0x18
361 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
362 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
363 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
364
365 /*
366 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
367 */
368 #define ASC_WARN_NO_ERROR 0x0000
369 #define ASC_WARN_IO_PORT_ROTATE 0x0001
370 #define ASC_WARN_EEPROM_CHKSUM 0x0002
371 #define ASC_WARN_IRQ_MODIFIED 0x0004
372 #define ASC_WARN_AUTO_CONFIG 0x0008
373 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
374 #define ASC_WARN_EEPROM_RECOVER 0x0020
375 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
376
377 /*
378 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
379 */
380 #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
381 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
382 #define ASC_IERR_SET_PC_ADDR 0x0004
383 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
384 #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
385 #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
386 #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
387 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
388 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
389 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
390 #define ASC_IERR_NO_BUS_TYPE 0x0400
391 #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
392 #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
393 #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
394
395 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
396 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
397 #define ASC_MIN_FREE_Q (0x02)
398 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
399 #define ASC_MAX_TOTAL_QNG 240
400 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
401 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
402 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
403 #define ASC_MAX_INRAM_TAG_QNG 16
404 #define ASC_IOADR_GAP 0x10
405 #define ASC_SYN_MAX_OFFSET 0x0F
406 #define ASC_DEF_SDTR_OFFSET 0x0F
407 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
408 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
409
410 /* The narrow chip only supports a limited selection of transfer rates.
411 * These are encoded in the range 0..7 or 0..15 depending whether the chip
412 * is Ultra-capable or not. These tables let us convert from one to the other.
413 */
414 static const unsigned char asc_syn_xfer_period[8] = {
415 25, 30, 35, 40, 50, 60, 70, 85
416 };
417
418 static const unsigned char asc_syn_ultra_xfer_period[16] = {
419 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
420 };
421
422 typedef struct ext_msg {
423 uchar msg_type;
424 uchar msg_len;
425 uchar msg_req;
426 union {
427 struct {
428 uchar sdtr_xfer_period;
429 uchar sdtr_req_ack_offset;
430 } sdtr;
431 struct {
432 uchar wdtr_width;
433 } wdtr;
434 struct {
435 uchar mdp_b3;
436 uchar mdp_b2;
437 uchar mdp_b1;
438 uchar mdp_b0;
439 } mdp;
440 } u_ext_msg;
441 uchar res;
442 } EXT_MSG;
443
444 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
445 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
446 #define wdtr_width u_ext_msg.wdtr.wdtr_width
447 #define mdp_b3 u_ext_msg.mdp_b3
448 #define mdp_b2 u_ext_msg.mdp_b2
449 #define mdp_b1 u_ext_msg.mdp_b1
450 #define mdp_b0 u_ext_msg.mdp_b0
451
452 typedef struct asc_dvc_cfg {
453 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
454 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
455 ASC_SCSI_BIT_ID_TYPE disc_enable;
456 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
457 uchar chip_scsi_id;
458 uchar chip_version;
459 ushort mcode_date;
460 ushort mcode_version;
461 uchar max_tag_qng[ASC_MAX_TID + 1];
462 uchar sdtr_period_offset[ASC_MAX_TID + 1];
463 uchar adapter_info[6];
464 } ASC_DVC_CFG;
465
466 #define ASC_DEF_DVC_CNTL 0xFFFF
467 #define ASC_DEF_CHIP_SCSI_ID 7
468 #define ASC_DEF_ISA_DMA_SPEED 4
469 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
470 #define ASC_INIT_STATE_END_GET_CFG 0x0002
471 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
472 #define ASC_INIT_STATE_END_SET_CFG 0x0008
473 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
474 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
475 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
476 #define ASC_INIT_STATE_END_INQUIRY 0x0080
477 #define ASC_INIT_RESET_SCSI_DONE 0x0100
478 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
479 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
480 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
481 #define ASC_MIN_TAGGED_CMD 7
482 #define ASC_MAX_SCSI_RESET_WAIT 30
483 #define ASC_OVERRUN_BSIZE 64
484
485 struct asc_dvc_var; /* Forward Declaration. */
486
487 typedef struct asc_dvc_var {
488 PortAddr iop_base;
489 ushort err_code;
490 ushort dvc_cntl;
491 ushort bug_fix_cntl;
492 ushort bus_type;
493 ASC_SCSI_BIT_ID_TYPE init_sdtr;
494 ASC_SCSI_BIT_ID_TYPE sdtr_done;
495 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
496 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
497 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
498 ASC_SCSI_BIT_ID_TYPE start_motor;
499 uchar *overrun_buf;
500 dma_addr_t overrun_dma;
501 uchar scsi_reset_wait;
502 uchar chip_no;
503 bool is_in_int;
504 uchar max_total_qng;
505 uchar cur_total_qng;
506 uchar in_critical_cnt;
507 uchar last_q_shortage;
508 ushort init_state;
509 uchar cur_dvc_qng[ASC_MAX_TID + 1];
510 uchar max_dvc_qng[ASC_MAX_TID + 1];
511 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
512 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
513 const uchar *sdtr_period_tbl;
514 ASC_DVC_CFG *cfg;
515 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
516 char redo_scam;
517 ushort res2;
518 uchar dos_int13_table[ASC_MAX_TID + 1];
519 unsigned int max_dma_count;
520 ASC_SCSI_BIT_ID_TYPE no_scam;
521 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
522 uchar min_sdtr_index;
523 uchar max_sdtr_index;
524 struct asc_board *drv_ptr;
525 unsigned int uc_break;
526 } ASC_DVC_VAR;
527
528 typedef struct asc_dvc_inq_info {
529 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
530 } ASC_DVC_INQ_INFO;
531
532 typedef struct asc_cap_info {
533 u32 lba;
534 u32 blk_size;
535 } ASC_CAP_INFO;
536
537 typedef struct asc_cap_info_array {
538 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
539 } ASC_CAP_INFO_ARRAY;
540
541 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
542 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
543 #define ASC_CNTL_INITIATOR (ushort)0x0001
544 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
545 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
546 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
547 #define ASC_CNTL_NO_SCAM (ushort)0x0010
548 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
549 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
550 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
551 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
552 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
553 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
554 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
555 #define ASC_CNTL_BURST_MODE (ushort)0x2000
556 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
557 #define ASC_EEP_DVC_CFG_BEG_VL 2
558 #define ASC_EEP_MAX_DVC_ADDR_VL 15
559 #define ASC_EEP_DVC_CFG_BEG 32
560 #define ASC_EEP_MAX_DVC_ADDR 45
561 #define ASC_EEP_MAX_RETRY 20
562
563 /*
564 * These macros keep the chip SCSI id bitfields in board order. C bitfields
565 * aren't portable between big and little-endian platforms so they are not used.
566 */
567
568 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
569 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
570 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
571 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
572 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
573 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
574
575 typedef struct asceep_config {
576 ushort cfg_lsw;
577 ushort cfg_msw;
578 uchar init_sdtr;
579 uchar disc_enable;
580 uchar use_cmd_qng;
581 uchar start_motor;
582 uchar max_total_qng;
583 uchar max_tag_qng;
584 uchar bios_scan;
585 uchar power_up_wait;
586 uchar no_scam;
587 uchar id_speed; /* low order 4 bits is chip scsi id */
588 /* high order 4 bits is isa dma speed */
589 uchar dos_int13_table[ASC_MAX_TID + 1];
590 uchar adapter_info[6];
591 ushort cntl;
592 ushort chksum;
593 } ASCEEP_CONFIG;
594
595 #define ASC_EEP_CMD_READ 0x80
596 #define ASC_EEP_CMD_WRITE 0x40
597 #define ASC_EEP_CMD_WRITE_ABLE 0x30
598 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
599 #define ASCV_MSGOUT_BEG 0x0000
600 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
601 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
602 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
603 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
604 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
605 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
606 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
607 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
608 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
609 #define ASCV_BREAK_ADDR (ushort)0x0028
610 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
611 #define ASCV_BREAK_CONTROL (ushort)0x002C
612 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
613
614 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
615 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
616 #define ASCV_MCODE_SIZE_W (ushort)0x0034
617 #define ASCV_STOP_CODE_B (ushort)0x0036
618 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
619 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
620 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
621 #define ASCV_HALTCODE_W (ushort)0x0040
622 #define ASCV_CHKSUM_W (ushort)0x0042
623 #define ASCV_MC_DATE_W (ushort)0x0044
624 #define ASCV_MC_VER_W (ushort)0x0046
625 #define ASCV_NEXTRDY_B (ushort)0x0048
626 #define ASCV_DONENEXT_B (ushort)0x0049
627 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
628 #define ASCV_SCSIBUSY_B (ushort)0x004B
629 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
630 #define ASCV_CURCDB_B (ushort)0x004D
631 #define ASCV_RCLUN_B (ushort)0x004E
632 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
633 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
634 #define ASCV_DISC_ENABLE_B (ushort)0x0052
635 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
636 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
637 #define ASCV_MCODE_CNTL_B (ushort)0x0056
638 #define ASCV_NULL_TARGET_B (ushort)0x0057
639 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
640 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
641 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
642 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
643 #define ASCV_HOST_FLAG_B (ushort)0x005D
644 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
645 #define ASCV_VER_SERIAL_B (ushort)0x0065
646 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
647 #define ASCV_WTM_FLAG_B (ushort)0x0068
648 #define ASCV_RISC_FLAG_B (ushort)0x006A
649 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
650 #define ASC_HOST_FLAG_IN_ISR 0x01
651 #define ASC_HOST_FLAG_ACK_INT 0x02
652 #define ASC_RISC_FLAG_GEN_INT 0x01
653 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
654 #define IOP_CTRL (0x0F)
655 #define IOP_STATUS (0x0E)
656 #define IOP_INT_ACK IOP_STATUS
657 #define IOP_REG_IFC (0x0D)
658 #define IOP_SYN_OFFSET (0x0B)
659 #define IOP_EXTRA_CONTROL (0x0D)
660 #define IOP_REG_PC (0x0C)
661 #define IOP_RAM_ADDR (0x0A)
662 #define IOP_RAM_DATA (0x08)
663 #define IOP_EEP_DATA (0x06)
664 #define IOP_EEP_CMD (0x07)
665 #define IOP_VERSION (0x03)
666 #define IOP_CONFIG_HIGH (0x04)
667 #define IOP_CONFIG_LOW (0x02)
668 #define IOP_SIG_BYTE (0x01)
669 #define IOP_SIG_WORD (0x00)
670 #define IOP_REG_DC1 (0x0E)
671 #define IOP_REG_DC0 (0x0C)
672 #define IOP_REG_SB (0x0B)
673 #define IOP_REG_DA1 (0x0A)
674 #define IOP_REG_DA0 (0x08)
675 #define IOP_REG_SC (0x09)
676 #define IOP_DMA_SPEED (0x07)
677 #define IOP_REG_FLAG (0x07)
678 #define IOP_FIFO_H (0x06)
679 #define IOP_FIFO_L (0x04)
680 #define IOP_REG_ID (0x05)
681 #define IOP_REG_QP (0x03)
682 #define IOP_REG_IH (0x02)
683 #define IOP_REG_IX (0x01)
684 #define IOP_REG_AX (0x00)
685 #define IFC_REG_LOCK (0x00)
686 #define IFC_REG_UNLOCK (0x09)
687 #define IFC_WR_EN_FILTER (0x10)
688 #define IFC_RD_NO_EEPROM (0x10)
689 #define IFC_SLEW_RATE (0x20)
690 #define IFC_ACT_NEG (0x40)
691 #define IFC_INP_FILTER (0x80)
692 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
693 #define SC_SEL (uchar)(0x80)
694 #define SC_BSY (uchar)(0x40)
695 #define SC_ACK (uchar)(0x20)
696 #define SC_REQ (uchar)(0x10)
697 #define SC_ATN (uchar)(0x08)
698 #define SC_IO (uchar)(0x04)
699 #define SC_CD (uchar)(0x02)
700 #define SC_MSG (uchar)(0x01)
701 #define SEC_SCSI_CTL (uchar)(0x80)
702 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
703 #define SEC_SLEW_RATE (uchar)(0x20)
704 #define SEC_ENABLE_FILTER (uchar)(0x10)
705 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
706 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
707 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
708 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
709 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
710 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
711 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
712 #define ASC_MAX_QNO 0xF8
713 #define ASC_DATA_SEC_BEG (ushort)0x0080
714 #define ASC_DATA_SEC_END (ushort)0x0080
715 #define ASC_CODE_SEC_BEG (ushort)0x0080
716 #define ASC_CODE_SEC_END (ushort)0x0080
717 #define ASC_QADR_BEG (0x4000)
718 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
719 #define ASC_QADR_END (ushort)0x7FFF
720 #define ASC_QLAST_ADR (ushort)0x7FC0
721 #define ASC_QBLK_SIZE 0x40
722 #define ASC_BIOS_DATA_QBEG 0xF8
723 #define ASC_MIN_ACTIVE_QNO 0x01
724 #define ASC_QLINK_END 0xFF
725 #define ASC_EEPROM_WORDS 0x10
726 #define ASC_MAX_MGS_LEN 0x10
727 #define ASC_BIOS_ADDR_DEF 0xDC00
728 #define ASC_BIOS_SIZE 0x3800
729 #define ASC_BIOS_RAM_OFF 0x3800
730 #define ASC_BIOS_RAM_SIZE 0x800
731 #define ASC_BIOS_MIN_ADDR 0xC000
732 #define ASC_BIOS_MAX_ADDR 0xEC00
733 #define ASC_BIOS_BANK_SIZE 0x0400
734 #define ASC_MCODE_START_ADDR 0x0080
735 #define ASC_CFG0_HOST_INT_ON 0x0020
736 #define ASC_CFG0_BIOS_ON 0x0040
737 #define ASC_CFG0_VERA_BURST_ON 0x0080
738 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
739 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
740 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
741 #define ASC_CFG_MSW_CLR_MASK 0x3080
742 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
743 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
744 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
745 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
746 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
747 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
748 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
749 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
750 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
751 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
752 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
753 #define CSW_HALTED (ASC_CS_TYPE)0x0010
754 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
755 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
756 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
757 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
758 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
759 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
760 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
761 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
762 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
763 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
764 #define CC_CHIP_RESET (uchar)0x80
765 #define CC_SCSI_RESET (uchar)0x40
766 #define CC_HALT (uchar)0x20
767 #define CC_SINGLE_STEP (uchar)0x10
768 #define CC_DMA_ABLE (uchar)0x08
769 #define CC_TEST (uchar)0x04
770 #define CC_BANK_ONE (uchar)0x02
771 #define CC_DIAG (uchar)0x01
772 #define ASC_1000_ID0W 0x04C1
773 #define ASC_1000_ID0W_FIX 0x00C1
774 #define ASC_1000_ID1B 0x25
775 #define ASC_EISA_REV_IOP_MASK (0x0C83)
776 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
777 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
778 #define INS_HALTINT (ushort)0x6281
779 #define INS_HALT (ushort)0x6280
780 #define INS_SINT (ushort)0x6200
781 #define INS_RFLAG_WTM (ushort)0x7380
782 #define ASC_MC_SAVE_CODE_WSIZE 0x500
783 #define ASC_MC_SAVE_DATA_WSIZE 0x40
784
785 typedef struct asc_mc_saved {
786 ushort data[ASC_MC_SAVE_DATA_WSIZE];
787 ushort code[ASC_MC_SAVE_CODE_WSIZE];
788 } ASC_MC_SAVED;
789
790 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
791 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
792 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
793 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
794 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
795 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
796 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
797 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
798 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
799 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
800 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
801 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
802 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
803 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
804 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
805 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
806 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
807 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
808 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
809 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
810 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
811 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
812 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
813 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
814 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
815 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
816 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
817 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
818 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
819 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
820 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
821 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
822 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
823 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
824 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
825 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
826 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
827 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
828 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
829 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
830 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
831 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
832 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
833 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
834 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
835 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
836 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
837 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
838 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
839 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
840 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
841 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
842 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
843 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
844 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
845 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
846 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
847 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
848 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
849 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
850 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
851 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
852 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
853 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
854 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
855 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
856 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
857
858 #define AdvPortAddr void __iomem * /* Virtual memory address size */
859
860 /*
861 * Define Adv Library required memory access macros.
862 */
863 #define ADV_MEM_READB(addr) readb(addr)
864 #define ADV_MEM_READW(addr) readw(addr)
865 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
866 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
867 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
868
869 /*
870 * Define total number of simultaneous maximum element scatter-gather
871 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
872 * maximum number of outstanding commands per wide host adapter. Each
873 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
874 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
875 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
876 * structures or 255 scatter-gather elements.
877 */
878 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
879
880 /*
881 * Define maximum number of scatter-gather elements per request.
882 */
883 #define ADV_MAX_SG_LIST 255
884 #define NO_OF_SG_PER_BLOCK 15
885
886 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
887 #define ADV_EEP_DVC_CFG_END (0x15)
888 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
889 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
890
891 #define ADV_EEP_DELAY_MS 100
892
893 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
894 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
895 /*
896 * For the ASC3550 Bit 13 is Termination Polarity control bit.
897 * For later ICs Bit 13 controls whether the CIS (Card Information
898 * Service Section) is loaded from EEPROM.
899 */
900 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
901 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
902 /*
903 * ASC38C1600 Bit 11
904 *
905 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
906 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
907 * Function 0 will specify INT B.
908 *
909 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
910 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
911 * Function 1 will specify INT A.
912 */
913 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
914
915 typedef struct adveep_3550_config {
916 /* Word Offset, Description */
917
918 ushort cfg_lsw; /* 00 power up initialization */
919 /* bit 13 set - Term Polarity Control */
920 /* bit 14 set - BIOS Enable */
921 /* bit 15 set - Big Endian Mode */
922 ushort cfg_msw; /* 01 unused */
923 ushort disc_enable; /* 02 disconnect enable */
924 ushort wdtr_able; /* 03 Wide DTR able */
925 ushort sdtr_able; /* 04 Synchronous DTR able */
926 ushort start_motor; /* 05 send start up motor */
927 ushort tagqng_able; /* 06 tag queuing able */
928 ushort bios_scan; /* 07 BIOS device control */
929 ushort scam_tolerant; /* 08 no scam */
930
931 uchar adapter_scsi_id; /* 09 Host Adapter ID */
932 uchar bios_boot_delay; /* power up wait */
933
934 uchar scsi_reset_delay; /* 10 reset delay */
935 uchar bios_id_lun; /* first boot device scsi id & lun */
936 /* high nibble is lun */
937 /* low nibble is scsi id */
938
939 uchar termination; /* 11 0 - automatic */
940 /* 1 - low off / high off */
941 /* 2 - low off / high on */
942 /* 3 - low on / high on */
943 /* There is no low on / high off */
944
945 uchar reserved1; /* reserved byte (not used) */
946
947 ushort bios_ctrl; /* 12 BIOS control bits */
948 /* bit 0 BIOS don't act as initiator. */
949 /* bit 1 BIOS > 1 GB support */
950 /* bit 2 BIOS > 2 Disk Support */
951 /* bit 3 BIOS don't support removables */
952 /* bit 4 BIOS support bootable CD */
953 /* bit 5 BIOS scan enabled */
954 /* bit 6 BIOS support multiple LUNs */
955 /* bit 7 BIOS display of message */
956 /* bit 8 SCAM disabled */
957 /* bit 9 Reset SCSI bus during init. */
958 /* bit 10 */
959 /* bit 11 No verbose initialization. */
960 /* bit 12 SCSI parity enabled */
961 /* bit 13 */
962 /* bit 14 */
963 /* bit 15 */
964 ushort ultra_able; /* 13 ULTRA speed able */
965 ushort reserved2; /* 14 reserved */
966 uchar max_host_qng; /* 15 maximum host queuing */
967 uchar max_dvc_qng; /* maximum per device queuing */
968 ushort dvc_cntl; /* 16 control bit for driver */
969 ushort bug_fix; /* 17 control bit for bug fix */
970 ushort serial_number_word1; /* 18 Board serial number word 1 */
971 ushort serial_number_word2; /* 19 Board serial number word 2 */
972 ushort serial_number_word3; /* 20 Board serial number word 3 */
973 ushort check_sum; /* 21 EEP check sum */
974 uchar oem_name[16]; /* 22 OEM name */
975 ushort dvc_err_code; /* 30 last device driver error code */
976 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
977 ushort adv_err_addr; /* 32 last uc error address */
978 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
979 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
980 ushort saved_adv_err_addr; /* 35 saved last uc error address */
981 ushort num_of_err; /* 36 number of error */
982 } ADVEEP_3550_CONFIG;
983
984 typedef struct adveep_38C0800_config {
985 /* Word Offset, Description */
986
987 ushort cfg_lsw; /* 00 power up initialization */
988 /* bit 13 set - Load CIS */
989 /* bit 14 set - BIOS Enable */
990 /* bit 15 set - Big Endian Mode */
991 ushort cfg_msw; /* 01 unused */
992 ushort disc_enable; /* 02 disconnect enable */
993 ushort wdtr_able; /* 03 Wide DTR able */
994 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
995 ushort start_motor; /* 05 send start up motor */
996 ushort tagqng_able; /* 06 tag queuing able */
997 ushort bios_scan; /* 07 BIOS device control */
998 ushort scam_tolerant; /* 08 no scam */
999
1000 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1001 uchar bios_boot_delay; /* power up wait */
1002
1003 uchar scsi_reset_delay; /* 10 reset delay */
1004 uchar bios_id_lun; /* first boot device scsi id & lun */
1005 /* high nibble is lun */
1006 /* low nibble is scsi id */
1007
1008 uchar termination_se; /* 11 0 - automatic */
1009 /* 1 - low off / high off */
1010 /* 2 - low off / high on */
1011 /* 3 - low on / high on */
1012 /* There is no low on / high off */
1013
1014 uchar termination_lvd; /* 11 0 - automatic */
1015 /* 1 - low off / high off */
1016 /* 2 - low off / high on */
1017 /* 3 - low on / high on */
1018 /* There is no low on / high off */
1019
1020 ushort bios_ctrl; /* 12 BIOS control bits */
1021 /* bit 0 BIOS don't act as initiator. */
1022 /* bit 1 BIOS > 1 GB support */
1023 /* bit 2 BIOS > 2 Disk Support */
1024 /* bit 3 BIOS don't support removables */
1025 /* bit 4 BIOS support bootable CD */
1026 /* bit 5 BIOS scan enabled */
1027 /* bit 6 BIOS support multiple LUNs */
1028 /* bit 7 BIOS display of message */
1029 /* bit 8 SCAM disabled */
1030 /* bit 9 Reset SCSI bus during init. */
1031 /* bit 10 */
1032 /* bit 11 No verbose initialization. */
1033 /* bit 12 SCSI parity enabled */
1034 /* bit 13 */
1035 /* bit 14 */
1036 /* bit 15 */
1037 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1038 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1039 uchar max_host_qng; /* 15 maximum host queueing */
1040 uchar max_dvc_qng; /* maximum per device queuing */
1041 ushort dvc_cntl; /* 16 control bit for driver */
1042 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1043 ushort serial_number_word1; /* 18 Board serial number word 1 */
1044 ushort serial_number_word2; /* 19 Board serial number word 2 */
1045 ushort serial_number_word3; /* 20 Board serial number word 3 */
1046 ushort check_sum; /* 21 EEP check sum */
1047 uchar oem_name[16]; /* 22 OEM name */
1048 ushort dvc_err_code; /* 30 last device driver error code */
1049 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1050 ushort adv_err_addr; /* 32 last uc error address */
1051 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1052 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1053 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1054 ushort reserved36; /* 36 reserved */
1055 ushort reserved37; /* 37 reserved */
1056 ushort reserved38; /* 38 reserved */
1057 ushort reserved39; /* 39 reserved */
1058 ushort reserved40; /* 40 reserved */
1059 ushort reserved41; /* 41 reserved */
1060 ushort reserved42; /* 42 reserved */
1061 ushort reserved43; /* 43 reserved */
1062 ushort reserved44; /* 44 reserved */
1063 ushort reserved45; /* 45 reserved */
1064 ushort reserved46; /* 46 reserved */
1065 ushort reserved47; /* 47 reserved */
1066 ushort reserved48; /* 48 reserved */
1067 ushort reserved49; /* 49 reserved */
1068 ushort reserved50; /* 50 reserved */
1069 ushort reserved51; /* 51 reserved */
1070 ushort reserved52; /* 52 reserved */
1071 ushort reserved53; /* 53 reserved */
1072 ushort reserved54; /* 54 reserved */
1073 ushort reserved55; /* 55 reserved */
1074 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1075 ushort cisprt_msw; /* 57 CIS PTR MSW */
1076 ushort subsysvid; /* 58 SubSystem Vendor ID */
1077 ushort subsysid; /* 59 SubSystem ID */
1078 ushort reserved60; /* 60 reserved */
1079 ushort reserved61; /* 61 reserved */
1080 ushort reserved62; /* 62 reserved */
1081 ushort reserved63; /* 63 reserved */
1082 } ADVEEP_38C0800_CONFIG;
1083
1084 typedef struct adveep_38C1600_config {
1085 /* Word Offset, Description */
1086
1087 ushort cfg_lsw; /* 00 power up initialization */
1088 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1089 /* clear - Func. 0 INTA, Func. 1 INTB */
1090 /* bit 13 set - Load CIS */
1091 /* bit 14 set - BIOS Enable */
1092 /* bit 15 set - Big Endian Mode */
1093 ushort cfg_msw; /* 01 unused */
1094 ushort disc_enable; /* 02 disconnect enable */
1095 ushort wdtr_able; /* 03 Wide DTR able */
1096 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1097 ushort start_motor; /* 05 send start up motor */
1098 ushort tagqng_able; /* 06 tag queuing able */
1099 ushort bios_scan; /* 07 BIOS device control */
1100 ushort scam_tolerant; /* 08 no scam */
1101
1102 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1103 uchar bios_boot_delay; /* power up wait */
1104
1105 uchar scsi_reset_delay; /* 10 reset delay */
1106 uchar bios_id_lun; /* first boot device scsi id & lun */
1107 /* high nibble is lun */
1108 /* low nibble is scsi id */
1109
1110 uchar termination_se; /* 11 0 - automatic */
1111 /* 1 - low off / high off */
1112 /* 2 - low off / high on */
1113 /* 3 - low on / high on */
1114 /* There is no low on / high off */
1115
1116 uchar termination_lvd; /* 11 0 - automatic */
1117 /* 1 - low off / high off */
1118 /* 2 - low off / high on */
1119 /* 3 - low on / high on */
1120 /* There is no low on / high off */
1121
1122 ushort bios_ctrl; /* 12 BIOS control bits */
1123 /* bit 0 BIOS don't act as initiator. */
1124 /* bit 1 BIOS > 1 GB support */
1125 /* bit 2 BIOS > 2 Disk Support */
1126 /* bit 3 BIOS don't support removables */
1127 /* bit 4 BIOS support bootable CD */
1128 /* bit 5 BIOS scan enabled */
1129 /* bit 6 BIOS support multiple LUNs */
1130 /* bit 7 BIOS display of message */
1131 /* bit 8 SCAM disabled */
1132 /* bit 9 Reset SCSI bus during init. */
1133 /* bit 10 Basic Integrity Checking disabled */
1134 /* bit 11 No verbose initialization. */
1135 /* bit 12 SCSI parity enabled */
1136 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1137 /* bit 14 */
1138 /* bit 15 */
1139 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1140 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1141 uchar max_host_qng; /* 15 maximum host queueing */
1142 uchar max_dvc_qng; /* maximum per device queuing */
1143 ushort dvc_cntl; /* 16 control bit for driver */
1144 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1145 ushort serial_number_word1; /* 18 Board serial number word 1 */
1146 ushort serial_number_word2; /* 19 Board serial number word 2 */
1147 ushort serial_number_word3; /* 20 Board serial number word 3 */
1148 ushort check_sum; /* 21 EEP check sum */
1149 uchar oem_name[16]; /* 22 OEM name */
1150 ushort dvc_err_code; /* 30 last device driver error code */
1151 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1152 ushort adv_err_addr; /* 32 last uc error address */
1153 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1154 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1155 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1156 ushort reserved36; /* 36 reserved */
1157 ushort reserved37; /* 37 reserved */
1158 ushort reserved38; /* 38 reserved */
1159 ushort reserved39; /* 39 reserved */
1160 ushort reserved40; /* 40 reserved */
1161 ushort reserved41; /* 41 reserved */
1162 ushort reserved42; /* 42 reserved */
1163 ushort reserved43; /* 43 reserved */
1164 ushort reserved44; /* 44 reserved */
1165 ushort reserved45; /* 45 reserved */
1166 ushort reserved46; /* 46 reserved */
1167 ushort reserved47; /* 47 reserved */
1168 ushort reserved48; /* 48 reserved */
1169 ushort reserved49; /* 49 reserved */
1170 ushort reserved50; /* 50 reserved */
1171 ushort reserved51; /* 51 reserved */
1172 ushort reserved52; /* 52 reserved */
1173 ushort reserved53; /* 53 reserved */
1174 ushort reserved54; /* 54 reserved */
1175 ushort reserved55; /* 55 reserved */
1176 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1177 ushort cisprt_msw; /* 57 CIS PTR MSW */
1178 ushort subsysvid; /* 58 SubSystem Vendor ID */
1179 ushort subsysid; /* 59 SubSystem ID */
1180 ushort reserved60; /* 60 reserved */
1181 ushort reserved61; /* 61 reserved */
1182 ushort reserved62; /* 62 reserved */
1183 ushort reserved63; /* 63 reserved */
1184 } ADVEEP_38C1600_CONFIG;
1185
1186 /*
1187 * EEPROM Commands
1188 */
1189 #define ASC_EEP_CMD_DONE 0x0200
1190
1191 /* bios_ctrl */
1192 #define BIOS_CTRL_BIOS 0x0001
1193 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
1194 #define BIOS_CTRL_GT_2_DISK 0x0004
1195 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1196 #define BIOS_CTRL_BOOTABLE_CD 0x0010
1197 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
1198 #define BIOS_CTRL_DISPLAY_MSG 0x0080
1199 #define BIOS_CTRL_NO_SCAM 0x0100
1200 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1201 #define BIOS_CTRL_INIT_VERBOSE 0x0800
1202 #define BIOS_CTRL_SCSI_PARITY 0x1000
1203 #define BIOS_CTRL_AIPP_DIS 0x2000
1204
1205 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1206
1207 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1208
1209 /*
1210 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1211 * a special 16K Adv Library and Microcode version. After the issue is
1212 * resolved, should restore 32K support.
1213 *
1214 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1215 */
1216 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1217
1218 /*
1219 * Byte I/O register address from base of 'iop_base'.
1220 */
1221 #define IOPB_INTR_STATUS_REG 0x00
1222 #define IOPB_CHIP_ID_1 0x01
1223 #define IOPB_INTR_ENABLES 0x02
1224 #define IOPB_CHIP_TYPE_REV 0x03
1225 #define IOPB_RES_ADDR_4 0x04
1226 #define IOPB_RES_ADDR_5 0x05
1227 #define IOPB_RAM_DATA 0x06
1228 #define IOPB_RES_ADDR_7 0x07
1229 #define IOPB_FLAG_REG 0x08
1230 #define IOPB_RES_ADDR_9 0x09
1231 #define IOPB_RISC_CSR 0x0A
1232 #define IOPB_RES_ADDR_B 0x0B
1233 #define IOPB_RES_ADDR_C 0x0C
1234 #define IOPB_RES_ADDR_D 0x0D
1235 #define IOPB_SOFT_OVER_WR 0x0E
1236 #define IOPB_RES_ADDR_F 0x0F
1237 #define IOPB_MEM_CFG 0x10
1238 #define IOPB_RES_ADDR_11 0x11
1239 #define IOPB_GPIO_DATA 0x12
1240 #define IOPB_RES_ADDR_13 0x13
1241 #define IOPB_FLASH_PAGE 0x14
1242 #define IOPB_RES_ADDR_15 0x15
1243 #define IOPB_GPIO_CNTL 0x16
1244 #define IOPB_RES_ADDR_17 0x17
1245 #define IOPB_FLASH_DATA 0x18
1246 #define IOPB_RES_ADDR_19 0x19
1247 #define IOPB_RES_ADDR_1A 0x1A
1248 #define IOPB_RES_ADDR_1B 0x1B
1249 #define IOPB_RES_ADDR_1C 0x1C
1250 #define IOPB_RES_ADDR_1D 0x1D
1251 #define IOPB_RES_ADDR_1E 0x1E
1252 #define IOPB_RES_ADDR_1F 0x1F
1253 #define IOPB_DMA_CFG0 0x20
1254 #define IOPB_DMA_CFG1 0x21
1255 #define IOPB_TICKLE 0x22
1256 #define IOPB_DMA_REG_WR 0x23
1257 #define IOPB_SDMA_STATUS 0x24
1258 #define IOPB_SCSI_BYTE_CNT 0x25
1259 #define IOPB_HOST_BYTE_CNT 0x26
1260 #define IOPB_BYTE_LEFT_TO_XFER 0x27
1261 #define IOPB_BYTE_TO_XFER_0 0x28
1262 #define IOPB_BYTE_TO_XFER_1 0x29
1263 #define IOPB_BYTE_TO_XFER_2 0x2A
1264 #define IOPB_BYTE_TO_XFER_3 0x2B
1265 #define IOPB_ACC_GRP 0x2C
1266 #define IOPB_RES_ADDR_2D 0x2D
1267 #define IOPB_DEV_ID 0x2E
1268 #define IOPB_RES_ADDR_2F 0x2F
1269 #define IOPB_SCSI_DATA 0x30
1270 #define IOPB_RES_ADDR_31 0x31
1271 #define IOPB_RES_ADDR_32 0x32
1272 #define IOPB_SCSI_DATA_HSHK 0x33
1273 #define IOPB_SCSI_CTRL 0x34
1274 #define IOPB_RES_ADDR_35 0x35
1275 #define IOPB_RES_ADDR_36 0x36
1276 #define IOPB_RES_ADDR_37 0x37
1277 #define IOPB_RAM_BIST 0x38
1278 #define IOPB_PLL_TEST 0x39
1279 #define IOPB_PCI_INT_CFG 0x3A
1280 #define IOPB_RES_ADDR_3B 0x3B
1281 #define IOPB_RFIFO_CNT 0x3C
1282 #define IOPB_RES_ADDR_3D 0x3D
1283 #define IOPB_RES_ADDR_3E 0x3E
1284 #define IOPB_RES_ADDR_3F 0x3F
1285
1286 /*
1287 * Word I/O register address from base of 'iop_base'.
1288 */
1289 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
1290 #define IOPW_CTRL_REG 0x02 /* CC */
1291 #define IOPW_RAM_ADDR 0x04 /* LA */
1292 #define IOPW_RAM_DATA 0x06 /* LD */
1293 #define IOPW_RES_ADDR_08 0x08
1294 #define IOPW_RISC_CSR 0x0A /* CSR */
1295 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1296 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1297 #define IOPW_RES_ADDR_10 0x10
1298 #define IOPW_SEL_MASK 0x12 /* SM */
1299 #define IOPW_RES_ADDR_14 0x14
1300 #define IOPW_FLASH_ADDR 0x16 /* FA */
1301 #define IOPW_RES_ADDR_18 0x18
1302 #define IOPW_EE_CMD 0x1A /* EC */
1303 #define IOPW_EE_DATA 0x1C /* ED */
1304 #define IOPW_SFIFO_CNT 0x1E /* SFC */
1305 #define IOPW_RES_ADDR_20 0x20
1306 #define IOPW_Q_BASE 0x22 /* QB */
1307 #define IOPW_QP 0x24 /* QP */
1308 #define IOPW_IX 0x26 /* IX */
1309 #define IOPW_SP 0x28 /* SP */
1310 #define IOPW_PC 0x2A /* PC */
1311 #define IOPW_RES_ADDR_2C 0x2C
1312 #define IOPW_RES_ADDR_2E 0x2E
1313 #define IOPW_SCSI_DATA 0x30 /* SD */
1314 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1315 #define IOPW_SCSI_CTRL 0x34 /* SC */
1316 #define IOPW_HSHK_CFG 0x36 /* HCFG */
1317 #define IOPW_SXFR_STATUS 0x36 /* SXS */
1318 #define IOPW_SXFR_CNTL 0x38 /* SXL */
1319 #define IOPW_SXFR_CNTH 0x3A /* SXH */
1320 #define IOPW_RES_ADDR_3C 0x3C
1321 #define IOPW_RFIFO_DATA 0x3E /* RFD */
1322
1323 /*
1324 * Doubleword I/O register address from base of 'iop_base'.
1325 */
1326 #define IOPDW_RES_ADDR_0 0x00
1327 #define IOPDW_RAM_DATA 0x04
1328 #define IOPDW_RES_ADDR_8 0x08
1329 #define IOPDW_RES_ADDR_C 0x0C
1330 #define IOPDW_RES_ADDR_10 0x10
1331 #define IOPDW_COMMA 0x14
1332 #define IOPDW_COMMB 0x18
1333 #define IOPDW_RES_ADDR_1C 0x1C
1334 #define IOPDW_SDMA_ADDR0 0x20
1335 #define IOPDW_SDMA_ADDR1 0x24
1336 #define IOPDW_SDMA_COUNT 0x28
1337 #define IOPDW_SDMA_ERROR 0x2C
1338 #define IOPDW_RDMA_ADDR0 0x30
1339 #define IOPDW_RDMA_ADDR1 0x34
1340 #define IOPDW_RDMA_COUNT 0x38
1341 #define IOPDW_RDMA_ERROR 0x3C
1342
1343 #define ADV_CHIP_ID_BYTE 0x25
1344 #define ADV_CHIP_ID_WORD 0x04C1
1345
1346 #define ADV_INTR_ENABLE_HOST_INTR 0x01
1347 #define ADV_INTR_ENABLE_SEL_INTR 0x02
1348 #define ADV_INTR_ENABLE_DPR_INTR 0x04
1349 #define ADV_INTR_ENABLE_RTA_INTR 0x08
1350 #define ADV_INTR_ENABLE_RMA_INTR 0x10
1351 #define ADV_INTR_ENABLE_RST_INTR 0x20
1352 #define ADV_INTR_ENABLE_DPE_INTR 0x40
1353 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1354
1355 #define ADV_INTR_STATUS_INTRA 0x01
1356 #define ADV_INTR_STATUS_INTRB 0x02
1357 #define ADV_INTR_STATUS_INTRC 0x04
1358
1359 #define ADV_RISC_CSR_STOP (0x0000)
1360 #define ADV_RISC_TEST_COND (0x2000)
1361 #define ADV_RISC_CSR_RUN (0x4000)
1362 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1363
1364 #define ADV_CTRL_REG_HOST_INTR 0x0100
1365 #define ADV_CTRL_REG_SEL_INTR 0x0200
1366 #define ADV_CTRL_REG_DPR_INTR 0x0400
1367 #define ADV_CTRL_REG_RTA_INTR 0x0800
1368 #define ADV_CTRL_REG_RMA_INTR 0x1000
1369 #define ADV_CTRL_REG_RES_BIT14 0x2000
1370 #define ADV_CTRL_REG_DPE_INTR 0x4000
1371 #define ADV_CTRL_REG_POWER_DONE 0x8000
1372 #define ADV_CTRL_REG_ANY_INTR 0xFF00
1373
1374 #define ADV_CTRL_REG_CMD_RESET 0x00C6
1375 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1376 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1377 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1378 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1379
1380 #define ADV_TICKLE_NOP 0x00
1381 #define ADV_TICKLE_A 0x01
1382 #define ADV_TICKLE_B 0x02
1383 #define ADV_TICKLE_C 0x03
1384
1385 #define AdvIsIntPending(port) \
1386 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1387
1388 /*
1389 * SCSI_CFG0 Register bit definitions
1390 */
1391 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1392 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1393 #define EVEN_PARITY 0x1000 /* Select Even Parity */
1394 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1395 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1396 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1397 #define SCAM_EN 0x0080 /* Enable SCAM selection */
1398 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1399 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1400 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1401 #define OUR_ID 0x000F /* SCSI ID */
1402
1403 /*
1404 * SCSI_CFG1 Register bit definitions
1405 */
1406 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1407 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1408 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1409 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
1410 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1411 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1412 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1413 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1414 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1415 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1416 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1417 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1418 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1419 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1420 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1421
1422 /*
1423 * Addendum for ASC-38C0800 Chip
1424 *
1425 * The ASC-38C1600 Chip uses the same definitions except that the
1426 * bus mode override bits [12:10] have been moved to byte register
1427 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1428 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1429 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1430 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1431 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1432 */
1433 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1434 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1435 #define HVD 0x1000 /* HVD Device Detect */
1436 #define LVD 0x0800 /* LVD Device Detect */
1437 #define SE 0x0400 /* SE Device Detect */
1438 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
1439 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1440 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1441 #define TERM_SE 0x0030 /* SE Termination Bits */
1442 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1443 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1444 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1445 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1446 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1447 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1448 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1449 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1450
1451 #define CABLE_ILLEGAL_A 0x7
1452 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1453
1454 #define CABLE_ILLEGAL_B 0xB
1455 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1456
1457 /*
1458 * MEM_CFG Register bit definitions
1459 */
1460 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1461 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1462 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1463 #define RAM_SZ_2KB 0x00 /* 2 KB */
1464 #define RAM_SZ_4KB 0x04 /* 4 KB */
1465 #define RAM_SZ_8KB 0x08 /* 8 KB */
1466 #define RAM_SZ_16KB 0x0C /* 16 KB */
1467 #define RAM_SZ_32KB 0x10 /* 32 KB */
1468 #define RAM_SZ_64KB 0x14 /* 64 KB */
1469
1470 /*
1471 * DMA_CFG0 Register bit definitions
1472 *
1473 * This register is only accessible to the host.
1474 */
1475 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1476 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1477 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
1478 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
1479 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
1480 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
1481 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1482 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
1483 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
1484 #define START_CTL 0x0C /* DMA start conditions */
1485 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
1486 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1487 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1488 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1489 #define READ_CMD 0x03 /* Memory Read Method */
1490 #define READ_CMD_MR 0x00 /* Memory Read */
1491 #define READ_CMD_MRL 0x02 /* Memory Read Long */
1492 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1493
1494 /*
1495 * ASC-38C0800 RAM BIST Register bit definitions
1496 */
1497 #define RAM_TEST_MODE 0x80
1498 #define PRE_TEST_MODE 0x40
1499 #define NORMAL_MODE 0x00
1500 #define RAM_TEST_DONE 0x10
1501 #define RAM_TEST_STATUS 0x0F
1502 #define RAM_TEST_HOST_ERROR 0x08
1503 #define RAM_TEST_INTRAM_ERROR 0x04
1504 #define RAM_TEST_RISC_ERROR 0x02
1505 #define RAM_TEST_SCSI_ERROR 0x01
1506 #define RAM_TEST_SUCCESS 0x00
1507 #define PRE_TEST_VALUE 0x05
1508 #define NORMAL_VALUE 0x00
1509
1510 /*
1511 * ASC38C1600 Definitions
1512 *
1513 * IOPB_PCI_INT_CFG Bit Field Definitions
1514 */
1515
1516 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1517
1518 /*
1519 * Bit 1 can be set to change the interrupt for the Function to operate in
1520 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1521 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1522 * mode, otherwise the operating mode is undefined.
1523 */
1524 #define TOTEMPOLE 0x02
1525
1526 /*
1527 * Bit 0 can be used to change the Int Pin for the Function. The value is
1528 * 0 by default for both Functions with Function 0 using INT A and Function
1529 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1530 * INT A is used.
1531 *
1532 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1533 * value specified in the PCI Configuration Space.
1534 */
1535 #define INTAB 0x01
1536
1537 /*
1538 * Adv Library Status Definitions
1539 */
1540 #define ADV_TRUE 1
1541 #define ADV_FALSE 0
1542 #define ADV_SUCCESS 1
1543 #define ADV_BUSY 0
1544 #define ADV_ERROR (-1)
1545
1546 /*
1547 * ADV_DVC_VAR 'warn_code' values
1548 */
1549 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1550 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1551 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
1552 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1553
1554 #define ADV_MAX_TID 15 /* max. target identifier */
1555 #define ADV_MAX_LUN 7 /* max. logical unit number */
1556
1557 /*
1558 * Fixed locations of microcode operating variables.
1559 */
1560 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1561 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1562 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1563 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1564 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1565 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1566 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1567 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1568 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1569 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1570 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1571 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1572 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1573 #define ASC_MC_CHIP_TYPE 0x009A
1574 #define ASC_MC_INTRB_CODE 0x009B
1575 #define ASC_MC_WDTR_ABLE 0x009C
1576 #define ASC_MC_SDTR_ABLE 0x009E
1577 #define ASC_MC_TAGQNG_ABLE 0x00A0
1578 #define ASC_MC_DISC_ENABLE 0x00A2
1579 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
1580 #define ASC_MC_IDLE_CMD 0x00A6
1581 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1582 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1583 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1584 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1585 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1586 #define ASC_MC_SDTR_DONE 0x00B6
1587 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1588 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1589 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
1590 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1591 #define ASC_MC_WDTR_DONE 0x0124
1592 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1593 #define ASC_MC_ICQ 0x0160
1594 #define ASC_MC_IRQ 0x0164
1595 #define ASC_MC_PPR_ABLE 0x017A
1596
1597 /*
1598 * BIOS LRAM variable absolute offsets.
1599 */
1600 #define BIOS_CODESEG 0x54
1601 #define BIOS_CODELEN 0x56
1602 #define BIOS_SIGNATURE 0x58
1603 #define BIOS_VERSION 0x5A
1604
1605 /*
1606 * Microcode Control Flags
1607 *
1608 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1609 * and handled by the microcode.
1610 */
1611 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1612 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1613
1614 /*
1615 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1616 */
1617 #define HSHK_CFG_WIDE_XFR 0x8000
1618 #define HSHK_CFG_RATE 0x0F00
1619 #define HSHK_CFG_OFFSET 0x001F
1620
1621 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1622 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1623 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1624 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1625
1626 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1627 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1628 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1629 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1630 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1631
1632 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1633 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1634 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1635 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1636 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1637 /*
1638 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1639 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1640 */
1641 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1642 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1643
1644 /*
1645 * All fields here are accessed by the board microcode and need to be
1646 * little-endian.
1647 */
1648 typedef struct adv_carr_t {
1649 __le32 carr_va; /* Carrier Virtual Address */
1650 __le32 carr_pa; /* Carrier Physical Address */
1651 __le32 areq_vpa; /* ADV_SCSI_REQ_Q Virtual or Physical Address */
1652 /*
1653 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1654 *
1655 * next_vpa [3:1] Reserved Bits
1656 * next_vpa [0] Done Flag set in Response Queue.
1657 */
1658 __le32 next_vpa;
1659 } ADV_CARR_T;
1660
1661 /*
1662 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1663 */
1664 #define ADV_NEXT_VPA_MASK 0xFFFFFFF0
1665
1666 #define ADV_RQ_DONE 0x00000001
1667 #define ADV_RQ_GOOD 0x00000002
1668 #define ADV_CQ_STOPPER 0x00000000
1669
1670 #define ADV_GET_CARRP(carrp) ((carrp) & ADV_NEXT_VPA_MASK)
1671
1672 /*
1673 * Each carrier is 64 bytes, and we need three additional
1674 * carrier for icq, irq, and the termination carrier.
1675 */
1676 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 3)
1677
1678 #define ADV_CARRIER_BUFSIZE \
1679 (ADV_CARRIER_COUNT * sizeof(ADV_CARR_T))
1680
1681 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1682 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1683 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1684
1685 /*
1686 * Adapter temporary configuration structure
1687 *
1688 * This structure can be discarded after initialization. Don't add
1689 * fields here needed after initialization.
1690 *
1691 * Field naming convention:
1692 *
1693 * *_enable indicates the field enables or disables a feature. The
1694 * value of the field is never reset.
1695 */
1696 typedef struct adv_dvc_cfg {
1697 ushort disc_enable; /* enable disconnection */
1698 uchar chip_version; /* chip version */
1699 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1700 ushort control_flag; /* Microcode Control Flag */
1701 ushort mcode_date; /* Microcode date */
1702 ushort mcode_version; /* Microcode version */
1703 ushort serial1; /* EEPROM serial number word 1 */
1704 ushort serial2; /* EEPROM serial number word 2 */
1705 ushort serial3; /* EEPROM serial number word 3 */
1706 } ADV_DVC_CFG;
1707
1708 struct adv_dvc_var;
1709 struct adv_scsi_req_q;
1710
1711 typedef struct adv_sg_block {
1712 uchar reserved1;
1713 uchar reserved2;
1714 uchar reserved3;
1715 uchar sg_cnt; /* Valid entries in block. */
1716 __le32 sg_ptr; /* Pointer to next sg block. */
1717 struct {
1718 __le32 sg_addr; /* SG element address. */
1719 __le32 sg_count; /* SG element count. */
1720 } sg_list[NO_OF_SG_PER_BLOCK];
1721 } ADV_SG_BLOCK;
1722
1723 /*
1724 * ADV_SCSI_REQ_Q - microcode request structure
1725 *
1726 * All fields in this structure up to byte 60 are used by the microcode.
1727 * The microcode makes assumptions about the size and ordering of fields
1728 * in this structure. Do not change the structure definition here without
1729 * coordinating the change with the microcode.
1730 *
1731 * All fields accessed by microcode must be maintained in little_endian
1732 * order.
1733 */
1734 typedef struct adv_scsi_req_q {
1735 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1736 uchar target_cmd;
1737 uchar target_id; /* Device target identifier. */
1738 uchar target_lun; /* Device target logical unit number. */
1739 __le32 data_addr; /* Data buffer physical address. */
1740 __le32 data_cnt; /* Data count. Ucode sets to residual. */
1741 __le32 sense_addr;
1742 __le32 carr_pa;
1743 uchar mflag;
1744 uchar sense_len;
1745 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1746 uchar scsi_cntl;
1747 uchar done_status; /* Completion status. */
1748 uchar scsi_status; /* SCSI status byte. */
1749 uchar host_status; /* Ucode host status. */
1750 uchar sg_working_ix;
1751 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1752 __le32 sg_real_addr; /* SG list physical address. */
1753 __le32 scsiq_rptr;
1754 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1755 __le32 scsiq_ptr;
1756 __le32 carr_va;
1757 /*
1758 * End of microcode structure - 60 bytes. The rest of the structure
1759 * is used by the Adv Library and ignored by the microcode.
1760 */
1761 u32 srb_tag;
1762 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1763 } ADV_SCSI_REQ_Q;
1764
1765 /*
1766 * The following two structures are used to process Wide Board requests.
1767 *
1768 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1769 * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the
1770 * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points
1771 * to the Mid-Level SCSI request structure.
1772 *
1773 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1774 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1775 * up to 255 scatter-gather elements may be used per request or
1776 * ADV_SCSI_REQ_Q.
1777 *
1778 * Both structures must be 32 byte aligned.
1779 */
1780 typedef struct adv_sgblk {
1781 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
1782 dma_addr_t sg_addr; /* Physical address */
1783 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
1784 } adv_sgblk_t;
1785
1786 typedef struct adv_req {
1787 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
1788 uchar align[24]; /* Request structure padding. */
1789 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
1790 dma_addr_t req_addr;
1791 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
1792 } adv_req_t __aligned(32);
1793
1794 /*
1795 * Adapter operation variable structure.
1796 *
1797 * One structure is required per host adapter.
1798 *
1799 * Field naming convention:
1800 *
1801 * *_able indicates both whether a feature should be enabled or disabled
1802 * and whether a device is capable of the feature. At initialization
1803 * this field may be set, but later if a device is found to be incapable
1804 * of the feature, the field is cleared.
1805 */
1806 typedef struct adv_dvc_var {
1807 AdvPortAddr iop_base; /* I/O port address */
1808 ushort err_code; /* fatal error code */
1809 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1810 ushort wdtr_able; /* try WDTR for a device */
1811 ushort sdtr_able; /* try SDTR for a device */
1812 ushort ultra_able; /* try SDTR Ultra speed for a device */
1813 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1814 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1815 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1816 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1817 ushort tagqng_able; /* try tagged queuing with a device */
1818 ushort ppr_able; /* PPR message capable per TID bitmask. */
1819 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1820 ushort start_motor; /* start motor command allowed */
1821 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1822 uchar chip_no; /* should be assigned by caller */
1823 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1824 ushort no_scam; /* scam_tolerant of EEPROM */
1825 struct asc_board *drv_ptr; /* driver pointer to private structure */
1826 uchar chip_scsi_id; /* chip SCSI target ID */
1827 uchar chip_type;
1828 uchar bist_err_code;
1829 ADV_CARR_T *carrier;
1830 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1831 dma_addr_t carrier_addr;
1832 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1833 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1834 ushort carr_pending_cnt; /* Count of pending carriers. */
1835 /*
1836 * Note: The following fields will not be used after initialization. The
1837 * driver may discard the buffer after initialization is done.
1838 */
1839 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1840 } ADV_DVC_VAR;
1841
1842 /*
1843 * Microcode idle loop commands
1844 */
1845 #define IDLE_CMD_COMPLETED 0
1846 #define IDLE_CMD_STOP_CHIP 0x0001
1847 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1848 #define IDLE_CMD_SEND_INT 0x0004
1849 #define IDLE_CMD_ABORT 0x0008
1850 #define IDLE_CMD_DEVICE_RESET 0x0010
1851 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1852 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1853 #define IDLE_CMD_SCSIREQ 0x0080
1854
1855 #define IDLE_CMD_STATUS_SUCCESS 0x0001
1856 #define IDLE_CMD_STATUS_FAILURE 0x0002
1857
1858 /*
1859 * AdvSendIdleCmd() flag definitions.
1860 */
1861 #define ADV_NOWAIT 0x01
1862
1863 /*
1864 * Wait loop time out values.
1865 */
1866 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
1867 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
1868 #define SCSI_MAX_RETRY 10 /* retry count */
1869
1870 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
1871 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
1872 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
1873 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
1874
1875 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
1876
1877 /* Read byte from a register. */
1878 #define AdvReadByteRegister(iop_base, reg_off) \
1879 (ADV_MEM_READB((iop_base) + (reg_off)))
1880
1881 /* Write byte to a register. */
1882 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
1883 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1884
1885 /* Read word (2 bytes) from a register. */
1886 #define AdvReadWordRegister(iop_base, reg_off) \
1887 (ADV_MEM_READW((iop_base) + (reg_off)))
1888
1889 /* Write word (2 bytes) to a register. */
1890 #define AdvWriteWordRegister(iop_base, reg_off, word) \
1891 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
1892
1893 /* Write dword (4 bytes) to a register. */
1894 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
1895 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
1896
1897 /* Read byte from LRAM. */
1898 #define AdvReadByteLram(iop_base, addr, byte) \
1899 do { \
1900 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1901 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
1902 } while (0)
1903
1904 /* Write byte to LRAM. */
1905 #define AdvWriteByteLram(iop_base, addr, byte) \
1906 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1907 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
1908
1909 /* Read word (2 bytes) from LRAM. */
1910 #define AdvReadWordLram(iop_base, addr, word) \
1911 do { \
1912 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1913 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
1914 } while (0)
1915
1916 /* Write word (2 bytes) to LRAM. */
1917 #define AdvWriteWordLram(iop_base, addr, word) \
1918 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1919 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
1920
1921 /* Write little-endian double word (4 bytes) to LRAM */
1922 /* Because of unspecified C language ordering don't use auto-increment. */
1923 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
1924 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1925 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
1926 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
1927 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
1928 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
1929 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
1930
1931 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
1932 #define AdvReadWordAutoIncLram(iop_base) \
1933 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
1934
1935 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
1936 #define AdvWriteWordAutoIncLram(iop_base, word) \
1937 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
1938
1939 /*
1940 * Define macro to check for Condor signature.
1941 *
1942 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
1943 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
1944 */
1945 #define AdvFindSignature(iop_base) \
1946 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
1947 ADV_CHIP_ID_BYTE) && \
1948 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
1949 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
1950
1951 /*
1952 * Define macro to Return the version number of the chip at 'iop_base'.
1953 *
1954 * The second parameter 'bus_type' is currently unused.
1955 */
1956 #define AdvGetChipVersion(iop_base, bus_type) \
1957 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
1958
1959 /*
1960 * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must
1961 * match the ADV_SCSI_REQ_Q 'srb_tag' field.
1962 *
1963 * If the request has not yet been sent to the device it will simply be
1964 * aborted from RISC memory. If the request is disconnected it will be
1965 * aborted on reselection by sending an Abort Message to the target ID.
1966 *
1967 * Return value:
1968 * ADV_TRUE(1) - Queue was successfully aborted.
1969 * ADV_FALSE(0) - Queue was not found on the active queue list.
1970 */
1971 #define AdvAbortQueue(asc_dvc, srb_tag) \
1972 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
1973 (ADV_DCNT) (srb_tag))
1974
1975 /*
1976 * Send a Bus Device Reset Message to the specified target ID.
1977 *
1978 * All outstanding commands will be purged if sending the
1979 * Bus Device Reset Message is successful.
1980 *
1981 * Return Value:
1982 * ADV_TRUE(1) - All requests on the target are purged.
1983 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
1984 * are not purged.
1985 */
1986 #define AdvResetDevice(asc_dvc, target_id) \
1987 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
1988 (ADV_DCNT) (target_id))
1989
1990 /*
1991 * SCSI Wide Type definition.
1992 */
1993 #define ADV_SCSI_BIT_ID_TYPE ushort
1994
1995 /*
1996 * AdvInitScsiTarget() 'cntl_flag' options.
1997 */
1998 #define ADV_SCAN_LUN 0x01
1999 #define ADV_CAPINFO_NOLUN 0x02
2000
2001 /*
2002 * Convert target id to target id bit mask.
2003 */
2004 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2005
2006 /*
2007 * ADV_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2008 */
2009
2010 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
2011 #define QD_NO_ERROR 0x01
2012 #define QD_ABORTED_BY_HOST 0x02
2013 #define QD_WITH_ERROR 0x04
2014
2015 #define QHSTA_NO_ERROR 0x00
2016 #define QHSTA_M_SEL_TIMEOUT 0x11
2017 #define QHSTA_M_DATA_OVER_RUN 0x12
2018 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2019 #define QHSTA_M_QUEUE_ABORTED 0x15
2020 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2021 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2022 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2023 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2024 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2025 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2026 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
2027 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2028 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2029 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2030 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2031 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2032 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2033 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2034 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2035 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
2036 #define QHSTA_M_WTM_TIMEOUT 0x41
2037 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2038 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2039 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2040 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2041 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2042 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
2043
2044 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2045 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2046
2047 /*
2048 * Total contiguous memory needed for driver SG blocks.
2049 *
2050 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2051 * number of scatter-gather elements the driver supports in a
2052 * single request.
2053 */
2054
2055 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2056 (sizeof(ADV_SG_BLOCK) * \
2057 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2058
2059 /* struct asc_board flags */
2060 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
2061
2062 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2063
2064 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
2065
2066 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
2067
2068 /* Asc Library return codes */
2069 #define ASC_TRUE 1
2070 #define ASC_FALSE 0
2071 #define ASC_NOERROR 1
2072 #define ASC_BUSY 0
2073 #define ASC_ERROR (-1)
2074
2075 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2076 #ifndef ADVANSYS_STATS
2077 #define ASC_STATS_ADD(shost, counter, count)
2078 #else /* ADVANSYS_STATS */
2079 #define ASC_STATS_ADD(shost, counter, count) \
2080 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2081 #endif /* ADVANSYS_STATS */
2082
2083 /* If the result wraps when calculating tenths, return 0. */
2084 #define ASC_TENTHS(num, den) \
2085 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2086 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2087
2088 /*
2089 * Display a message to the console.
2090 */
2091 #define ASC_PRINT(s) \
2092 { \
2093 printk("advansys: "); \
2094 printk(s); \
2095 }
2096
2097 #define ASC_PRINT1(s, a1) \
2098 { \
2099 printk("advansys: "); \
2100 printk((s), (a1)); \
2101 }
2102
2103 #define ASC_PRINT2(s, a1, a2) \
2104 { \
2105 printk("advansys: "); \
2106 printk((s), (a1), (a2)); \
2107 }
2108
2109 #define ASC_PRINT3(s, a1, a2, a3) \
2110 { \
2111 printk("advansys: "); \
2112 printk((s), (a1), (a2), (a3)); \
2113 }
2114
2115 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2116 { \
2117 printk("advansys: "); \
2118 printk((s), (a1), (a2), (a3), (a4)); \
2119 }
2120
2121 #ifndef ADVANSYS_DEBUG
2122
2123 #define ASC_DBG(lvl, s...)
2124 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2125 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2126 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2127 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2128 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2129 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2130 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2131 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2132 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2133
2134 #else /* ADVANSYS_DEBUG */
2135
2136 /*
2137 * Debugging Message Levels:
2138 * 0: Errors Only
2139 * 1: High-Level Tracing
2140 * 2-N: Verbose Tracing
2141 */
2142
2143 #define ASC_DBG(lvl, format, arg...) { \
2144 if (asc_dbglvl >= (lvl)) \
2145 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
2146 __func__ , ## arg); \
2147 }
2148
2149 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2150 { \
2151 if (asc_dbglvl >= (lvl)) { \
2152 asc_prt_scsi_host(s); \
2153 } \
2154 }
2155
2156 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2157 { \
2158 if (asc_dbglvl >= (lvl)) { \
2159 asc_prt_asc_scsi_q(scsiqp); \
2160 } \
2161 }
2162
2163 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2164 { \
2165 if (asc_dbglvl >= (lvl)) { \
2166 asc_prt_asc_qdone_info(qdone); \
2167 } \
2168 }
2169
2170 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2171 { \
2172 if (asc_dbglvl >= (lvl)) { \
2173 asc_prt_adv_scsi_req_q(scsiqp); \
2174 } \
2175 }
2176
2177 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2178 { \
2179 if (asc_dbglvl >= (lvl)) { \
2180 asc_prt_hex((name), (start), (length)); \
2181 } \
2182 }
2183
2184 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2185 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2186
2187 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2188 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2189
2190 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2191 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2192 #endif /* ADVANSYS_DEBUG */
2193
2194 #ifdef ADVANSYS_STATS
2195
2196 /* Per board statistics structure */
2197 struct asc_stats {
2198 /* Driver Entrypoint Statistics */
2199 unsigned int queuecommand; /* # calls to advansys_queuecommand() */
2200 unsigned int reset; /* # calls to advansys_eh_bus_reset() */
2201 unsigned int biosparam; /* # calls to advansys_biosparam() */
2202 unsigned int interrupt; /* # advansys_interrupt() calls */
2203 unsigned int callback; /* # calls to asc/adv_isr_callback() */
2204 unsigned int done; /* # calls to request's scsi_done function */
2205 unsigned int build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2206 unsigned int adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2207 unsigned int adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2208 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2209 unsigned int exe_noerror; /* # ASC_NOERROR returns. */
2210 unsigned int exe_busy; /* # ASC_BUSY returns. */
2211 unsigned int exe_error; /* # ASC_ERROR returns. */
2212 unsigned int exe_unknown; /* # unknown returns. */
2213 /* Data Transfer Statistics */
2214 unsigned int xfer_cnt; /* # I/O requests received */
2215 unsigned int xfer_elem; /* # scatter-gather elements */
2216 unsigned int xfer_sect; /* # 512-byte blocks */
2217 };
2218 #endif /* ADVANSYS_STATS */
2219
2220 /*
2221 * Structure allocated for each board.
2222 *
2223 * This structure is allocated by scsi_host_alloc() at the end
2224 * of the 'Scsi_Host' structure starting at the 'hostdata'
2225 * field. It is guaranteed to be allocated from DMA-able memory.
2226 */
2227 struct asc_board {
2228 struct device *dev;
2229 struct Scsi_Host *shost;
2230 uint flags; /* Board flags */
2231 unsigned int irq;
2232 union {
2233 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2234 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2235 } dvc_var;
2236 union {
2237 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2238 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2239 } dvc_cfg;
2240 ushort asc_n_io_port; /* Number I/O ports. */
2241 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
2242 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2243 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2244 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2245 union {
2246 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2247 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2248 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2249 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2250 } eep_config;
2251 /* /proc/scsi/advansys/[0...] */
2252 #ifdef ADVANSYS_STATS
2253 struct asc_stats asc_stats; /* Board statistics */
2254 #endif /* ADVANSYS_STATS */
2255 /*
2256 * The following fields are used only for Narrow Boards.
2257 */
2258 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2259 /*
2260 * The following fields are used only for Wide Boards.
2261 */
2262 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2263 ushort ioport; /* I/O Port address. */
2264 adv_req_t *adv_reqp; /* Request structures. */
2265 dma_addr_t adv_reqp_addr;
2266 size_t adv_reqp_size;
2267 struct dma_pool *adv_sgblk_pool; /* Scatter-gather structures. */
2268 ushort bios_signature; /* BIOS Signature. */
2269 ushort bios_version; /* BIOS Version. */
2270 ushort bios_codeseg; /* BIOS Code Segment. */
2271 ushort bios_codelen; /* BIOS Code Segment Length. */
2272 };
2273
2274 #define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2275 dvc_var.asc_dvc_var)
2276 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2277 dvc_var.adv_dvc_var)
2278 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2279
2280 struct advansys_cmd {
2281 dma_addr_t dma_handle;
2282 };
2283
2284 static struct advansys_cmd *advansys_cmd(struct scsi_cmnd *cmd)
2285 {
2286 return scsi_cmd_priv(cmd);
2287 }
2288
2289 #ifdef ADVANSYS_DEBUG
2290 static int asc_dbglvl = 3;
2291
2292 /*
2293 * asc_prt_asc_dvc_var()
2294 */
2295 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2296 {
2297 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2298
2299 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2300 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2301
2302 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2303 (unsigned)h->init_sdtr);
2304
2305 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2306 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2307 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2308 (unsigned)h->chip_no);
2309
2310 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2311 "%u,\n", (unsigned)h->queue_full_or_busy,
2312 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2313
2314 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2315 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2316 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2317 (unsigned)h->in_critical_cnt);
2318
2319 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2320 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2321 (unsigned)h->init_state, (unsigned)h->no_scam,
2322 (unsigned)h->pci_fix_asyn_xfer);
2323
2324 printk(" cfg 0x%lx\n", (ulong)h->cfg);
2325 }
2326
2327 /*
2328 * asc_prt_asc_dvc_cfg()
2329 */
2330 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2331 {
2332 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2333
2334 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2335 h->can_tagged_qng, h->cmd_qng_enabled);
2336 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2337 h->disc_enable, h->sdtr_enable);
2338
2339 printk(" chip_scsi_id %d, chip_version %d,\n",
2340 h->chip_scsi_id, h->chip_version);
2341
2342 printk(" mcode_date 0x%x, mcode_version %d\n",
2343 h->mcode_date, h->mcode_version);
2344 }
2345
2346 /*
2347 * asc_prt_adv_dvc_var()
2348 *
2349 * Display an ADV_DVC_VAR structure.
2350 */
2351 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2352 {
2353 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2354
2355 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2356 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2357
2358 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
2359 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2360
2361 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2362 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2363
2364 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n",
2365 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2366 h->carr_freelist);
2367
2368 printk(" icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp);
2369
2370 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2371 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2372
2373 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2374 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2375 }
2376
2377 /*
2378 * asc_prt_adv_dvc_cfg()
2379 *
2380 * Display an ADV_DVC_CFG structure.
2381 */
2382 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2383 {
2384 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2385
2386 printk(" disc_enable 0x%x, termination 0x%x\n",
2387 h->disc_enable, h->termination);
2388
2389 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2390 h->chip_version, h->mcode_date);
2391
2392 printk(" mcode_version 0x%x, control_flag 0x%x\n",
2393 h->mcode_version, h->control_flag);
2394 }
2395
2396 /*
2397 * asc_prt_scsi_host()
2398 */
2399 static void asc_prt_scsi_host(struct Scsi_Host *s)
2400 {
2401 struct asc_board *boardp = shost_priv(s);
2402
2403 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
2404 printk(" host_busy %d, host_no %d,\n",
2405 scsi_host_busy(s), s->host_no);
2406
2407 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2408 (ulong)s->base, (ulong)s->io_port, boardp->irq);
2409
2410 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2411 s->dma_channel, s->this_id, s->can_queue);
2412
2413 printk(" cmd_per_lun %d, sg_tablesize %d\n",
2414 s->cmd_per_lun, s->sg_tablesize);
2415
2416 if (ASC_NARROW_BOARD(boardp)) {
2417 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2418 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2419 } else {
2420 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2421 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2422 }
2423 }
2424
2425 /*
2426 * asc_prt_hex()
2427 *
2428 * Print hexadecimal output in 4 byte groupings 32 bytes
2429 * or 8 double-words per line.
2430 */
2431 static void asc_prt_hex(char *f, uchar *s, int l)
2432 {
2433 int i;
2434 int j;
2435 int k;
2436 int m;
2437
2438 printk("%s: (%d bytes)\n", f, l);
2439
2440 for (i = 0; i < l; i += 32) {
2441
2442 /* Display a maximum of 8 double-words per line. */
2443 if ((k = (l - i) / 4) >= 8) {
2444 k = 8;
2445 m = 0;
2446 } else {
2447 m = (l - i) % 4;
2448 }
2449
2450 for (j = 0; j < k; j++) {
2451 printk(" %2.2X%2.2X%2.2X%2.2X",
2452 (unsigned)s[i + (j * 4)],
2453 (unsigned)s[i + (j * 4) + 1],
2454 (unsigned)s[i + (j * 4) + 2],
2455 (unsigned)s[i + (j * 4) + 3]);
2456 }
2457
2458 switch (m) {
2459 case 0:
2460 default:
2461 break;
2462 case 1:
2463 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2464 break;
2465 case 2:
2466 printk(" %2.2X%2.2X",
2467 (unsigned)s[i + (j * 4)],
2468 (unsigned)s[i + (j * 4) + 1]);
2469 break;
2470 case 3:
2471 printk(" %2.2X%2.2X%2.2X",
2472 (unsigned)s[i + (j * 4) + 1],
2473 (unsigned)s[i + (j * 4) + 2],
2474 (unsigned)s[i + (j * 4) + 3]);
2475 break;
2476 }
2477
2478 printk("\n");
2479 }
2480 }
2481
2482 /*
2483 * asc_prt_asc_scsi_q()
2484 */
2485 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2486 {
2487 ASC_SG_HEAD *sgp;
2488 int i;
2489
2490 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2491
2492 printk
2493 (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n",
2494 q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag,
2495 q->q2.tag_code);
2496
2497 printk
2498 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2499 (ulong)le32_to_cpu(q->q1.data_addr),
2500 (ulong)le32_to_cpu(q->q1.data_cnt),
2501 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2502
2503 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2504 (ulong)q->cdbptr, q->q2.cdb_len,
2505 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2506
2507 if (q->sg_head) {
2508 sgp = q->sg_head;
2509 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2510 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2511 sgp->queue_cnt);
2512 for (i = 0; i < sgp->entry_cnt; i++) {
2513 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2514 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2515 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2516 }
2517
2518 }
2519 }
2520
2521 /*
2522 * asc_prt_asc_qdone_info()
2523 */
2524 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2525 {
2526 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2527 printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n",
2528 q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len,
2529 q->d2.tag_code);
2530 printk
2531 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2532 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2533 }
2534
2535 /*
2536 * asc_prt_adv_sgblock()
2537 *
2538 * Display an ADV_SG_BLOCK structure.
2539 */
2540 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2541 {
2542 int i;
2543
2544 printk(" ADV_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2545 (ulong)b, sgblockno);
2546 printk(" sg_cnt %u, sg_ptr 0x%x\n",
2547 b->sg_cnt, (u32)le32_to_cpu(b->sg_ptr));
2548 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2549 if (b->sg_ptr != 0)
2550 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2551 for (i = 0; i < b->sg_cnt; i++) {
2552 printk(" [%u]: sg_addr 0x%x, sg_count 0x%x\n",
2553 i, (u32)le32_to_cpu(b->sg_list[i].sg_addr),
2554 (u32)le32_to_cpu(b->sg_list[i].sg_count));
2555 }
2556 }
2557
2558 /*
2559 * asc_prt_adv_scsi_req_q()
2560 *
2561 * Display an ADV_SCSI_REQ_Q structure.
2562 */
2563 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2564 {
2565 int sg_blk_cnt;
2566 struct adv_sg_block *sg_ptr;
2567 adv_sgblk_t *sgblkp;
2568
2569 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2570
2571 printk(" target_id %u, target_lun %u, srb_tag 0x%x\n",
2572 q->target_id, q->target_lun, q->srb_tag);
2573
2574 printk(" cntl 0x%x, data_addr 0x%lx\n",
2575 q->cntl, (ulong)le32_to_cpu(q->data_addr));
2576
2577 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2578 (ulong)le32_to_cpu(q->data_cnt),
2579 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2580
2581 printk
2582 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2583 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2584
2585 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2586 q->sg_working_ix, q->target_cmd);
2587
2588 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2589 (ulong)le32_to_cpu(q->scsiq_rptr),
2590 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2591
2592 /* Display the request's ADV_SG_BLOCK structures. */
2593 if (q->sg_list_ptr != NULL) {
2594 sgblkp = container_of(q->sg_list_ptr, adv_sgblk_t, sg_block);
2595 sg_blk_cnt = 0;
2596 while (sgblkp) {
2597 sg_ptr = &sgblkp->sg_block;
2598 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2599 if (sg_ptr->sg_ptr == 0) {
2600 break;
2601 }
2602 sgblkp = sgblkp->next_sgblkp;
2603 sg_blk_cnt++;
2604 }
2605 }
2606 }
2607 #endif /* ADVANSYS_DEBUG */
2608
2609 /*
2610 * advansys_info()
2611 *
2612 * Return suitable for printing on the console with the argument
2613 * adapter's configuration information.
2614 *
2615 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2616 * otherwise the static 'info' array will be overrun.
2617 */
2618 static const char *advansys_info(struct Scsi_Host *shost)
2619 {
2620 static char info[ASC_INFO_SIZE];
2621 struct asc_board *boardp = shost_priv(shost);
2622 ASC_DVC_VAR *asc_dvc_varp;
2623 ADV_DVC_VAR *adv_dvc_varp;
2624 char *busname;
2625 char *widename = NULL;
2626
2627 if (ASC_NARROW_BOARD(boardp)) {
2628 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2629 ASC_DBG(1, "begin\n");
2630
2631 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2632 busname = "VL";
2633 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2634 busname = "EISA";
2635 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2636 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2637 == ASC_IS_PCI_ULTRA) {
2638 busname = "PCI Ultra";
2639 } else {
2640 busname = "PCI";
2641 }
2642 } else {
2643 busname = "?";
2644 shost_printk(KERN_ERR, shost, "unknown bus "
2645 "type %d\n", asc_dvc_varp->bus_type);
2646 }
2647 sprintf(info,
2648 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2649 ASC_VERSION, busname, (ulong)shost->io_port,
2650 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2651 boardp->irq);
2652 } else {
2653 /*
2654 * Wide Adapter Information
2655 *
2656 * Memory-mapped I/O is used instead of I/O space to access
2657 * the adapter, but display the I/O Port range. The Memory
2658 * I/O address is displayed through the driver /proc file.
2659 */
2660 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2661 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2662 widename = "Ultra-Wide";
2663 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2664 widename = "Ultra2-Wide";
2665 } else {
2666 widename = "Ultra3-Wide";
2667 }
2668 sprintf(info,
2669 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2670 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2671 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2672 }
2673 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2674 ASC_DBG(1, "end\n");
2675 return info;
2676 }
2677
2678 #ifdef CONFIG_PROC_FS
2679
2680 /*
2681 * asc_prt_board_devices()
2682 *
2683 * Print driver information for devices attached to the board.
2684 */
2685 static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
2686 {
2687 struct asc_board *boardp = shost_priv(shost);
2688 int chip_scsi_id;
2689 int i;
2690
2691 seq_printf(m,
2692 "\nDevice Information for AdvanSys SCSI Host %d:\n",
2693 shost->host_no);
2694
2695 if (ASC_NARROW_BOARD(boardp)) {
2696 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2697 } else {
2698 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2699 }
2700
2701 seq_puts(m, "Target IDs Detected:");
2702 for (i = 0; i <= ADV_MAX_TID; i++) {
2703 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2704 seq_printf(m, " %X,", i);
2705 }
2706 seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
2707 }
2708
2709 /*
2710 * Display Wide Board BIOS Information.
2711 */
2712 static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
2713 {
2714 struct asc_board *boardp = shost_priv(shost);
2715 ushort major, minor, letter;
2716
2717 seq_puts(m, "\nROM BIOS Version: ");
2718
2719 /*
2720 * If the BIOS saved a valid signature, then fill in
2721 * the BIOS code segment base address.
2722 */
2723 if (boardp->bios_signature != 0x55AA) {
2724 seq_puts(m, "Disabled or Pre-3.1\n"
2725 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"
2726 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2727 } else {
2728 major = (boardp->bios_version >> 12) & 0xF;
2729 minor = (boardp->bios_version >> 8) & 0xF;
2730 letter = (boardp->bios_version & 0xFF);
2731
2732 seq_printf(m, "%d.%d%c\n",
2733 major, minor,
2734 letter >= 26 ? '?' : letter + 'A');
2735 /*
2736 * Current available ROM BIOS release is 3.1I for UW
2737 * and 3.2I for U2W. This code doesn't differentiate
2738 * UW and U2W boards.
2739 */
2740 if (major < 3 || (major <= 3 && minor < 1) ||
2741 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
2742 seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"
2743 "ftp://ftp.connectcom.net/pub\n");
2744 }
2745 }
2746 }
2747
2748 /*
2749 * Add serial number to information bar if signature AAh
2750 * is found in at bit 15-9 (7 bits) of word 1.
2751 *
2752 * Serial Number consists fo 12 alpha-numeric digits.
2753 *
2754 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
2755 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
2756 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
2757 * 5 - Product revision (A-J) Word0: " "
2758 *
2759 * Signature Word1: 15-9 (7 bits)
2760 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2761 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
2762 *
2763 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
2764 *
2765 * Note 1: Only production cards will have a serial number.
2766 *
2767 * Note 2: Signature is most significant 7 bits (0xFE).
2768 *
2769 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
2770 */
2771 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
2772 {
2773 ushort w, num;
2774
2775 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2776 return ASC_FALSE;
2777 } else {
2778 /*
2779 * First word - 6 digits.
2780 */
2781 w = serialnum[0];
2782
2783 /* Product type - 1st digit. */
2784 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2785 /* Product type is P=Prototype */
2786 *cp += 0x8;
2787 }
2788 cp++;
2789
2790 /* Manufacturing location - 2nd digit. */
2791 *cp++ = 'A' + ((w & 0x1C00) >> 10);
2792
2793 /* Product ID - 3rd, 4th digits. */
2794 num = w & 0x3FF;
2795 *cp++ = '0' + (num / 100);
2796 num %= 100;
2797 *cp++ = '0' + (num / 10);
2798
2799 /* Product revision - 5th digit. */
2800 *cp++ = 'A' + (num % 10);
2801
2802 /*
2803 * Second word
2804 */
2805 w = serialnum[1];
2806
2807 /*
2808 * Year - 6th digit.
2809 *
2810 * If bit 15 of third word is set, then the
2811 * last digit of the year is greater than 7.
2812 */
2813 if (serialnum[2] & 0x8000) {
2814 *cp++ = '8' + ((w & 0x1C0) >> 6);
2815 } else {
2816 *cp++ = '0' + ((w & 0x1C0) >> 6);
2817 }
2818
2819 /* Week of year - 7th, 8th digits. */
2820 num = w & 0x003F;
2821 *cp++ = '0' + num / 10;
2822 num %= 10;
2823 *cp++ = '0' + num;
2824
2825 /*
2826 * Third word
2827 */
2828 w = serialnum[2] & 0x7FFF;
2829
2830 /* Serial number - 9th digit. */
2831 *cp++ = 'A' + (w / 1000);
2832
2833 /* 10th, 11th, 12th digits. */
2834 num = w % 1000;
2835 *cp++ = '0' + num / 100;
2836 num %= 100;
2837 *cp++ = '0' + num / 10;
2838 num %= 10;
2839 *cp++ = '0' + num;
2840
2841 *cp = '\0'; /* Null Terminate the string. */
2842 return ASC_TRUE;
2843 }
2844 }
2845
2846 /*
2847 * asc_prt_asc_board_eeprom()
2848 *
2849 * Print board EEPROM configuration.
2850 */
2851 static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
2852 {
2853 struct asc_board *boardp = shost_priv(shost);
2854 ASCEEP_CONFIG *ep;
2855 int i;
2856 uchar serialstr[13];
2857
2858 ep = &boardp->eep_config.asc_eep;
2859
2860 seq_printf(m,
2861 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2862 shost->host_no);
2863
2864 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
2865 == ASC_TRUE)
2866 seq_printf(m, " Serial Number: %s\n", serialstr);
2867 else if (ep->adapter_info[5] == 0xBB)
2868 seq_puts(m,
2869 " Default Settings Used for EEPROM-less Adapter.\n");
2870 else
2871 seq_puts(m, " Serial Number Signature Not Present.\n");
2872
2873 seq_printf(m,
2874 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2875 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
2876 ep->max_tag_qng);
2877
2878 seq_printf(m,
2879 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
2880
2881 seq_puts(m, " Target ID: ");
2882 for (i = 0; i <= ASC_MAX_TID; i++)
2883 seq_printf(m, " %d", i);
2884
2885 seq_puts(m, "\n Disconnects: ");
2886 for (i = 0; i <= ASC_MAX_TID; i++)
2887 seq_printf(m, " %c",
2888 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2889
2890 seq_puts(m, "\n Command Queuing: ");
2891 for (i = 0; i <= ASC_MAX_TID; i++)
2892 seq_printf(m, " %c",
2893 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2894
2895 seq_puts(m, "\n Start Motor: ");
2896 for (i = 0; i <= ASC_MAX_TID; i++)
2897 seq_printf(m, " %c",
2898 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2899
2900 seq_puts(m, "\n Synchronous Transfer:");
2901 for (i = 0; i <= ASC_MAX_TID; i++)
2902 seq_printf(m, " %c",
2903 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2904 seq_putc(m, '\n');
2905 }
2906
2907 /*
2908 * asc_prt_adv_board_eeprom()
2909 *
2910 * Print board EEPROM configuration.
2911 */
2912 static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
2913 {
2914 struct asc_board *boardp = shost_priv(shost);
2915 ADV_DVC_VAR *adv_dvc_varp;
2916 int i;
2917 char *termstr;
2918 uchar serialstr[13];
2919 ADVEEP_3550_CONFIG *ep_3550 = NULL;
2920 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
2921 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
2922 ushort word;
2923 ushort *wordp;
2924 ushort sdtr_speed = 0;
2925
2926 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2927 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2928 ep_3550 = &boardp->eep_config.adv_3550_eep;
2929 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2930 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
2931 } else {
2932 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
2933 }
2934
2935 seq_printf(m,
2936 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2937 shost->host_no);
2938
2939 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2940 wordp = &ep_3550->serial_number_word1;
2941 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2942 wordp = &ep_38C0800->serial_number_word1;
2943 } else {
2944 wordp = &ep_38C1600->serial_number_word1;
2945 }
2946
2947 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
2948 seq_printf(m, " Serial Number: %s\n", serialstr);
2949 else
2950 seq_puts(m, " Serial Number Signature Not Present.\n");
2951
2952 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
2953 seq_printf(m,
2954 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2955 ep_3550->adapter_scsi_id,
2956 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
2957 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
2958 seq_printf(m,
2959 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2960 ep_38C0800->adapter_scsi_id,
2961 ep_38C0800->max_host_qng,
2962 ep_38C0800->max_dvc_qng);
2963 else
2964 seq_printf(m,
2965 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2966 ep_38C1600->adapter_scsi_id,
2967 ep_38C1600->max_host_qng,
2968 ep_38C1600->max_dvc_qng);
2969 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2970 word = ep_3550->termination;
2971 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2972 word = ep_38C0800->termination_lvd;
2973 } else {
2974 word = ep_38C1600->termination_lvd;
2975 }
2976 switch (word) {
2977 case 1:
2978 termstr = "Low Off/High Off";
2979 break;
2980 case 2:
2981 termstr = "Low Off/High On";
2982 break;
2983 case 3:
2984 termstr = "Low On/High On";
2985 break;
2986 default:
2987 case 0:
2988 termstr = "Automatic";
2989 break;
2990 }
2991
2992 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
2993 seq_printf(m,
2994 " termination: %u (%s), bios_ctrl: 0x%x\n",
2995 ep_3550->termination, termstr,
2996 ep_3550->bios_ctrl);
2997 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
2998 seq_printf(m,
2999 " termination: %u (%s), bios_ctrl: 0x%x\n",
3000 ep_38C0800->termination_lvd, termstr,
3001 ep_38C0800->bios_ctrl);
3002 else
3003 seq_printf(m,
3004 " termination: %u (%s), bios_ctrl: 0x%x\n",
3005 ep_38C1600->termination_lvd, termstr,
3006 ep_38C1600->bios_ctrl);
3007
3008 seq_puts(m, " Target ID: ");
3009 for (i = 0; i <= ADV_MAX_TID; i++)
3010 seq_printf(m, " %X", i);
3011 seq_putc(m, '\n');
3012
3013 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3014 word = ep_3550->disc_enable;
3015 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3016 word = ep_38C0800->disc_enable;
3017 } else {
3018 word = ep_38C1600->disc_enable;
3019 }
3020 seq_puts(m, " Disconnects: ");
3021 for (i = 0; i <= ADV_MAX_TID; i++)
3022 seq_printf(m, " %c",
3023 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3024 seq_putc(m, '\n');
3025
3026 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3027 word = ep_3550->tagqng_able;
3028 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3029 word = ep_38C0800->tagqng_able;
3030 } else {
3031 word = ep_38C1600->tagqng_able;
3032 }
3033 seq_puts(m, " Command Queuing: ");
3034 for (i = 0; i <= ADV_MAX_TID; i++)
3035 seq_printf(m, " %c",
3036 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3037 seq_putc(m, '\n');
3038
3039 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3040 word = ep_3550->start_motor;
3041 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3042 word = ep_38C0800->start_motor;
3043 } else {
3044 word = ep_38C1600->start_motor;
3045 }
3046 seq_puts(m, " Start Motor: ");
3047 for (i = 0; i <= ADV_MAX_TID; i++)
3048 seq_printf(m, " %c",
3049 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3050 seq_putc(m, '\n');
3051
3052 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3053 seq_puts(m, " Synchronous Transfer:");
3054 for (i = 0; i <= ADV_MAX_TID; i++)
3055 seq_printf(m, " %c",
3056 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3057 'Y' : 'N');
3058 seq_putc(m, '\n');
3059 }
3060
3061 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3062 seq_puts(m, " Ultra Transfer: ");
3063 for (i = 0; i <= ADV_MAX_TID; i++)
3064 seq_printf(m, " %c",
3065 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3066 ? 'Y' : 'N');
3067 seq_putc(m, '\n');
3068 }
3069
3070 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3071 word = ep_3550->wdtr_able;
3072 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3073 word = ep_38C0800->wdtr_able;
3074 } else {
3075 word = ep_38C1600->wdtr_able;
3076 }
3077 seq_puts(m, " Wide Transfer: ");
3078 for (i = 0; i <= ADV_MAX_TID; i++)
3079 seq_printf(m, " %c",
3080 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3081 seq_putc(m, '\n');
3082
3083 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3084 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3085 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n ");
3086 for (i = 0; i <= ADV_MAX_TID; i++) {
3087 char *speed_str;
3088
3089 if (i == 0) {
3090 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3091 } else if (i == 4) {
3092 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3093 } else if (i == 8) {
3094 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3095 } else if (i == 12) {
3096 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3097 }
3098 switch (sdtr_speed & ADV_MAX_TID) {
3099 case 0:
3100 speed_str = "Off";
3101 break;
3102 case 1:
3103 speed_str = " 5";
3104 break;
3105 case 2:
3106 speed_str = " 10";
3107 break;
3108 case 3:
3109 speed_str = " 20";
3110 break;
3111 case 4:
3112 speed_str = " 40";
3113 break;
3114 case 5:
3115 speed_str = " 80";
3116 break;
3117 default:
3118 speed_str = "Unk";
3119 break;
3120 }
3121 seq_printf(m, "%X:%s ", i, speed_str);
3122 if (i == 7)
3123 seq_puts(m, "\n ");
3124 sdtr_speed >>= 4;
3125 }
3126 seq_putc(m, '\n');
3127 }
3128 }
3129
3130 /*
3131 * asc_prt_driver_conf()
3132 */
3133 static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
3134 {
3135 struct asc_board *boardp = shost_priv(shost);
3136
3137 seq_printf(m,
3138 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3139 shost->host_no);
3140
3141 seq_printf(m,
3142 " host_busy %d, max_id %u, max_lun %llu, max_channel %u\n",
3143 scsi_host_busy(shost), shost->max_id,
3144 shost->max_lun, shost->max_channel);
3145
3146 seq_printf(m,
3147 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3148 shost->unique_id, shost->can_queue, shost->this_id,
3149 shost->sg_tablesize, shost->cmd_per_lun);
3150
3151 seq_printf(m,
3152 " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
3153 boardp->flags, shost->last_reset, jiffies,
3154 boardp->asc_n_io_port);
3155
3156 seq_printf(m, " io_port 0x%lx\n", shost->io_port);
3157 }
3158
3159 /*
3160 * asc_prt_asc_board_info()
3161 *
3162 * Print dynamic board configuration information.
3163 */
3164 static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
3165 {
3166 struct asc_board *boardp = shost_priv(shost);
3167 int chip_scsi_id;
3168 ASC_DVC_VAR *v;
3169 ASC_DVC_CFG *c;
3170 int i;
3171 int renegotiate = 0;
3172
3173 v = &boardp->dvc_var.asc_dvc_var;
3174 c = &boardp->dvc_cfg.asc_dvc_cfg;
3175 chip_scsi_id = c->chip_scsi_id;
3176
3177 seq_printf(m,
3178 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3179 shost->host_no);
3180
3181 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3182 "mcode_version 0x%x, err_code %u\n",
3183 c->chip_version, c->mcode_date, c->mcode_version,
3184 v->err_code);
3185
3186 /* Current number of commands waiting for the host. */
3187 seq_printf(m,
3188 " Total Command Pending: %d\n", v->cur_total_qng);
3189
3190 seq_puts(m, " Command Queuing:");
3191 for (i = 0; i <= ASC_MAX_TID; i++) {
3192 if ((chip_scsi_id == i) ||
3193 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3194 continue;
3195 }
3196 seq_printf(m, " %X:%c",
3197 i,
3198 (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3199 }
3200
3201 /* Current number of commands waiting for a device. */
3202 seq_puts(m, "\n Command Queue Pending:");
3203 for (i = 0; i <= ASC_MAX_TID; i++) {
3204 if ((chip_scsi_id == i) ||
3205 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3206 continue;
3207 }
3208 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
3209 }
3210
3211 /* Current limit on number of commands that can be sent to a device. */
3212 seq_puts(m, "\n Command Queue Limit:");
3213 for (i = 0; i <= ASC_MAX_TID; i++) {
3214 if ((chip_scsi_id == i) ||
3215 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3216 continue;
3217 }
3218 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
3219 }
3220
3221 /* Indicate whether the device has returned queue full status. */
3222 seq_puts(m, "\n Command Queue Full:");
3223 for (i = 0; i <= ASC_MAX_TID; i++) {
3224 if ((chip_scsi_id == i) ||
3225 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3226 continue;
3227 }
3228 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3229 seq_printf(m, " %X:Y-%d",
3230 i, boardp->queue_full_cnt[i]);
3231 else
3232 seq_printf(m, " %X:N", i);
3233 }
3234
3235 seq_puts(m, "\n Synchronous Transfer:");
3236 for (i = 0; i <= ASC_MAX_TID; i++) {
3237 if ((chip_scsi_id == i) ||
3238 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3239 continue;
3240 }
3241 seq_printf(m, " %X:%c",
3242 i,
3243 (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3244 }
3245 seq_putc(m, '\n');
3246
3247 for (i = 0; i <= ASC_MAX_TID; i++) {
3248 uchar syn_period_ix;
3249
3250 if ((chip_scsi_id == i) ||
3251 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3252 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3253 continue;
3254 }
3255
3256 seq_printf(m, " %X:", i);
3257
3258 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3259 seq_puts(m, " Asynchronous");
3260 } else {
3261 syn_period_ix =
3262 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3263 1);
3264
3265 seq_printf(m,
3266 " Transfer Period Factor: %d (%d.%d Mhz),",
3267 v->sdtr_period_tbl[syn_period_ix],
3268 250 / v->sdtr_period_tbl[syn_period_ix],
3269 ASC_TENTHS(250,
3270 v->sdtr_period_tbl[syn_period_ix]));
3271
3272 seq_printf(m, " REQ/ACK Offset: %d",
3273 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3274 }
3275
3276 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3277 seq_puts(m, "*\n");
3278 renegotiate = 1;
3279 } else {
3280 seq_putc(m, '\n');
3281 }
3282 }
3283
3284 if (renegotiate) {
3285 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3286 }
3287 }
3288
3289 /*
3290 * asc_prt_adv_board_info()
3291 *
3292 * Print dynamic board configuration information.
3293 */
3294 static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
3295 {
3296 struct asc_board *boardp = shost_priv(shost);
3297 int i;
3298 ADV_DVC_VAR *v;
3299 ADV_DVC_CFG *c;
3300 AdvPortAddr iop_base;
3301 ushort chip_scsi_id;
3302 ushort lramword;
3303 uchar lrambyte;
3304 ushort tagqng_able;
3305 ushort sdtr_able, wdtr_able;
3306 ushort wdtr_done, sdtr_done;
3307 ushort period = 0;
3308 int renegotiate = 0;
3309
3310 v = &boardp->dvc_var.adv_dvc_var;
3311 c = &boardp->dvc_cfg.adv_dvc_cfg;
3312 iop_base = v->iop_base;
3313 chip_scsi_id = v->chip_scsi_id;
3314
3315 seq_printf(m,
3316 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3317 shost->host_no);
3318
3319 seq_printf(m,
3320 " iop_base 0x%p, cable_detect: %X, err_code %u\n",
3321 v->iop_base,
3322 AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3323 v->err_code);
3324
3325 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3326 "mcode_version 0x%x\n", c->chip_version,
3327 c->mcode_date, c->mcode_version);
3328
3329 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3330 seq_puts(m, " Queuing Enabled:");
3331 for (i = 0; i <= ADV_MAX_TID; i++) {
3332 if ((chip_scsi_id == i) ||
3333 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3334 continue;
3335 }
3336
3337 seq_printf(m, " %X:%c",
3338 i,
3339 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3340 }
3341
3342 seq_puts(m, "\n Queue Limit:");
3343 for (i = 0; i <= ADV_MAX_TID; i++) {
3344 if ((chip_scsi_id == i) ||
3345 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3346 continue;
3347 }
3348
3349 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3350 lrambyte);
3351
3352 seq_printf(m, " %X:%d", i, lrambyte);
3353 }
3354
3355 seq_puts(m, "\n Command Pending:");
3356 for (i = 0; i <= ADV_MAX_TID; i++) {
3357 if ((chip_scsi_id == i) ||
3358 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3359 continue;
3360 }
3361
3362 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3363 lrambyte);
3364
3365 seq_printf(m, " %X:%d", i, lrambyte);
3366 }
3367 seq_putc(m, '\n');
3368
3369 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3370 seq_puts(m, " Wide Enabled:");
3371 for (i = 0; i <= ADV_MAX_TID; i++) {
3372 if ((chip_scsi_id == i) ||
3373 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3374 continue;
3375 }
3376
3377 seq_printf(m, " %X:%c",
3378 i,
3379 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3380 }
3381 seq_putc(m, '\n');
3382
3383 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3384 seq_puts(m, " Transfer Bit Width:");
3385 for (i = 0; i <= ADV_MAX_TID; i++) {
3386 if ((chip_scsi_id == i) ||
3387 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3388 continue;
3389 }
3390
3391 AdvReadWordLram(iop_base,
3392 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3393 lramword);
3394
3395 seq_printf(m, " %X:%d",
3396 i, (lramword & 0x8000) ? 16 : 8);
3397
3398 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3399 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3400 seq_putc(m, '*');
3401 renegotiate = 1;
3402 }
3403 }
3404 seq_putc(m, '\n');
3405
3406 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3407 seq_puts(m, " Synchronous Enabled:");
3408 for (i = 0; i <= ADV_MAX_TID; i++) {
3409 if ((chip_scsi_id == i) ||
3410 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3411 continue;
3412 }
3413
3414 seq_printf(m, " %X:%c",
3415 i,
3416 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3417 }
3418 seq_putc(m, '\n');
3419
3420 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3421 for (i = 0; i <= ADV_MAX_TID; i++) {
3422
3423 AdvReadWordLram(iop_base,
3424 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3425 lramword);
3426 lramword &= ~0x8000;
3427
3428 if ((chip_scsi_id == i) ||
3429 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3430 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3431 continue;
3432 }
3433
3434 seq_printf(m, " %X:", i);
3435
3436 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
3437 seq_puts(m, " Asynchronous");
3438 } else {
3439 seq_puts(m, " Transfer Period Factor: ");
3440
3441 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
3442 seq_puts(m, "9 (80.0 Mhz),");
3443 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
3444 seq_puts(m, "10 (40.0 Mhz),");
3445 } else { /* 20 Mhz or below. */
3446
3447 period = (((lramword >> 8) * 25) + 50) / 4;
3448
3449 if (period == 0) { /* Should never happen. */
3450 seq_printf(m, "%d (? Mhz), ", period);
3451 } else {
3452 seq_printf(m,
3453 "%d (%d.%d Mhz),",
3454 period, 250 / period,
3455 ASC_TENTHS(250, period));
3456 }
3457 }
3458
3459 seq_printf(m, " REQ/ACK Offset: %d",
3460 lramword & 0x1F);
3461 }
3462
3463 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3464 seq_puts(m, "*\n");
3465 renegotiate = 1;
3466 } else {
3467 seq_putc(m, '\n');
3468 }
3469 }
3470
3471 if (renegotiate) {
3472 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3473 }
3474 }
3475
3476 #ifdef ADVANSYS_STATS
3477 /*
3478 * asc_prt_board_stats()
3479 */
3480 static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
3481 {
3482 struct asc_board *boardp = shost_priv(shost);
3483 struct asc_stats *s = &boardp->asc_stats;
3484
3485 seq_printf(m,
3486 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3487 shost->host_no);
3488
3489 seq_printf(m,
3490 " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
3491 s->queuecommand, s->reset, s->biosparam,
3492 s->interrupt);
3493
3494 seq_printf(m,
3495 " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
3496 s->callback, s->done, s->build_error,
3497 s->adv_build_noreq, s->adv_build_nosg);
3498
3499 seq_printf(m,
3500 " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
3501 s->exe_noerror, s->exe_busy, s->exe_error,
3502 s->exe_unknown);
3503
3504 /*
3505 * Display data transfer statistics.
3506 */
3507 if (s->xfer_cnt > 0) {
3508 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
3509 s->xfer_cnt, s->xfer_elem);
3510
3511 seq_printf(m, "xfer_bytes %u.%01u kb\n",
3512 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
3513
3514 /* Scatter gather transfer statistics */
3515 seq_printf(m, " avg_num_elem %u.%01u, ",
3516 s->xfer_elem / s->xfer_cnt,
3517 ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
3518
3519 seq_printf(m, "avg_elem_size %u.%01u kb, ",
3520 (s->xfer_sect / 2) / s->xfer_elem,
3521 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
3522
3523 seq_printf(m, "avg_xfer_size %u.%01u kb\n",
3524 (s->xfer_sect / 2) / s->xfer_cnt,
3525 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
3526 }
3527 }
3528 #endif /* ADVANSYS_STATS */
3529
3530 /*
3531 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
3532 *
3533 * m: seq_file to print into
3534 * shost: Scsi_Host
3535 *
3536 * Return the number of bytes read from or written to a
3537 * /proc/scsi/advansys/[0...] file.
3538 */
3539 static int
3540 advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
3541 {
3542 struct asc_board *boardp = shost_priv(shost);
3543
3544 ASC_DBG(1, "begin\n");
3545
3546 /*
3547 * User read of /proc/scsi/advansys/[0...] file.
3548 */
3549
3550 /*
3551 * Get board configuration information.
3552 *
3553 * advansys_info() returns the board string from its own static buffer.
3554 */
3555 /* Copy board information. */
3556 seq_printf(m, "%s\n", (char *)advansys_info(shost));
3557 /*
3558 * Display Wide Board BIOS Information.
3559 */
3560 if (!ASC_NARROW_BOARD(boardp))
3561 asc_prt_adv_bios(m, shost);
3562
3563 /*
3564 * Display driver information for each device attached to the board.
3565 */
3566 asc_prt_board_devices(m, shost);
3567
3568 /*
3569 * Display EEPROM configuration for the board.
3570 */
3571 if (ASC_NARROW_BOARD(boardp))
3572 asc_prt_asc_board_eeprom(m, shost);
3573 else
3574 asc_prt_adv_board_eeprom(m, shost);
3575
3576 /*
3577 * Display driver configuration and information for the board.
3578 */
3579 asc_prt_driver_conf(m, shost);
3580
3581 #ifdef ADVANSYS_STATS
3582 /*
3583 * Display driver statistics for the board.
3584 */
3585 asc_prt_board_stats(m, shost);
3586 #endif /* ADVANSYS_STATS */
3587
3588 /*
3589 * Display Asc Library dynamic configuration information
3590 * for the board.
3591 */
3592 if (ASC_NARROW_BOARD(boardp))
3593 asc_prt_asc_board_info(m, shost);
3594 else
3595 asc_prt_adv_board_info(m, shost);
3596 return 0;
3597 }
3598 #endif /* CONFIG_PROC_FS */
3599
3600 static void asc_scsi_done(struct scsi_cmnd *scp)
3601 {
3602 scsi_dma_unmap(scp);
3603 ASC_STATS(scp->device->host, done);
3604 scsi_done(scp);
3605 }
3606
3607 static void AscSetBank(PortAddr iop_base, uchar bank)
3608 {
3609 uchar val;
3610
3611 val = AscGetChipControl(iop_base) &
3612 (~
3613 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3614 CC_CHIP_RESET));
3615 if (bank == 1) {
3616 val |= CC_BANK_ONE;
3617 } else if (bank == 2) {
3618 val |= CC_DIAG | CC_BANK_ONE;
3619 } else {
3620 val &= ~CC_BANK_ONE;
3621 }
3622 AscSetChipControl(iop_base, val);
3623 }
3624
3625 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3626 {
3627 AscSetBank(iop_base, 1);
3628 AscWriteChipIH(iop_base, ins_code);
3629 AscSetBank(iop_base, 0);
3630 }
3631
3632 static int AscStartChip(PortAddr iop_base)
3633 {
3634 AscSetChipControl(iop_base, 0);
3635 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3636 return (0);
3637 }
3638 return (1);
3639 }
3640
3641 static bool AscStopChip(PortAddr iop_base)
3642 {
3643 uchar cc_val;
3644
3645 cc_val =
3646 AscGetChipControl(iop_base) &
3647 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3648 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3649 AscSetChipIH(iop_base, INS_HALT);
3650 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3651 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
3652 return false;
3653 }
3654 return true;
3655 }
3656
3657 static bool AscIsChipHalted(PortAddr iop_base)
3658 {
3659 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3660 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
3661 return true;
3662 }
3663 }
3664 return false;
3665 }
3666
3667 static bool AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
3668 {
3669 PortAddr iop_base;
3670 int i = 10;
3671
3672 iop_base = asc_dvc->iop_base;
3673 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3674 && (i-- > 0)) {
3675 mdelay(100);
3676 }
3677 AscStopChip(iop_base);
3678 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3679 udelay(60);
3680 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3681 AscSetChipIH(iop_base, INS_HALT);
3682 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3683 AscSetChipControl(iop_base, CC_HALT);
3684 mdelay(200);
3685 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3686 AscSetChipStatus(iop_base, 0);
3687 return (AscIsChipHalted(iop_base));
3688 }
3689
3690 static int AscFindSignature(PortAddr iop_base)
3691 {
3692 ushort sig_word;
3693
3694 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
3695 iop_base, AscGetChipSignatureByte(iop_base));
3696 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
3697 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
3698 iop_base, AscGetChipSignatureWord(iop_base));
3699 sig_word = AscGetChipSignatureWord(iop_base);
3700 if ((sig_word == (ushort)ASC_1000_ID0W) ||
3701 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3702 return (1);
3703 }
3704 }
3705 return (0);
3706 }
3707
3708 static void AscEnableInterrupt(PortAddr iop_base)
3709 {
3710 ushort cfg;
3711
3712 cfg = AscGetChipCfgLsw(iop_base);
3713 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
3714 }
3715
3716 static void AscDisableInterrupt(PortAddr iop_base)
3717 {
3718 ushort cfg;
3719
3720 cfg = AscGetChipCfgLsw(iop_base);
3721 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
3722 }
3723
3724 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3725 {
3726 unsigned char byte_data;
3727 unsigned short word_data;
3728
3729 if (isodd_word(addr)) {
3730 AscSetChipLramAddr(iop_base, addr - 1);
3731 word_data = AscGetChipLramData(iop_base);
3732 byte_data = (word_data >> 8) & 0xFF;
3733 } else {
3734 AscSetChipLramAddr(iop_base, addr);
3735 word_data = AscGetChipLramData(iop_base);
3736 byte_data = word_data & 0xFF;
3737 }
3738 return byte_data;
3739 }
3740
3741 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3742 {
3743 ushort word_data;
3744
3745 AscSetChipLramAddr(iop_base, addr);
3746 word_data = AscGetChipLramData(iop_base);
3747 return (word_data);
3748 }
3749
3750 static void
3751 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3752 {
3753 int i;
3754
3755 AscSetChipLramAddr(iop_base, s_addr);
3756 for (i = 0; i < words; i++) {
3757 AscSetChipLramData(iop_base, set_wval);
3758 }
3759 }
3760
3761 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
3762 {
3763 AscSetChipLramAddr(iop_base, addr);
3764 AscSetChipLramData(iop_base, word_val);
3765 }
3766
3767 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
3768 {
3769 ushort word_data;
3770
3771 if (isodd_word(addr)) {
3772 addr--;
3773 word_data = AscReadLramWord(iop_base, addr);
3774 word_data &= 0x00FF;
3775 word_data |= (((ushort)byte_val << 8) & 0xFF00);
3776 } else {
3777 word_data = AscReadLramWord(iop_base, addr);
3778 word_data &= 0xFF00;
3779 word_data |= ((ushort)byte_val & 0x00FF);
3780 }
3781 AscWriteLramWord(iop_base, addr, word_data);
3782 }
3783
3784 /*
3785 * Copy 2 bytes to LRAM.
3786 *
3787 * The source data is assumed to be in little-endian order in memory
3788 * and is maintained in little-endian order when written to LRAM.
3789 */
3790 static void
3791 AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
3792 const uchar *s_buffer, int words)
3793 {
3794 int i;
3795
3796 AscSetChipLramAddr(iop_base, s_addr);
3797 for (i = 0; i < 2 * words; i += 2) {
3798 /*
3799 * On a little-endian system the second argument below
3800 * produces a little-endian ushort which is written to
3801 * LRAM in little-endian order. On a big-endian system
3802 * the second argument produces a big-endian ushort which
3803 * is "transparently" byte-swapped by outpw() and written
3804 * in little-endian order to LRAM.
3805 */
3806 outpw(iop_base + IOP_RAM_DATA,
3807 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
3808 }
3809 }
3810
3811 /*
3812 * Copy 4 bytes to LRAM.
3813 *
3814 * The source data is assumed to be in little-endian order in memory
3815 * and is maintained in little-endian order when written to LRAM.
3816 */
3817 static void
3818 AscMemDWordCopyPtrToLram(PortAddr iop_base,
3819 ushort s_addr, uchar *s_buffer, int dwords)
3820 {
3821 int i;
3822
3823 AscSetChipLramAddr(iop_base, s_addr);
3824 for (i = 0; i < 4 * dwords; i += 4) {
3825 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
3826 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
3827 }
3828 }
3829
3830 /*
3831 * Copy 2 bytes from LRAM.
3832 *
3833 * The source data is assumed to be in little-endian order in LRAM
3834 * and is maintained in little-endian order when written to memory.
3835 */
3836 static void
3837 AscMemWordCopyPtrFromLram(PortAddr iop_base,
3838 ushort s_addr, uchar *d_buffer, int words)
3839 {
3840 int i;
3841 ushort word;
3842
3843 AscSetChipLramAddr(iop_base, s_addr);
3844 for (i = 0; i < 2 * words; i += 2) {
3845 word = inpw(iop_base + IOP_RAM_DATA);
3846 d_buffer[i] = word & 0xff;
3847 d_buffer[i + 1] = (word >> 8) & 0xff;
3848 }
3849 }
3850
3851 static u32 AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
3852 {
3853 u32 sum = 0;
3854 int i;
3855
3856 for (i = 0; i < words; i++, s_addr += 2) {
3857 sum += AscReadLramWord(iop_base, s_addr);
3858 }
3859 return (sum);
3860 }
3861
3862 static void AscInitLram(ASC_DVC_VAR *asc_dvc)
3863 {
3864 uchar i;
3865 ushort s_addr;
3866 PortAddr iop_base;
3867
3868 iop_base = asc_dvc->iop_base;
3869 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
3870 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
3871 64) >> 1));
3872 i = ASC_MIN_ACTIVE_QNO;
3873 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
3874 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3875 (uchar)(i + 1));
3876 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3877 (uchar)(asc_dvc->max_total_qng));
3878 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3879 (uchar)i);
3880 i++;
3881 s_addr += ASC_QBLK_SIZE;
3882 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
3883 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3884 (uchar)(i + 1));
3885 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3886 (uchar)(i - 1));
3887 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3888 (uchar)i);
3889 }
3890 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3891 (uchar)ASC_QLINK_END);
3892 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3893 (uchar)(asc_dvc->max_total_qng - 1));
3894 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3895 (uchar)asc_dvc->max_total_qng);
3896 i++;
3897 s_addr += ASC_QBLK_SIZE;
3898 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
3899 i++, s_addr += ASC_QBLK_SIZE) {
3900 AscWriteLramByte(iop_base,
3901 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
3902 AscWriteLramByte(iop_base,
3903 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
3904 AscWriteLramByte(iop_base,
3905 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
3906 }
3907 }
3908
3909 static u32
3910 AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
3911 const uchar *mcode_buf, ushort mcode_size)
3912 {
3913 u32 chksum;
3914 ushort mcode_word_size;
3915 ushort mcode_chksum;
3916
3917 /* Write the microcode buffer starting at LRAM address 0. */
3918 mcode_word_size = (ushort)(mcode_size >> 1);
3919 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
3920 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
3921
3922 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
3923 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
3924 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
3925 (ushort)ASC_CODE_SEC_BEG,
3926 (ushort)((mcode_size -
3927 s_addr - (ushort)
3928 ASC_CODE_SEC_BEG) /
3929 2));
3930 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
3931 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
3932 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
3933 return chksum;
3934 }
3935
3936 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
3937 {
3938 PortAddr iop_base;
3939 int i;
3940 ushort lram_addr;
3941
3942 iop_base = asc_dvc->iop_base;
3943 AscPutRiscVarFreeQHead(iop_base, 1);
3944 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
3945 AscPutVarFreeQHead(iop_base, 1);
3946 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
3947 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
3948 (uchar)((int)asc_dvc->max_total_qng + 1));
3949 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
3950 (uchar)((int)asc_dvc->max_total_qng + 2));
3951 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
3952 asc_dvc->max_total_qng);
3953 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
3954 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
3955 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
3956 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
3957 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
3958 AscPutQDoneInProgress(iop_base, 0);
3959 lram_addr = ASC_QADR_BEG;
3960 for (i = 0; i < 32; i++, lram_addr += 2) {
3961 AscWriteLramWord(iop_base, lram_addr, 0);
3962 }
3963 }
3964
3965 static int AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
3966 {
3967 int i;
3968 int warn_code;
3969 PortAddr iop_base;
3970 __le32 phy_addr;
3971 __le32 phy_size;
3972 struct asc_board *board = asc_dvc_to_board(asc_dvc);
3973
3974 iop_base = asc_dvc->iop_base;
3975 warn_code = 0;
3976 for (i = 0; i <= ASC_MAX_TID; i++) {
3977 AscPutMCodeInitSDTRAtID(iop_base, i,
3978 asc_dvc->cfg->sdtr_period_offset[i]);
3979 }
3980
3981 AscInitQLinkVar(asc_dvc);
3982 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
3983 asc_dvc->cfg->disc_enable);
3984 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
3985 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
3986
3987 /* Ensure overrun buffer is aligned on an 8 byte boundary. */
3988 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
3989 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
3990 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
3991 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
3992 warn_code = -ENOMEM;
3993 goto err_dma_map;
3994 }
3995 phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
3996 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
3997 (uchar *)&phy_addr, 1);
3998 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
3999 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4000 (uchar *)&phy_size, 1);
4001
4002 asc_dvc->cfg->mcode_date =
4003 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4004 asc_dvc->cfg->mcode_version =
4005 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4006
4007 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4008 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4009 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
4010 warn_code = -EINVAL;
4011 goto err_mcode_start;
4012 }
4013 if (AscStartChip(iop_base) != 1) {
4014 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
4015 warn_code = -EIO;
4016 goto err_mcode_start;
4017 }
4018
4019 return warn_code;
4020
4021 err_mcode_start:
4022 dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4023 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4024 err_dma_map:
4025 asc_dvc->overrun_dma = 0;
4026 return warn_code;
4027 }
4028
4029 static int AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4030 {
4031 const struct firmware *fw;
4032 const char fwname[] = "advansys/mcode.bin";
4033 int err;
4034 unsigned long chksum;
4035 int warn_code;
4036 PortAddr iop_base;
4037
4038 iop_base = asc_dvc->iop_base;
4039 warn_code = 0;
4040 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4041 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4042 AscResetChipAndScsiBus(asc_dvc);
4043 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4044 }
4045 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4046 if (asc_dvc->err_code != 0)
4047 return ASC_ERROR;
4048 if (!AscFindSignature(asc_dvc->iop_base)) {
4049 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4050 return warn_code;
4051 }
4052 AscDisableInterrupt(iop_base);
4053 AscInitLram(asc_dvc);
4054
4055 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4056 if (err) {
4057 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4058 fwname, err);
4059 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4060 return err;
4061 }
4062 if (fw->size < 4) {
4063 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4064 fw->size, fwname);
4065 release_firmware(fw);
4066 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4067 return -EINVAL;
4068 }
4069 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4070 (fw->data[1] << 8) | fw->data[0];
4071 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4072 if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4073 fw->size - 4) != chksum) {
4074 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4075 release_firmware(fw);
4076 return warn_code;
4077 }
4078 release_firmware(fw);
4079 warn_code |= AscInitMicroCodeVar(asc_dvc);
4080 if (!asc_dvc->overrun_dma)
4081 return warn_code;
4082 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4083 AscEnableInterrupt(iop_base);
4084 return warn_code;
4085 }
4086
4087 /*
4088 * Load the Microcode
4089 *
4090 * Write the microcode image to RISC memory starting at address 0.
4091 *
4092 * The microcode is stored compressed in the following format:
4093 *
4094 * 254 word (508 byte) table indexed by byte code followed
4095 * by the following byte codes:
4096 *
4097 * 1-Byte Code:
4098 * 00: Emit word 0 in table.
4099 * 01: Emit word 1 in table.
4100 * .
4101 * FD: Emit word 253 in table.
4102 *
4103 * Multi-Byte Code:
4104 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4105 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4106 *
4107 * Returns 0 or an error if the checksum doesn't match
4108 */
4109 static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4110 int size, int memsize, int chksum)
4111 {
4112 int i, j, end, len = 0;
4113 u32 sum;
4114
4115 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4116
4117 for (i = 253 * 2; i < size; i++) {
4118 if (buf[i] == 0xff) {
4119 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4120 for (j = 0; j < buf[i + 1]; j++) {
4121 AdvWriteWordAutoIncLram(iop_base, word);
4122 len += 2;
4123 }
4124 i += 3;
4125 } else if (buf[i] == 0xfe) {
4126 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4127 AdvWriteWordAutoIncLram(iop_base, word);
4128 i += 2;
4129 len += 2;
4130 } else {
4131 unsigned int off = buf[i] * 2;
4132 unsigned short word = (buf[off + 1] << 8) | buf[off];
4133 AdvWriteWordAutoIncLram(iop_base, word);
4134 len += 2;
4135 }
4136 }
4137
4138 end = len;
4139
4140 while (len < memsize) {
4141 AdvWriteWordAutoIncLram(iop_base, 0);
4142 len += 2;
4143 }
4144
4145 /* Verify the microcode checksum. */
4146 sum = 0;
4147 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4148
4149 for (len = 0; len < end; len += 2) {
4150 sum += AdvReadWordAutoIncLram(iop_base);
4151 }
4152
4153 if (sum != chksum)
4154 return ASC_IERR_MCODE_CHKSUM;
4155
4156 return 0;
4157 }
4158
4159 static void AdvBuildCarrierFreelist(struct adv_dvc_var *adv_dvc)
4160 {
4161 off_t carr_offset = 0, next_offset;
4162 dma_addr_t carr_paddr;
4163 int carr_num = ADV_CARRIER_BUFSIZE / sizeof(ADV_CARR_T), i;
4164
4165 for (i = 0; i < carr_num; i++) {
4166 carr_offset = i * sizeof(ADV_CARR_T);
4167 /* Get physical address of the carrier 'carrp'. */
4168 carr_paddr = adv_dvc->carrier_addr + carr_offset;
4169
4170 adv_dvc->carrier[i].carr_pa = cpu_to_le32(carr_paddr);
4171 adv_dvc->carrier[i].carr_va = cpu_to_le32(carr_offset);
4172 adv_dvc->carrier[i].areq_vpa = 0;
4173 next_offset = carr_offset + sizeof(ADV_CARR_T);
4174 if (i == carr_num)
4175 next_offset = ~0;
4176 adv_dvc->carrier[i].next_vpa = cpu_to_le32(next_offset);
4177 }
4178 /*
4179 * We cannot have a carrier with 'carr_va' of '0', as
4180 * a reference to this carrier would be interpreted as
4181 * list termination.
4182 * So start at carrier 1 with the freelist.
4183 */
4184 adv_dvc->carr_freelist = &adv_dvc->carrier[1];
4185 }
4186
4187 static ADV_CARR_T *adv_get_carrier(struct adv_dvc_var *adv_dvc, u32 offset)
4188 {
4189 int index;
4190
4191 BUG_ON(offset > ADV_CARRIER_BUFSIZE);
4192
4193 index = offset / sizeof(ADV_CARR_T);
4194 return &adv_dvc->carrier[index];
4195 }
4196
4197 static ADV_CARR_T *adv_get_next_carrier(struct adv_dvc_var *adv_dvc)
4198 {
4199 ADV_CARR_T *carrp = adv_dvc->carr_freelist;
4200 u32 next_vpa = le32_to_cpu(carrp->next_vpa);
4201
4202 if (next_vpa == 0 || next_vpa == ~0) {
4203 ASC_DBG(1, "invalid vpa offset 0x%x\n", next_vpa);
4204 return NULL;
4205 }
4206
4207 adv_dvc->carr_freelist = adv_get_carrier(adv_dvc, next_vpa);
4208 /*
4209 * insert stopper carrier to terminate list
4210 */
4211 carrp->next_vpa = cpu_to_le32(ADV_CQ_STOPPER);
4212
4213 return carrp;
4214 }
4215
4216 /*
4217 * 'offset' is the index in the request pointer array
4218 */
4219 static adv_req_t * adv_get_reqp(struct adv_dvc_var *adv_dvc, u32 offset)
4220 {
4221 struct asc_board *boardp = adv_dvc->drv_ptr;
4222
4223 BUG_ON(offset > adv_dvc->max_host_qng);
4224 return &boardp->adv_reqp[offset];
4225 }
4226
4227 /*
4228 * Send an idle command to the chip and wait for completion.
4229 *
4230 * Command completion is polled for once per microsecond.
4231 *
4232 * The function can be called from anywhere including an interrupt handler.
4233 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4234 * functions to prevent reentrancy.
4235 *
4236 * Return Values:
4237 * ADV_TRUE - command completed successfully
4238 * ADV_FALSE - command failed
4239 * ADV_ERROR - command timed out
4240 */
4241 static int
4242 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4243 ushort idle_cmd, u32 idle_cmd_parameter)
4244 {
4245 int result, i, j;
4246 AdvPortAddr iop_base;
4247
4248 iop_base = asc_dvc->iop_base;
4249
4250 /*
4251 * Clear the idle command status which is set by the microcode
4252 * to a non-zero value to indicate when the command is completed.
4253 * The non-zero result is one of the IDLE_CMD_STATUS_* values
4254 */
4255 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4256
4257 /*
4258 * Write the idle command value after the idle command parameter
4259 * has been written to avoid a race condition. If the order is not
4260 * followed, the microcode may process the idle command before the
4261 * parameters have been written to LRAM.
4262 */
4263 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4264 cpu_to_le32(idle_cmd_parameter));
4265 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4266
4267 /*
4268 * Tickle the RISC to tell it to process the idle command.
4269 */
4270 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4271 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4272 /*
4273 * Clear the tickle value. In the ASC-3550 the RISC flag
4274 * command 'clr_tickle_b' does not work unless the host
4275 * value is cleared.
4276 */
4277 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4278 }
4279
4280 /* Wait for up to 100 millisecond for the idle command to timeout. */
4281 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4282 /* Poll once each microsecond for command completion. */
4283 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4284 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4285 result);
4286 if (result != 0)
4287 return result;
4288 udelay(1);
4289 }
4290 }
4291
4292 BUG(); /* The idle command should never timeout. */
4293 return ADV_ERROR;
4294 }
4295
4296 /*
4297 * Reset SCSI Bus and purge all outstanding requests.
4298 *
4299 * Return Value:
4300 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
4301 * ADV_FALSE(0) - Microcode command failed.
4302 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4303 * may be hung which requires driver recovery.
4304 */
4305 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4306 {
4307 int status;
4308
4309 /*
4310 * Send the SCSI Bus Reset idle start idle command which asserts
4311 * the SCSI Bus Reset signal.
4312 */
4313 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4314 if (status != ADV_TRUE) {
4315 return status;
4316 }
4317
4318 /*
4319 * Delay for the specified SCSI Bus Reset hold time.
4320 *
4321 * The hold time delay is done on the host because the RISC has no
4322 * microsecond accurate timer.
4323 */
4324 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4325
4326 /*
4327 * Send the SCSI Bus Reset end idle command which de-asserts
4328 * the SCSI Bus Reset signal and purges any pending requests.
4329 */
4330 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4331 if (status != ADV_TRUE) {
4332 return status;
4333 }
4334
4335 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4336
4337 return status;
4338 }
4339
4340 /*
4341 * Initialize the ASC-3550.
4342 *
4343 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4344 *
4345 * For a non-fatal error return a warning code. If there are no warnings
4346 * then 0 is returned.
4347 *
4348 * Needed after initialization for error recovery.
4349 */
4350 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4351 {
4352 const struct firmware *fw;
4353 const char fwname[] = "advansys/3550.bin";
4354 AdvPortAddr iop_base;
4355 ushort warn_code;
4356 int begin_addr;
4357 int end_addr;
4358 ushort code_sum;
4359 int word;
4360 int i;
4361 int err;
4362 unsigned long chksum;
4363 ushort scsi_cfg1;
4364 uchar tid;
4365 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4366 ushort wdtr_able = 0, sdtr_able, tagqng_able;
4367 uchar max_cmd[ADV_MAX_TID + 1];
4368
4369 /* If there is already an error, don't continue. */
4370 if (asc_dvc->err_code != 0)
4371 return ADV_ERROR;
4372
4373 /*
4374 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4375 */
4376 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4377 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4378 return ADV_ERROR;
4379 }
4380
4381 warn_code = 0;
4382 iop_base = asc_dvc->iop_base;
4383
4384 /*
4385 * Save the RISC memory BIOS region before writing the microcode.
4386 * The BIOS may already be loaded and using its RISC LRAM region
4387 * so its region must be saved and restored.
4388 *
4389 * Note: This code makes the assumption, which is currently true,
4390 * that a chip reset does not clear RISC LRAM.
4391 */
4392 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4393 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4394 bios_mem[i]);
4395 }
4396
4397 /*
4398 * Save current per TID negotiated values.
4399 */
4400 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4401 ushort bios_version, major, minor;
4402
4403 bios_version =
4404 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4405 major = (bios_version >> 12) & 0xF;
4406 minor = (bios_version >> 8) & 0xF;
4407 if (major < 3 || (major == 3 && minor == 1)) {
4408 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4409 AdvReadWordLram(iop_base, 0x120, wdtr_able);
4410 } else {
4411 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4412 }
4413 }
4414 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4415 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4416 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4417 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4418 max_cmd[tid]);
4419 }
4420
4421 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4422 if (err) {
4423 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4424 fwname, err);
4425 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4426 return err;
4427 }
4428 if (fw->size < 4) {
4429 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4430 fw->size, fwname);
4431 release_firmware(fw);
4432 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4433 return -EINVAL;
4434 }
4435 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4436 (fw->data[1] << 8) | fw->data[0];
4437 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4438 fw->size - 4, ADV_3550_MEMSIZE,
4439 chksum);
4440 release_firmware(fw);
4441 if (asc_dvc->err_code)
4442 return ADV_ERROR;
4443
4444 /*
4445 * Restore the RISC memory BIOS region.
4446 */
4447 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4448 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4449 bios_mem[i]);
4450 }
4451
4452 /*
4453 * Calculate and write the microcode code checksum to the microcode
4454 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4455 */
4456 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4457 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4458 code_sum = 0;
4459 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4460 for (word = begin_addr; word < end_addr; word += 2) {
4461 code_sum += AdvReadWordAutoIncLram(iop_base);
4462 }
4463 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4464
4465 /*
4466 * Read and save microcode version and date.
4467 */
4468 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4469 asc_dvc->cfg->mcode_date);
4470 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4471 asc_dvc->cfg->mcode_version);
4472
4473 /*
4474 * Set the chip type to indicate the ASC3550.
4475 */
4476 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4477
4478 /*
4479 * If the PCI Configuration Command Register "Parity Error Response
4480 * Control" Bit was clear (0), then set the microcode variable
4481 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4482 * to ignore DMA parity errors.
4483 */
4484 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4485 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4486 word |= CONTROL_FLAG_IGNORE_PERR;
4487 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4488 }
4489
4490 /*
4491 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4492 * threshold of 128 bytes. This register is only accessible to the host.
4493 */
4494 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4495 START_CTL_EMFU | READ_CMD_MRM);
4496
4497 /*
4498 * Microcode operating variables for WDTR, SDTR, and command tag
4499 * queuing will be set in slave_configure() based on what a
4500 * device reports it is capable of in Inquiry byte 7.
4501 *
4502 * If SCSI Bus Resets have been disabled, then directly set
4503 * SDTR and WDTR from the EEPROM configuration. This will allow
4504 * the BIOS and warm boot to work without a SCSI bus hang on
4505 * the Inquiry caused by host and target mismatched DTR values.
4506 * Without the SCSI Bus Reset, before an Inquiry a device can't
4507 * be assumed to be in Asynchronous, Narrow mode.
4508 */
4509 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4510 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4511 asc_dvc->wdtr_able);
4512 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4513 asc_dvc->sdtr_able);
4514 }
4515
4516 /*
4517 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4518 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4519 * bitmask. These values determine the maximum SDTR speed negotiated
4520 * with a device.
4521 *
4522 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4523 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4524 * without determining here whether the device supports SDTR.
4525 *
4526 * 4-bit speed SDTR speed name
4527 * =========== ===============
4528 * 0000b (0x0) SDTR disabled
4529 * 0001b (0x1) 5 Mhz
4530 * 0010b (0x2) 10 Mhz
4531 * 0011b (0x3) 20 Mhz (Ultra)
4532 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
4533 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
4534 * 0110b (0x6) Undefined
4535 * .
4536 * 1111b (0xF) Undefined
4537 */
4538 word = 0;
4539 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4540 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4541 /* Set Ultra speed for TID 'tid'. */
4542 word |= (0x3 << (4 * (tid % 4)));
4543 } else {
4544 /* Set Fast speed for TID 'tid'. */
4545 word |= (0x2 << (4 * (tid % 4)));
4546 }
4547 if (tid == 3) { /* Check if done with sdtr_speed1. */
4548 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4549 word = 0;
4550 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
4551 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4552 word = 0;
4553 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
4554 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4555 word = 0;
4556 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
4557 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4558 /* End of loop. */
4559 }
4560 }
4561
4562 /*
4563 * Set microcode operating variable for the disconnect per TID bitmask.
4564 */
4565 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4566 asc_dvc->cfg->disc_enable);
4567
4568 /*
4569 * Set SCSI_CFG0 Microcode Default Value.
4570 *
4571 * The microcode will set the SCSI_CFG0 register using this value
4572 * after it is started below.
4573 */
4574 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4575 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4576 asc_dvc->chip_scsi_id);
4577
4578 /*
4579 * Determine SCSI_CFG1 Microcode Default Value.
4580 *
4581 * The microcode will set the SCSI_CFG1 register using this value
4582 * after it is started below.
4583 */
4584
4585 /* Read current SCSI_CFG1 Register value. */
4586 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4587
4588 /*
4589 * If all three connectors are in use, return an error.
4590 */
4591 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4592 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4593 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4594 return ADV_ERROR;
4595 }
4596
4597 /*
4598 * If the internal narrow cable is reversed all of the SCSI_CTRL
4599 * register signals will be set. Check for and return an error if
4600 * this condition is found.
4601 */
4602 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4603 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4604 return ADV_ERROR;
4605 }
4606
4607 /*
4608 * If this is a differential board and a single-ended device
4609 * is attached to one of the connectors, return an error.
4610 */
4611 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4612 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4613 return ADV_ERROR;
4614 }
4615
4616 /*
4617 * If automatic termination control is enabled, then set the
4618 * termination value based on a table listed in a_condor.h.
4619 *
4620 * If manual termination was specified with an EEPROM setting
4621 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4622 * is ready to be 'ored' into SCSI_CFG1.
4623 */
4624 if (asc_dvc->cfg->termination == 0) {
4625 /*
4626 * The software always controls termination by setting TERM_CTL_SEL.
4627 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4628 */
4629 asc_dvc->cfg->termination |= TERM_CTL_SEL;
4630
4631 switch (scsi_cfg1 & CABLE_DETECT) {
4632 /* TERM_CTL_H: on, TERM_CTL_L: on */
4633 case 0x3:
4634 case 0x7:
4635 case 0xB:
4636 case 0xD:
4637 case 0xE:
4638 case 0xF:
4639 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4640 break;
4641
4642 /* TERM_CTL_H: on, TERM_CTL_L: off */
4643 case 0x1:
4644 case 0x5:
4645 case 0x9:
4646 case 0xA:
4647 case 0xC:
4648 asc_dvc->cfg->termination |= TERM_CTL_H;
4649 break;
4650
4651 /* TERM_CTL_H: off, TERM_CTL_L: off */
4652 case 0x2:
4653 case 0x6:
4654 break;
4655 }
4656 }
4657
4658 /*
4659 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4660 */
4661 scsi_cfg1 &= ~TERM_CTL;
4662
4663 /*
4664 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4665 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4666 * referenced, because the hardware internally inverts
4667 * the Termination High and Low bits if TERM_POL is set.
4668 */
4669 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4670
4671 /*
4672 * Set SCSI_CFG1 Microcode Default Value
4673 *
4674 * Set filter value and possibly modified termination control
4675 * bits in the Microcode SCSI_CFG1 Register Value.
4676 *
4677 * The microcode will set the SCSI_CFG1 register using this value
4678 * after it is started below.
4679 */
4680 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4681 FLTR_DISABLE | scsi_cfg1);
4682
4683 /*
4684 * Set MEM_CFG Microcode Default Value
4685 *
4686 * The microcode will set the MEM_CFG register using this value
4687 * after it is started below.
4688 *
4689 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4690 * are defined.
4691 *
4692 * ASC-3550 has 8KB internal memory.
4693 */
4694 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4695 BIOS_EN | RAM_SZ_8KB);
4696
4697 /*
4698 * Set SEL_MASK Microcode Default Value
4699 *
4700 * The microcode will set the SEL_MASK register using this value
4701 * after it is started below.
4702 */
4703 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4704 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4705
4706 AdvBuildCarrierFreelist(asc_dvc);
4707
4708 /*
4709 * Set-up the Host->RISC Initiator Command Queue (ICQ).
4710 */
4711
4712 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
4713 if (!asc_dvc->icq_sp) {
4714 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4715 return ADV_ERROR;
4716 }
4717
4718 /*
4719 * Set RISC ICQ physical address start value.
4720 */
4721 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4722
4723 /*
4724 * Set-up the RISC->Host Initiator Response Queue (IRQ).
4725 */
4726 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
4727 if (!asc_dvc->irq_sp) {
4728 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4729 return ADV_ERROR;
4730 }
4731
4732 /*
4733 * Set RISC IRQ physical address start value.
4734 */
4735 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4736 asc_dvc->carr_pending_cnt = 0;
4737
4738 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4739 (ADV_INTR_ENABLE_HOST_INTR |
4740 ADV_INTR_ENABLE_GLOBAL_INTR));
4741
4742 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4743 AdvWriteWordRegister(iop_base, IOPW_PC, word);
4744
4745 /* finally, finally, gentlemen, start your engine */
4746 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4747
4748 /*
4749 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4750 * Resets should be performed. The RISC has to be running
4751 * to issue a SCSI Bus Reset.
4752 */
4753 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4754 /*
4755 * If the BIOS Signature is present in memory, restore the
4756 * BIOS Handshake Configuration Table and do not perform
4757 * a SCSI Bus Reset.
4758 */
4759 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4760 0x55AA) {
4761 /*
4762 * Restore per TID negotiated values.
4763 */
4764 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4765 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4766 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4767 tagqng_able);
4768 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4769 AdvWriteByteLram(iop_base,
4770 ASC_MC_NUMBER_OF_MAX_CMD + tid,
4771 max_cmd[tid]);
4772 }
4773 } else {
4774 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
4775 warn_code = ASC_WARN_BUSRESET_ERROR;
4776 }
4777 }
4778 }
4779
4780 return warn_code;
4781 }
4782
4783 /*
4784 * Initialize the ASC-38C0800.
4785 *
4786 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4787 *
4788 * For a non-fatal error return a warning code. If there are no warnings
4789 * then 0 is returned.
4790 *
4791 * Needed after initialization for error recovery.
4792 */
4793 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
4794 {
4795 const struct firmware *fw;
4796 const char fwname[] = "advansys/38C0800.bin";
4797 AdvPortAddr iop_base;
4798 ushort warn_code;
4799 int begin_addr;
4800 int end_addr;
4801 ushort code_sum;
4802 int word;
4803 int i;
4804 int err;
4805 unsigned long chksum;
4806 ushort scsi_cfg1;
4807 uchar byte;
4808 uchar tid;
4809 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4810 ushort wdtr_able, sdtr_able, tagqng_able;
4811 uchar max_cmd[ADV_MAX_TID + 1];
4812
4813 /* If there is already an error, don't continue. */
4814 if (asc_dvc->err_code != 0)
4815 return ADV_ERROR;
4816
4817 /*
4818 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
4819 */
4820 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
4821 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4822 return ADV_ERROR;
4823 }
4824
4825 warn_code = 0;
4826 iop_base = asc_dvc->iop_base;
4827
4828 /*
4829 * Save the RISC memory BIOS region before writing the microcode.
4830 * The BIOS may already be loaded and using its RISC LRAM region
4831 * so its region must be saved and restored.
4832 *
4833 * Note: This code makes the assumption, which is currently true,
4834 * that a chip reset does not clear RISC LRAM.
4835 */
4836 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4837 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4838 bios_mem[i]);
4839 }
4840
4841 /*
4842 * Save current per TID negotiated values.
4843 */
4844 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4845 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4846 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4847 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4848 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4849 max_cmd[tid]);
4850 }
4851
4852 /*
4853 * RAM BIST (RAM Built-In Self Test)
4854 *
4855 * Address : I/O base + offset 0x38h register (byte).
4856 * Function: Bit 7-6(RW) : RAM mode
4857 * Normal Mode : 0x00
4858 * Pre-test Mode : 0x40
4859 * RAM Test Mode : 0x80
4860 * Bit 5 : unused
4861 * Bit 4(RO) : Done bit
4862 * Bit 3-0(RO) : Status
4863 * Host Error : 0x08
4864 * Int_RAM Error : 0x04
4865 * RISC Error : 0x02
4866 * SCSI Error : 0x01
4867 * No Error : 0x00
4868 *
4869 * Note: RAM BIST code should be put right here, before loading the
4870 * microcode and after saving the RISC memory BIOS region.
4871 */
4872
4873 /*
4874 * LRAM Pre-test
4875 *
4876 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
4877 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
4878 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
4879 * to NORMAL_MODE, return an error too.
4880 */
4881 for (i = 0; i < 2; i++) {
4882 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
4883 mdelay(10); /* Wait for 10ms before reading back. */
4884 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
4885 if ((byte & RAM_TEST_DONE) == 0
4886 || (byte & 0x0F) != PRE_TEST_VALUE) {
4887 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
4888 return ADV_ERROR;
4889 }
4890
4891 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
4892 mdelay(10); /* Wait for 10ms before reading back. */
4893 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
4894 != NORMAL_VALUE) {
4895 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
4896 return ADV_ERROR;
4897 }
4898 }
4899
4900 /*
4901 * LRAM Test - It takes about 1.5 ms to run through the test.
4902 *
4903 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
4904 * If Done bit not set or Status not 0, save register byte, set the
4905 * err_code, and return an error.
4906 */
4907 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
4908 mdelay(10); /* Wait for 10ms before checking status. */
4909
4910 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
4911 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
4912 /* Get here if Done bit not set or Status not 0. */
4913 asc_dvc->bist_err_code = byte; /* for BIOS display message */
4914 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
4915 return ADV_ERROR;
4916 }
4917
4918 /* We need to reset back to normal mode after LRAM test passes. */
4919 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
4920
4921 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4922 if (err) {
4923 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4924 fwname, err);
4925 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4926 return err;
4927 }
4928 if (fw->size < 4) {
4929 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4930 fw->size, fwname);
4931 release_firmware(fw);
4932 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4933 return -EINVAL;
4934 }
4935 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4936 (fw->data[1] << 8) | fw->data[0];
4937 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4938 fw->size - 4, ADV_38C0800_MEMSIZE,
4939 chksum);
4940 release_firmware(fw);
4941 if (asc_dvc->err_code)
4942 return ADV_ERROR;
4943
4944 /*
4945 * Restore the RISC memory BIOS region.
4946 */
4947 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4948 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4949 bios_mem[i]);
4950 }
4951
4952 /*
4953 * Calculate and write the microcode code checksum to the microcode
4954 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4955 */
4956 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4957 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4958 code_sum = 0;
4959 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4960 for (word = begin_addr; word < end_addr; word += 2) {
4961 code_sum += AdvReadWordAutoIncLram(iop_base);
4962 }
4963 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4964
4965 /*
4966 * Read microcode version and date.
4967 */
4968 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4969 asc_dvc->cfg->mcode_date);
4970 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4971 asc_dvc->cfg->mcode_version);
4972
4973 /*
4974 * Set the chip type to indicate the ASC38C0800.
4975 */
4976 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
4977
4978 /*
4979 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
4980 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
4981 * cable detection and then we are able to read C_DET[3:0].
4982 *
4983 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
4984 * Microcode Default Value' section below.
4985 */
4986 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4987 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
4988 scsi_cfg1 | DIS_TERM_DRV);
4989
4990 /*
4991 * If the PCI Configuration Command Register "Parity Error Response
4992 * Control" Bit was clear (0), then set the microcode variable
4993 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4994 * to ignore DMA parity errors.
4995 */
4996 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4997 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4998 word |= CONTROL_FLAG_IGNORE_PERR;
4999 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5000 }
5001
5002 /*
5003 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5004 * bits for the default FIFO threshold.
5005 *
5006 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5007 *
5008 * For DMA Errata #4 set the BC_THRESH_ENB bit.
5009 */
5010 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5011 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5012 READ_CMD_MRM);
5013
5014 /*
5015 * Microcode operating variables for WDTR, SDTR, and command tag
5016 * queuing will be set in slave_configure() based on what a
5017 * device reports it is capable of in Inquiry byte 7.
5018 *
5019 * If SCSI Bus Resets have been disabled, then directly set
5020 * SDTR and WDTR from the EEPROM configuration. This will allow
5021 * the BIOS and warm boot to work without a SCSI bus hang on
5022 * the Inquiry caused by host and target mismatched DTR values.
5023 * Without the SCSI Bus Reset, before an Inquiry a device can't
5024 * be assumed to be in Asynchronous, Narrow mode.
5025 */
5026 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5027 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5028 asc_dvc->wdtr_able);
5029 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5030 asc_dvc->sdtr_able);
5031 }
5032
5033 /*
5034 * Set microcode operating variables for DISC and SDTR_SPEED1,
5035 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5036 * configuration values.
5037 *
5038 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5039 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5040 * without determining here whether the device supports SDTR.
5041 */
5042 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5043 asc_dvc->cfg->disc_enable);
5044 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5045 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5046 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5047 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5048
5049 /*
5050 * Set SCSI_CFG0 Microcode Default Value.
5051 *
5052 * The microcode will set the SCSI_CFG0 register using this value
5053 * after it is started below.
5054 */
5055 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5056 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5057 asc_dvc->chip_scsi_id);
5058
5059 /*
5060 * Determine SCSI_CFG1 Microcode Default Value.
5061 *
5062 * The microcode will set the SCSI_CFG1 register using this value
5063 * after it is started below.
5064 */
5065
5066 /* Read current SCSI_CFG1 Register value. */
5067 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5068
5069 /*
5070 * If the internal narrow cable is reversed all of the SCSI_CTRL
5071 * register signals will be set. Check for and return an error if
5072 * this condition is found.
5073 */
5074 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5075 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5076 return ADV_ERROR;
5077 }
5078
5079 /*
5080 * All kind of combinations of devices attached to one of four
5081 * connectors are acceptable except HVD device attached. For example,
5082 * LVD device can be attached to SE connector while SE device attached
5083 * to LVD connector. If LVD device attached to SE connector, it only
5084 * runs up to Ultra speed.
5085 *
5086 * If an HVD device is attached to one of LVD connectors, return an
5087 * error. However, there is no way to detect HVD device attached to
5088 * SE connectors.
5089 */
5090 if (scsi_cfg1 & HVD) {
5091 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5092 return ADV_ERROR;
5093 }
5094
5095 /*
5096 * If either SE or LVD automatic termination control is enabled, then
5097 * set the termination value based on a table listed in a_condor.h.
5098 *
5099 * If manual termination was specified with an EEPROM setting then
5100 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5101 * to be 'ored' into SCSI_CFG1.
5102 */
5103 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5104 /* SE automatic termination control is enabled. */
5105 switch (scsi_cfg1 & C_DET_SE) {
5106 /* TERM_SE_HI: on, TERM_SE_LO: on */
5107 case 0x1:
5108 case 0x2:
5109 case 0x3:
5110 asc_dvc->cfg->termination |= TERM_SE;
5111 break;
5112
5113 /* TERM_SE_HI: on, TERM_SE_LO: off */
5114 case 0x0:
5115 asc_dvc->cfg->termination |= TERM_SE_HI;
5116 break;
5117 }
5118 }
5119
5120 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5121 /* LVD automatic termination control is enabled. */
5122 switch (scsi_cfg1 & C_DET_LVD) {
5123 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
5124 case 0x4:
5125 case 0x8:
5126 case 0xC:
5127 asc_dvc->cfg->termination |= TERM_LVD;
5128 break;
5129
5130 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
5131 case 0x0:
5132 break;
5133 }
5134 }
5135
5136 /*
5137 * Clear any set TERM_SE and TERM_LVD bits.
5138 */
5139 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5140
5141 /*
5142 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5143 */
5144 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5145
5146 /*
5147 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5148 * bits and set possibly modified termination control bits in the
5149 * Microcode SCSI_CFG1 Register Value.
5150 */
5151 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5152
5153 /*
5154 * Set SCSI_CFG1 Microcode Default Value
5155 *
5156 * Set possibly modified termination control and reset DIS_TERM_DRV
5157 * bits in the Microcode SCSI_CFG1 Register Value.
5158 *
5159 * The microcode will set the SCSI_CFG1 register using this value
5160 * after it is started below.
5161 */
5162 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5163
5164 /*
5165 * Set MEM_CFG Microcode Default Value
5166 *
5167 * The microcode will set the MEM_CFG register using this value
5168 * after it is started below.
5169 *
5170 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5171 * are defined.
5172 *
5173 * ASC-38C0800 has 16KB internal memory.
5174 */
5175 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5176 BIOS_EN | RAM_SZ_16KB);
5177
5178 /*
5179 * Set SEL_MASK Microcode Default Value
5180 *
5181 * The microcode will set the SEL_MASK register using this value
5182 * after it is started below.
5183 */
5184 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5185 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5186
5187 AdvBuildCarrierFreelist(asc_dvc);
5188
5189 /*
5190 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5191 */
5192
5193 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5194 if (!asc_dvc->icq_sp) {
5195 ASC_DBG(0, "Failed to get ICQ carrier\n");
5196 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5197 return ADV_ERROR;
5198 }
5199
5200 /*
5201 * Set RISC ICQ physical address start value.
5202 * carr_pa is LE, must be native before write
5203 */
5204 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5205
5206 /*
5207 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5208 */
5209 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5210 if (!asc_dvc->irq_sp) {
5211 ASC_DBG(0, "Failed to get IRQ carrier\n");
5212 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5213 return ADV_ERROR;
5214 }
5215
5216 /*
5217 * Set RISC IRQ physical address start value.
5218 *
5219 * carr_pa is LE, must be native before write *
5220 */
5221 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5222 asc_dvc->carr_pending_cnt = 0;
5223
5224 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5225 (ADV_INTR_ENABLE_HOST_INTR |
5226 ADV_INTR_ENABLE_GLOBAL_INTR));
5227
5228 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5229 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5230
5231 /* finally, finally, gentlemen, start your engine */
5232 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5233
5234 /*
5235 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5236 * Resets should be performed. The RISC has to be running
5237 * to issue a SCSI Bus Reset.
5238 */
5239 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5240 /*
5241 * If the BIOS Signature is present in memory, restore the
5242 * BIOS Handshake Configuration Table and do not perform
5243 * a SCSI Bus Reset.
5244 */
5245 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5246 0x55AA) {
5247 /*
5248 * Restore per TID negotiated values.
5249 */
5250 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5251 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5252 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5253 tagqng_able);
5254 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5255 AdvWriteByteLram(iop_base,
5256 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5257 max_cmd[tid]);
5258 }
5259 } else {
5260 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5261 warn_code = ASC_WARN_BUSRESET_ERROR;
5262 }
5263 }
5264 }
5265
5266 return warn_code;
5267 }
5268
5269 /*
5270 * Initialize the ASC-38C1600.
5271 *
5272 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
5273 *
5274 * For a non-fatal error return a warning code. If there are no warnings
5275 * then 0 is returned.
5276 *
5277 * Needed after initialization for error recovery.
5278 */
5279 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
5280 {
5281 const struct firmware *fw;
5282 const char fwname[] = "advansys/38C1600.bin";
5283 AdvPortAddr iop_base;
5284 ushort warn_code;
5285 int begin_addr;
5286 int end_addr;
5287 ushort code_sum;
5288 long word;
5289 int i;
5290 int err;
5291 unsigned long chksum;
5292 ushort scsi_cfg1;
5293 uchar byte;
5294 uchar tid;
5295 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
5296 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5297 uchar max_cmd[ASC_MAX_TID + 1];
5298
5299 /* If there is already an error, don't continue. */
5300 if (asc_dvc->err_code != 0) {
5301 return ADV_ERROR;
5302 }
5303
5304 /*
5305 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
5306 */
5307 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
5308 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5309 return ADV_ERROR;
5310 }
5311
5312 warn_code = 0;
5313 iop_base = asc_dvc->iop_base;
5314
5315 /*
5316 * Save the RISC memory BIOS region before writing the microcode.
5317 * The BIOS may already be loaded and using its RISC LRAM region
5318 * so its region must be saved and restored.
5319 *
5320 * Note: This code makes the assumption, which is currently true,
5321 * that a chip reset does not clear RISC LRAM.
5322 */
5323 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5324 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5325 bios_mem[i]);
5326 }
5327
5328 /*
5329 * Save current per TID negotiated values.
5330 */
5331 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5332 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5333 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5334 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5335 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5336 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5337 max_cmd[tid]);
5338 }
5339
5340 /*
5341 * RAM BIST (Built-In Self Test)
5342 *
5343 * Address : I/O base + offset 0x38h register (byte).
5344 * Function: Bit 7-6(RW) : RAM mode
5345 * Normal Mode : 0x00
5346 * Pre-test Mode : 0x40
5347 * RAM Test Mode : 0x80
5348 * Bit 5 : unused
5349 * Bit 4(RO) : Done bit
5350 * Bit 3-0(RO) : Status
5351 * Host Error : 0x08
5352 * Int_RAM Error : 0x04
5353 * RISC Error : 0x02
5354 * SCSI Error : 0x01
5355 * No Error : 0x00
5356 *
5357 * Note: RAM BIST code should be put right here, before loading the
5358 * microcode and after saving the RISC memory BIOS region.
5359 */
5360
5361 /*
5362 * LRAM Pre-test
5363 *
5364 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5365 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5366 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5367 * to NORMAL_MODE, return an error too.
5368 */
5369 for (i = 0; i < 2; i++) {
5370 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5371 mdelay(10); /* Wait for 10ms before reading back. */
5372 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5373 if ((byte & RAM_TEST_DONE) == 0
5374 || (byte & 0x0F) != PRE_TEST_VALUE) {
5375 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5376 return ADV_ERROR;
5377 }
5378
5379 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5380 mdelay(10); /* Wait for 10ms before reading back. */
5381 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5382 != NORMAL_VALUE) {
5383 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5384 return ADV_ERROR;
5385 }
5386 }
5387
5388 /*
5389 * LRAM Test - It takes about 1.5 ms to run through the test.
5390 *
5391 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5392 * If Done bit not set or Status not 0, save register byte, set the
5393 * err_code, and return an error.
5394 */
5395 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5396 mdelay(10); /* Wait for 10ms before checking status. */
5397
5398 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5399 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5400 /* Get here if Done bit not set or Status not 0. */
5401 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5402 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5403 return ADV_ERROR;
5404 }
5405
5406 /* We need to reset back to normal mode after LRAM test passes. */
5407 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5408
5409 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5410 if (err) {
5411 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5412 fwname, err);
5413 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5414 return err;
5415 }
5416 if (fw->size < 4) {
5417 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5418 fw->size, fwname);
5419 release_firmware(fw);
5420 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5421 return -EINVAL;
5422 }
5423 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5424 (fw->data[1] << 8) | fw->data[0];
5425 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5426 fw->size - 4, ADV_38C1600_MEMSIZE,
5427 chksum);
5428 release_firmware(fw);
5429 if (asc_dvc->err_code)
5430 return ADV_ERROR;
5431
5432 /*
5433 * Restore the RISC memory BIOS region.
5434 */
5435 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5436 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5437 bios_mem[i]);
5438 }
5439
5440 /*
5441 * Calculate and write the microcode code checksum to the microcode
5442 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5443 */
5444 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5445 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5446 code_sum = 0;
5447 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5448 for (word = begin_addr; word < end_addr; word += 2) {
5449 code_sum += AdvReadWordAutoIncLram(iop_base);
5450 }
5451 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5452
5453 /*
5454 * Read microcode version and date.
5455 */
5456 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5457 asc_dvc->cfg->mcode_date);
5458 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5459 asc_dvc->cfg->mcode_version);
5460
5461 /*
5462 * Set the chip type to indicate the ASC38C1600.
5463 */
5464 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
5465
5466 /*
5467 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5468 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5469 * cable detection and then we are able to read C_DET[3:0].
5470 *
5471 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5472 * Microcode Default Value' section below.
5473 */
5474 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5475 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5476 scsi_cfg1 | DIS_TERM_DRV);
5477
5478 /*
5479 * If the PCI Configuration Command Register "Parity Error Response
5480 * Control" Bit was clear (0), then set the microcode variable
5481 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5482 * to ignore DMA parity errors.
5483 */
5484 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5485 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5486 word |= CONTROL_FLAG_IGNORE_PERR;
5487 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5488 }
5489
5490 /*
5491 * If the BIOS control flag AIPP (Asynchronous Information
5492 * Phase Protection) disable bit is not set, then set the firmware
5493 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
5494 * AIPP checking and encoding.
5495 */
5496 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
5497 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5498 word |= CONTROL_FLAG_ENABLE_AIPP;
5499 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5500 }
5501
5502 /*
5503 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
5504 * and START_CTL_TH [3:2].
5505 */
5506 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5507 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
5508
5509 /*
5510 * Microcode operating variables for WDTR, SDTR, and command tag
5511 * queuing will be set in slave_configure() based on what a
5512 * device reports it is capable of in Inquiry byte 7.
5513 *
5514 * If SCSI Bus Resets have been disabled, then directly set
5515 * SDTR and WDTR from the EEPROM configuration. This will allow
5516 * the BIOS and warm boot to work without a SCSI bus hang on
5517 * the Inquiry caused by host and target mismatched DTR values.
5518 * Without the SCSI Bus Reset, before an Inquiry a device can't
5519 * be assumed to be in Asynchronous, Narrow mode.
5520 */
5521 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5522 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5523 asc_dvc->wdtr_able);
5524 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5525 asc_dvc->sdtr_able);
5526 }
5527
5528 /*
5529 * Set microcode operating variables for DISC and SDTR_SPEED1,
5530 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5531 * configuration values.
5532 *
5533 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5534 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5535 * without determining here whether the device supports SDTR.
5536 */
5537 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5538 asc_dvc->cfg->disc_enable);
5539 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5540 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5541 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5542 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5543
5544 /*
5545 * Set SCSI_CFG0 Microcode Default Value.
5546 *
5547 * The microcode will set the SCSI_CFG0 register using this value
5548 * after it is started below.
5549 */
5550 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5551 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5552 asc_dvc->chip_scsi_id);
5553
5554 /*
5555 * Calculate SCSI_CFG1 Microcode Default Value.
5556 *
5557 * The microcode will set the SCSI_CFG1 register using this value
5558 * after it is started below.
5559 *
5560 * Each ASC-38C1600 function has only two cable detect bits.
5561 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
5562 */
5563 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5564
5565 /*
5566 * If the cable is reversed all of the SCSI_CTRL register signals
5567 * will be set. Check for and return an error if this condition is
5568 * found.
5569 */
5570 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5571 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5572 return ADV_ERROR;
5573 }
5574
5575 /*
5576 * Each ASC-38C1600 function has two connectors. Only an HVD device
5577 * can not be connected to either connector. An LVD device or SE device
5578 * may be connected to either connecor. If an SE device is connected,
5579 * then at most Ultra speed (20 Mhz) can be used on both connectors.
5580 *
5581 * If an HVD device is attached, return an error.
5582 */
5583 if (scsi_cfg1 & HVD) {
5584 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
5585 return ADV_ERROR;
5586 }
5587
5588 /*
5589 * Each function in the ASC-38C1600 uses only the SE cable detect and
5590 * termination because there are two connectors for each function. Each
5591 * function may use either LVD or SE mode. Corresponding the SE automatic
5592 * termination control EEPROM bits are used for each function. Each
5593 * function has its own EEPROM. If SE automatic control is enabled for
5594 * the function, then set the termination value based on a table listed
5595 * in a_condor.h.
5596 *
5597 * If manual termination is specified in the EEPROM for the function,
5598 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
5599 * ready to be 'ored' into SCSI_CFG1.
5600 */
5601 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5602 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
5603 /* SE automatic termination control is enabled. */
5604 switch (scsi_cfg1 & C_DET_SE) {
5605 /* TERM_SE_HI: on, TERM_SE_LO: on */
5606 case 0x1:
5607 case 0x2:
5608 case 0x3:
5609 asc_dvc->cfg->termination |= TERM_SE;
5610 break;
5611
5612 case 0x0:
5613 if (PCI_FUNC(pdev->devfn) == 0) {
5614 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
5615 } else {
5616 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
5617 asc_dvc->cfg->termination |= TERM_SE_HI;
5618 }
5619 break;
5620 }
5621 }
5622
5623 /*
5624 * Clear any set TERM_SE bits.
5625 */
5626 scsi_cfg1 &= ~TERM_SE;
5627
5628 /*
5629 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
5630 */
5631 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
5632
5633 /*
5634 * Clear Big Endian and Terminator Polarity bits and set possibly
5635 * modified termination control bits in the Microcode SCSI_CFG1
5636 * Register Value.
5637 *
5638 * Big Endian bit is not used even on big endian machines.
5639 */
5640 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
5641
5642 /*
5643 * Set SCSI_CFG1 Microcode Default Value
5644 *
5645 * Set possibly modified termination control bits in the Microcode
5646 * SCSI_CFG1 Register Value.
5647 *
5648 * The microcode will set the SCSI_CFG1 register using this value
5649 * after it is started below.
5650 */
5651 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5652
5653 /*
5654 * Set MEM_CFG Microcode Default Value
5655 *
5656 * The microcode will set the MEM_CFG register using this value
5657 * after it is started below.
5658 *
5659 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5660 * are defined.
5661 *
5662 * ASC-38C1600 has 32KB internal memory.
5663 *
5664 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
5665 * out a special 16K Adv Library and Microcode version. After the issue
5666 * resolved, we should turn back to the 32K support. Both a_condor.h and
5667 * mcode.sas files also need to be updated.
5668 *
5669 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5670 * BIOS_EN | RAM_SZ_32KB);
5671 */
5672 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5673 BIOS_EN | RAM_SZ_16KB);
5674
5675 /*
5676 * Set SEL_MASK Microcode Default Value
5677 *
5678 * The microcode will set the SEL_MASK register using this value
5679 * after it is started below.
5680 */
5681 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5682 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5683
5684 AdvBuildCarrierFreelist(asc_dvc);
5685
5686 /*
5687 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5688 */
5689 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5690 if (!asc_dvc->icq_sp) {
5691 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5692 return ADV_ERROR;
5693 }
5694
5695 /*
5696 * Set RISC ICQ physical address start value. Initialize the
5697 * COMMA register to the same value otherwise the RISC will
5698 * prematurely detect a command is available.
5699 */
5700 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5701 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
5702 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
5703
5704 /*
5705 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5706 */
5707 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5708 if (!asc_dvc->irq_sp) {
5709 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5710 return ADV_ERROR;
5711 }
5712
5713 /*
5714 * Set RISC IRQ physical address start value.
5715 */
5716 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5717 asc_dvc->carr_pending_cnt = 0;
5718
5719 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5720 (ADV_INTR_ENABLE_HOST_INTR |
5721 ADV_INTR_ENABLE_GLOBAL_INTR));
5722 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5723 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5724
5725 /* finally, finally, gentlemen, start your engine */
5726 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5727
5728 /*
5729 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5730 * Resets should be performed. The RISC has to be running
5731 * to issue a SCSI Bus Reset.
5732 */
5733 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5734 /*
5735 * If the BIOS Signature is present in memory, restore the
5736 * per TID microcode operating variables.
5737 */
5738 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5739 0x55AA) {
5740 /*
5741 * Restore per TID negotiated values.
5742 */
5743 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5744 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5745 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5746 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5747 tagqng_able);
5748 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5749 AdvWriteByteLram(iop_base,
5750 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5751 max_cmd[tid]);
5752 }
5753 } else {
5754 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5755 warn_code = ASC_WARN_BUSRESET_ERROR;
5756 }
5757 }
5758 }
5759
5760 return warn_code;
5761 }
5762
5763 /*
5764 * Reset chip and SCSI Bus.
5765 *
5766 * Return Value:
5767 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
5768 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
5769 */
5770 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
5771 {
5772 int status;
5773 ushort wdtr_able, sdtr_able, tagqng_able;
5774 ushort ppr_able = 0;
5775 uchar tid, max_cmd[ADV_MAX_TID + 1];
5776 AdvPortAddr iop_base;
5777 ushort bios_sig;
5778
5779 iop_base = asc_dvc->iop_base;
5780
5781 /*
5782 * Save current per TID negotiated values.
5783 */
5784 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5785 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5786 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5787 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5788 }
5789 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5790 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5791 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5792 max_cmd[tid]);
5793 }
5794
5795 /*
5796 * Force the AdvInitAsc3550/38C0800Driver() function to
5797 * perform a SCSI Bus Reset by clearing the BIOS signature word.
5798 * The initialization functions assumes a SCSI Bus Reset is not
5799 * needed if the BIOS signature word is present.
5800 */
5801 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5802 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
5803
5804 /*
5805 * Stop chip and reset it.
5806 */
5807 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
5808 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
5809 mdelay(100);
5810 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
5811 ADV_CTRL_REG_CMD_WR_IO_REG);
5812
5813 /*
5814 * Reset Adv Library error code, if any, and try
5815 * re-initializing the chip.
5816 */
5817 asc_dvc->err_code = 0;
5818 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5819 status = AdvInitAsc38C1600Driver(asc_dvc);
5820 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
5821 status = AdvInitAsc38C0800Driver(asc_dvc);
5822 } else {
5823 status = AdvInitAsc3550Driver(asc_dvc);
5824 }
5825
5826 /* Translate initialization return value to status value. */
5827 if (status == 0) {
5828 status = ADV_TRUE;
5829 } else {
5830 status = ADV_FALSE;
5831 }
5832
5833 /*
5834 * Restore the BIOS signature word.
5835 */
5836 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5837
5838 /*
5839 * Restore per TID negotiated values.
5840 */
5841 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5842 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5843 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5844 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5845 }
5846 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5847 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5848 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5849 max_cmd[tid]);
5850 }
5851
5852 return status;
5853 }
5854
5855 /*
5856 * adv_async_callback() - Adv Library asynchronous event callback function.
5857 */
5858 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
5859 {
5860 switch (code) {
5861 case ADV_ASYNC_SCSI_BUS_RESET_DET:
5862 /*
5863 * The firmware detected a SCSI Bus reset.
5864 */
5865 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
5866 break;
5867
5868 case ADV_ASYNC_RDMA_FAILURE:
5869 /*
5870 * Handle RDMA failure by resetting the SCSI Bus and
5871 * possibly the chip if it is unresponsive. Log the error
5872 * with a unique code.
5873 */
5874 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
5875 AdvResetChipAndSB(adv_dvc_varp);
5876 break;
5877
5878 case ADV_HOST_SCSI_BUS_RESET:
5879 /*
5880 * Host generated SCSI bus reset occurred.
5881 */
5882 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
5883 break;
5884
5885 default:
5886 ASC_DBG(0, "unknown code 0x%x\n", code);
5887 break;
5888 }
5889 }
5890
5891 /*
5892 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
5893 *
5894 * Callback function for the Wide SCSI Adv Library.
5895 */
5896 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
5897 {
5898 struct asc_board *boardp = adv_dvc_varp->drv_ptr;
5899 adv_req_t *reqp;
5900 adv_sgblk_t *sgblkp;
5901 struct scsi_cmnd *scp;
5902 u32 resid_cnt;
5903 dma_addr_t sense_addr;
5904
5905 ASC_DBG(1, "adv_dvc_varp 0x%p, scsiqp 0x%p\n",
5906 adv_dvc_varp, scsiqp);
5907 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
5908
5909 /*
5910 * Get the adv_req_t structure for the command that has been
5911 * completed. The adv_req_t structure actually contains the
5912 * completed ADV_SCSI_REQ_Q structure.
5913 */
5914 scp = scsi_host_find_tag(boardp->shost, scsiqp->srb_tag);
5915
5916 ASC_DBG(1, "scp 0x%p\n", scp);
5917 if (scp == NULL) {
5918 ASC_PRINT
5919 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
5920 return;
5921 }
5922 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
5923
5924 reqp = (adv_req_t *)scp->host_scribble;
5925 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
5926 if (reqp == NULL) {
5927 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
5928 return;
5929 }
5930 /*
5931 * Remove backreferences to avoid duplicate
5932 * command completions.
5933 */
5934 scp->host_scribble = NULL;
5935 reqp->cmndp = NULL;
5936
5937 ASC_STATS(boardp->shost, callback);
5938 ASC_DBG(1, "shost 0x%p\n", boardp->shost);
5939
5940 sense_addr = le32_to_cpu(scsiqp->sense_addr);
5941 dma_unmap_single(boardp->dev, sense_addr,
5942 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
5943
5944 /*
5945 * 'done_status' contains the command's ending status.
5946 */
5947 scp->result = 0;
5948 switch (scsiqp->done_status) {
5949 case QD_NO_ERROR:
5950 ASC_DBG(2, "QD_NO_ERROR\n");
5951
5952 /*
5953 * Check for an underrun condition.
5954 *
5955 * If there was no error and an underrun condition, then
5956 * then return the number of underrun bytes.
5957 */
5958 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
5959 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
5960 resid_cnt <= scsi_bufflen(scp)) {
5961 ASC_DBG(1, "underrun condition %lu bytes\n",
5962 (ulong)resid_cnt);
5963 scsi_set_resid(scp, resid_cnt);
5964 }
5965 break;
5966
5967 case QD_WITH_ERROR:
5968 ASC_DBG(2, "QD_WITH_ERROR\n");
5969 switch (scsiqp->host_status) {
5970 case QHSTA_NO_ERROR:
5971 set_status_byte(scp, scsiqp->scsi_status);
5972 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
5973 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
5974 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
5975 SCSI_SENSE_BUFFERSIZE);
5976 }
5977 break;
5978
5979 default:
5980 /* Some other QHSTA error occurred. */
5981 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
5982 set_host_byte(scp, DID_BAD_TARGET);
5983 break;
5984 }
5985 break;
5986
5987 case QD_ABORTED_BY_HOST:
5988 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
5989 set_status_byte(scp, scsiqp->scsi_status);
5990 set_host_byte(scp, DID_ABORT);
5991 break;
5992
5993 default:
5994 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
5995 set_status_byte(scp, scsiqp->scsi_status);
5996 set_host_byte(scp, DID_ERROR);
5997 break;
5998 }
5999
6000 /*
6001 * If the 'init_tidmask' bit isn't already set for the target and the
6002 * current request finished normally, then set the bit for the target
6003 * to indicate that a device is present.
6004 */
6005 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6006 scsiqp->done_status == QD_NO_ERROR &&
6007 scsiqp->host_status == QHSTA_NO_ERROR) {
6008 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6009 }
6010
6011 asc_scsi_done(scp);
6012
6013 /*
6014 * Free all 'adv_sgblk_t' structures allocated for the request.
6015 */
6016 while ((sgblkp = reqp->sgblkp) != NULL) {
6017 /* Remove 'sgblkp' from the request list. */
6018 reqp->sgblkp = sgblkp->next_sgblkp;
6019
6020 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
6021 sgblkp->sg_addr);
6022 }
6023
6024 ASC_DBG(1, "done\n");
6025 }
6026
6027 /*
6028 * Adv Library Interrupt Service Routine
6029 *
6030 * This function is called by a driver's interrupt service routine.
6031 * The function disables and re-enables interrupts.
6032 *
6033 * When a microcode idle command is completed, the ADV_DVC_VAR
6034 * 'idle_cmd_done' field is set to ADV_TRUE.
6035 *
6036 * Note: AdvISR() can be called when interrupts are disabled or even
6037 * when there is no hardware interrupt condition present. It will
6038 * always check for completed idle commands and microcode requests.
6039 * This is an important feature that shouldn't be changed because it
6040 * allows commands to be completed from polling mode loops.
6041 *
6042 * Return:
6043 * ADV_TRUE(1) - interrupt was pending
6044 * ADV_FALSE(0) - no interrupt was pending
6045 */
6046 static int AdvISR(ADV_DVC_VAR *asc_dvc)
6047 {
6048 AdvPortAddr iop_base;
6049 uchar int_stat;
6050 ADV_CARR_T *free_carrp;
6051 __le32 irq_next_vpa;
6052 ADV_SCSI_REQ_Q *scsiq;
6053 adv_req_t *reqp;
6054
6055 iop_base = asc_dvc->iop_base;
6056
6057 /* Reading the register clears the interrupt. */
6058 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6059
6060 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6061 ADV_INTR_STATUS_INTRC)) == 0) {
6062 return ADV_FALSE;
6063 }
6064
6065 /*
6066 * Notify the driver of an asynchronous microcode condition by
6067 * calling the adv_async_callback function. The function
6068 * is passed the microcode ASC_MC_INTRB_CODE byte value.
6069 */
6070 if (int_stat & ADV_INTR_STATUS_INTRB) {
6071 uchar intrb_code;
6072
6073 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6074
6075 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6076 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6077 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6078 asc_dvc->carr_pending_cnt != 0) {
6079 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6080 ADV_TICKLE_A);
6081 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6082 AdvWriteByteRegister(iop_base,
6083 IOPB_TICKLE,
6084 ADV_TICKLE_NOP);
6085 }
6086 }
6087 }
6088
6089 adv_async_callback(asc_dvc, intrb_code);
6090 }
6091
6092 /*
6093 * Check if the IRQ stopper carrier contains a completed request.
6094 */
6095 while (((irq_next_vpa =
6096 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ADV_RQ_DONE) != 0) {
6097 /*
6098 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6099 * The RISC will have set 'areq_vpa' to a virtual address.
6100 *
6101 * The firmware will have copied the ADV_SCSI_REQ_Q.scsiq_ptr
6102 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
6103 * below complements the conversion of ADV_SCSI_REQ_Q.scsiq_ptr'
6104 * in AdvExeScsiQueue().
6105 */
6106 u32 pa_offset = le32_to_cpu(asc_dvc->irq_sp->areq_vpa);
6107 ASC_DBG(1, "irq_sp %p areq_vpa %u\n",
6108 asc_dvc->irq_sp, pa_offset);
6109 reqp = adv_get_reqp(asc_dvc, pa_offset);
6110 scsiq = &reqp->scsi_req_q;
6111
6112 /*
6113 * Request finished with good status and the queue was not
6114 * DMAed to host memory by the firmware. Set all status fields
6115 * to indicate good status.
6116 */
6117 if ((irq_next_vpa & ADV_RQ_GOOD) != 0) {
6118 scsiq->done_status = QD_NO_ERROR;
6119 scsiq->host_status = scsiq->scsi_status = 0;
6120 scsiq->data_cnt = 0L;
6121 }
6122
6123 /*
6124 * Advance the stopper pointer to the next carrier
6125 * ignoring the lower four bits. Free the previous
6126 * stopper carrier.
6127 */
6128 free_carrp = asc_dvc->irq_sp;
6129 asc_dvc->irq_sp = adv_get_carrier(asc_dvc,
6130 ADV_GET_CARRP(irq_next_vpa));
6131
6132 free_carrp->next_vpa = asc_dvc->carr_freelist->carr_va;
6133 asc_dvc->carr_freelist = free_carrp;
6134 asc_dvc->carr_pending_cnt--;
6135
6136 /*
6137 * Clear request microcode control flag.
6138 */
6139 scsiq->cntl = 0;
6140
6141 /*
6142 * Notify the driver of the completed request by passing
6143 * the ADV_SCSI_REQ_Q pointer to its callback function.
6144 */
6145 adv_isr_callback(asc_dvc, scsiq);
6146 /*
6147 * Note: After the driver callback function is called, 'scsiq'
6148 * can no longer be referenced.
6149 *
6150 * Fall through and continue processing other completed
6151 * requests...
6152 */
6153 }
6154 return ADV_TRUE;
6155 }
6156
6157 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6158 {
6159 if (asc_dvc->err_code == 0) {
6160 asc_dvc->err_code = err_code;
6161 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6162 err_code);
6163 }
6164 return err_code;
6165 }
6166
6167 static void AscAckInterrupt(PortAddr iop_base)
6168 {
6169 uchar host_flag;
6170 uchar risc_flag;
6171 ushort loop;
6172
6173 loop = 0;
6174 do {
6175 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6176 if (loop++ > 0x7FFF) {
6177 break;
6178 }
6179 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6180 host_flag =
6181 AscReadLramByte(iop_base,
6182 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6183 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6184 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6185 AscSetChipStatus(iop_base, CIW_INT_ACK);
6186 loop = 0;
6187 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6188 AscSetChipStatus(iop_base, CIW_INT_ACK);
6189 if (loop++ > 3) {
6190 break;
6191 }
6192 }
6193 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
6194 }
6195
6196 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6197 {
6198 const uchar *period_table;
6199 int max_index;
6200 int min_index;
6201 int i;
6202
6203 period_table = asc_dvc->sdtr_period_tbl;
6204 max_index = (int)asc_dvc->max_sdtr_index;
6205 min_index = (int)asc_dvc->min_sdtr_index;
6206 if ((syn_time <= period_table[max_index])) {
6207 for (i = min_index; i < (max_index - 1); i++) {
6208 if (syn_time <= period_table[i]) {
6209 return (uchar)i;
6210 }
6211 }
6212 return (uchar)max_index;
6213 } else {
6214 return (uchar)(max_index + 1);
6215 }
6216 }
6217
6218 static uchar
6219 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6220 {
6221 PortAddr iop_base = asc_dvc->iop_base;
6222 uchar sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6223 EXT_MSG sdtr_buf = {
6224 .msg_type = EXTENDED_MESSAGE,
6225 .msg_len = MS_SDTR_LEN,
6226 .msg_req = EXTENDED_SDTR,
6227 .xfer_period = sdtr_period,
6228 .req_ack_offset = sdtr_offset,
6229 };
6230 sdtr_offset &= ASC_SYN_MAX_OFFSET;
6231
6232 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
6233 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6234 (uchar *)&sdtr_buf,
6235 sizeof(EXT_MSG) >> 1);
6236 return ((sdtr_period_index << 4) | sdtr_offset);
6237 } else {
6238 sdtr_buf.req_ack_offset = 0;
6239 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6240 (uchar *)&sdtr_buf,
6241 sizeof(EXT_MSG) >> 1);
6242 return 0;
6243 }
6244 }
6245
6246 static uchar
6247 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
6248 {
6249 uchar byte;
6250 uchar sdtr_period_ix;
6251
6252 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6253 if (sdtr_period_ix > asc_dvc->max_sdtr_index)
6254 return 0xFF;
6255 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6256 return byte;
6257 }
6258
6259 static bool AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
6260 {
6261 ASC_SCSI_BIT_ID_TYPE org_id;
6262 int i;
6263 bool sta = true;
6264
6265 AscSetBank(iop_base, 1);
6266 org_id = AscReadChipDvcID(iop_base);
6267 for (i = 0; i <= ASC_MAX_TID; i++) {
6268 if (org_id == (0x01 << i))
6269 break;
6270 }
6271 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
6272 AscWriteChipDvcID(iop_base, id);
6273 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
6274 AscSetBank(iop_base, 0);
6275 AscSetChipSyn(iop_base, sdtr_data);
6276 if (AscGetChipSyn(iop_base) != sdtr_data) {
6277 sta = false;
6278 }
6279 } else {
6280 sta = false;
6281 }
6282 AscSetBank(iop_base, 1);
6283 AscWriteChipDvcID(iop_base, org_id);
6284 AscSetBank(iop_base, 0);
6285 return (sta);
6286 }
6287
6288 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
6289 {
6290 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
6291 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
6292 }
6293
6294 static void AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
6295 {
6296 EXT_MSG ext_msg;
6297 EXT_MSG out_msg;
6298 ushort halt_q_addr;
6299 bool sdtr_accept;
6300 ushort int_halt_code;
6301 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6302 ASC_SCSI_BIT_ID_TYPE target_id;
6303 PortAddr iop_base;
6304 uchar tag_code;
6305 uchar q_status;
6306 uchar halt_qp;
6307 uchar sdtr_data;
6308 uchar target_ix;
6309 uchar q_cntl, tid_no;
6310 uchar cur_dvc_qng;
6311 uchar asyn_sdtr;
6312 uchar scsi_status;
6313 struct asc_board *boardp;
6314
6315 BUG_ON(!asc_dvc->drv_ptr);
6316 boardp = asc_dvc->drv_ptr;
6317
6318 iop_base = asc_dvc->iop_base;
6319 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6320
6321 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6322 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6323 target_ix = AscReadLramByte(iop_base,
6324 (ushort)(halt_q_addr +
6325 (ushort)ASC_SCSIQ_B_TARGET_IX));
6326 q_cntl = AscReadLramByte(iop_base,
6327 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6328 tid_no = ASC_TIX_TO_TID(target_ix);
6329 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6330 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6331 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6332 } else {
6333 asyn_sdtr = 0;
6334 }
6335 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6336 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6337 AscSetChipSDTR(iop_base, 0, tid_no);
6338 boardp->sdtr_data[tid_no] = 0;
6339 }
6340 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6341 return;
6342 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6343 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6344 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6345 boardp->sdtr_data[tid_no] = asyn_sdtr;
6346 }
6347 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6348 return;
6349 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6350 AscMemWordCopyPtrFromLram(iop_base,
6351 ASCV_MSGIN_BEG,
6352 (uchar *)&ext_msg,
6353 sizeof(EXT_MSG) >> 1);
6354
6355 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6356 ext_msg.msg_req == EXTENDED_SDTR &&
6357 ext_msg.msg_len == MS_SDTR_LEN) {
6358 sdtr_accept = true;
6359 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6360
6361 sdtr_accept = false;
6362 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6363 }
6364 if ((ext_msg.xfer_period <
6365 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
6366 || (ext_msg.xfer_period >
6367 asc_dvc->sdtr_period_tbl[asc_dvc->
6368 max_sdtr_index])) {
6369 sdtr_accept = false;
6370 ext_msg.xfer_period =
6371 asc_dvc->sdtr_period_tbl[asc_dvc->
6372 min_sdtr_index];
6373 }
6374 if (sdtr_accept) {
6375 sdtr_data =
6376 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6377 ext_msg.req_ack_offset);
6378 if (sdtr_data == 0xFF) {
6379
6380 q_cntl |= QC_MSG_OUT;
6381 asc_dvc->init_sdtr &= ~target_id;
6382 asc_dvc->sdtr_done &= ~target_id;
6383 AscSetChipSDTR(iop_base, asyn_sdtr,
6384 tid_no);
6385 boardp->sdtr_data[tid_no] = asyn_sdtr;
6386 }
6387 }
6388 if (ext_msg.req_ack_offset == 0) {
6389
6390 q_cntl &= ~QC_MSG_OUT;
6391 asc_dvc->init_sdtr &= ~target_id;
6392 asc_dvc->sdtr_done &= ~target_id;
6393 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6394 } else {
6395 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
6396 q_cntl &= ~QC_MSG_OUT;
6397 asc_dvc->sdtr_done |= target_id;
6398 asc_dvc->init_sdtr |= target_id;
6399 asc_dvc->pci_fix_asyn_xfer &=
6400 ~target_id;
6401 sdtr_data =
6402 AscCalSDTRData(asc_dvc,
6403 ext_msg.xfer_period,
6404 ext_msg.
6405 req_ack_offset);
6406 AscSetChipSDTR(iop_base, sdtr_data,
6407 tid_no);
6408 boardp->sdtr_data[tid_no] = sdtr_data;
6409 } else {
6410 q_cntl |= QC_MSG_OUT;
6411 AscMsgOutSDTR(asc_dvc,
6412 ext_msg.xfer_period,
6413 ext_msg.req_ack_offset);
6414 asc_dvc->pci_fix_asyn_xfer &=
6415 ~target_id;
6416 sdtr_data =
6417 AscCalSDTRData(asc_dvc,
6418 ext_msg.xfer_period,
6419 ext_msg.
6420 req_ack_offset);
6421 AscSetChipSDTR(iop_base, sdtr_data,
6422 tid_no);
6423 boardp->sdtr_data[tid_no] = sdtr_data;
6424 asc_dvc->sdtr_done |= target_id;
6425 asc_dvc->init_sdtr |= target_id;
6426 }
6427 }
6428
6429 AscWriteLramByte(iop_base,
6430 (ushort)(halt_q_addr +
6431 (ushort)ASC_SCSIQ_B_CNTL),
6432 q_cntl);
6433 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6434 return;
6435 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6436 ext_msg.msg_req == EXTENDED_WDTR &&
6437 ext_msg.msg_len == MS_WDTR_LEN) {
6438
6439 ext_msg.wdtr_width = 0;
6440 AscMemWordCopyPtrToLram(iop_base,
6441 ASCV_MSGOUT_BEG,
6442 (uchar *)&ext_msg,
6443 sizeof(EXT_MSG) >> 1);
6444 q_cntl |= QC_MSG_OUT;
6445 AscWriteLramByte(iop_base,
6446 (ushort)(halt_q_addr +
6447 (ushort)ASC_SCSIQ_B_CNTL),
6448 q_cntl);
6449 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6450 return;
6451 } else {
6452
6453 ext_msg.msg_type = MESSAGE_REJECT;
6454 AscMemWordCopyPtrToLram(iop_base,
6455 ASCV_MSGOUT_BEG,
6456 (uchar *)&ext_msg,
6457 sizeof(EXT_MSG) >> 1);
6458 q_cntl |= QC_MSG_OUT;
6459 AscWriteLramByte(iop_base,
6460 (ushort)(halt_q_addr +
6461 (ushort)ASC_SCSIQ_B_CNTL),
6462 q_cntl);
6463 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6464 return;
6465 }
6466 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6467
6468 q_cntl |= QC_REQ_SENSE;
6469
6470 if ((asc_dvc->init_sdtr & target_id) != 0) {
6471
6472 asc_dvc->sdtr_done &= ~target_id;
6473
6474 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6475 q_cntl |= QC_MSG_OUT;
6476 AscMsgOutSDTR(asc_dvc,
6477 asc_dvc->
6478 sdtr_period_tbl[(sdtr_data >> 4) &
6479 (uchar)(asc_dvc->
6480 max_sdtr_index -
6481 1)],
6482 (uchar)(sdtr_data & (uchar)
6483 ASC_SYN_MAX_OFFSET));
6484 }
6485
6486 AscWriteLramByte(iop_base,
6487 (ushort)(halt_q_addr +
6488 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6489
6490 tag_code = AscReadLramByte(iop_base,
6491 (ushort)(halt_q_addr + (ushort)
6492 ASC_SCSIQ_B_TAG_CODE));
6493 tag_code &= 0xDC;
6494 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6495 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6496 ) {
6497
6498 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6499 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6500
6501 }
6502 AscWriteLramByte(iop_base,
6503 (ushort)(halt_q_addr +
6504 (ushort)ASC_SCSIQ_B_TAG_CODE),
6505 tag_code);
6506
6507 q_status = AscReadLramByte(iop_base,
6508 (ushort)(halt_q_addr + (ushort)
6509 ASC_SCSIQ_B_STATUS));
6510 q_status |= (QS_READY | QS_BUSY);
6511 AscWriteLramByte(iop_base,
6512 (ushort)(halt_q_addr +
6513 (ushort)ASC_SCSIQ_B_STATUS),
6514 q_status);
6515
6516 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6517 scsi_busy &= ~target_id;
6518 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6519
6520 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6521 return;
6522 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6523
6524 AscMemWordCopyPtrFromLram(iop_base,
6525 ASCV_MSGOUT_BEG,
6526 (uchar *)&out_msg,
6527 sizeof(EXT_MSG) >> 1);
6528
6529 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6530 (out_msg.msg_len == MS_SDTR_LEN) &&
6531 (out_msg.msg_req == EXTENDED_SDTR)) {
6532
6533 asc_dvc->init_sdtr &= ~target_id;
6534 asc_dvc->sdtr_done &= ~target_id;
6535 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6536 boardp->sdtr_data[tid_no] = asyn_sdtr;
6537 }
6538 q_cntl &= ~QC_MSG_OUT;
6539 AscWriteLramByte(iop_base,
6540 (ushort)(halt_q_addr +
6541 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6542 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6543 return;
6544 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6545
6546 scsi_status = AscReadLramByte(iop_base,
6547 (ushort)((ushort)halt_q_addr +
6548 (ushort)
6549 ASC_SCSIQ_SCSI_STATUS));
6550 cur_dvc_qng =
6551 AscReadLramByte(iop_base,
6552 (ushort)((ushort)ASC_QADR_BEG +
6553 (ushort)target_ix));
6554 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6555
6556 scsi_busy = AscReadLramByte(iop_base,
6557 (ushort)ASCV_SCSIBUSY_B);
6558 scsi_busy |= target_id;
6559 AscWriteLramByte(iop_base,
6560 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6561 asc_dvc->queue_full_or_busy |= target_id;
6562
6563 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6564 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6565 cur_dvc_qng -= 1;
6566 asc_dvc->max_dvc_qng[tid_no] =
6567 cur_dvc_qng;
6568
6569 AscWriteLramByte(iop_base,
6570 (ushort)((ushort)
6571 ASCV_MAX_DVC_QNG_BEG
6572 + (ushort)
6573 tid_no),
6574 cur_dvc_qng);
6575
6576 /*
6577 * Set the device queue depth to the
6578 * number of active requests when the
6579 * QUEUE FULL condition was encountered.
6580 */
6581 boardp->queue_full |= target_id;
6582 boardp->queue_full_cnt[tid_no] =
6583 cur_dvc_qng;
6584 }
6585 }
6586 }
6587 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6588 return;
6589 }
6590 return;
6591 }
6592
6593 /*
6594 * void
6595 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6596 *
6597 * Calling/Exit State:
6598 * none
6599 *
6600 * Description:
6601 * Input an ASC_QDONE_INFO structure from the chip
6602 */
6603 static void
6604 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6605 {
6606 int i;
6607 ushort word;
6608
6609 AscSetChipLramAddr(iop_base, s_addr);
6610 for (i = 0; i < 2 * words; i += 2) {
6611 if (i == 10) {
6612 continue;
6613 }
6614 word = inpw(iop_base + IOP_RAM_DATA);
6615 inbuf[i] = word & 0xff;
6616 inbuf[i + 1] = (word >> 8) & 0xff;
6617 }
6618 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
6619 }
6620
6621 static uchar
6622 _AscCopyLramScsiDoneQ(PortAddr iop_base,
6623 ushort q_addr,
6624 ASC_QDONE_INFO *scsiq, unsigned int max_dma_count)
6625 {
6626 ushort _val;
6627 uchar sg_queue_cnt;
6628
6629 DvcGetQinfo(iop_base,
6630 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
6631 (uchar *)scsiq,
6632 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
6633
6634 _val = AscReadLramWord(iop_base,
6635 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
6636 scsiq->q_status = (uchar)_val;
6637 scsiq->q_no = (uchar)(_val >> 8);
6638 _val = AscReadLramWord(iop_base,
6639 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6640 scsiq->cntl = (uchar)_val;
6641 sg_queue_cnt = (uchar)(_val >> 8);
6642 _val = AscReadLramWord(iop_base,
6643 (ushort)(q_addr +
6644 (ushort)ASC_SCSIQ_B_SENSE_LEN));
6645 scsiq->sense_len = (uchar)_val;
6646 scsiq->extra_bytes = (uchar)(_val >> 8);
6647
6648 /*
6649 * Read high word of remain bytes from alternate location.
6650 */
6651 scsiq->remain_bytes = (((u32)AscReadLramWord(iop_base,
6652 (ushort)(q_addr +
6653 (ushort)
6654 ASC_SCSIQ_W_ALT_DC1)))
6655 << 16);
6656 /*
6657 * Read low word of remain bytes from original location.
6658 */
6659 scsiq->remain_bytes += AscReadLramWord(iop_base,
6660 (ushort)(q_addr + (ushort)
6661 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
6662
6663 scsiq->remain_bytes &= max_dma_count;
6664 return sg_queue_cnt;
6665 }
6666
6667 /*
6668 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
6669 *
6670 * Interrupt callback function for the Narrow SCSI Asc Library.
6671 */
6672 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
6673 {
6674 struct asc_board *boardp = asc_dvc_varp->drv_ptr;
6675 u32 srb_tag;
6676 struct scsi_cmnd *scp;
6677
6678 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
6679 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
6680
6681 /*
6682 * Decrease the srb_tag by 1 to find the SCSI command
6683 */
6684 srb_tag = qdonep->d2.srb_tag - 1;
6685 scp = scsi_host_find_tag(boardp->shost, srb_tag);
6686 if (!scp)
6687 return;
6688
6689 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6690
6691 ASC_STATS(boardp->shost, callback);
6692
6693 dma_unmap_single(boardp->dev, advansys_cmd(scp)->dma_handle,
6694 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
6695 /*
6696 * 'qdonep' contains the command's ending status.
6697 */
6698 scp->result = 0;
6699 switch (qdonep->d3.done_stat) {
6700 case QD_NO_ERROR:
6701 ASC_DBG(2, "QD_NO_ERROR\n");
6702
6703 /*
6704 * Check for an underrun condition.
6705 *
6706 * If there was no error and an underrun condition, then
6707 * return the number of underrun bytes.
6708 */
6709 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
6710 qdonep->remain_bytes <= scsi_bufflen(scp)) {
6711 ASC_DBG(1, "underrun condition %u bytes\n",
6712 (unsigned)qdonep->remain_bytes);
6713 scsi_set_resid(scp, qdonep->remain_bytes);
6714 }
6715 break;
6716
6717 case QD_WITH_ERROR:
6718 ASC_DBG(2, "QD_WITH_ERROR\n");
6719 switch (qdonep->d3.host_stat) {
6720 case QHSTA_NO_ERROR:
6721 set_status_byte(scp, qdonep->d3.scsi_stat);
6722 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
6723 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
6724 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6725 SCSI_SENSE_BUFFERSIZE);
6726 }
6727 break;
6728
6729 default:
6730 /* QHSTA error occurred */
6731 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
6732 set_host_byte(scp, DID_BAD_TARGET);
6733 break;
6734 }
6735 break;
6736
6737 case QD_ABORTED_BY_HOST:
6738 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
6739 set_status_byte(scp, qdonep->d3.scsi_stat);
6740 set_host_byte(scp, DID_ABORT);
6741 break;
6742
6743 default:
6744 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
6745 set_status_byte(scp, qdonep->d3.scsi_stat);
6746 set_host_byte(scp, DID_ERROR);
6747 break;
6748 }
6749
6750 /*
6751 * If the 'init_tidmask' bit isn't already set for the target and the
6752 * current request finished normally, then set the bit for the target
6753 * to indicate that a device is present.
6754 */
6755 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6756 qdonep->d3.done_stat == QD_NO_ERROR &&
6757 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
6758 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6759 }
6760
6761 asc_scsi_done(scp);
6762 }
6763
6764 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
6765 {
6766 uchar next_qp;
6767 uchar n_q_used;
6768 uchar sg_list_qp;
6769 uchar sg_queue_cnt;
6770 uchar q_cnt;
6771 uchar done_q_tail;
6772 uchar tid_no;
6773 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6774 ASC_SCSI_BIT_ID_TYPE target_id;
6775 PortAddr iop_base;
6776 ushort q_addr;
6777 ushort sg_q_addr;
6778 uchar cur_target_qng;
6779 ASC_QDONE_INFO scsiq_buf;
6780 ASC_QDONE_INFO *scsiq;
6781 bool false_overrun;
6782
6783 iop_base = asc_dvc->iop_base;
6784 n_q_used = 1;
6785 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
6786 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
6787 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
6788 next_qp = AscReadLramByte(iop_base,
6789 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
6790 if (next_qp != ASC_QLINK_END) {
6791 AscPutVarDoneQTail(iop_base, next_qp);
6792 q_addr = ASC_QNO_TO_QADDR(next_qp);
6793 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
6794 asc_dvc->max_dma_count);
6795 AscWriteLramByte(iop_base,
6796 (ushort)(q_addr +
6797 (ushort)ASC_SCSIQ_B_STATUS),
6798 (uchar)(scsiq->
6799 q_status & (uchar)~(QS_READY |
6800 QS_ABORTED)));
6801 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
6802 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
6803 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
6804 sg_q_addr = q_addr;
6805 sg_list_qp = next_qp;
6806 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
6807 sg_list_qp = AscReadLramByte(iop_base,
6808 (ushort)(sg_q_addr
6809 + (ushort)
6810 ASC_SCSIQ_B_FWD));
6811 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
6812 if (sg_list_qp == ASC_QLINK_END) {
6813 AscSetLibErrorCode(asc_dvc,
6814 ASCQ_ERR_SG_Q_LINKS);
6815 scsiq->d3.done_stat = QD_WITH_ERROR;
6816 scsiq->d3.host_stat =
6817 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
6818 goto FATAL_ERR_QDONE;
6819 }
6820 AscWriteLramByte(iop_base,
6821 (ushort)(sg_q_addr + (ushort)
6822 ASC_SCSIQ_B_STATUS),
6823 QS_FREE);
6824 }
6825 n_q_used = sg_queue_cnt + 1;
6826 AscPutVarDoneQTail(iop_base, sg_list_qp);
6827 }
6828 if (asc_dvc->queue_full_or_busy & target_id) {
6829 cur_target_qng = AscReadLramByte(iop_base,
6830 (ushort)((ushort)
6831 ASC_QADR_BEG
6832 + (ushort)
6833 scsiq->d2.
6834 target_ix));
6835 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
6836 scsi_busy = AscReadLramByte(iop_base, (ushort)
6837 ASCV_SCSIBUSY_B);
6838 scsi_busy &= ~target_id;
6839 AscWriteLramByte(iop_base,
6840 (ushort)ASCV_SCSIBUSY_B,
6841 scsi_busy);
6842 asc_dvc->queue_full_or_busy &= ~target_id;
6843 }
6844 }
6845 if (asc_dvc->cur_total_qng >= n_q_used) {
6846 asc_dvc->cur_total_qng -= n_q_used;
6847 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
6848 asc_dvc->cur_dvc_qng[tid_no]--;
6849 }
6850 } else {
6851 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
6852 scsiq->d3.done_stat = QD_WITH_ERROR;
6853 goto FATAL_ERR_QDONE;
6854 }
6855 if ((scsiq->d2.srb_tag == 0UL) ||
6856 ((scsiq->q_status & QS_ABORTED) != 0)) {
6857 return (0x11);
6858 } else if (scsiq->q_status == QS_DONE) {
6859 /*
6860 * This is also curious.
6861 * false_overrun will _always_ be set to 'false'
6862 */
6863 false_overrun = false;
6864 if (scsiq->extra_bytes != 0) {
6865 scsiq->remain_bytes += scsiq->extra_bytes;
6866 }
6867 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
6868 if (scsiq->d3.host_stat ==
6869 QHSTA_M_DATA_OVER_RUN) {
6870 if ((scsiq->
6871 cntl & (QC_DATA_IN | QC_DATA_OUT))
6872 == 0) {
6873 scsiq->d3.done_stat =
6874 QD_NO_ERROR;
6875 scsiq->d3.host_stat =
6876 QHSTA_NO_ERROR;
6877 } else if (false_overrun) {
6878 scsiq->d3.done_stat =
6879 QD_NO_ERROR;
6880 scsiq->d3.host_stat =
6881 QHSTA_NO_ERROR;
6882 }
6883 } else if (scsiq->d3.host_stat ==
6884 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
6885 AscStopChip(iop_base);
6886 AscSetChipControl(iop_base,
6887 (uchar)(CC_SCSI_RESET
6888 | CC_HALT));
6889 udelay(60);
6890 AscSetChipControl(iop_base, CC_HALT);
6891 AscSetChipStatus(iop_base,
6892 CIW_CLR_SCSI_RESET_INT);
6893 AscSetChipStatus(iop_base, 0);
6894 AscSetChipControl(iop_base, 0);
6895 }
6896 }
6897 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
6898 asc_isr_callback(asc_dvc, scsiq);
6899 } else {
6900 if ((AscReadLramByte(iop_base,
6901 (ushort)(q_addr + (ushort)
6902 ASC_SCSIQ_CDB_BEG))
6903 == START_STOP)) {
6904 asc_dvc->unit_not_ready &= ~target_id;
6905 if (scsiq->d3.done_stat != QD_NO_ERROR) {
6906 asc_dvc->start_motor &=
6907 ~target_id;
6908 }
6909 }
6910 }
6911 return (1);
6912 } else {
6913 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
6914 FATAL_ERR_QDONE:
6915 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
6916 asc_isr_callback(asc_dvc, scsiq);
6917 }
6918 return (0x80);
6919 }
6920 }
6921 return (0);
6922 }
6923
6924 static int AscISR(ASC_DVC_VAR *asc_dvc)
6925 {
6926 ASC_CS_TYPE chipstat;
6927 PortAddr iop_base;
6928 ushort saved_ram_addr;
6929 uchar ctrl_reg;
6930 uchar saved_ctrl_reg;
6931 int int_pending;
6932 int status;
6933 uchar host_flag;
6934
6935 iop_base = asc_dvc->iop_base;
6936 int_pending = ASC_FALSE;
6937
6938 if (AscIsIntPending(iop_base) == 0)
6939 return int_pending;
6940
6941 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
6942 return ASC_ERROR;
6943 }
6944 if (asc_dvc->in_critical_cnt != 0) {
6945 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
6946 return ASC_ERROR;
6947 }
6948 if (asc_dvc->is_in_int) {
6949 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
6950 return ASC_ERROR;
6951 }
6952 asc_dvc->is_in_int = true;
6953 ctrl_reg = AscGetChipControl(iop_base);
6954 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
6955 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
6956 chipstat = AscGetChipStatus(iop_base);
6957 if (chipstat & CSW_SCSI_RESET_LATCH) {
6958 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
6959 int i = 10;
6960 int_pending = ASC_TRUE;
6961 asc_dvc->sdtr_done = 0;
6962 saved_ctrl_reg &= (uchar)(~CC_HALT);
6963 while ((AscGetChipStatus(iop_base) &
6964 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
6965 mdelay(100);
6966 }
6967 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
6968 AscSetChipControl(iop_base, CC_HALT);
6969 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
6970 AscSetChipStatus(iop_base, 0);
6971 chipstat = AscGetChipStatus(iop_base);
6972 }
6973 }
6974 saved_ram_addr = AscGetChipLramAddr(iop_base);
6975 host_flag = AscReadLramByte(iop_base,
6976 ASCV_HOST_FLAG_B) &
6977 (uchar)(~ASC_HOST_FLAG_IN_ISR);
6978 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6979 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
6980 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
6981 AscAckInterrupt(iop_base);
6982 int_pending = ASC_TRUE;
6983 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
6984 AscIsrChipHalted(asc_dvc);
6985 saved_ctrl_reg &= (uchar)(~CC_HALT);
6986 } else {
6987 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
6988 while (((status =
6989 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
6990 }
6991 } else {
6992 do {
6993 if ((status =
6994 AscIsrQDone(asc_dvc)) == 1) {
6995 break;
6996 }
6997 } while (status == 0x11);
6998 }
6999 if ((status & 0x80) != 0)
7000 int_pending = ASC_ERROR;
7001 }
7002 }
7003 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7004 AscSetChipLramAddr(iop_base, saved_ram_addr);
7005 AscSetChipControl(iop_base, saved_ctrl_reg);
7006 asc_dvc->is_in_int = false;
7007 return int_pending;
7008 }
7009
7010 /*
7011 * advansys_reset()
7012 *
7013 * Reset the host associated with the command 'scp'.
7014 *
7015 * This function runs its own thread. Interrupts must be blocked but
7016 * sleeping is allowed and no locking other than for host structures is
7017 * required. Returns SUCCESS or FAILED.
7018 */
7019 static int advansys_reset(struct scsi_cmnd *scp)
7020 {
7021 struct Scsi_Host *shost = scp->device->host;
7022 struct asc_board *boardp = shost_priv(shost);
7023 unsigned long flags;
7024 int status;
7025 int ret = SUCCESS;
7026
7027 ASC_DBG(1, "0x%p\n", scp);
7028
7029 ASC_STATS(shost, reset);
7030
7031 scmd_printk(KERN_INFO, scp, "SCSI host reset started...\n");
7032
7033 if (ASC_NARROW_BOARD(boardp)) {
7034 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7035
7036 /* Reset the chip and SCSI bus. */
7037 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
7038 status = AscInitAsc1000Driver(asc_dvc);
7039
7040 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
7041 if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
7042 scmd_printk(KERN_INFO, scp, "SCSI host reset error: "
7043 "0x%x, status: 0x%x\n", asc_dvc->err_code,
7044 status);
7045 ret = FAILED;
7046 } else if (status) {
7047 scmd_printk(KERN_INFO, scp, "SCSI host reset warning: "
7048 "0x%x\n", status);
7049 } else {
7050 scmd_printk(KERN_INFO, scp, "SCSI host reset "
7051 "successful\n");
7052 }
7053
7054 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
7055 } else {
7056 /*
7057 * If the suggest reset bus flags are set, then reset the bus.
7058 * Otherwise only reset the device.
7059 */
7060 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
7061
7062 /*
7063 * Reset the chip and SCSI bus.
7064 */
7065 ASC_DBG(1, "before AdvResetChipAndSB()\n");
7066 switch (AdvResetChipAndSB(adv_dvc)) {
7067 case ASC_TRUE:
7068 scmd_printk(KERN_INFO, scp, "SCSI host reset "
7069 "successful\n");
7070 break;
7071 case ASC_FALSE:
7072 default:
7073 scmd_printk(KERN_INFO, scp, "SCSI host reset error\n");
7074 ret = FAILED;
7075 break;
7076 }
7077 spin_lock_irqsave(shost->host_lock, flags);
7078 AdvISR(adv_dvc);
7079 spin_unlock_irqrestore(shost->host_lock, flags);
7080 }
7081
7082 ASC_DBG(1, "ret %d\n", ret);
7083
7084 return ret;
7085 }
7086
7087 /*
7088 * advansys_biosparam()
7089 *
7090 * Translate disk drive geometry if the "BIOS greater than 1 GB"
7091 * support is enabled for a drive.
7092 *
7093 * ip (information pointer) is an int array with the following definition:
7094 * ip[0]: heads
7095 * ip[1]: sectors
7096 * ip[2]: cylinders
7097 */
7098 static int
7099 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
7100 sector_t capacity, int ip[])
7101 {
7102 struct asc_board *boardp = shost_priv(sdev->host);
7103
7104 ASC_DBG(1, "begin\n");
7105 ASC_STATS(sdev->host, biosparam);
7106 if (ASC_NARROW_BOARD(boardp)) {
7107 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
7108 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
7109 ip[0] = 255;
7110 ip[1] = 63;
7111 } else {
7112 ip[0] = 64;
7113 ip[1] = 32;
7114 }
7115 } else {
7116 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
7117 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
7118 ip[0] = 255;
7119 ip[1] = 63;
7120 } else {
7121 ip[0] = 64;
7122 ip[1] = 32;
7123 }
7124 }
7125 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
7126 ASC_DBG(1, "end\n");
7127 return 0;
7128 }
7129
7130 /*
7131 * First-level interrupt handler.
7132 *
7133 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
7134 */
7135 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
7136 {
7137 struct Scsi_Host *shost = dev_id;
7138 struct asc_board *boardp = shost_priv(shost);
7139 irqreturn_t result = IRQ_NONE;
7140 unsigned long flags;
7141
7142 ASC_DBG(2, "boardp 0x%p\n", boardp);
7143 spin_lock_irqsave(shost->host_lock, flags);
7144 if (ASC_NARROW_BOARD(boardp)) {
7145 if (AscIsIntPending(shost->io_port)) {
7146 result = IRQ_HANDLED;
7147 ASC_STATS(shost, interrupt);
7148 ASC_DBG(1, "before AscISR()\n");
7149 AscISR(&boardp->dvc_var.asc_dvc_var);
7150 }
7151 } else {
7152 ASC_DBG(1, "before AdvISR()\n");
7153 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
7154 result = IRQ_HANDLED;
7155 ASC_STATS(shost, interrupt);
7156 }
7157 }
7158 spin_unlock_irqrestore(shost->host_lock, flags);
7159
7160 ASC_DBG(1, "end\n");
7161 return result;
7162 }
7163
7164 static bool AscHostReqRiscHalt(PortAddr iop_base)
7165 {
7166 int count = 0;
7167 bool sta = false;
7168 uchar saved_stop_code;
7169
7170 if (AscIsChipHalted(iop_base))
7171 return true;
7172 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
7173 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
7174 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
7175 do {
7176 if (AscIsChipHalted(iop_base)) {
7177 sta = true;
7178 break;
7179 }
7180 mdelay(100);
7181 } while (count++ < 20);
7182 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
7183 return sta;
7184 }
7185
7186 static bool
7187 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
7188 {
7189 bool sta = false;
7190
7191 if (AscHostReqRiscHalt(iop_base)) {
7192 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
7193 AscStartChip(iop_base);
7194 }
7195 return sta;
7196 }
7197
7198 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
7199 {
7200 char type = sdev->type;
7201 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
7202
7203 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
7204 return;
7205 if (asc_dvc->init_sdtr & tid_bits)
7206 return;
7207
7208 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
7209 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
7210
7211 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
7212 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
7213 (type == TYPE_ROM) || (type == TYPE_TAPE))
7214 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
7215
7216 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
7217 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
7218 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
7219 }
7220
7221 static void
7222 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
7223 {
7224 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
7225 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
7226
7227 if (sdev->lun == 0) {
7228 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
7229 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
7230 asc_dvc->init_sdtr |= tid_bit;
7231 } else {
7232 asc_dvc->init_sdtr &= ~tid_bit;
7233 }
7234
7235 if (orig_init_sdtr != asc_dvc->init_sdtr)
7236 AscAsyncFix(asc_dvc, sdev);
7237 }
7238
7239 if (sdev->tagged_supported) {
7240 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
7241 if (sdev->lun == 0) {
7242 asc_dvc->cfg->can_tagged_qng |= tid_bit;
7243 asc_dvc->use_tagged_qng |= tid_bit;
7244 }
7245 scsi_change_queue_depth(sdev,
7246 asc_dvc->max_dvc_qng[sdev->id]);
7247 }
7248 } else {
7249 if (sdev->lun == 0) {
7250 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
7251 asc_dvc->use_tagged_qng &= ~tid_bit;
7252 }
7253 }
7254
7255 if ((sdev->lun == 0) &&
7256 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
7257 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
7258 asc_dvc->cfg->disc_enable);
7259 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
7260 asc_dvc->use_tagged_qng);
7261 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
7262 asc_dvc->cfg->can_tagged_qng);
7263
7264 asc_dvc->max_dvc_qng[sdev->id] =
7265 asc_dvc->cfg->max_tag_qng[sdev->id];
7266 AscWriteLramByte(asc_dvc->iop_base,
7267 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
7268 asc_dvc->max_dvc_qng[sdev->id]);
7269 }
7270 }
7271
7272 /*
7273 * Wide Transfers
7274 *
7275 * If the EEPROM enabled WDTR for the device and the device supports wide
7276 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
7277 * write the new value to the microcode.
7278 */
7279 static void
7280 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
7281 {
7282 unsigned short cfg_word;
7283 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7284 if ((cfg_word & tidmask) != 0)
7285 return;
7286
7287 cfg_word |= tidmask;
7288 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7289
7290 /*
7291 * Clear the microcode SDTR and WDTR negotiation done indicators for
7292 * the target to cause it to negotiate with the new setting set above.
7293 * WDTR when accepted causes the target to enter asynchronous mode, so
7294 * SDTR must be negotiated.
7295 */
7296 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7297 cfg_word &= ~tidmask;
7298 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7299 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7300 cfg_word &= ~tidmask;
7301 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7302 }
7303
7304 /*
7305 * Synchronous Transfers
7306 *
7307 * If the EEPROM enabled SDTR for the device and the device
7308 * supports synchronous transfers, then turn on the device's
7309 * 'sdtr_able' bit. Write the new value to the microcode.
7310 */
7311 static void
7312 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
7313 {
7314 unsigned short cfg_word;
7315 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7316 if ((cfg_word & tidmask) != 0)
7317 return;
7318
7319 cfg_word |= tidmask;
7320 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7321
7322 /*
7323 * Clear the microcode "SDTR negotiation" done indicator for the
7324 * target to cause it to negotiate with the new setting set above.
7325 */
7326 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7327 cfg_word &= ~tidmask;
7328 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7329 }
7330
7331 /*
7332 * PPR (Parallel Protocol Request) Capable
7333 *
7334 * If the device supports DT mode, then it must be PPR capable.
7335 * The PPR message will be used in place of the SDTR and WDTR
7336 * messages to negotiate synchronous speed and offset, transfer
7337 * width, and protocol options.
7338 */
7339 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
7340 AdvPortAddr iop_base, unsigned short tidmask)
7341 {
7342 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7343 adv_dvc->ppr_able |= tidmask;
7344 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7345 }
7346
7347 static void
7348 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
7349 {
7350 AdvPortAddr iop_base = adv_dvc->iop_base;
7351 unsigned short tidmask = 1 << sdev->id;
7352
7353 if (sdev->lun == 0) {
7354 /*
7355 * Handle WDTR, SDTR, and Tag Queuing. If the feature
7356 * is enabled in the EEPROM and the device supports the
7357 * feature, then enable it in the microcode.
7358 */
7359
7360 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
7361 advansys_wide_enable_wdtr(iop_base, tidmask);
7362 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
7363 advansys_wide_enable_sdtr(iop_base, tidmask);
7364 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
7365 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
7366
7367 /*
7368 * Tag Queuing is disabled for the BIOS which runs in polled
7369 * mode and would see no benefit from Tag Queuing. Also by
7370 * disabling Tag Queuing in the BIOS devices with Tag Queuing
7371 * bugs will at least work with the BIOS.
7372 */
7373 if ((adv_dvc->tagqng_able & tidmask) &&
7374 sdev->tagged_supported) {
7375 unsigned short cfg_word;
7376 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
7377 cfg_word |= tidmask;
7378 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7379 cfg_word);
7380 AdvWriteByteLram(iop_base,
7381 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
7382 adv_dvc->max_dvc_qng);
7383 }
7384 }
7385
7386 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported)
7387 scsi_change_queue_depth(sdev, adv_dvc->max_dvc_qng);
7388 }
7389
7390 /*
7391 * Set the number of commands to queue per device for the
7392 * specified host adapter.
7393 */
7394 static int advansys_slave_configure(struct scsi_device *sdev)
7395 {
7396 struct asc_board *boardp = shost_priv(sdev->host);
7397
7398 if (ASC_NARROW_BOARD(boardp))
7399 advansys_narrow_slave_configure(sdev,
7400 &boardp->dvc_var.asc_dvc_var);
7401 else
7402 advansys_wide_slave_configure(sdev,
7403 &boardp->dvc_var.adv_dvc_var);
7404
7405 return 0;
7406 }
7407
7408 static __le32 asc_get_sense_buffer_dma(struct scsi_cmnd *scp)
7409 {
7410 struct asc_board *board = shost_priv(scp->device->host);
7411 struct advansys_cmd *acmd = advansys_cmd(scp);
7412
7413 acmd->dma_handle = dma_map_single(board->dev, scp->sense_buffer,
7414 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7415 if (dma_mapping_error(board->dev, acmd->dma_handle)) {
7416 ASC_DBG(1, "failed to map sense buffer\n");
7417 return 0;
7418 }
7419 return cpu_to_le32(acmd->dma_handle);
7420 }
7421
7422 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
7423 struct asc_scsi_q *asc_scsi_q)
7424 {
7425 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7426 int use_sg;
7427 u32 srb_tag;
7428
7429 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
7430
7431 /*
7432 * Set the srb_tag to the command tag + 1, as
7433 * srb_tag '0' is used internally by the chip.
7434 */
7435 srb_tag = scsi_cmd_to_rq(scp)->tag + 1;
7436 asc_scsi_q->q2.srb_tag = srb_tag;
7437
7438 /*
7439 * Build the ASC_SCSI_Q request.
7440 */
7441 asc_scsi_q->cdbptr = &scp->cmnd[0];
7442 asc_scsi_q->q2.cdb_len = scp->cmd_len;
7443 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
7444 asc_scsi_q->q1.target_lun = scp->device->lun;
7445 asc_scsi_q->q2.target_ix =
7446 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
7447 asc_scsi_q->q1.sense_addr = asc_get_sense_buffer_dma(scp);
7448 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE;
7449 if (!asc_scsi_q->q1.sense_addr)
7450 return ASC_BUSY;
7451
7452 /*
7453 * If there are any outstanding requests for the current target,
7454 * then every 255th request send an ORDERED request. This heuristic
7455 * tries to retain the benefit of request sorting while preventing
7456 * request starvation. 255 is the max number of tags or pending commands
7457 * a device may have outstanding.
7458 *
7459 * The request count is incremented below for every successfully
7460 * started request.
7461 *
7462 */
7463 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
7464 (boardp->reqcnt[scp->device->id] % 255) == 0) {
7465 asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG;
7466 } else {
7467 asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG;
7468 }
7469
7470 /* Build ASC_SCSI_Q */
7471 use_sg = scsi_dma_map(scp);
7472 if (use_sg < 0) {
7473 ASC_DBG(1, "failed to map sglist\n");
7474 return ASC_BUSY;
7475 } else if (use_sg > 0) {
7476 int sgcnt;
7477 struct scatterlist *slp;
7478 struct asc_sg_head *asc_sg_head;
7479
7480 if (use_sg > scp->device->host->sg_tablesize) {
7481 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7482 "sg_tablesize %d\n", use_sg,
7483 scp->device->host->sg_tablesize);
7484 scsi_dma_unmap(scp);
7485 set_host_byte(scp, DID_ERROR);
7486 return ASC_ERROR;
7487 }
7488
7489 asc_sg_head = kzalloc(struct_size(asc_sg_head, sg_list, use_sg),
7490 GFP_ATOMIC);
7491 if (!asc_sg_head) {
7492 scsi_dma_unmap(scp);
7493 set_host_byte(scp, DID_SOFT_ERROR);
7494 return ASC_ERROR;
7495 }
7496
7497 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
7498 asc_scsi_q->sg_head = asc_sg_head;
7499 asc_scsi_q->q1.data_cnt = 0;
7500 asc_scsi_q->q1.data_addr = 0;
7501 /* This is a byte value, otherwise it would need to be swapped. */
7502 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
7503 ASC_STATS_ADD(scp->device->host, xfer_elem,
7504 asc_sg_head->entry_cnt);
7505
7506 /*
7507 * Convert scatter-gather list into ASC_SG_HEAD list.
7508 */
7509 scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
7510 asc_sg_head->sg_list[sgcnt].addr =
7511 cpu_to_le32(sg_dma_address(slp));
7512 asc_sg_head->sg_list[sgcnt].bytes =
7513 cpu_to_le32(sg_dma_len(slp));
7514 ASC_STATS_ADD(scp->device->host, xfer_sect,
7515 DIV_ROUND_UP(sg_dma_len(slp), 512));
7516 }
7517 }
7518
7519 ASC_STATS(scp->device->host, xfer_cnt);
7520
7521 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
7522 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7523
7524 return ASC_NOERROR;
7525 }
7526
7527 /*
7528 * Build scatter-gather list for Adv Library (Wide Board).
7529 *
7530 * Additional ADV_SG_BLOCK structures will need to be allocated
7531 * if the total number of scatter-gather elements exceeds
7532 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
7533 * assumed to be physically contiguous.
7534 *
7535 * Return:
7536 * ADV_SUCCESS(1) - SG List successfully created
7537 * ADV_ERROR(-1) - SG List creation failed
7538 */
7539 static int
7540 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp,
7541 ADV_SCSI_REQ_Q *scsiqp, struct scsi_cmnd *scp, int use_sg)
7542 {
7543 adv_sgblk_t *sgblkp, *prev_sgblkp;
7544 struct scatterlist *slp;
7545 int sg_elem_cnt;
7546 ADV_SG_BLOCK *sg_block, *prev_sg_block;
7547 dma_addr_t sgblk_paddr;
7548 int i;
7549
7550 slp = scsi_sglist(scp);
7551 sg_elem_cnt = use_sg;
7552 prev_sgblkp = NULL;
7553 prev_sg_block = NULL;
7554 reqp->sgblkp = NULL;
7555
7556 for (;;) {
7557 /*
7558 * Allocate a 'adv_sgblk_t' structure from the board free
7559 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
7560 * (15) scatter-gather elements.
7561 */
7562 sgblkp = dma_pool_alloc(boardp->adv_sgblk_pool, GFP_ATOMIC,
7563 &sgblk_paddr);
7564 if (!sgblkp) {
7565 ASC_DBG(1, "no free adv_sgblk_t\n");
7566 ASC_STATS(scp->device->host, adv_build_nosg);
7567
7568 /*
7569 * Allocation failed. Free 'adv_sgblk_t' structures
7570 * already allocated for the request.
7571 */
7572 while ((sgblkp = reqp->sgblkp) != NULL) {
7573 /* Remove 'sgblkp' from the request list. */
7574 reqp->sgblkp = sgblkp->next_sgblkp;
7575 sgblkp->next_sgblkp = NULL;
7576 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
7577 sgblkp->sg_addr);
7578 }
7579 return ASC_BUSY;
7580 }
7581 /* Complete 'adv_sgblk_t' board allocation. */
7582 sgblkp->sg_addr = sgblk_paddr;
7583 sgblkp->next_sgblkp = NULL;
7584 sg_block = &sgblkp->sg_block;
7585
7586 /*
7587 * Check if this is the first 'adv_sgblk_t' for the
7588 * request.
7589 */
7590 if (reqp->sgblkp == NULL) {
7591 /* Request's first scatter-gather block. */
7592 reqp->sgblkp = sgblkp;
7593
7594 /*
7595 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
7596 * address pointers.
7597 */
7598 scsiqp->sg_list_ptr = sg_block;
7599 scsiqp->sg_real_addr = cpu_to_le32(sgblk_paddr);
7600 } else {
7601 /* Request's second or later scatter-gather block. */
7602 prev_sgblkp->next_sgblkp = sgblkp;
7603
7604 /*
7605 * Point the previous ADV_SG_BLOCK structure to
7606 * the newly allocated ADV_SG_BLOCK structure.
7607 */
7608 prev_sg_block->sg_ptr = cpu_to_le32(sgblk_paddr);
7609 }
7610
7611 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
7612 sg_block->sg_list[i].sg_addr =
7613 cpu_to_le32(sg_dma_address(slp));
7614 sg_block->sg_list[i].sg_count =
7615 cpu_to_le32(sg_dma_len(slp));
7616 ASC_STATS_ADD(scp->device->host, xfer_sect,
7617 DIV_ROUND_UP(sg_dma_len(slp), 512));
7618
7619 if (--sg_elem_cnt == 0) {
7620 /*
7621 * Last ADV_SG_BLOCK and scatter-gather entry.
7622 */
7623 sg_block->sg_cnt = i + 1;
7624 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
7625 return ADV_SUCCESS;
7626 }
7627 slp = sg_next(slp);
7628 }
7629 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
7630 prev_sg_block = sg_block;
7631 prev_sgblkp = sgblkp;
7632 }
7633 }
7634
7635 /*
7636 * Build a request structure for the Adv Library (Wide Board).
7637 *
7638 * If an adv_req_t can not be allocated to issue the request,
7639 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
7640 *
7641 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the
7642 * microcode for DMA addresses or math operations are byte swapped
7643 * to little-endian order.
7644 */
7645 static int
7646 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
7647 adv_req_t **adv_reqpp)
7648 {
7649 u32 srb_tag = scsi_cmd_to_rq(scp)->tag;
7650 adv_req_t *reqp;
7651 ADV_SCSI_REQ_Q *scsiqp;
7652 int ret;
7653 int use_sg;
7654 dma_addr_t sense_addr;
7655
7656 /*
7657 * Allocate an adv_req_t structure from the board to execute
7658 * the command.
7659 */
7660 reqp = &boardp->adv_reqp[srb_tag];
7661 if (reqp->cmndp && reqp->cmndp != scp ) {
7662 ASC_DBG(1, "no free adv_req_t\n");
7663 ASC_STATS(scp->device->host, adv_build_noreq);
7664 return ASC_BUSY;
7665 }
7666
7667 reqp->req_addr = boardp->adv_reqp_addr + (srb_tag * sizeof(adv_req_t));
7668
7669 scsiqp = &reqp->scsi_req_q;
7670
7671 /*
7672 * Initialize the structure.
7673 */
7674 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
7675
7676 /*
7677 * Set the srb_tag to the command tag.
7678 */
7679 scsiqp->srb_tag = srb_tag;
7680
7681 /*
7682 * Set 'host_scribble' to point to the adv_req_t structure.
7683 */
7684 reqp->cmndp = scp;
7685 scp->host_scribble = (void *)reqp;
7686
7687 /*
7688 * Build the ADV_SCSI_REQ_Q request.
7689 */
7690
7691 /* Set CDB length and copy it to the request structure. */
7692 scsiqp->cdb_len = scp->cmd_len;
7693 /* Copy first 12 CDB bytes to cdb[]. */
7694 memcpy(scsiqp->cdb, scp->cmnd, scp->cmd_len < 12 ? scp->cmd_len : 12);
7695 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
7696 if (scp->cmd_len > 12) {
7697 int cdb16_len = scp->cmd_len - 12;
7698
7699 memcpy(scsiqp->cdb16, &scp->cmnd[12], cdb16_len);
7700 }
7701
7702 scsiqp->target_id = scp->device->id;
7703 scsiqp->target_lun = scp->device->lun;
7704
7705 sense_addr = dma_map_single(boardp->dev, scp->sense_buffer,
7706 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7707 if (dma_mapping_error(boardp->dev, sense_addr)) {
7708 ASC_DBG(1, "failed to map sense buffer\n");
7709 ASC_STATS(scp->device->host, adv_build_noreq);
7710 return ASC_BUSY;
7711 }
7712 scsiqp->sense_addr = cpu_to_le32(sense_addr);
7713 scsiqp->sense_len = SCSI_SENSE_BUFFERSIZE;
7714
7715 /* Build ADV_SCSI_REQ_Q */
7716
7717 use_sg = scsi_dma_map(scp);
7718 if (use_sg < 0) {
7719 ASC_DBG(1, "failed to map SG list\n");
7720 ASC_STATS(scp->device->host, adv_build_noreq);
7721 return ASC_BUSY;
7722 } else if (use_sg == 0) {
7723 /* Zero-length transfer */
7724 reqp->sgblkp = NULL;
7725 scsiqp->data_cnt = 0;
7726
7727 scsiqp->data_addr = 0;
7728 scsiqp->sg_list_ptr = NULL;
7729 scsiqp->sg_real_addr = 0;
7730 } else {
7731 if (use_sg > ADV_MAX_SG_LIST) {
7732 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7733 "ADV_MAX_SG_LIST %d\n", use_sg,
7734 scp->device->host->sg_tablesize);
7735 scsi_dma_unmap(scp);
7736 set_host_byte(scp, DID_ERROR);
7737 reqp->cmndp = NULL;
7738 scp->host_scribble = NULL;
7739
7740 return ASC_ERROR;
7741 }
7742
7743 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
7744
7745 ret = adv_get_sglist(boardp, reqp, scsiqp, scp, use_sg);
7746 if (ret != ADV_SUCCESS) {
7747 scsi_dma_unmap(scp);
7748 set_host_byte(scp, DID_ERROR);
7749 reqp->cmndp = NULL;
7750 scp->host_scribble = NULL;
7751
7752 return ret;
7753 }
7754
7755 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
7756 }
7757
7758 ASC_STATS(scp->device->host, xfer_cnt);
7759
7760 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
7761 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7762
7763 *adv_reqpp = reqp;
7764
7765 return ASC_NOERROR;
7766 }
7767
7768 static int AscSgListToQueue(int sg_list)
7769 {
7770 int n_sg_list_qs;
7771
7772 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
7773 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
7774 n_sg_list_qs++;
7775 return n_sg_list_qs + 1;
7776 }
7777
7778 static uint
7779 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
7780 {
7781 uint cur_used_qs;
7782 uint cur_free_qs;
7783 ASC_SCSI_BIT_ID_TYPE target_id;
7784 uchar tid_no;
7785
7786 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
7787 tid_no = ASC_TIX_TO_TID(target_ix);
7788 if ((asc_dvc->unit_not_ready & target_id) ||
7789 (asc_dvc->queue_full_or_busy & target_id)) {
7790 return 0;
7791 }
7792 if (n_qs == 1) {
7793 cur_used_qs = (uint) asc_dvc->cur_total_qng +
7794 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
7795 } else {
7796 cur_used_qs = (uint) asc_dvc->cur_total_qng +
7797 (uint) ASC_MIN_FREE_Q;
7798 }
7799 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
7800 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
7801 if (asc_dvc->cur_dvc_qng[tid_no] >=
7802 asc_dvc->max_dvc_qng[tid_no]) {
7803 return 0;
7804 }
7805 return cur_free_qs;
7806 }
7807 if (n_qs > 1) {
7808 if ((n_qs > asc_dvc->last_q_shortage)
7809 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
7810 asc_dvc->last_q_shortage = n_qs;
7811 }
7812 }
7813 return 0;
7814 }
7815
7816 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
7817 {
7818 ushort q_addr;
7819 uchar next_qp;
7820 uchar q_status;
7821
7822 q_addr = ASC_QNO_TO_QADDR(free_q_head);
7823 q_status = (uchar)AscReadLramByte(iop_base,
7824 (ushort)(q_addr +
7825 ASC_SCSIQ_B_STATUS));
7826 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
7827 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
7828 return next_qp;
7829 return ASC_QLINK_END;
7830 }
7831
7832 static uchar
7833 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
7834 {
7835 uchar i;
7836
7837 for (i = 0; i < n_free_q; i++) {
7838 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
7839 if (free_q_head == ASC_QLINK_END)
7840 break;
7841 }
7842 return free_q_head;
7843 }
7844
7845 /*
7846 * void
7847 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
7848 *
7849 * Calling/Exit State:
7850 * none
7851 *
7852 * Description:
7853 * Output an ASC_SCSI_Q structure to the chip
7854 */
7855 static void
7856 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
7857 {
7858 int i;
7859
7860 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
7861 AscSetChipLramAddr(iop_base, s_addr);
7862 for (i = 0; i < 2 * words; i += 2) {
7863 if (i == 4 || i == 20) {
7864 continue;
7865 }
7866 outpw(iop_base + IOP_RAM_DATA,
7867 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
7868 }
7869 }
7870
7871 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
7872 {
7873 ushort q_addr;
7874 uchar tid_no;
7875 uchar sdtr_data;
7876 uchar syn_period_ix;
7877 uchar syn_offset;
7878 PortAddr iop_base;
7879
7880 iop_base = asc_dvc->iop_base;
7881 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
7882 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
7883 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
7884 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
7885 syn_period_ix =
7886 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
7887 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
7888 AscMsgOutSDTR(asc_dvc,
7889 asc_dvc->sdtr_period_tbl[syn_period_ix],
7890 syn_offset);
7891 scsiq->q1.cntl |= QC_MSG_OUT;
7892 }
7893 q_addr = ASC_QNO_TO_QADDR(q_no);
7894 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
7895 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
7896 }
7897 scsiq->q1.status = QS_FREE;
7898 AscMemWordCopyPtrToLram(iop_base,
7899 q_addr + ASC_SCSIQ_CDB_BEG,
7900 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
7901
7902 DvcPutScsiQ(iop_base,
7903 q_addr + ASC_SCSIQ_CPY_BEG,
7904 (uchar *)&scsiq->q1.cntl,
7905 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
7906 AscWriteLramWord(iop_base,
7907 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
7908 (ushort)(((ushort)scsiq->q1.
7909 q_no << 8) | (ushort)QS_READY));
7910 return 1;
7911 }
7912
7913 static int
7914 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
7915 {
7916 int sta;
7917 int i;
7918 ASC_SG_HEAD *sg_head;
7919 ASC_SG_LIST_Q scsi_sg_q;
7920 __le32 saved_data_addr;
7921 __le32 saved_data_cnt;
7922 PortAddr iop_base;
7923 ushort sg_list_dwords;
7924 ushort sg_index;
7925 ushort sg_entry_cnt;
7926 ushort q_addr;
7927 uchar next_qp;
7928
7929 iop_base = asc_dvc->iop_base;
7930 sg_head = scsiq->sg_head;
7931 saved_data_addr = scsiq->q1.data_addr;
7932 saved_data_cnt = scsiq->q1.data_cnt;
7933 scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr);
7934 scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes);
7935 /*
7936 * Set sg_entry_cnt to be the number of SG elements that
7937 * will fit in the allocated SG queues. It is minus 1, because
7938 * the first SG element is handled above.
7939 */
7940 sg_entry_cnt = sg_head->entry_cnt - 1;
7941
7942 if (sg_entry_cnt != 0) {
7943 scsiq->q1.cntl |= QC_SG_HEAD;
7944 q_addr = ASC_QNO_TO_QADDR(q_no);
7945 sg_index = 1;
7946 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
7947 scsi_sg_q.sg_head_qp = q_no;
7948 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
7949 for (i = 0; i < sg_head->queue_cnt; i++) {
7950 scsi_sg_q.seq_no = i + 1;
7951 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
7952 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
7953 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
7954 if (i == 0) {
7955 scsi_sg_q.sg_list_cnt =
7956 ASC_SG_LIST_PER_Q;
7957 scsi_sg_q.sg_cur_list_cnt =
7958 ASC_SG_LIST_PER_Q;
7959 } else {
7960 scsi_sg_q.sg_list_cnt =
7961 ASC_SG_LIST_PER_Q - 1;
7962 scsi_sg_q.sg_cur_list_cnt =
7963 ASC_SG_LIST_PER_Q - 1;
7964 }
7965 } else {
7966 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
7967 sg_list_dwords = sg_entry_cnt << 1;
7968 if (i == 0) {
7969 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
7970 scsi_sg_q.sg_cur_list_cnt =
7971 sg_entry_cnt;
7972 } else {
7973 scsi_sg_q.sg_list_cnt =
7974 sg_entry_cnt - 1;
7975 scsi_sg_q.sg_cur_list_cnt =
7976 sg_entry_cnt - 1;
7977 }
7978 sg_entry_cnt = 0;
7979 }
7980 next_qp = AscReadLramByte(iop_base,
7981 (ushort)(q_addr +
7982 ASC_SCSIQ_B_FWD));
7983 scsi_sg_q.q_no = next_qp;
7984 q_addr = ASC_QNO_TO_QADDR(next_qp);
7985 AscMemWordCopyPtrToLram(iop_base,
7986 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
7987 (uchar *)&scsi_sg_q,
7988 sizeof(ASC_SG_LIST_Q) >> 1);
7989 AscMemDWordCopyPtrToLram(iop_base,
7990 q_addr + ASC_SGQ_LIST_BEG,
7991 (uchar *)&sg_head->
7992 sg_list[sg_index],
7993 sg_list_dwords);
7994 sg_index += ASC_SG_LIST_PER_Q;
7995 scsiq->next_sg_index = sg_index;
7996 }
7997 } else {
7998 scsiq->q1.cntl &= ~QC_SG_HEAD;
7999 }
8000 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
8001 scsiq->q1.data_addr = saved_data_addr;
8002 scsiq->q1.data_cnt = saved_data_cnt;
8003 return (sta);
8004 }
8005
8006 static int
8007 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
8008 {
8009 PortAddr iop_base;
8010 uchar free_q_head;
8011 uchar next_qp;
8012 uchar tid_no;
8013 uchar target_ix;
8014 int sta;
8015
8016 iop_base = asc_dvc->iop_base;
8017 target_ix = scsiq->q2.target_ix;
8018 tid_no = ASC_TIX_TO_TID(target_ix);
8019 sta = 0;
8020 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
8021 if (n_q_required > 1) {
8022 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
8023 (uchar)n_q_required);
8024 if (next_qp != ASC_QLINK_END) {
8025 asc_dvc->last_q_shortage = 0;
8026 scsiq->sg_head->queue_cnt = n_q_required - 1;
8027 scsiq->q1.q_no = free_q_head;
8028 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
8029 free_q_head);
8030 }
8031 } else if (n_q_required == 1) {
8032 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
8033 if (next_qp != ASC_QLINK_END) {
8034 scsiq->q1.q_no = free_q_head;
8035 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
8036 }
8037 }
8038 if (sta == 1) {
8039 AscPutVarFreeQHead(iop_base, next_qp);
8040 asc_dvc->cur_total_qng += n_q_required;
8041 asc_dvc->cur_dvc_qng[tid_no]++;
8042 }
8043 return sta;
8044 }
8045
8046 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
8047 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
8048 INQUIRY,
8049 REQUEST_SENSE,
8050 READ_CAPACITY,
8051 READ_TOC,
8052 MODE_SELECT,
8053 MODE_SENSE,
8054 MODE_SELECT_10,
8055 MODE_SENSE_10,
8056 0xFF,
8057 0xFF,
8058 0xFF,
8059 0xFF,
8060 0xFF,
8061 0xFF,
8062 0xFF,
8063 0xFF
8064 };
8065
8066 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
8067 {
8068 PortAddr iop_base;
8069 int sta;
8070 int n_q_required;
8071 bool disable_syn_offset_one_fix;
8072 int i;
8073 u32 addr;
8074 ushort sg_entry_cnt = 0;
8075 ushort sg_entry_cnt_minus_one = 0;
8076 uchar target_ix;
8077 uchar tid_no;
8078 uchar sdtr_data;
8079 uchar extra_bytes;
8080 uchar scsi_cmd;
8081 uchar disable_cmd;
8082 ASC_SG_HEAD *sg_head;
8083 unsigned long data_cnt;
8084
8085 iop_base = asc_dvc->iop_base;
8086 sg_head = scsiq->sg_head;
8087 if (asc_dvc->err_code != 0)
8088 return ASC_ERROR;
8089 scsiq->q1.q_no = 0;
8090 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
8091 scsiq->q1.extra_bytes = 0;
8092 }
8093 sta = 0;
8094 target_ix = scsiq->q2.target_ix;
8095 tid_no = ASC_TIX_TO_TID(target_ix);
8096 n_q_required = 1;
8097 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
8098 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
8099 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
8100 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8101 AscMsgOutSDTR(asc_dvc,
8102 asc_dvc->
8103 sdtr_period_tbl[(sdtr_data >> 4) &
8104 (uchar)(asc_dvc->
8105 max_sdtr_index -
8106 1)],
8107 (uchar)(sdtr_data & (uchar)
8108 ASC_SYN_MAX_OFFSET));
8109 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
8110 }
8111 }
8112 if (asc_dvc->in_critical_cnt != 0) {
8113 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
8114 return ASC_ERROR;
8115 }
8116 asc_dvc->in_critical_cnt++;
8117 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8118 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
8119 asc_dvc->in_critical_cnt--;
8120 return ASC_ERROR;
8121 }
8122 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8123 asc_dvc->in_critical_cnt--;
8124 return ASC_ERROR;
8125 }
8126 if (sg_entry_cnt == 1) {
8127 scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr);
8128 scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes);
8129 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
8130 }
8131 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
8132 }
8133 scsi_cmd = scsiq->cdbptr[0];
8134 disable_syn_offset_one_fix = false;
8135 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
8136 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
8137 if (scsiq->q1.cntl & QC_SG_HEAD) {
8138 data_cnt = 0;
8139 for (i = 0; i < sg_entry_cnt; i++) {
8140 data_cnt += le32_to_cpu(sg_head->sg_list[i].
8141 bytes);
8142 }
8143 } else {
8144 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
8145 }
8146 if (data_cnt != 0UL) {
8147 if (data_cnt < 512UL) {
8148 disable_syn_offset_one_fix = true;
8149 } else {
8150 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
8151 i++) {
8152 disable_cmd =
8153 _syn_offset_one_disable_cmd[i];
8154 if (disable_cmd == 0xFF) {
8155 break;
8156 }
8157 if (scsi_cmd == disable_cmd) {
8158 disable_syn_offset_one_fix =
8159 true;
8160 break;
8161 }
8162 }
8163 }
8164 }
8165 }
8166 if (disable_syn_offset_one_fix) {
8167 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
8168 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
8169 ASC_TAG_FLAG_DISABLE_DISCONNECT);
8170 } else {
8171 scsiq->q2.tag_code &= 0x27;
8172 }
8173 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8174 if (asc_dvc->bug_fix_cntl) {
8175 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8176 if ((scsi_cmd == READ_6) ||
8177 (scsi_cmd == READ_10)) {
8178 addr = le32_to_cpu(sg_head->
8179 sg_list
8180 [sg_entry_cnt_minus_one].
8181 addr) +
8182 le32_to_cpu(sg_head->
8183 sg_list
8184 [sg_entry_cnt_minus_one].
8185 bytes);
8186 extra_bytes =
8187 (uchar)((ushort)addr & 0x0003);
8188 if ((extra_bytes != 0)
8189 &&
8190 ((scsiq->q2.
8191 tag_code &
8192 ASC_TAG_FLAG_EXTRA_BYTES)
8193 == 0)) {
8194 scsiq->q2.tag_code |=
8195 ASC_TAG_FLAG_EXTRA_BYTES;
8196 scsiq->q1.extra_bytes =
8197 extra_bytes;
8198 data_cnt =
8199 le32_to_cpu(sg_head->
8200 sg_list
8201 [sg_entry_cnt_minus_one].
8202 bytes);
8203 data_cnt -= extra_bytes;
8204 sg_head->
8205 sg_list
8206 [sg_entry_cnt_minus_one].
8207 bytes =
8208 cpu_to_le32(data_cnt);
8209 }
8210 }
8211 }
8212 }
8213 sg_head->entry_to_copy = sg_head->entry_cnt;
8214 n_q_required = AscSgListToQueue(sg_entry_cnt);
8215 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
8216 (uint) n_q_required)
8217 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8218 if ((sta =
8219 AscSendScsiQueue(asc_dvc, scsiq,
8220 n_q_required)) == 1) {
8221 asc_dvc->in_critical_cnt--;
8222 return (sta);
8223 }
8224 }
8225 } else {
8226 if (asc_dvc->bug_fix_cntl) {
8227 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8228 if ((scsi_cmd == READ_6) ||
8229 (scsi_cmd == READ_10)) {
8230 addr =
8231 le32_to_cpu(scsiq->q1.data_addr) +
8232 le32_to_cpu(scsiq->q1.data_cnt);
8233 extra_bytes =
8234 (uchar)((ushort)addr & 0x0003);
8235 if ((extra_bytes != 0)
8236 &&
8237 ((scsiq->q2.
8238 tag_code &
8239 ASC_TAG_FLAG_EXTRA_BYTES)
8240 == 0)) {
8241 data_cnt =
8242 le32_to_cpu(scsiq->q1.
8243 data_cnt);
8244 if (((ushort)data_cnt & 0x01FF)
8245 == 0) {
8246 scsiq->q2.tag_code |=
8247 ASC_TAG_FLAG_EXTRA_BYTES;
8248 data_cnt -= extra_bytes;
8249 scsiq->q1.data_cnt =
8250 cpu_to_le32
8251 (data_cnt);
8252 scsiq->q1.extra_bytes =
8253 extra_bytes;
8254 }
8255 }
8256 }
8257 }
8258 }
8259 n_q_required = 1;
8260 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
8261 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8262 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
8263 n_q_required)) == 1) {
8264 asc_dvc->in_critical_cnt--;
8265 return (sta);
8266 }
8267 }
8268 }
8269 asc_dvc->in_critical_cnt--;
8270 return (sta);
8271 }
8272
8273 /*
8274 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
8275 *
8276 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
8277 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
8278 * RISC to notify it a new command is ready to be executed.
8279 *
8280 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
8281 * set to SCSI_MAX_RETRY.
8282 *
8283 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the microcode
8284 * for DMA addresses or math operations are byte swapped to little-endian
8285 * order.
8286 *
8287 * Return:
8288 * ADV_SUCCESS(1) - The request was successfully queued.
8289 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
8290 * request completes.
8291 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
8292 * host IC error.
8293 */
8294 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, adv_req_t *reqp)
8295 {
8296 AdvPortAddr iop_base;
8297 ADV_CARR_T *new_carrp;
8298 ADV_SCSI_REQ_Q *scsiq = &reqp->scsi_req_q;
8299
8300 /*
8301 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
8302 */
8303 if (scsiq->target_id > ADV_MAX_TID) {
8304 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
8305 scsiq->done_status = QD_WITH_ERROR;
8306 return ADV_ERROR;
8307 }
8308
8309 iop_base = asc_dvc->iop_base;
8310
8311 /*
8312 * Allocate a carrier ensuring at least one carrier always
8313 * remains on the freelist and initialize fields.
8314 */
8315 new_carrp = adv_get_next_carrier(asc_dvc);
8316 if (!new_carrp) {
8317 ASC_DBG(1, "No free carriers\n");
8318 return ADV_BUSY;
8319 }
8320
8321 asc_dvc->carr_pending_cnt++;
8322
8323 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
8324 scsiq->scsiq_ptr = cpu_to_le32(scsiq->srb_tag);
8325 scsiq->scsiq_rptr = cpu_to_le32(reqp->req_addr);
8326
8327 scsiq->carr_va = asc_dvc->icq_sp->carr_va;
8328 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
8329
8330 /*
8331 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
8332 * the microcode. The newly allocated stopper will become the new
8333 * stopper.
8334 */
8335 asc_dvc->icq_sp->areq_vpa = scsiq->scsiq_rptr;
8336
8337 /*
8338 * Set the 'next_vpa' pointer for the old stopper to be the
8339 * physical address of the new stopper. The RISC can only
8340 * follow physical addresses.
8341 */
8342 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
8343
8344 /*
8345 * Set the host adapter stopper pointer to point to the new carrier.
8346 */
8347 asc_dvc->icq_sp = new_carrp;
8348
8349 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8350 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8351 /*
8352 * Tickle the RISC to tell it to read its Command Queue Head pointer.
8353 */
8354 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
8355 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8356 /*
8357 * Clear the tickle value. In the ASC-3550 the RISC flag
8358 * command 'clr_tickle_a' does not work unless the host
8359 * value is cleared.
8360 */
8361 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8362 ADV_TICKLE_NOP);
8363 }
8364 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8365 /*
8366 * Notify the RISC a carrier is ready by writing the physical
8367 * address of the new carrier stopper to the COMMA register.
8368 */
8369 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8370 le32_to_cpu(new_carrp->carr_pa));
8371 }
8372
8373 return ADV_SUCCESS;
8374 }
8375
8376 /*
8377 * Execute a single 'struct scsi_cmnd'.
8378 */
8379 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
8380 {
8381 int ret, err_code;
8382 struct asc_board *boardp = shost_priv(scp->device->host);
8383
8384 ASC_DBG(1, "scp 0x%p\n", scp);
8385
8386 if (ASC_NARROW_BOARD(boardp)) {
8387 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
8388 struct asc_scsi_q asc_scsi_q;
8389
8390 ret = asc_build_req(boardp, scp, &asc_scsi_q);
8391 if (ret != ASC_NOERROR) {
8392 ASC_STATS(scp->device->host, build_error);
8393 return ret;
8394 }
8395
8396 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
8397 kfree(asc_scsi_q.sg_head);
8398 err_code = asc_dvc->err_code;
8399 } else {
8400 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
8401 adv_req_t *adv_reqp;
8402
8403 switch (adv_build_req(boardp, scp, &adv_reqp)) {
8404 case ASC_NOERROR:
8405 ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
8406 break;
8407 case ASC_BUSY:
8408 ASC_DBG(1, "adv_build_req ASC_BUSY\n");
8409 /*
8410 * The asc_stats fields 'adv_build_noreq' and
8411 * 'adv_build_nosg' count wide board busy conditions.
8412 * They are updated in adv_build_req and
8413 * adv_get_sglist, respectively.
8414 */
8415 return ASC_BUSY;
8416 case ASC_ERROR:
8417 default:
8418 ASC_DBG(1, "adv_build_req ASC_ERROR\n");
8419 ASC_STATS(scp->device->host, build_error);
8420 return ASC_ERROR;
8421 }
8422
8423 ret = AdvExeScsiQueue(adv_dvc, adv_reqp);
8424 err_code = adv_dvc->err_code;
8425 }
8426
8427 switch (ret) {
8428 case ASC_NOERROR:
8429 ASC_STATS(scp->device->host, exe_noerror);
8430 /*
8431 * Increment monotonically increasing per device
8432 * successful request counter. Wrapping doesn't matter.
8433 */
8434 boardp->reqcnt[scp->device->id]++;
8435 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
8436 break;
8437 case ASC_BUSY:
8438 ASC_DBG(1, "ExeScsiQueue() ASC_BUSY\n");
8439 ASC_STATS(scp->device->host, exe_busy);
8440 break;
8441 case ASC_ERROR:
8442 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
8443 "err_code 0x%x\n", err_code);
8444 ASC_STATS(scp->device->host, exe_error);
8445 set_host_byte(scp, DID_ERROR);
8446 break;
8447 default:
8448 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
8449 "err_code 0x%x\n", err_code);
8450 ASC_STATS(scp->device->host, exe_unknown);
8451 set_host_byte(scp, DID_ERROR);
8452 break;
8453 }
8454
8455 ASC_DBG(1, "end\n");
8456 return ret;
8457 }
8458
8459 /*
8460 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
8461 *
8462 * This function always returns 0. Command return status is saved
8463 * in the 'scp' result field.
8464 */
8465 static int advansys_queuecommand_lck(struct scsi_cmnd *scp)
8466 {
8467 struct Scsi_Host *shost = scp->device->host;
8468 int asc_res, result = 0;
8469
8470 ASC_STATS(shost, queuecommand);
8471
8472 asc_res = asc_execute_scsi_cmnd(scp);
8473
8474 switch (asc_res) {
8475 case ASC_NOERROR:
8476 break;
8477 case ASC_BUSY:
8478 result = SCSI_MLQUEUE_HOST_BUSY;
8479 break;
8480 case ASC_ERROR:
8481 default:
8482 asc_scsi_done(scp);
8483 break;
8484 }
8485
8486 return result;
8487 }
8488
8489 static DEF_SCSI_QCMD(advansys_queuecommand)
8490
8491 static ushort AscGetEisaChipCfg(PortAddr iop_base)
8492 {
8493 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8494 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
8495 return inpw(eisa_cfg_iop);
8496 }
8497
8498 /*
8499 * Return the BIOS address of the adapter at the specified
8500 * I/O port and with the specified bus type.
8501 */
8502 static unsigned short AscGetChipBiosAddress(PortAddr iop_base,
8503 unsigned short bus_type)
8504 {
8505 unsigned short cfg_lsw;
8506 unsigned short bios_addr;
8507
8508 /*
8509 * The PCI BIOS is re-located by the motherboard BIOS. Because
8510 * of this the driver can not determine where a PCI BIOS is
8511 * loaded and executes.
8512 */
8513 if (bus_type & ASC_IS_PCI)
8514 return 0;
8515
8516 if ((bus_type & ASC_IS_EISA) != 0) {
8517 cfg_lsw = AscGetEisaChipCfg(iop_base);
8518 cfg_lsw &= 0x000F;
8519 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
8520 return bios_addr;
8521 }
8522
8523 cfg_lsw = AscGetChipCfgLsw(iop_base);
8524 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
8525 return bios_addr;
8526 }
8527
8528 static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
8529 {
8530 ushort cfg_lsw;
8531
8532 if (AscGetChipScsiID(iop_base) == new_host_id) {
8533 return (new_host_id);
8534 }
8535 cfg_lsw = AscGetChipCfgLsw(iop_base);
8536 cfg_lsw &= 0xF8FF;
8537 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
8538 AscSetChipCfgLsw(iop_base, cfg_lsw);
8539 return (AscGetChipScsiID(iop_base));
8540 }
8541
8542 static unsigned char AscGetChipScsiCtrl(PortAddr iop_base)
8543 {
8544 unsigned char sc;
8545
8546 AscSetBank(iop_base, 1);
8547 sc = inp(iop_base + IOP_REG_SC);
8548 AscSetBank(iop_base, 0);
8549 return sc;
8550 }
8551
8552 static unsigned char AscGetChipVersion(PortAddr iop_base,
8553 unsigned short bus_type)
8554 {
8555 if (bus_type & ASC_IS_EISA) {
8556 PortAddr eisa_iop;
8557 unsigned char revision;
8558 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8559 (PortAddr) ASC_EISA_REV_IOP_MASK;
8560 revision = inp(eisa_iop);
8561 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
8562 }
8563 return AscGetChipVerNo(iop_base);
8564 }
8565
8566 static int AscStopQueueExe(PortAddr iop_base)
8567 {
8568 int count = 0;
8569
8570 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
8571 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
8572 ASC_STOP_REQ_RISC_STOP);
8573 do {
8574 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
8575 ASC_STOP_ACK_RISC_STOP) {
8576 return (1);
8577 }
8578 mdelay(100);
8579 } while (count++ < 20);
8580 }
8581 return (0);
8582 }
8583
8584 static unsigned int AscGetMaxDmaCount(ushort bus_type)
8585 {
8586 if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
8587 return ASC_MAX_VL_DMA_COUNT;
8588 return ASC_MAX_PCI_DMA_COUNT;
8589 }
8590
8591 static void AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
8592 {
8593 int i;
8594 PortAddr iop_base;
8595 uchar chip_version;
8596
8597 iop_base = asc_dvc->iop_base;
8598 asc_dvc->err_code = 0;
8599 if ((asc_dvc->bus_type &
8600 (ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
8601 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
8602 }
8603 AscSetChipControl(iop_base, CC_HALT);
8604 AscSetChipStatus(iop_base, 0);
8605 asc_dvc->bug_fix_cntl = 0;
8606 asc_dvc->pci_fix_asyn_xfer = 0;
8607 asc_dvc->pci_fix_asyn_xfer_always = 0;
8608 /* asc_dvc->init_state initialized in AscInitGetConfig(). */
8609 asc_dvc->sdtr_done = 0;
8610 asc_dvc->cur_total_qng = 0;
8611 asc_dvc->is_in_int = false;
8612 asc_dvc->in_critical_cnt = 0;
8613 asc_dvc->last_q_shortage = 0;
8614 asc_dvc->use_tagged_qng = 0;
8615 asc_dvc->no_scam = 0;
8616 asc_dvc->unit_not_ready = 0;
8617 asc_dvc->queue_full_or_busy = 0;
8618 asc_dvc->redo_scam = 0;
8619 asc_dvc->res2 = 0;
8620 asc_dvc->min_sdtr_index = 0;
8621 asc_dvc->cfg->can_tagged_qng = 0;
8622 asc_dvc->cfg->cmd_qng_enabled = 0;
8623 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
8624 asc_dvc->init_sdtr = 0;
8625 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
8626 asc_dvc->scsi_reset_wait = 3;
8627 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
8628 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
8629 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
8630 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
8631 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
8632 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
8633 asc_dvc->cfg->chip_version = chip_version;
8634 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
8635 asc_dvc->max_sdtr_index = 7;
8636 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
8637 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
8638 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
8639 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
8640 asc_dvc->max_sdtr_index = 15;
8641 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
8642 AscSetExtraControl(iop_base,
8643 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
8644 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
8645 AscSetExtraControl(iop_base,
8646 (SEC_ACTIVE_NEGATE |
8647 SEC_ENABLE_FILTER));
8648 }
8649 }
8650 if (asc_dvc->bus_type == ASC_IS_PCI) {
8651 AscSetExtraControl(iop_base,
8652 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
8653 }
8654
8655 for (i = 0; i <= ASC_MAX_TID; i++) {
8656 asc_dvc->cur_dvc_qng[i] = 0;
8657 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
8658 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
8659 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
8660 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
8661 }
8662 }
8663
8664 static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
8665 {
8666 int retry;
8667
8668 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
8669 unsigned char read_back;
8670 AscSetChipEEPCmd(iop_base, cmd_reg);
8671 mdelay(1);
8672 read_back = AscGetChipEEPCmd(iop_base);
8673 if (read_back == cmd_reg)
8674 return 1;
8675 }
8676 return 0;
8677 }
8678
8679 static void AscWaitEEPRead(void)
8680 {
8681 mdelay(1);
8682 }
8683
8684 static ushort AscReadEEPWord(PortAddr iop_base, uchar addr)
8685 {
8686 ushort read_wval;
8687 uchar cmd_reg;
8688
8689 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
8690 AscWaitEEPRead();
8691 cmd_reg = addr | ASC_EEP_CMD_READ;
8692 AscWriteEEPCmdReg(iop_base, cmd_reg);
8693 AscWaitEEPRead();
8694 read_wval = AscGetChipEEPData(iop_base);
8695 AscWaitEEPRead();
8696 return read_wval;
8697 }
8698
8699 static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
8700 ushort bus_type)
8701 {
8702 ushort wval;
8703 ushort sum;
8704 ushort *wbuf;
8705 int cfg_beg;
8706 int cfg_end;
8707 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
8708 int s_addr;
8709
8710 wbuf = (ushort *)cfg_buf;
8711 sum = 0;
8712 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
8713 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
8714 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
8715 sum += *wbuf;
8716 }
8717 if (bus_type & ASC_IS_VL) {
8718 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
8719 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
8720 } else {
8721 cfg_beg = ASC_EEP_DVC_CFG_BEG;
8722 cfg_end = ASC_EEP_MAX_DVC_ADDR;
8723 }
8724 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
8725 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
8726 if (s_addr <= uchar_end_in_config) {
8727 /*
8728 * Swap all char fields - must unswap bytes already swapped
8729 * by AscReadEEPWord().
8730 */
8731 *wbuf = le16_to_cpu(wval);
8732 } else {
8733 /* Don't swap word field at the end - cntl field. */
8734 *wbuf = wval;
8735 }
8736 sum += wval; /* Checksum treats all EEPROM data as words. */
8737 }
8738 /*
8739 * Read the checksum word which will be compared against 'sum'
8740 * by the caller. Word field already swapped.
8741 */
8742 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
8743 return sum;
8744 }
8745
8746 static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
8747 {
8748 PortAddr iop_base;
8749 ushort q_addr;
8750 ushort saved_word;
8751 int sta;
8752
8753 iop_base = asc_dvc->iop_base;
8754 sta = 0;
8755 q_addr = ASC_QNO_TO_QADDR(241);
8756 saved_word = AscReadLramWord(iop_base, q_addr);
8757 AscSetChipLramAddr(iop_base, q_addr);
8758 AscSetChipLramData(iop_base, 0x55AA);
8759 mdelay(10);
8760 AscSetChipLramAddr(iop_base, q_addr);
8761 if (AscGetChipLramData(iop_base) == 0x55AA) {
8762 sta = 1;
8763 AscWriteLramWord(iop_base, q_addr, saved_word);
8764 }
8765 return (sta);
8766 }
8767
8768 static void AscWaitEEPWrite(void)
8769 {
8770 mdelay(20);
8771 }
8772
8773 static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
8774 {
8775 ushort read_back;
8776 int retry;
8777
8778 retry = 0;
8779 while (true) {
8780 AscSetChipEEPData(iop_base, data_reg);
8781 mdelay(1);
8782 read_back = AscGetChipEEPData(iop_base);
8783 if (read_back == data_reg) {
8784 return (1);
8785 }
8786 if (retry++ > ASC_EEP_MAX_RETRY) {
8787 return (0);
8788 }
8789 }
8790 }
8791
8792 static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
8793 {
8794 ushort read_wval;
8795
8796 read_wval = AscReadEEPWord(iop_base, addr);
8797 if (read_wval != word_val) {
8798 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
8799 AscWaitEEPRead();
8800 AscWriteEEPDataReg(iop_base, word_val);
8801 AscWaitEEPRead();
8802 AscWriteEEPCmdReg(iop_base,
8803 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
8804 AscWaitEEPWrite();
8805 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
8806 AscWaitEEPRead();
8807 return (AscReadEEPWord(iop_base, addr));
8808 }
8809 return (read_wval);
8810 }
8811
8812 static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
8813 ushort bus_type)
8814 {
8815 int n_error;
8816 ushort *wbuf;
8817 ushort word;
8818 ushort sum;
8819 int s_addr;
8820 int cfg_beg;
8821 int cfg_end;
8822 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
8823
8824 wbuf = (ushort *)cfg_buf;
8825 n_error = 0;
8826 sum = 0;
8827 /* Write two config words; AscWriteEEPWord() will swap bytes. */
8828 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
8829 sum += *wbuf;
8830 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
8831 n_error++;
8832 }
8833 }
8834 if (bus_type & ASC_IS_VL) {
8835 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
8836 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
8837 } else {
8838 cfg_beg = ASC_EEP_DVC_CFG_BEG;
8839 cfg_end = ASC_EEP_MAX_DVC_ADDR;
8840 }
8841 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
8842 if (s_addr <= uchar_end_in_config) {
8843 /*
8844 * This is a char field. Swap char fields before they are
8845 * swapped again by AscWriteEEPWord().
8846 */
8847 word = cpu_to_le16(*wbuf);
8848 if (word !=
8849 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
8850 n_error++;
8851 }
8852 } else {
8853 /* Don't swap word field at the end - cntl field. */
8854 if (*wbuf !=
8855 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
8856 n_error++;
8857 }
8858 }
8859 sum += *wbuf; /* Checksum calculated from word values. */
8860 }
8861 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
8862 *wbuf = sum;
8863 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
8864 n_error++;
8865 }
8866
8867 /* Read EEPROM back again. */
8868 wbuf = (ushort *)cfg_buf;
8869 /*
8870 * Read two config words; Byte-swapping done by AscReadEEPWord().
8871 */
8872 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
8873 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
8874 n_error++;
8875 }
8876 }
8877 if (bus_type & ASC_IS_VL) {
8878 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
8879 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
8880 } else {
8881 cfg_beg = ASC_EEP_DVC_CFG_BEG;
8882 cfg_end = ASC_EEP_MAX_DVC_ADDR;
8883 }
8884 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
8885 if (s_addr <= uchar_end_in_config) {
8886 /*
8887 * Swap all char fields. Must unswap bytes already swapped
8888 * by AscReadEEPWord().
8889 */
8890 word =
8891 le16_to_cpu(AscReadEEPWord
8892 (iop_base, (uchar)s_addr));
8893 } else {
8894 /* Don't swap word field at the end - cntl field. */
8895 word = AscReadEEPWord(iop_base, (uchar)s_addr);
8896 }
8897 if (*wbuf != word) {
8898 n_error++;
8899 }
8900 }
8901 /* Read checksum; Byte swapping not needed. */
8902 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
8903 n_error++;
8904 }
8905 return n_error;
8906 }
8907
8908 static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
8909 ushort bus_type)
8910 {
8911 int retry;
8912 int n_error;
8913
8914 retry = 0;
8915 while (true) {
8916 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
8917 bus_type)) == 0) {
8918 break;
8919 }
8920 if (++retry > ASC_EEP_MAX_RETRY) {
8921 break;
8922 }
8923 }
8924 return n_error;
8925 }
8926
8927 static int AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
8928 {
8929 ASCEEP_CONFIG eep_config_buf;
8930 ASCEEP_CONFIG *eep_config;
8931 PortAddr iop_base;
8932 ushort chksum;
8933 ushort warn_code;
8934 ushort cfg_msw, cfg_lsw;
8935 int i;
8936 int write_eep = 0;
8937
8938 iop_base = asc_dvc->iop_base;
8939 warn_code = 0;
8940 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
8941 AscStopQueueExe(iop_base);
8942 if ((AscStopChip(iop_base)) ||
8943 (AscGetChipScsiCtrl(iop_base) != 0)) {
8944 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
8945 AscResetChipAndScsiBus(asc_dvc);
8946 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
8947 }
8948 if (!AscIsChipHalted(iop_base)) {
8949 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
8950 return (warn_code);
8951 }
8952 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
8953 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
8954 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
8955 return (warn_code);
8956 }
8957 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
8958 cfg_msw = AscGetChipCfgMsw(iop_base);
8959 cfg_lsw = AscGetChipCfgLsw(iop_base);
8960 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
8961 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
8962 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
8963 AscSetChipCfgMsw(iop_base, cfg_msw);
8964 }
8965 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
8966 ASC_DBG(1, "chksum 0x%x\n", chksum);
8967 if (chksum == 0) {
8968 chksum = 0xaa55;
8969 }
8970 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
8971 warn_code |= ASC_WARN_AUTO_CONFIG;
8972 if (asc_dvc->cfg->chip_version == 3) {
8973 if (eep_config->cfg_lsw != cfg_lsw) {
8974 warn_code |= ASC_WARN_EEPROM_RECOVER;
8975 eep_config->cfg_lsw =
8976 AscGetChipCfgLsw(iop_base);
8977 }
8978 if (eep_config->cfg_msw != cfg_msw) {
8979 warn_code |= ASC_WARN_EEPROM_RECOVER;
8980 eep_config->cfg_msw =
8981 AscGetChipCfgMsw(iop_base);
8982 }
8983 }
8984 }
8985 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
8986 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
8987 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
8988 if (chksum != eep_config->chksum) {
8989 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
8990 ASC_CHIP_VER_PCI_ULTRA_3050) {
8991 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
8992 eep_config->init_sdtr = 0xFF;
8993 eep_config->disc_enable = 0xFF;
8994 eep_config->start_motor = 0xFF;
8995 eep_config->use_cmd_qng = 0;
8996 eep_config->max_total_qng = 0xF0;
8997 eep_config->max_tag_qng = 0x20;
8998 eep_config->cntl = 0xBFFF;
8999 ASC_EEP_SET_CHIP_ID(eep_config, 7);
9000 eep_config->no_scam = 0;
9001 eep_config->adapter_info[0] = 0;
9002 eep_config->adapter_info[1] = 0;
9003 eep_config->adapter_info[2] = 0;
9004 eep_config->adapter_info[3] = 0;
9005 eep_config->adapter_info[4] = 0;
9006 /* Indicate EEPROM-less board. */
9007 eep_config->adapter_info[5] = 0xBB;
9008 } else {
9009 ASC_PRINT
9010 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
9011 write_eep = 1;
9012 warn_code |= ASC_WARN_EEPROM_CHKSUM;
9013 }
9014 }
9015 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
9016 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
9017 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
9018 asc_dvc->start_motor = eep_config->start_motor;
9019 asc_dvc->dvc_cntl = eep_config->cntl;
9020 asc_dvc->no_scam = eep_config->no_scam;
9021 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
9022 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
9023 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
9024 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
9025 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
9026 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
9027 if (!AscTestExternalLram(asc_dvc)) {
9028 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
9029 ASC_IS_PCI_ULTRA)) {
9030 eep_config->max_total_qng =
9031 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
9032 eep_config->max_tag_qng =
9033 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
9034 } else {
9035 eep_config->cfg_msw |= 0x0800;
9036 cfg_msw |= 0x0800;
9037 AscSetChipCfgMsw(iop_base, cfg_msw);
9038 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
9039 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
9040 }
9041 } else {
9042 }
9043 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
9044 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
9045 }
9046 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
9047 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
9048 }
9049 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
9050 eep_config->max_tag_qng = eep_config->max_total_qng;
9051 }
9052 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
9053 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
9054 }
9055 asc_dvc->max_total_qng = eep_config->max_total_qng;
9056 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
9057 eep_config->use_cmd_qng) {
9058 eep_config->disc_enable = eep_config->use_cmd_qng;
9059 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9060 }
9061 ASC_EEP_SET_CHIP_ID(eep_config,
9062 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
9063 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
9064 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
9065 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
9066 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
9067 }
9068
9069 for (i = 0; i <= ASC_MAX_TID; i++) {
9070 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
9071 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
9072 asc_dvc->cfg->sdtr_period_offset[i] =
9073 (uchar)(ASC_DEF_SDTR_OFFSET |
9074 (asc_dvc->min_sdtr_index << 4));
9075 }
9076 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
9077 if (write_eep) {
9078 if ((i = AscSetEEPConfig(iop_base, eep_config,
9079 asc_dvc->bus_type)) != 0) {
9080 ASC_PRINT1
9081 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
9082 i);
9083 } else {
9084 ASC_PRINT
9085 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
9086 }
9087 }
9088 return (warn_code);
9089 }
9090
9091 static int AscInitGetConfig(struct Scsi_Host *shost)
9092 {
9093 struct asc_board *board = shost_priv(shost);
9094 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9095 unsigned short warn_code = 0;
9096
9097 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
9098 if (asc_dvc->err_code != 0)
9099 return asc_dvc->err_code;
9100
9101 if (AscFindSignature(asc_dvc->iop_base)) {
9102 AscInitAscDvcVar(asc_dvc);
9103 warn_code = AscInitFromEEP(asc_dvc);
9104 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
9105 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
9106 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
9107 } else {
9108 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9109 }
9110
9111 switch (warn_code) {
9112 case 0: /* No error */
9113 break;
9114 case ASC_WARN_IO_PORT_ROTATE:
9115 shost_printk(KERN_WARNING, shost, "I/O port address "
9116 "modified\n");
9117 break;
9118 case ASC_WARN_AUTO_CONFIG:
9119 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9120 "enabled\n");
9121 break;
9122 case ASC_WARN_EEPROM_CHKSUM:
9123 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9124 break;
9125 case ASC_WARN_IRQ_MODIFIED:
9126 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9127 break;
9128 case ASC_WARN_CMD_QNG_CONFLICT:
9129 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
9130 "disconnects\n");
9131 break;
9132 default:
9133 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9134 warn_code);
9135 break;
9136 }
9137
9138 if (asc_dvc->err_code != 0)
9139 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9140 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9141
9142 return asc_dvc->err_code;
9143 }
9144
9145 static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
9146 {
9147 struct asc_board *board = shost_priv(shost);
9148 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9149 PortAddr iop_base = asc_dvc->iop_base;
9150 unsigned short cfg_msw;
9151 unsigned short warn_code = 0;
9152
9153 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
9154 if (asc_dvc->err_code != 0)
9155 return asc_dvc->err_code;
9156 if (!AscFindSignature(asc_dvc->iop_base)) {
9157 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9158 return asc_dvc->err_code;
9159 }
9160
9161 cfg_msw = AscGetChipCfgMsw(iop_base);
9162 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9163 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9164 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9165 AscSetChipCfgMsw(iop_base, cfg_msw);
9166 }
9167 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
9168 asc_dvc->cfg->cmd_qng_enabled) {
9169 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
9170 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9171 }
9172 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9173 warn_code |= ASC_WARN_AUTO_CONFIG;
9174 }
9175 #ifdef CONFIG_PCI
9176 if (asc_dvc->bus_type & ASC_IS_PCI) {
9177 cfg_msw &= 0xFFC0;
9178 AscSetChipCfgMsw(iop_base, cfg_msw);
9179 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
9180 } else {
9181 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
9182 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
9183 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
9184 asc_dvc->bug_fix_cntl |=
9185 ASC_BUG_FIX_ASYN_USE_SYN;
9186 }
9187 }
9188 } else
9189 #endif /* CONFIG_PCI */
9190 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
9191 asc_dvc->cfg->chip_scsi_id) {
9192 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
9193 }
9194
9195 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
9196
9197 switch (warn_code) {
9198 case 0: /* No error. */
9199 break;
9200 case ASC_WARN_IO_PORT_ROTATE:
9201 shost_printk(KERN_WARNING, shost, "I/O port address "
9202 "modified\n");
9203 break;
9204 case ASC_WARN_AUTO_CONFIG:
9205 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9206 "enabled\n");
9207 break;
9208 case ASC_WARN_EEPROM_CHKSUM:
9209 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9210 break;
9211 case ASC_WARN_IRQ_MODIFIED:
9212 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9213 break;
9214 case ASC_WARN_CMD_QNG_CONFLICT:
9215 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
9216 "disconnects\n");
9217 break;
9218 default:
9219 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9220 warn_code);
9221 break;
9222 }
9223
9224 if (asc_dvc->err_code != 0)
9225 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9226 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9227
9228 return asc_dvc->err_code;
9229 }
9230
9231 /*
9232 * EEPROM Configuration.
9233 *
9234 * All drivers should use this structure to set the default EEPROM
9235 * configuration. The BIOS now uses this structure when it is built.
9236 * Additional structure information can be found in a_condor.h where
9237 * the structure is defined.
9238 *
9239 * The *_Field_IsChar structs are needed to correct for endianness.
9240 * These values are read from the board 16 bits at a time directly
9241 * into the structs. Because some fields are char, the values will be
9242 * in the wrong order. The *_Field_IsChar tells when to flip the
9243 * bytes. Data read and written to PCI memory is automatically swapped
9244 * on big-endian platforms so char fields read as words are actually being
9245 * unswapped on big-endian platforms.
9246 */
9247 #ifdef CONFIG_PCI
9248 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = {
9249 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
9250 0x0000, /* cfg_msw */
9251 0xFFFF, /* disc_enable */
9252 0xFFFF, /* wdtr_able */
9253 0xFFFF, /* sdtr_able */
9254 0xFFFF, /* start_motor */
9255 0xFFFF, /* tagqng_able */
9256 0xFFFF, /* bios_scan */
9257 0, /* scam_tolerant */
9258 7, /* adapter_scsi_id */
9259 0, /* bios_boot_delay */
9260 3, /* scsi_reset_delay */
9261 0, /* bios_id_lun */
9262 0, /* termination */
9263 0, /* reserved1 */
9264 0xFFE7, /* bios_ctrl */
9265 0xFFFF, /* ultra_able */
9266 0, /* reserved2 */
9267 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
9268 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9269 0, /* dvc_cntl */
9270 0, /* bug_fix */
9271 0, /* serial_number_word1 */
9272 0, /* serial_number_word2 */
9273 0, /* serial_number_word3 */
9274 0, /* check_sum */
9275 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9276 , /* oem_name[16] */
9277 0, /* dvc_err_code */
9278 0, /* adv_err_code */
9279 0, /* adv_err_addr */
9280 0, /* saved_dvc_err_code */
9281 0, /* saved_adv_err_code */
9282 0, /* saved_adv_err_addr */
9283 0 /* num_of_err */
9284 };
9285
9286 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = {
9287 0, /* cfg_lsw */
9288 0, /* cfg_msw */
9289 0, /* -disc_enable */
9290 0, /* wdtr_able */
9291 0, /* sdtr_able */
9292 0, /* start_motor */
9293 0, /* tagqng_able */
9294 0, /* bios_scan */
9295 0, /* scam_tolerant */
9296 1, /* adapter_scsi_id */
9297 1, /* bios_boot_delay */
9298 1, /* scsi_reset_delay */
9299 1, /* bios_id_lun */
9300 1, /* termination */
9301 1, /* reserved1 */
9302 0, /* bios_ctrl */
9303 0, /* ultra_able */
9304 0, /* reserved2 */
9305 1, /* max_host_qng */
9306 1, /* max_dvc_qng */
9307 0, /* dvc_cntl */
9308 0, /* bug_fix */
9309 0, /* serial_number_word1 */
9310 0, /* serial_number_word2 */
9311 0, /* serial_number_word3 */
9312 0, /* check_sum */
9313 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9314 , /* oem_name[16] */
9315 0, /* dvc_err_code */
9316 0, /* adv_err_code */
9317 0, /* adv_err_addr */
9318 0, /* saved_dvc_err_code */
9319 0, /* saved_adv_err_code */
9320 0, /* saved_adv_err_addr */
9321 0 /* num_of_err */
9322 };
9323
9324 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = {
9325 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9326 0x0000, /* 01 cfg_msw */
9327 0xFFFF, /* 02 disc_enable */
9328 0xFFFF, /* 03 wdtr_able */
9329 0x4444, /* 04 sdtr_speed1 */
9330 0xFFFF, /* 05 start_motor */
9331 0xFFFF, /* 06 tagqng_able */
9332 0xFFFF, /* 07 bios_scan */
9333 0, /* 08 scam_tolerant */
9334 7, /* 09 adapter_scsi_id */
9335 0, /* bios_boot_delay */
9336 3, /* 10 scsi_reset_delay */
9337 0, /* bios_id_lun */
9338 0, /* 11 termination_se */
9339 0, /* termination_lvd */
9340 0xFFE7, /* 12 bios_ctrl */
9341 0x4444, /* 13 sdtr_speed2 */
9342 0x4444, /* 14 sdtr_speed3 */
9343 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9344 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9345 0, /* 16 dvc_cntl */
9346 0x4444, /* 17 sdtr_speed4 */
9347 0, /* 18 serial_number_word1 */
9348 0, /* 19 serial_number_word2 */
9349 0, /* 20 serial_number_word3 */
9350 0, /* 21 check_sum */
9351 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9352 , /* 22-29 oem_name[16] */
9353 0, /* 30 dvc_err_code */
9354 0, /* 31 adv_err_code */
9355 0, /* 32 adv_err_addr */
9356 0, /* 33 saved_dvc_err_code */
9357 0, /* 34 saved_adv_err_code */
9358 0, /* 35 saved_adv_err_addr */
9359 0, /* 36 reserved */
9360 0, /* 37 reserved */
9361 0, /* 38 reserved */
9362 0, /* 39 reserved */
9363 0, /* 40 reserved */
9364 0, /* 41 reserved */
9365 0, /* 42 reserved */
9366 0, /* 43 reserved */
9367 0, /* 44 reserved */
9368 0, /* 45 reserved */
9369 0, /* 46 reserved */
9370 0, /* 47 reserved */
9371 0, /* 48 reserved */
9372 0, /* 49 reserved */
9373 0, /* 50 reserved */
9374 0, /* 51 reserved */
9375 0, /* 52 reserved */
9376 0, /* 53 reserved */
9377 0, /* 54 reserved */
9378 0, /* 55 reserved */
9379 0, /* 56 cisptr_lsw */
9380 0, /* 57 cisprt_msw */
9381 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9382 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
9383 0, /* 60 reserved */
9384 0, /* 61 reserved */
9385 0, /* 62 reserved */
9386 0 /* 63 reserved */
9387 };
9388
9389 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = {
9390 0, /* 00 cfg_lsw */
9391 0, /* 01 cfg_msw */
9392 0, /* 02 disc_enable */
9393 0, /* 03 wdtr_able */
9394 0, /* 04 sdtr_speed1 */
9395 0, /* 05 start_motor */
9396 0, /* 06 tagqng_able */
9397 0, /* 07 bios_scan */
9398 0, /* 08 scam_tolerant */
9399 1, /* 09 adapter_scsi_id */
9400 1, /* bios_boot_delay */
9401 1, /* 10 scsi_reset_delay */
9402 1, /* bios_id_lun */
9403 1, /* 11 termination_se */
9404 1, /* termination_lvd */
9405 0, /* 12 bios_ctrl */
9406 0, /* 13 sdtr_speed2 */
9407 0, /* 14 sdtr_speed3 */
9408 1, /* 15 max_host_qng */
9409 1, /* max_dvc_qng */
9410 0, /* 16 dvc_cntl */
9411 0, /* 17 sdtr_speed4 */
9412 0, /* 18 serial_number_word1 */
9413 0, /* 19 serial_number_word2 */
9414 0, /* 20 serial_number_word3 */
9415 0, /* 21 check_sum */
9416 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9417 , /* 22-29 oem_name[16] */
9418 0, /* 30 dvc_err_code */
9419 0, /* 31 adv_err_code */
9420 0, /* 32 adv_err_addr */
9421 0, /* 33 saved_dvc_err_code */
9422 0, /* 34 saved_adv_err_code */
9423 0, /* 35 saved_adv_err_addr */
9424 0, /* 36 reserved */
9425 0, /* 37 reserved */
9426 0, /* 38 reserved */
9427 0, /* 39 reserved */
9428 0, /* 40 reserved */
9429 0, /* 41 reserved */
9430 0, /* 42 reserved */
9431 0, /* 43 reserved */
9432 0, /* 44 reserved */
9433 0, /* 45 reserved */
9434 0, /* 46 reserved */
9435 0, /* 47 reserved */
9436 0, /* 48 reserved */
9437 0, /* 49 reserved */
9438 0, /* 50 reserved */
9439 0, /* 51 reserved */
9440 0, /* 52 reserved */
9441 0, /* 53 reserved */
9442 0, /* 54 reserved */
9443 0, /* 55 reserved */
9444 0, /* 56 cisptr_lsw */
9445 0, /* 57 cisprt_msw */
9446 0, /* 58 subsysvid */
9447 0, /* 59 subsysid */
9448 0, /* 60 reserved */
9449 0, /* 61 reserved */
9450 0, /* 62 reserved */
9451 0 /* 63 reserved */
9452 };
9453
9454 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = {
9455 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9456 0x0000, /* 01 cfg_msw */
9457 0xFFFF, /* 02 disc_enable */
9458 0xFFFF, /* 03 wdtr_able */
9459 0x5555, /* 04 sdtr_speed1 */
9460 0xFFFF, /* 05 start_motor */
9461 0xFFFF, /* 06 tagqng_able */
9462 0xFFFF, /* 07 bios_scan */
9463 0, /* 08 scam_tolerant */
9464 7, /* 09 adapter_scsi_id */
9465 0, /* bios_boot_delay */
9466 3, /* 10 scsi_reset_delay */
9467 0, /* bios_id_lun */
9468 0, /* 11 termination_se */
9469 0, /* termination_lvd */
9470 0xFFE7, /* 12 bios_ctrl */
9471 0x5555, /* 13 sdtr_speed2 */
9472 0x5555, /* 14 sdtr_speed3 */
9473 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9474 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9475 0, /* 16 dvc_cntl */
9476 0x5555, /* 17 sdtr_speed4 */
9477 0, /* 18 serial_number_word1 */
9478 0, /* 19 serial_number_word2 */
9479 0, /* 20 serial_number_word3 */
9480 0, /* 21 check_sum */
9481 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9482 , /* 22-29 oem_name[16] */
9483 0, /* 30 dvc_err_code */
9484 0, /* 31 adv_err_code */
9485 0, /* 32 adv_err_addr */
9486 0, /* 33 saved_dvc_err_code */
9487 0, /* 34 saved_adv_err_code */
9488 0, /* 35 saved_adv_err_addr */
9489 0, /* 36 reserved */
9490 0, /* 37 reserved */
9491 0, /* 38 reserved */
9492 0, /* 39 reserved */
9493 0, /* 40 reserved */
9494 0, /* 41 reserved */
9495 0, /* 42 reserved */
9496 0, /* 43 reserved */
9497 0, /* 44 reserved */
9498 0, /* 45 reserved */
9499 0, /* 46 reserved */
9500 0, /* 47 reserved */
9501 0, /* 48 reserved */
9502 0, /* 49 reserved */
9503 0, /* 50 reserved */
9504 0, /* 51 reserved */
9505 0, /* 52 reserved */
9506 0, /* 53 reserved */
9507 0, /* 54 reserved */
9508 0, /* 55 reserved */
9509 0, /* 56 cisptr_lsw */
9510 0, /* 57 cisprt_msw */
9511 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9512 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
9513 0, /* 60 reserved */
9514 0, /* 61 reserved */
9515 0, /* 62 reserved */
9516 0 /* 63 reserved */
9517 };
9518
9519 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = {
9520 0, /* 00 cfg_lsw */
9521 0, /* 01 cfg_msw */
9522 0, /* 02 disc_enable */
9523 0, /* 03 wdtr_able */
9524 0, /* 04 sdtr_speed1 */
9525 0, /* 05 start_motor */
9526 0, /* 06 tagqng_able */
9527 0, /* 07 bios_scan */
9528 0, /* 08 scam_tolerant */
9529 1, /* 09 adapter_scsi_id */
9530 1, /* bios_boot_delay */
9531 1, /* 10 scsi_reset_delay */
9532 1, /* bios_id_lun */
9533 1, /* 11 termination_se */
9534 1, /* termination_lvd */
9535 0, /* 12 bios_ctrl */
9536 0, /* 13 sdtr_speed2 */
9537 0, /* 14 sdtr_speed3 */
9538 1, /* 15 max_host_qng */
9539 1, /* max_dvc_qng */
9540 0, /* 16 dvc_cntl */
9541 0, /* 17 sdtr_speed4 */
9542 0, /* 18 serial_number_word1 */
9543 0, /* 19 serial_number_word2 */
9544 0, /* 20 serial_number_word3 */
9545 0, /* 21 check_sum */
9546 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9547 , /* 22-29 oem_name[16] */
9548 0, /* 30 dvc_err_code */
9549 0, /* 31 adv_err_code */
9550 0, /* 32 adv_err_addr */
9551 0, /* 33 saved_dvc_err_code */
9552 0, /* 34 saved_adv_err_code */
9553 0, /* 35 saved_adv_err_addr */
9554 0, /* 36 reserved */
9555 0, /* 37 reserved */
9556 0, /* 38 reserved */
9557 0, /* 39 reserved */
9558 0, /* 40 reserved */
9559 0, /* 41 reserved */
9560 0, /* 42 reserved */
9561 0, /* 43 reserved */
9562 0, /* 44 reserved */
9563 0, /* 45 reserved */
9564 0, /* 46 reserved */
9565 0, /* 47 reserved */
9566 0, /* 48 reserved */
9567 0, /* 49 reserved */
9568 0, /* 50 reserved */
9569 0, /* 51 reserved */
9570 0, /* 52 reserved */
9571 0, /* 53 reserved */
9572 0, /* 54 reserved */
9573 0, /* 55 reserved */
9574 0, /* 56 cisptr_lsw */
9575 0, /* 57 cisprt_msw */
9576 0, /* 58 subsysvid */
9577 0, /* 59 subsysid */
9578 0, /* 60 reserved */
9579 0, /* 61 reserved */
9580 0, /* 62 reserved */
9581 0 /* 63 reserved */
9582 };
9583
9584 /*
9585 * Wait for EEPROM command to complete
9586 */
9587 static void AdvWaitEEPCmd(AdvPortAddr iop_base)
9588 {
9589 int eep_delay_ms;
9590
9591 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
9592 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
9593 ASC_EEP_CMD_DONE) {
9594 break;
9595 }
9596 mdelay(1);
9597 }
9598 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
9599 0)
9600 BUG();
9601 }
9602
9603 /*
9604 * Read the EEPROM from specified location
9605 */
9606 static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
9607 {
9608 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9609 ASC_EEP_CMD_READ | eep_word_addr);
9610 AdvWaitEEPCmd(iop_base);
9611 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
9612 }
9613
9614 /*
9615 * Write the EEPROM from 'cfg_buf'.
9616 */
9617 static void AdvSet3550EEPConfig(AdvPortAddr iop_base,
9618 ADVEEP_3550_CONFIG *cfg_buf)
9619 {
9620 ushort *wbuf;
9621 ushort addr, chksum;
9622 ushort *charfields;
9623
9624 wbuf = (ushort *)cfg_buf;
9625 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
9626 chksum = 0;
9627
9628 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
9629 AdvWaitEEPCmd(iop_base);
9630
9631 /*
9632 * Write EEPROM from word 0 to word 20.
9633 */
9634 for (addr = ADV_EEP_DVC_CFG_BEGIN;
9635 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
9636 ushort word;
9637
9638 if (*charfields++) {
9639 word = cpu_to_le16(*wbuf);
9640 } else {
9641 word = *wbuf;
9642 }
9643 chksum += *wbuf; /* Checksum is calculated from word values. */
9644 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9645 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9646 ASC_EEP_CMD_WRITE | addr);
9647 AdvWaitEEPCmd(iop_base);
9648 mdelay(ADV_EEP_DELAY_MS);
9649 }
9650
9651 /*
9652 * Write EEPROM checksum at word 21.
9653 */
9654 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
9655 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
9656 AdvWaitEEPCmd(iop_base);
9657 wbuf++;
9658 charfields++;
9659
9660 /*
9661 * Write EEPROM OEM name at words 22 to 29.
9662 */
9663 for (addr = ADV_EEP_DVC_CTL_BEGIN;
9664 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
9665 ushort word;
9666
9667 if (*charfields++) {
9668 word = cpu_to_le16(*wbuf);
9669 } else {
9670 word = *wbuf;
9671 }
9672 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9673 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9674 ASC_EEP_CMD_WRITE | addr);
9675 AdvWaitEEPCmd(iop_base);
9676 }
9677 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
9678 AdvWaitEEPCmd(iop_base);
9679 }
9680
9681 /*
9682 * Write the EEPROM from 'cfg_buf'.
9683 */
9684 static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
9685 ADVEEP_38C0800_CONFIG *cfg_buf)
9686 {
9687 ushort *wbuf;
9688 ushort *charfields;
9689 ushort addr, chksum;
9690
9691 wbuf = (ushort *)cfg_buf;
9692 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
9693 chksum = 0;
9694
9695 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
9696 AdvWaitEEPCmd(iop_base);
9697
9698 /*
9699 * Write EEPROM from word 0 to word 20.
9700 */
9701 for (addr = ADV_EEP_DVC_CFG_BEGIN;
9702 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
9703 ushort word;
9704
9705 if (*charfields++) {
9706 word = cpu_to_le16(*wbuf);
9707 } else {
9708 word = *wbuf;
9709 }
9710 chksum += *wbuf; /* Checksum is calculated from word values. */
9711 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9712 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9713 ASC_EEP_CMD_WRITE | addr);
9714 AdvWaitEEPCmd(iop_base);
9715 mdelay(ADV_EEP_DELAY_MS);
9716 }
9717
9718 /*
9719 * Write EEPROM checksum at word 21.
9720 */
9721 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
9722 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
9723 AdvWaitEEPCmd(iop_base);
9724 wbuf++;
9725 charfields++;
9726
9727 /*
9728 * Write EEPROM OEM name at words 22 to 29.
9729 */
9730 for (addr = ADV_EEP_DVC_CTL_BEGIN;
9731 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
9732 ushort word;
9733
9734 if (*charfields++) {
9735 word = cpu_to_le16(*wbuf);
9736 } else {
9737 word = *wbuf;
9738 }
9739 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9740 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9741 ASC_EEP_CMD_WRITE | addr);
9742 AdvWaitEEPCmd(iop_base);
9743 }
9744 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
9745 AdvWaitEEPCmd(iop_base);
9746 }
9747
9748 /*
9749 * Write the EEPROM from 'cfg_buf'.
9750 */
9751 static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
9752 ADVEEP_38C1600_CONFIG *cfg_buf)
9753 {
9754 ushort *wbuf;
9755 ushort *charfields;
9756 ushort addr, chksum;
9757
9758 wbuf = (ushort *)cfg_buf;
9759 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
9760 chksum = 0;
9761
9762 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
9763 AdvWaitEEPCmd(iop_base);
9764
9765 /*
9766 * Write EEPROM from word 0 to word 20.
9767 */
9768 for (addr = ADV_EEP_DVC_CFG_BEGIN;
9769 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
9770 ushort word;
9771
9772 if (*charfields++) {
9773 word = cpu_to_le16(*wbuf);
9774 } else {
9775 word = *wbuf;
9776 }
9777 chksum += *wbuf; /* Checksum is calculated from word values. */
9778 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9779 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9780 ASC_EEP_CMD_WRITE | addr);
9781 AdvWaitEEPCmd(iop_base);
9782 mdelay(ADV_EEP_DELAY_MS);
9783 }
9784
9785 /*
9786 * Write EEPROM checksum at word 21.
9787 */
9788 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
9789 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
9790 AdvWaitEEPCmd(iop_base);
9791 wbuf++;
9792 charfields++;
9793
9794 /*
9795 * Write EEPROM OEM name at words 22 to 29.
9796 */
9797 for (addr = ADV_EEP_DVC_CTL_BEGIN;
9798 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
9799 ushort word;
9800
9801 if (*charfields++) {
9802 word = cpu_to_le16(*wbuf);
9803 } else {
9804 word = *wbuf;
9805 }
9806 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9807 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9808 ASC_EEP_CMD_WRITE | addr);
9809 AdvWaitEEPCmd(iop_base);
9810 }
9811 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
9812 AdvWaitEEPCmd(iop_base);
9813 }
9814
9815 /*
9816 * Read EEPROM configuration into the specified buffer.
9817 *
9818 * Return a checksum based on the EEPROM configuration read.
9819 */
9820 static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base,
9821 ADVEEP_3550_CONFIG *cfg_buf)
9822 {
9823 ushort wval, chksum;
9824 ushort *wbuf;
9825 int eep_addr;
9826 ushort *charfields;
9827
9828 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
9829 wbuf = (ushort *)cfg_buf;
9830 chksum = 0;
9831
9832 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
9833 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
9834 wval = AdvReadEEPWord(iop_base, eep_addr);
9835 chksum += wval; /* Checksum is calculated from word values. */
9836 if (*charfields++) {
9837 *wbuf = le16_to_cpu(wval);
9838 } else {
9839 *wbuf = wval;
9840 }
9841 }
9842 /* Read checksum word. */
9843 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
9844 wbuf++;
9845 charfields++;
9846
9847 /* Read rest of EEPROM not covered by the checksum. */
9848 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
9849 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
9850 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
9851 if (*charfields++) {
9852 *wbuf = le16_to_cpu(*wbuf);
9853 }
9854 }
9855 return chksum;
9856 }
9857
9858 /*
9859 * Read EEPROM configuration into the specified buffer.
9860 *
9861 * Return a checksum based on the EEPROM configuration read.
9862 */
9863 static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
9864 ADVEEP_38C0800_CONFIG *cfg_buf)
9865 {
9866 ushort wval, chksum;
9867 ushort *wbuf;
9868 int eep_addr;
9869 ushort *charfields;
9870
9871 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
9872 wbuf = (ushort *)cfg_buf;
9873 chksum = 0;
9874
9875 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
9876 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
9877 wval = AdvReadEEPWord(iop_base, eep_addr);
9878 chksum += wval; /* Checksum is calculated from word values. */
9879 if (*charfields++) {
9880 *wbuf = le16_to_cpu(wval);
9881 } else {
9882 *wbuf = wval;
9883 }
9884 }
9885 /* Read checksum word. */
9886 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
9887 wbuf++;
9888 charfields++;
9889
9890 /* Read rest of EEPROM not covered by the checksum. */
9891 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
9892 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
9893 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
9894 if (*charfields++) {
9895 *wbuf = le16_to_cpu(*wbuf);
9896 }
9897 }
9898 return chksum;
9899 }
9900
9901 /*
9902 * Read EEPROM configuration into the specified buffer.
9903 *
9904 * Return a checksum based on the EEPROM configuration read.
9905 */
9906 static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
9907 ADVEEP_38C1600_CONFIG *cfg_buf)
9908 {
9909 ushort wval, chksum;
9910 ushort *wbuf;
9911 int eep_addr;
9912 ushort *charfields;
9913
9914 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
9915 wbuf = (ushort *)cfg_buf;
9916 chksum = 0;
9917
9918 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
9919 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
9920 wval = AdvReadEEPWord(iop_base, eep_addr);
9921 chksum += wval; /* Checksum is calculated from word values. */
9922 if (*charfields++) {
9923 *wbuf = le16_to_cpu(wval);
9924 } else {
9925 *wbuf = wval;
9926 }
9927 }
9928 /* Read checksum word. */
9929 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
9930 wbuf++;
9931 charfields++;
9932
9933 /* Read rest of EEPROM not covered by the checksum. */
9934 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
9935 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
9936 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
9937 if (*charfields++) {
9938 *wbuf = le16_to_cpu(*wbuf);
9939 }
9940 }
9941 return chksum;
9942 }
9943
9944 /*
9945 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
9946 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
9947 * all of this is done.
9948 *
9949 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
9950 *
9951 * For a non-fatal error return a warning code. If there are no warnings
9952 * then 0 is returned.
9953 *
9954 * Note: Chip is stopped on entry.
9955 */
9956 static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
9957 {
9958 AdvPortAddr iop_base;
9959 ushort warn_code;
9960 ADVEEP_3550_CONFIG eep_config;
9961
9962 iop_base = asc_dvc->iop_base;
9963
9964 warn_code = 0;
9965
9966 /*
9967 * Read the board's EEPROM configuration.
9968 *
9969 * Set default values if a bad checksum is found.
9970 */
9971 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
9972 warn_code |= ASC_WARN_EEPROM_CHKSUM;
9973
9974 /*
9975 * Set EEPROM default values.
9976 */
9977 memcpy(&eep_config, &Default_3550_EEPROM_Config,
9978 sizeof(ADVEEP_3550_CONFIG));
9979
9980 /*
9981 * Assume the 6 byte board serial number that was read from
9982 * EEPROM is correct even if the EEPROM checksum failed.
9983 */
9984 eep_config.serial_number_word3 =
9985 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
9986
9987 eep_config.serial_number_word2 =
9988 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
9989
9990 eep_config.serial_number_word1 =
9991 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
9992
9993 AdvSet3550EEPConfig(iop_base, &eep_config);
9994 }
9995 /*
9996 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
9997 * EEPROM configuration that was read.
9998 *
9999 * This is the mapping of EEPROM fields to Adv Library fields.
10000 */
10001 asc_dvc->wdtr_able = eep_config.wdtr_able;
10002 asc_dvc->sdtr_able = eep_config.sdtr_able;
10003 asc_dvc->ultra_able = eep_config.ultra_able;
10004 asc_dvc->tagqng_able = eep_config.tagqng_able;
10005 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10006 asc_dvc->max_host_qng = eep_config.max_host_qng;
10007 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10008 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10009 asc_dvc->start_motor = eep_config.start_motor;
10010 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10011 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10012 asc_dvc->no_scam = eep_config.scam_tolerant;
10013 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10014 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10015 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10016
10017 /*
10018 * Set the host maximum queuing (max. 253, min. 16) and the per device
10019 * maximum queuing (max. 63, min. 4).
10020 */
10021 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10022 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10023 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10024 /* If the value is zero, assume it is uninitialized. */
10025 if (eep_config.max_host_qng == 0) {
10026 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10027 } else {
10028 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10029 }
10030 }
10031
10032 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10033 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10034 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10035 /* If the value is zero, assume it is uninitialized. */
10036 if (eep_config.max_dvc_qng == 0) {
10037 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10038 } else {
10039 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10040 }
10041 }
10042
10043 /*
10044 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10045 * set 'max_dvc_qng' to 'max_host_qng'.
10046 */
10047 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10048 eep_config.max_dvc_qng = eep_config.max_host_qng;
10049 }
10050
10051 /*
10052 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10053 * values based on possibly adjusted EEPROM values.
10054 */
10055 asc_dvc->max_host_qng = eep_config.max_host_qng;
10056 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10057
10058 /*
10059 * If the EEPROM 'termination' field is set to automatic (0), then set
10060 * the ADV_DVC_CFG 'termination' field to automatic also.
10061 *
10062 * If the termination is specified with a non-zero 'termination'
10063 * value check that a legal value is set and set the ADV_DVC_CFG
10064 * 'termination' field appropriately.
10065 */
10066 if (eep_config.termination == 0) {
10067 asc_dvc->cfg->termination = 0; /* auto termination */
10068 } else {
10069 /* Enable manual control with low off / high off. */
10070 if (eep_config.termination == 1) {
10071 asc_dvc->cfg->termination = TERM_CTL_SEL;
10072
10073 /* Enable manual control with low off / high on. */
10074 } else if (eep_config.termination == 2) {
10075 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
10076
10077 /* Enable manual control with low on / high on. */
10078 } else if (eep_config.termination == 3) {
10079 asc_dvc->cfg->termination =
10080 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
10081 } else {
10082 /*
10083 * The EEPROM 'termination' field contains a bad value. Use
10084 * automatic termination instead.
10085 */
10086 asc_dvc->cfg->termination = 0;
10087 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10088 }
10089 }
10090
10091 return warn_code;
10092 }
10093
10094 /*
10095 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10096 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10097 * all of this is done.
10098 *
10099 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10100 *
10101 * For a non-fatal error return a warning code. If there are no warnings
10102 * then 0 is returned.
10103 *
10104 * Note: Chip is stopped on entry.
10105 */
10106 static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
10107 {
10108 AdvPortAddr iop_base;
10109 ushort warn_code;
10110 ADVEEP_38C0800_CONFIG eep_config;
10111 uchar tid, termination;
10112 ushort sdtr_speed = 0;
10113
10114 iop_base = asc_dvc->iop_base;
10115
10116 warn_code = 0;
10117
10118 /*
10119 * Read the board's EEPROM configuration.
10120 *
10121 * Set default values if a bad checksum is found.
10122 */
10123 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
10124 eep_config.check_sum) {
10125 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10126
10127 /*
10128 * Set EEPROM default values.
10129 */
10130 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
10131 sizeof(ADVEEP_38C0800_CONFIG));
10132
10133 /*
10134 * Assume the 6 byte board serial number that was read from
10135 * EEPROM is correct even if the EEPROM checksum failed.
10136 */
10137 eep_config.serial_number_word3 =
10138 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10139
10140 eep_config.serial_number_word2 =
10141 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10142
10143 eep_config.serial_number_word1 =
10144 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10145
10146 AdvSet38C0800EEPConfig(iop_base, &eep_config);
10147 }
10148 /*
10149 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
10150 * EEPROM configuration that was read.
10151 *
10152 * This is the mapping of EEPROM fields to Adv Library fields.
10153 */
10154 asc_dvc->wdtr_able = eep_config.wdtr_able;
10155 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10156 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10157 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10158 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10159 asc_dvc->tagqng_able = eep_config.tagqng_able;
10160 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10161 asc_dvc->max_host_qng = eep_config.max_host_qng;
10162 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10163 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10164 asc_dvc->start_motor = eep_config.start_motor;
10165 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10166 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10167 asc_dvc->no_scam = eep_config.scam_tolerant;
10168 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10169 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10170 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10171
10172 /*
10173 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10174 * are set, then set an 'sdtr_able' bit for it.
10175 */
10176 asc_dvc->sdtr_able = 0;
10177 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
10178 if (tid == 0) {
10179 sdtr_speed = asc_dvc->sdtr_speed1;
10180 } else if (tid == 4) {
10181 sdtr_speed = asc_dvc->sdtr_speed2;
10182 } else if (tid == 8) {
10183 sdtr_speed = asc_dvc->sdtr_speed3;
10184 } else if (tid == 12) {
10185 sdtr_speed = asc_dvc->sdtr_speed4;
10186 }
10187 if (sdtr_speed & ADV_MAX_TID) {
10188 asc_dvc->sdtr_able |= (1 << tid);
10189 }
10190 sdtr_speed >>= 4;
10191 }
10192
10193 /*
10194 * Set the host maximum queuing (max. 253, min. 16) and the per device
10195 * maximum queuing (max. 63, min. 4).
10196 */
10197 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10198 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10199 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10200 /* If the value is zero, assume it is uninitialized. */
10201 if (eep_config.max_host_qng == 0) {
10202 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10203 } else {
10204 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10205 }
10206 }
10207
10208 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10209 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10210 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10211 /* If the value is zero, assume it is uninitialized. */
10212 if (eep_config.max_dvc_qng == 0) {
10213 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10214 } else {
10215 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10216 }
10217 }
10218
10219 /*
10220 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10221 * set 'max_dvc_qng' to 'max_host_qng'.
10222 */
10223 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10224 eep_config.max_dvc_qng = eep_config.max_host_qng;
10225 }
10226
10227 /*
10228 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10229 * values based on possibly adjusted EEPROM values.
10230 */
10231 asc_dvc->max_host_qng = eep_config.max_host_qng;
10232 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10233
10234 /*
10235 * If the EEPROM 'termination' field is set to automatic (0), then set
10236 * the ADV_DVC_CFG 'termination' field to automatic also.
10237 *
10238 * If the termination is specified with a non-zero 'termination'
10239 * value check that a legal value is set and set the ADV_DVC_CFG
10240 * 'termination' field appropriately.
10241 */
10242 if (eep_config.termination_se == 0) {
10243 termination = 0; /* auto termination for SE */
10244 } else {
10245 /* Enable manual control with low off / high off. */
10246 if (eep_config.termination_se == 1) {
10247 termination = 0;
10248
10249 /* Enable manual control with low off / high on. */
10250 } else if (eep_config.termination_se == 2) {
10251 termination = TERM_SE_HI;
10252
10253 /* Enable manual control with low on / high on. */
10254 } else if (eep_config.termination_se == 3) {
10255 termination = TERM_SE;
10256 } else {
10257 /*
10258 * The EEPROM 'termination_se' field contains a bad value.
10259 * Use automatic termination instead.
10260 */
10261 termination = 0;
10262 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10263 }
10264 }
10265
10266 if (eep_config.termination_lvd == 0) {
10267 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10268 } else {
10269 /* Enable manual control with low off / high off. */
10270 if (eep_config.termination_lvd == 1) {
10271 asc_dvc->cfg->termination = termination;
10272
10273 /* Enable manual control with low off / high on. */
10274 } else if (eep_config.termination_lvd == 2) {
10275 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10276
10277 /* Enable manual control with low on / high on. */
10278 } else if (eep_config.termination_lvd == 3) {
10279 asc_dvc->cfg->termination = termination | TERM_LVD;
10280 } else {
10281 /*
10282 * The EEPROM 'termination_lvd' field contains a bad value.
10283 * Use automatic termination instead.
10284 */
10285 asc_dvc->cfg->termination = termination;
10286 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10287 }
10288 }
10289
10290 return warn_code;
10291 }
10292
10293 /*
10294 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
10295 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
10296 * all of this is done.
10297 *
10298 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
10299 *
10300 * For a non-fatal error return a warning code. If there are no warnings
10301 * then 0 is returned.
10302 *
10303 * Note: Chip is stopped on entry.
10304 */
10305 static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
10306 {
10307 AdvPortAddr iop_base;
10308 ushort warn_code;
10309 ADVEEP_38C1600_CONFIG eep_config;
10310 uchar tid, termination;
10311 ushort sdtr_speed = 0;
10312
10313 iop_base = asc_dvc->iop_base;
10314
10315 warn_code = 0;
10316
10317 /*
10318 * Read the board's EEPROM configuration.
10319 *
10320 * Set default values if a bad checksum is found.
10321 */
10322 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
10323 eep_config.check_sum) {
10324 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
10325 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10326
10327 /*
10328 * Set EEPROM default values.
10329 */
10330 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
10331 sizeof(ADVEEP_38C1600_CONFIG));
10332
10333 if (PCI_FUNC(pdev->devfn) != 0) {
10334 u8 ints;
10335 /*
10336 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
10337 * and old Mac system booting problem. The Expansion
10338 * ROM must be disabled in Function 1 for these systems
10339 */
10340 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
10341 /*
10342 * Clear the INTAB (bit 11) if the GPIO 0 input
10343 * indicates the Function 1 interrupt line is wired
10344 * to INTB.
10345 *
10346 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
10347 * 1 - Function 1 interrupt line wired to INT A.
10348 * 0 - Function 1 interrupt line wired to INT B.
10349 *
10350 * Note: Function 0 is always wired to INTA.
10351 * Put all 5 GPIO bits in input mode and then read
10352 * their input values.
10353 */
10354 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
10355 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
10356 if ((ints & 0x01) == 0)
10357 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
10358 }
10359
10360 /*
10361 * Assume the 6 byte board serial number that was read from
10362 * EEPROM is correct even if the EEPROM checksum failed.
10363 */
10364 eep_config.serial_number_word3 =
10365 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10366 eep_config.serial_number_word2 =
10367 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10368 eep_config.serial_number_word1 =
10369 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10370
10371 AdvSet38C1600EEPConfig(iop_base, &eep_config);
10372 }
10373
10374 /*
10375 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10376 * EEPROM configuration that was read.
10377 *
10378 * This is the mapping of EEPROM fields to Adv Library fields.
10379 */
10380 asc_dvc->wdtr_able = eep_config.wdtr_able;
10381 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10382 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10383 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10384 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10385 asc_dvc->ppr_able = 0;
10386 asc_dvc->tagqng_able = eep_config.tagqng_able;
10387 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10388 asc_dvc->max_host_qng = eep_config.max_host_qng;
10389 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10390 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
10391 asc_dvc->start_motor = eep_config.start_motor;
10392 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10393 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10394 asc_dvc->no_scam = eep_config.scam_tolerant;
10395
10396 /*
10397 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10398 * are set, then set an 'sdtr_able' bit for it.
10399 */
10400 asc_dvc->sdtr_able = 0;
10401 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
10402 if (tid == 0) {
10403 sdtr_speed = asc_dvc->sdtr_speed1;
10404 } else if (tid == 4) {
10405 sdtr_speed = asc_dvc->sdtr_speed2;
10406 } else if (tid == 8) {
10407 sdtr_speed = asc_dvc->sdtr_speed3;
10408 } else if (tid == 12) {
10409 sdtr_speed = asc_dvc->sdtr_speed4;
10410 }
10411 if (sdtr_speed & ASC_MAX_TID) {
10412 asc_dvc->sdtr_able |= (1 << tid);
10413 }
10414 sdtr_speed >>= 4;
10415 }
10416
10417 /*
10418 * Set the host maximum queuing (max. 253, min. 16) and the per device
10419 * maximum queuing (max. 63, min. 4).
10420 */
10421 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10422 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10423 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10424 /* If the value is zero, assume it is uninitialized. */
10425 if (eep_config.max_host_qng == 0) {
10426 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10427 } else {
10428 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10429 }
10430 }
10431
10432 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10433 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10434 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10435 /* If the value is zero, assume it is uninitialized. */
10436 if (eep_config.max_dvc_qng == 0) {
10437 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10438 } else {
10439 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10440 }
10441 }
10442
10443 /*
10444 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10445 * set 'max_dvc_qng' to 'max_host_qng'.
10446 */
10447 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10448 eep_config.max_dvc_qng = eep_config.max_host_qng;
10449 }
10450
10451 /*
10452 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
10453 * values based on possibly adjusted EEPROM values.
10454 */
10455 asc_dvc->max_host_qng = eep_config.max_host_qng;
10456 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10457
10458 /*
10459 * If the EEPROM 'termination' field is set to automatic (0), then set
10460 * the ASC_DVC_CFG 'termination' field to automatic also.
10461 *
10462 * If the termination is specified with a non-zero 'termination'
10463 * value check that a legal value is set and set the ASC_DVC_CFG
10464 * 'termination' field appropriately.
10465 */
10466 if (eep_config.termination_se == 0) {
10467 termination = 0; /* auto termination for SE */
10468 } else {
10469 /* Enable manual control with low off / high off. */
10470 if (eep_config.termination_se == 1) {
10471 termination = 0;
10472
10473 /* Enable manual control with low off / high on. */
10474 } else if (eep_config.termination_se == 2) {
10475 termination = TERM_SE_HI;
10476
10477 /* Enable manual control with low on / high on. */
10478 } else if (eep_config.termination_se == 3) {
10479 termination = TERM_SE;
10480 } else {
10481 /*
10482 * The EEPROM 'termination_se' field contains a bad value.
10483 * Use automatic termination instead.
10484 */
10485 termination = 0;
10486 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10487 }
10488 }
10489
10490 if (eep_config.termination_lvd == 0) {
10491 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10492 } else {
10493 /* Enable manual control with low off / high off. */
10494 if (eep_config.termination_lvd == 1) {
10495 asc_dvc->cfg->termination = termination;
10496
10497 /* Enable manual control with low off / high on. */
10498 } else if (eep_config.termination_lvd == 2) {
10499 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10500
10501 /* Enable manual control with low on / high on. */
10502 } else if (eep_config.termination_lvd == 3) {
10503 asc_dvc->cfg->termination = termination | TERM_LVD;
10504 } else {
10505 /*
10506 * The EEPROM 'termination_lvd' field contains a bad value.
10507 * Use automatic termination instead.
10508 */
10509 asc_dvc->cfg->termination = termination;
10510 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10511 }
10512 }
10513
10514 return warn_code;
10515 }
10516
10517 /*
10518 * Initialize the ADV_DVC_VAR structure.
10519 *
10520 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10521 *
10522 * For a non-fatal error return a warning code. If there are no warnings
10523 * then 0 is returned.
10524 */
10525 static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
10526 {
10527 struct asc_board *board = shost_priv(shost);
10528 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
10529 unsigned short warn_code = 0;
10530 AdvPortAddr iop_base = asc_dvc->iop_base;
10531 u16 cmd;
10532 int status;
10533
10534 asc_dvc->err_code = 0;
10535
10536 /*
10537 * Save the state of the PCI Configuration Command Register
10538 * "Parity Error Response Control" Bit. If the bit is clear (0),
10539 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
10540 * DMA parity errors.
10541 */
10542 asc_dvc->cfg->control_flag = 0;
10543 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
10544 if ((cmd & PCI_COMMAND_PARITY) == 0)
10545 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
10546
10547 asc_dvc->cfg->chip_version =
10548 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
10549
10550 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
10551 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
10552 (ushort)ADV_CHIP_ID_BYTE);
10553
10554 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
10555 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
10556 (ushort)ADV_CHIP_ID_WORD);
10557
10558 /*
10559 * Reset the chip to start and allow register writes.
10560 */
10561 if (AdvFindSignature(iop_base) == 0) {
10562 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
10563 return ADV_ERROR;
10564 } else {
10565 /*
10566 * The caller must set 'chip_type' to a valid setting.
10567 */
10568 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
10569 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
10570 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
10571 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
10572 return ADV_ERROR;
10573 }
10574
10575 /*
10576 * Reset Chip.
10577 */
10578 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
10579 ADV_CTRL_REG_CMD_RESET);
10580 mdelay(100);
10581 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
10582 ADV_CTRL_REG_CMD_WR_IO_REG);
10583
10584 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
10585 status = AdvInitFrom38C1600EEP(asc_dvc);
10586 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
10587 status = AdvInitFrom38C0800EEP(asc_dvc);
10588 } else {
10589 status = AdvInitFrom3550EEP(asc_dvc);
10590 }
10591 warn_code |= status;
10592 }
10593
10594 if (warn_code != 0)
10595 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
10596
10597 if (asc_dvc->err_code)
10598 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
10599 asc_dvc->err_code);
10600
10601 return asc_dvc->err_code;
10602 }
10603 #endif
10604
10605 static const struct scsi_host_template advansys_template = {
10606 .proc_name = DRV_NAME,
10607 #ifdef CONFIG_PROC_FS
10608 .show_info = advansys_show_info,
10609 #endif
10610 .name = DRV_NAME,
10611 .info = advansys_info,
10612 .queuecommand = advansys_queuecommand,
10613 .eh_host_reset_handler = advansys_reset,
10614 .bios_param = advansys_biosparam,
10615 .slave_configure = advansys_slave_configure,
10616 .cmd_size = sizeof(struct advansys_cmd),
10617 };
10618
10619 static int advansys_wide_init_chip(struct Scsi_Host *shost)
10620 {
10621 struct asc_board *board = shost_priv(shost);
10622 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
10623 size_t sgblk_pool_size;
10624 int warn_code, err_code;
10625
10626 /*
10627 * Allocate buffer carrier structures. The total size
10628 * is about 8 KB, so allocate all at once.
10629 */
10630 adv_dvc->carrier = dma_alloc_coherent(board->dev,
10631 ADV_CARRIER_BUFSIZE, &adv_dvc->carrier_addr, GFP_KERNEL);
10632 ASC_DBG(1, "carrier 0x%p\n", adv_dvc->carrier);
10633
10634 if (!adv_dvc->carrier)
10635 goto kmalloc_failed;
10636
10637 /*
10638 * Allocate up to 'max_host_qng' request structures for the Wide
10639 * board. The total size is about 16 KB, so allocate all at once.
10640 * If the allocation fails decrement and try again.
10641 */
10642 board->adv_reqp_size = adv_dvc->max_host_qng * sizeof(adv_req_t);
10643 if (board->adv_reqp_size & 0x1f) {
10644 ASC_DBG(1, "unaligned reqp %lu bytes\n", sizeof(adv_req_t));
10645 board->adv_reqp_size = ADV_32BALIGN(board->adv_reqp_size);
10646 }
10647 board->adv_reqp = dma_alloc_coherent(board->dev, board->adv_reqp_size,
10648 &board->adv_reqp_addr, GFP_KERNEL);
10649
10650 if (!board->adv_reqp)
10651 goto kmalloc_failed;
10652
10653 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", board->adv_reqp,
10654 adv_dvc->max_host_qng, board->adv_reqp_size);
10655
10656 /*
10657 * Allocate up to ADV_TOT_SG_BLOCK request structures for
10658 * the Wide board. Each structure is about 136 bytes.
10659 */
10660 sgblk_pool_size = sizeof(adv_sgblk_t) * ADV_TOT_SG_BLOCK;
10661 board->adv_sgblk_pool = dma_pool_create("adv_sgblk", board->dev,
10662 sgblk_pool_size, 32, 0);
10663
10664 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", ADV_TOT_SG_BLOCK,
10665 sizeof(adv_sgblk_t), sgblk_pool_size);
10666
10667 if (!board->adv_sgblk_pool)
10668 goto kmalloc_failed;
10669
10670 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
10671 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
10672 warn_code = AdvInitAsc3550Driver(adv_dvc);
10673 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
10674 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
10675 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
10676 } else {
10677 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
10678 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
10679 }
10680 err_code = adv_dvc->err_code;
10681
10682 if (warn_code || err_code) {
10683 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
10684 "0x%x\n", warn_code, err_code);
10685 }
10686
10687 goto exit;
10688
10689 kmalloc_failed:
10690 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
10691 err_code = ADV_ERROR;
10692 exit:
10693 return err_code;
10694 }
10695
10696 static void advansys_wide_free_mem(struct asc_board *board)
10697 {
10698 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
10699
10700 if (adv_dvc->carrier) {
10701 dma_free_coherent(board->dev, ADV_CARRIER_BUFSIZE,
10702 adv_dvc->carrier, adv_dvc->carrier_addr);
10703 adv_dvc->carrier = NULL;
10704 }
10705 if (board->adv_reqp) {
10706 dma_free_coherent(board->dev, board->adv_reqp_size,
10707 board->adv_reqp, board->adv_reqp_addr);
10708 board->adv_reqp = NULL;
10709 }
10710 if (board->adv_sgblk_pool) {
10711 dma_pool_destroy(board->adv_sgblk_pool);
10712 board->adv_sgblk_pool = NULL;
10713 }
10714 }
10715
10716 static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
10717 int bus_type)
10718 {
10719 struct pci_dev *pdev;
10720 struct asc_board *boardp = shost_priv(shost);
10721 ASC_DVC_VAR *asc_dvc_varp = NULL;
10722 ADV_DVC_VAR *adv_dvc_varp = NULL;
10723 int share_irq, warn_code, ret;
10724
10725 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
10726
10727 if (ASC_NARROW_BOARD(boardp)) {
10728 ASC_DBG(1, "narrow board\n");
10729 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
10730 asc_dvc_varp->bus_type = bus_type;
10731 asc_dvc_varp->drv_ptr = boardp;
10732 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
10733 asc_dvc_varp->iop_base = iop;
10734 } else {
10735 #ifdef CONFIG_PCI
10736 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
10737 adv_dvc_varp->drv_ptr = boardp;
10738 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
10739 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
10740 ASC_DBG(1, "wide board ASC-3550\n");
10741 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
10742 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
10743 ASC_DBG(1, "wide board ASC-38C0800\n");
10744 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
10745 } else {
10746 ASC_DBG(1, "wide board ASC-38C1600\n");
10747 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
10748 }
10749
10750 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
10751 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1);
10752 if (!boardp->ioremap_addr) {
10753 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) "
10754 "returned NULL\n",
10755 (long)pci_resource_start(pdev, 1),
10756 boardp->asc_n_io_port);
10757 ret = -ENODEV;
10758 goto err_shost;
10759 }
10760 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
10761 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
10762
10763 /*
10764 * Even though it isn't used to access wide boards, other
10765 * than for the debug line below, save I/O Port address so
10766 * that it can be reported.
10767 */
10768 boardp->ioport = iop;
10769
10770 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
10771 (ushort)inp(iop + 1), (ushort)inpw(iop));
10772 #endif /* CONFIG_PCI */
10773 }
10774
10775 if (ASC_NARROW_BOARD(boardp)) {
10776 /*
10777 * Set the board bus type and PCI IRQ before
10778 * calling AscInitGetConfig().
10779 */
10780 switch (asc_dvc_varp->bus_type) {
10781 #ifdef CONFIG_ISA
10782 case ASC_IS_VL:
10783 share_irq = 0;
10784 break;
10785 case ASC_IS_EISA:
10786 share_irq = IRQF_SHARED;
10787 break;
10788 #endif /* CONFIG_ISA */
10789 #ifdef CONFIG_PCI
10790 case ASC_IS_PCI:
10791 share_irq = IRQF_SHARED;
10792 break;
10793 #endif /* CONFIG_PCI */
10794 default:
10795 shost_printk(KERN_ERR, shost, "unknown adapter type: "
10796 "%d\n", asc_dvc_varp->bus_type);
10797 share_irq = 0;
10798 break;
10799 }
10800
10801 /*
10802 * NOTE: AscInitGetConfig() may change the board's
10803 * bus_type value. The bus_type value should no
10804 * longer be used. If the bus_type field must be
10805 * referenced only use the bit-wise AND operator "&".
10806 */
10807 ASC_DBG(2, "AscInitGetConfig()\n");
10808 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
10809 } else {
10810 #ifdef CONFIG_PCI
10811 /*
10812 * For Wide boards set PCI information before calling
10813 * AdvInitGetConfig().
10814 */
10815 share_irq = IRQF_SHARED;
10816 ASC_DBG(2, "AdvInitGetConfig()\n");
10817
10818 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
10819 #else
10820 share_irq = 0;
10821 ret = -ENODEV;
10822 #endif /* CONFIG_PCI */
10823 }
10824
10825 if (ret)
10826 goto err_unmap;
10827
10828 /*
10829 * Save the EEPROM configuration so that it can be displayed
10830 * from /proc/scsi/advansys/[0...].
10831 */
10832 if (ASC_NARROW_BOARD(boardp)) {
10833
10834 ASCEEP_CONFIG *ep;
10835
10836 /*
10837 * Set the adapter's target id bit in the 'init_tidmask' field.
10838 */
10839 boardp->init_tidmask |=
10840 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
10841
10842 /*
10843 * Save EEPROM settings for the board.
10844 */
10845 ep = &boardp->eep_config.asc_eep;
10846
10847 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
10848 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
10849 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
10850 ASC_EEP_SET_DMA_SPD(ep, ASC_DEF_ISA_DMA_SPEED);
10851 ep->start_motor = asc_dvc_varp->start_motor;
10852 ep->cntl = asc_dvc_varp->dvc_cntl;
10853 ep->no_scam = asc_dvc_varp->no_scam;
10854 ep->max_total_qng = asc_dvc_varp->max_total_qng;
10855 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
10856 /* 'max_tag_qng' is set to the same value for every device. */
10857 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
10858 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
10859 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
10860 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
10861 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
10862 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
10863 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
10864
10865 /*
10866 * Modify board configuration.
10867 */
10868 ASC_DBG(2, "AscInitSetConfig()\n");
10869 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
10870 if (ret)
10871 goto err_unmap;
10872 } else {
10873 ADVEEP_3550_CONFIG *ep_3550;
10874 ADVEEP_38C0800_CONFIG *ep_38C0800;
10875 ADVEEP_38C1600_CONFIG *ep_38C1600;
10876
10877 /*
10878 * Save Wide EEP Configuration Information.
10879 */
10880 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
10881 ep_3550 = &boardp->eep_config.adv_3550_eep;
10882
10883 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
10884 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
10885 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
10886 ep_3550->termination = adv_dvc_varp->cfg->termination;
10887 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
10888 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
10889 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
10890 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
10891 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
10892 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
10893 ep_3550->start_motor = adv_dvc_varp->start_motor;
10894 ep_3550->scsi_reset_delay =
10895 adv_dvc_varp->scsi_reset_wait;
10896 ep_3550->serial_number_word1 =
10897 adv_dvc_varp->cfg->serial1;
10898 ep_3550->serial_number_word2 =
10899 adv_dvc_varp->cfg->serial2;
10900 ep_3550->serial_number_word3 =
10901 adv_dvc_varp->cfg->serial3;
10902 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
10903 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
10904
10905 ep_38C0800->adapter_scsi_id =
10906 adv_dvc_varp->chip_scsi_id;
10907 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
10908 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
10909 ep_38C0800->termination_lvd =
10910 adv_dvc_varp->cfg->termination;
10911 ep_38C0800->disc_enable =
10912 adv_dvc_varp->cfg->disc_enable;
10913 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
10914 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
10915 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
10916 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
10917 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
10918 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
10919 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
10920 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
10921 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
10922 ep_38C0800->scsi_reset_delay =
10923 adv_dvc_varp->scsi_reset_wait;
10924 ep_38C0800->serial_number_word1 =
10925 adv_dvc_varp->cfg->serial1;
10926 ep_38C0800->serial_number_word2 =
10927 adv_dvc_varp->cfg->serial2;
10928 ep_38C0800->serial_number_word3 =
10929 adv_dvc_varp->cfg->serial3;
10930 } else {
10931 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
10932
10933 ep_38C1600->adapter_scsi_id =
10934 adv_dvc_varp->chip_scsi_id;
10935 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
10936 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
10937 ep_38C1600->termination_lvd =
10938 adv_dvc_varp->cfg->termination;
10939 ep_38C1600->disc_enable =
10940 adv_dvc_varp->cfg->disc_enable;
10941 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
10942 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
10943 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
10944 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
10945 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
10946 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
10947 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
10948 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
10949 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
10950 ep_38C1600->scsi_reset_delay =
10951 adv_dvc_varp->scsi_reset_wait;
10952 ep_38C1600->serial_number_word1 =
10953 adv_dvc_varp->cfg->serial1;
10954 ep_38C1600->serial_number_word2 =
10955 adv_dvc_varp->cfg->serial2;
10956 ep_38C1600->serial_number_word3 =
10957 adv_dvc_varp->cfg->serial3;
10958 }
10959
10960 /*
10961 * Set the adapter's target id bit in the 'init_tidmask' field.
10962 */
10963 boardp->init_tidmask |=
10964 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
10965 }
10966
10967 /*
10968 * Channels are numbered beginning with 0. For AdvanSys one host
10969 * structure supports one channel. Multi-channel boards have a
10970 * separate host structure for each channel.
10971 */
10972 shost->max_channel = 0;
10973 if (ASC_NARROW_BOARD(boardp)) {
10974 shost->max_id = ASC_MAX_TID + 1;
10975 shost->max_lun = ASC_MAX_LUN + 1;
10976 shost->max_cmd_len = ASC_MAX_CDB_LEN;
10977
10978 shost->io_port = asc_dvc_varp->iop_base;
10979 boardp->asc_n_io_port = ASC_IOADR_GAP;
10980 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
10981
10982 /* Set maximum number of queues the adapter can handle. */
10983 shost->can_queue = asc_dvc_varp->max_total_qng;
10984 } else {
10985 shost->max_id = ADV_MAX_TID + 1;
10986 shost->max_lun = ADV_MAX_LUN + 1;
10987 shost->max_cmd_len = ADV_MAX_CDB_LEN;
10988
10989 /*
10990 * Save the I/O Port address and length even though
10991 * I/O ports are not used to access Wide boards.
10992 * Instead the Wide boards are accessed with
10993 * PCI Memory Mapped I/O.
10994 */
10995 shost->io_port = iop;
10996
10997 shost->this_id = adv_dvc_varp->chip_scsi_id;
10998
10999 /* Set maximum number of queues the adapter can handle. */
11000 shost->can_queue = adv_dvc_varp->max_host_qng;
11001 }
11002
11003 /*
11004 * Set the maximum number of scatter-gather elements the
11005 * adapter can handle.
11006 */
11007 if (ASC_NARROW_BOARD(boardp)) {
11008 /*
11009 * Allow two commands with 'sg_tablesize' scatter-gather
11010 * elements to be executed simultaneously. This value is
11011 * the theoretical hardware limit. It may be decreased
11012 * below.
11013 */
11014 shost->sg_tablesize =
11015 (((asc_dvc_varp->max_total_qng - 2) / 2) *
11016 ASC_SG_LIST_PER_Q) + 1;
11017 } else {
11018 shost->sg_tablesize = ADV_MAX_SG_LIST;
11019 }
11020
11021 /*
11022 * The value of 'sg_tablesize' can not exceed the SCSI
11023 * mid-level driver definition of SG_ALL. SG_ALL also
11024 * must not be exceeded, because it is used to define the
11025 * size of the scatter-gather table in 'struct asc_sg_head'.
11026 */
11027 if (shost->sg_tablesize > SG_ALL) {
11028 shost->sg_tablesize = SG_ALL;
11029 }
11030
11031 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
11032
11033 /* BIOS start address. */
11034 if (ASC_NARROW_BOARD(boardp)) {
11035 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
11036 asc_dvc_varp->bus_type);
11037 } else {
11038 /*
11039 * Fill-in BIOS board variables. The Wide BIOS saves
11040 * information in LRAM that is used by the driver.
11041 */
11042 AdvReadWordLram(adv_dvc_varp->iop_base,
11043 BIOS_SIGNATURE, boardp->bios_signature);
11044 AdvReadWordLram(adv_dvc_varp->iop_base,
11045 BIOS_VERSION, boardp->bios_version);
11046 AdvReadWordLram(adv_dvc_varp->iop_base,
11047 BIOS_CODESEG, boardp->bios_codeseg);
11048 AdvReadWordLram(adv_dvc_varp->iop_base,
11049 BIOS_CODELEN, boardp->bios_codelen);
11050
11051 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
11052 boardp->bios_signature, boardp->bios_version);
11053
11054 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
11055 boardp->bios_codeseg, boardp->bios_codelen);
11056
11057 /*
11058 * If the BIOS saved a valid signature, then fill in
11059 * the BIOS code segment base address.
11060 */
11061 if (boardp->bios_signature == 0x55AA) {
11062 /*
11063 * Convert x86 realmode code segment to a linear
11064 * address by shifting left 4.
11065 */
11066 shost->base = ((ulong)boardp->bios_codeseg << 4);
11067 } else {
11068 shost->base = 0;
11069 }
11070 }
11071
11072 /*
11073 * Register Board Resources - I/O Port, DMA, IRQ
11074 */
11075
11076 /* Register DMA Channel for Narrow boards. */
11077 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
11078
11079 /* Register IRQ Number. */
11080 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
11081
11082 ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
11083 DRV_NAME, shost);
11084
11085 if (ret) {
11086 if (ret == -EBUSY) {
11087 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11088 "already in use\n", boardp->irq);
11089 } else if (ret == -EINVAL) {
11090 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11091 "not valid\n", boardp->irq);
11092 } else {
11093 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11094 "failed with %d\n", boardp->irq, ret);
11095 }
11096 goto err_unmap;
11097 }
11098
11099 /*
11100 * Initialize board RISC chip and enable interrupts.
11101 */
11102 if (ASC_NARROW_BOARD(boardp)) {
11103 ASC_DBG(2, "AscInitAsc1000Driver()\n");
11104
11105 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL);
11106 if (!asc_dvc_varp->overrun_buf) {
11107 ret = -ENOMEM;
11108 goto err_free_irq;
11109 }
11110 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
11111
11112 if (warn_code || asc_dvc_varp->err_code) {
11113 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
11114 "warn 0x%x, error 0x%x\n",
11115 asc_dvc_varp->init_state, warn_code,
11116 asc_dvc_varp->err_code);
11117 if (!asc_dvc_varp->overrun_dma) {
11118 ret = -ENODEV;
11119 goto err_free_mem;
11120 }
11121 }
11122 } else {
11123 if (advansys_wide_init_chip(shost)) {
11124 ret = -ENODEV;
11125 goto err_free_mem;
11126 }
11127 }
11128
11129 ASC_DBG_PRT_SCSI_HOST(2, shost);
11130
11131 ret = scsi_add_host(shost, boardp->dev);
11132 if (ret)
11133 goto err_free_mem;
11134
11135 scsi_scan_host(shost);
11136 return 0;
11137
11138 err_free_mem:
11139 if (ASC_NARROW_BOARD(boardp)) {
11140 if (asc_dvc_varp->overrun_dma)
11141 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma,
11142 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11143 kfree(asc_dvc_varp->overrun_buf);
11144 } else
11145 advansys_wide_free_mem(boardp);
11146 err_free_irq:
11147 free_irq(boardp->irq, shost);
11148 err_unmap:
11149 if (boardp->ioremap_addr)
11150 iounmap(boardp->ioremap_addr);
11151 #ifdef CONFIG_PCI
11152 err_shost:
11153 #endif
11154 return ret;
11155 }
11156
11157 /*
11158 * advansys_release()
11159 *
11160 * Release resources allocated for a single AdvanSys adapter.
11161 */
11162 static int advansys_release(struct Scsi_Host *shost)
11163 {
11164 struct asc_board *board = shost_priv(shost);
11165 ASC_DBG(1, "begin\n");
11166 scsi_remove_host(shost);
11167 free_irq(board->irq, shost);
11168
11169 if (ASC_NARROW_BOARD(board)) {
11170 dma_unmap_single(board->dev,
11171 board->dvc_var.asc_dvc_var.overrun_dma,
11172 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11173 kfree(board->dvc_var.asc_dvc_var.overrun_buf);
11174 } else {
11175 iounmap(board->ioremap_addr);
11176 advansys_wide_free_mem(board);
11177 }
11178 scsi_host_put(shost);
11179 ASC_DBG(1, "end\n");
11180 return 0;
11181 }
11182
11183 #define ASC_IOADR_TABLE_MAX_IX 11
11184
11185 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = {
11186 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
11187 0x0210, 0x0230, 0x0250, 0x0330
11188 };
11189
11190 static void advansys_vlb_remove(struct device *dev, unsigned int id)
11191 {
11192 int ioport = _asc_def_iop_base[id];
11193 advansys_release(dev_get_drvdata(dev));
11194 release_region(ioport, ASC_IOADR_GAP);
11195 }
11196
11197 /*
11198 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
11199 * 000: invalid
11200 * 001: 10
11201 * 010: 11
11202 * 011: 12
11203 * 100: invalid
11204 * 101: 14
11205 * 110: 15
11206 * 111: invalid
11207 */
11208 static unsigned int advansys_vlb_irq_no(PortAddr iop_base)
11209 {
11210 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11211 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
11212 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
11213 return 0;
11214 return chip_irq;
11215 }
11216
11217 static int advansys_vlb_probe(struct device *dev, unsigned int id)
11218 {
11219 int err = -ENODEV;
11220 PortAddr iop_base = _asc_def_iop_base[id];
11221 struct Scsi_Host *shost;
11222 struct asc_board *board;
11223
11224 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
11225 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
11226 return -ENODEV;
11227 }
11228 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
11229 if (!AscFindSignature(iop_base))
11230 goto release_region;
11231 /*
11232 * I don't think this condition can actually happen, but the old
11233 * driver did it, and the chances of finding a VLB setup in 2007
11234 * to do testing with is slight to none.
11235 */
11236 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
11237 goto release_region;
11238
11239 err = -ENOMEM;
11240 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11241 if (!shost)
11242 goto release_region;
11243
11244 board = shost_priv(shost);
11245 board->irq = advansys_vlb_irq_no(iop_base);
11246 board->dev = dev;
11247 board->shost = shost;
11248
11249 err = advansys_board_found(shost, iop_base, ASC_IS_VL);
11250 if (err)
11251 goto free_host;
11252
11253 dev_set_drvdata(dev, shost);
11254 return 0;
11255
11256 free_host:
11257 scsi_host_put(shost);
11258 release_region:
11259 release_region(iop_base, ASC_IOADR_GAP);
11260 return -ENODEV;
11261 }
11262
11263 static struct isa_driver advansys_vlb_driver = {
11264 .probe = advansys_vlb_probe,
11265 .remove = advansys_vlb_remove,
11266 .driver = {
11267 .owner = THIS_MODULE,
11268 .name = "advansys_vlb",
11269 },
11270 };
11271
11272 static struct eisa_device_id advansys_eisa_table[] = {
11273 { "ABP7401" },
11274 { "ABP7501" },
11275 { "" }
11276 };
11277
11278 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
11279
11280 /*
11281 * EISA is a little more tricky than PCI; each EISA device may have two
11282 * channels, and this driver is written to make each channel its own Scsi_Host
11283 */
11284 struct eisa_scsi_data {
11285 struct Scsi_Host *host[2];
11286 };
11287
11288 /*
11289 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
11290 * 000: 10
11291 * 001: 11
11292 * 010: 12
11293 * 011: invalid
11294 * 100: 14
11295 * 101: 15
11296 * 110: invalid
11297 * 111: invalid
11298 */
11299 static unsigned int advansys_eisa_irq_no(struct eisa_device *edev)
11300 {
11301 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
11302 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
11303 if ((chip_irq == 13) || (chip_irq > 15))
11304 return 0;
11305 return chip_irq;
11306 }
11307
11308 static int advansys_eisa_probe(struct device *dev)
11309 {
11310 int i, ioport, irq = 0;
11311 int err;
11312 struct eisa_device *edev = to_eisa_device(dev);
11313 struct eisa_scsi_data *data;
11314
11315 err = -ENOMEM;
11316 data = kzalloc(sizeof(*data), GFP_KERNEL);
11317 if (!data)
11318 goto fail;
11319 ioport = edev->base_addr + 0xc30;
11320
11321 err = -ENODEV;
11322 for (i = 0; i < 2; i++, ioport += 0x20) {
11323 struct asc_board *board;
11324 struct Scsi_Host *shost;
11325 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
11326 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
11327 ioport + ASC_IOADR_GAP - 1);
11328 continue;
11329 }
11330 if (!AscFindSignature(ioport)) {
11331 release_region(ioport, ASC_IOADR_GAP);
11332 continue;
11333 }
11334
11335 /*
11336 * I don't know why we need to do this for EISA chips, but
11337 * not for any others. It looks to be equivalent to
11338 * AscGetChipCfgMsw, but I may have overlooked something,
11339 * so I'm not converting it until I get an EISA board to
11340 * test with.
11341 */
11342 inw(ioport + 4);
11343
11344 if (!irq)
11345 irq = advansys_eisa_irq_no(edev);
11346
11347 err = -ENOMEM;
11348 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11349 if (!shost)
11350 goto release_region;
11351
11352 board = shost_priv(shost);
11353 board->irq = irq;
11354 board->dev = dev;
11355 board->shost = shost;
11356
11357 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
11358 if (!err) {
11359 data->host[i] = shost;
11360 continue;
11361 }
11362
11363 scsi_host_put(shost);
11364 release_region:
11365 release_region(ioport, ASC_IOADR_GAP);
11366 break;
11367 }
11368
11369 if (err)
11370 goto free_data;
11371 dev_set_drvdata(dev, data);
11372 return 0;
11373
11374 free_data:
11375 kfree(data->host[0]);
11376 kfree(data->host[1]);
11377 kfree(data);
11378 fail:
11379 return err;
11380 }
11381
11382 static int advansys_eisa_remove(struct device *dev)
11383 {
11384 int i;
11385 struct eisa_scsi_data *data = dev_get_drvdata(dev);
11386
11387 for (i = 0; i < 2; i++) {
11388 int ioport;
11389 struct Scsi_Host *shost = data->host[i];
11390 if (!shost)
11391 continue;
11392 ioport = shost->io_port;
11393 advansys_release(shost);
11394 release_region(ioport, ASC_IOADR_GAP);
11395 }
11396
11397 kfree(data);
11398 return 0;
11399 }
11400
11401 static struct eisa_driver advansys_eisa_driver = {
11402 .id_table = advansys_eisa_table,
11403 .driver = {
11404 .name = DRV_NAME,
11405 .probe = advansys_eisa_probe,
11406 .remove = advansys_eisa_remove,
11407 }
11408 };
11409
11410 /* PCI Devices supported by this driver */
11411 static struct pci_device_id advansys_pci_tbl[] = {
11412 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
11413 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11414 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
11415 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11416 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
11417 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11418 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
11419 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11420 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
11421 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11422 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
11423 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11424 {}
11425 };
11426
11427 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
11428
11429 static void advansys_set_latency(struct pci_dev *pdev)
11430 {
11431 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
11432 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
11433 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
11434 } else {
11435 u8 latency;
11436 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
11437 if (latency < 0x20)
11438 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
11439 }
11440 }
11441
11442 static int advansys_pci_probe(struct pci_dev *pdev,
11443 const struct pci_device_id *ent)
11444 {
11445 int err, ioport;
11446 struct Scsi_Host *shost;
11447 struct asc_board *board;
11448
11449 err = pci_enable_device(pdev);
11450 if (err)
11451 goto fail;
11452 err = pci_request_regions(pdev, DRV_NAME);
11453 if (err)
11454 goto disable_device;
11455 pci_set_master(pdev);
11456 advansys_set_latency(pdev);
11457
11458 err = -ENODEV;
11459 if (pci_resource_len(pdev, 0) == 0)
11460 goto release_region;
11461
11462 ioport = pci_resource_start(pdev, 0);
11463
11464 err = -ENOMEM;
11465 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11466 if (!shost)
11467 goto release_region;
11468
11469 board = shost_priv(shost);
11470 board->irq = pdev->irq;
11471 board->dev = &pdev->dev;
11472 board->shost = shost;
11473
11474 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
11475 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
11476 pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
11477 board->flags |= ASC_IS_WIDE_BOARD;
11478 }
11479
11480 err = advansys_board_found(shost, ioport, ASC_IS_PCI);
11481 if (err)
11482 goto free_host;
11483
11484 pci_set_drvdata(pdev, shost);
11485 return 0;
11486
11487 free_host:
11488 scsi_host_put(shost);
11489 release_region:
11490 pci_release_regions(pdev);
11491 disable_device:
11492 pci_disable_device(pdev);
11493 fail:
11494 return err;
11495 }
11496
11497 static void advansys_pci_remove(struct pci_dev *pdev)
11498 {
11499 advansys_release(pci_get_drvdata(pdev));
11500 pci_release_regions(pdev);
11501 pci_disable_device(pdev);
11502 }
11503
11504 static struct pci_driver advansys_pci_driver = {
11505 .name = DRV_NAME,
11506 .id_table = advansys_pci_tbl,
11507 .probe = advansys_pci_probe,
11508 .remove = advansys_pci_remove,
11509 };
11510
11511 static int __init advansys_init(void)
11512 {
11513 int error;
11514
11515 error = isa_register_driver(&advansys_vlb_driver,
11516 ASC_IOADR_TABLE_MAX_IX);
11517 if (error)
11518 goto fail;
11519
11520 error = eisa_driver_register(&advansys_eisa_driver);
11521 if (error)
11522 goto unregister_vlb;
11523
11524 error = pci_register_driver(&advansys_pci_driver);
11525 if (error)
11526 goto unregister_eisa;
11527
11528 return 0;
11529
11530 unregister_eisa:
11531 eisa_driver_unregister(&advansys_eisa_driver);
11532 unregister_vlb:
11533 isa_unregister_driver(&advansys_vlb_driver);
11534 fail:
11535 return error;
11536 }
11537
11538 static void __exit advansys_exit(void)
11539 {
11540 pci_unregister_driver(&advansys_pci_driver);
11541 eisa_driver_unregister(&advansys_eisa_driver);
11542 isa_unregister_driver(&advansys_vlb_driver);
11543 }
11544
11545 module_init(advansys_init);
11546 module_exit(advansys_exit);
11547
11548 MODULE_DESCRIPTION("AdvanSys SCSI Adapter driver");
11549 MODULE_LICENSE("GPL");
11550 MODULE_FIRMWARE("advansys/mcode.bin");
11551 MODULE_FIRMWARE("advansys/3550.bin");
11552 MODULE_FIRMWARE("advansys/38C0800.bin");
11553 MODULE_FIRMWARE("advansys/38C1600.bin");
Kernel DRM miscellaneous fixes and cross-tree changes