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drm/tests: hdmi: Fix memory leaks in drm_display_mode_from_cea_vic()
[drm/drm-misc.git] / drivers / i2c / busses / i2c-davinci.c
blobc4fb5e9ab50611b0c6e536786fcd023a0c4743fd
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * TI DAVINCI I2C adapter driver.
4 *
5 * Copyright (C) 2006 Texas Instruments.
6 * Copyright (C) 2007 MontaVista Software Inc.
7 *
8 * Updated by Vinod & Sudhakar Feb 2005
9 *
10 * ----------------------------------------------------------------------------
11 *
12 * ----------------------------------------------------------------------------
13 */
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/clk.h>
19 #include <linux/errno.h>
20 #include <linux/sched.h>
21 #include <linux/err.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/io.h>
25 #include <linux/slab.h>
26 #include <linux/cpufreq.h>
27 #include <linux/gpio/consumer.h>
28 #include <linux/of.h>
29 #include <linux/platform_data/i2c-davinci.h>
30 #include <linux/pm_runtime.h>
31
32 /* ----- global defines ----------------------------------------------- */
33
34 #define DAVINCI_I2C_TIMEOUT (1*HZ)
35 #define DAVINCI_I2C_MAX_TRIES 2
36 #define DAVINCI_I2C_OWN_ADDRESS 0x08
37 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_SCD | \
38 DAVINCI_I2C_IMR_ARDY | \
39 DAVINCI_I2C_IMR_NACK | \
40 DAVINCI_I2C_IMR_AL)
41
42 #define DAVINCI_I2C_OAR_REG 0x00
43 #define DAVINCI_I2C_IMR_REG 0x04
44 #define DAVINCI_I2C_STR_REG 0x08
45 #define DAVINCI_I2C_CLKL_REG 0x0c
46 #define DAVINCI_I2C_CLKH_REG 0x10
47 #define DAVINCI_I2C_CNT_REG 0x14
48 #define DAVINCI_I2C_DRR_REG 0x18
49 #define DAVINCI_I2C_SAR_REG 0x1c
50 #define DAVINCI_I2C_DXR_REG 0x20
51 #define DAVINCI_I2C_MDR_REG 0x24
52 #define DAVINCI_I2C_IVR_REG 0x28
53 #define DAVINCI_I2C_EMDR_REG 0x2c
54 #define DAVINCI_I2C_PSC_REG 0x30
55 #define DAVINCI_I2C_FUNC_REG 0x48
56 #define DAVINCI_I2C_DIR_REG 0x4c
57 #define DAVINCI_I2C_DIN_REG 0x50
58 #define DAVINCI_I2C_DOUT_REG 0x54
59 #define DAVINCI_I2C_DSET_REG 0x58
60 #define DAVINCI_I2C_DCLR_REG 0x5c
61
62 #define DAVINCI_I2C_IVR_AAS 0x07
63 #define DAVINCI_I2C_IVR_SCD 0x06
64 #define DAVINCI_I2C_IVR_XRDY 0x05
65 #define DAVINCI_I2C_IVR_RDR 0x04
66 #define DAVINCI_I2C_IVR_ARDY 0x03
67 #define DAVINCI_I2C_IVR_NACK 0x02
68 #define DAVINCI_I2C_IVR_AL 0x01
69
70 #define DAVINCI_I2C_STR_BB BIT(12)
71 #define DAVINCI_I2C_STR_RSFULL BIT(11)
72 #define DAVINCI_I2C_STR_SCD BIT(5)
73 #define DAVINCI_I2C_STR_ARDY BIT(2)
74 #define DAVINCI_I2C_STR_NACK BIT(1)
75 #define DAVINCI_I2C_STR_AL BIT(0)
76
77 #define DAVINCI_I2C_MDR_NACK BIT(15)
78 #define DAVINCI_I2C_MDR_STT BIT(13)
79 #define DAVINCI_I2C_MDR_STP BIT(11)
80 #define DAVINCI_I2C_MDR_MST BIT(10)
81 #define DAVINCI_I2C_MDR_TRX BIT(9)
82 #define DAVINCI_I2C_MDR_XA BIT(8)
83 #define DAVINCI_I2C_MDR_RM BIT(7)
84 #define DAVINCI_I2C_MDR_IRS BIT(5)
85
86 #define DAVINCI_I2C_IMR_AAS BIT(6)
87 #define DAVINCI_I2C_IMR_SCD BIT(5)
88 #define DAVINCI_I2C_IMR_XRDY BIT(4)
89 #define DAVINCI_I2C_IMR_RRDY BIT(3)
90 #define DAVINCI_I2C_IMR_ARDY BIT(2)
91 #define DAVINCI_I2C_IMR_NACK BIT(1)
92 #define DAVINCI_I2C_IMR_AL BIT(0)
93
94 /* set SDA and SCL as GPIO */
95 #define DAVINCI_I2C_FUNC_PFUNC0 BIT(0)
96
97 /* set SCL as output when used as GPIO*/
98 #define DAVINCI_I2C_DIR_PDIR0 BIT(0)
99 /* set SDA as output when used as GPIO*/
100 #define DAVINCI_I2C_DIR_PDIR1 BIT(1)
101
102 /* read SCL GPIO level */
103 #define DAVINCI_I2C_DIN_PDIN0 BIT(0)
104 /* read SDA GPIO level */
105 #define DAVINCI_I2C_DIN_PDIN1 BIT(1)
106
107 /*set the SCL GPIO high */
108 #define DAVINCI_I2C_DSET_PDSET0 BIT(0)
109 /*set the SDA GPIO high */
110 #define DAVINCI_I2C_DSET_PDSET1 BIT(1)
111
112 /* set the SCL GPIO low */
113 #define DAVINCI_I2C_DCLR_PDCLR0 BIT(0)
114 /* set the SDA GPIO low */
115 #define DAVINCI_I2C_DCLR_PDCLR1 BIT(1)
116
117 /* timeout for pm runtime autosuspend */
118 #define DAVINCI_I2C_PM_TIMEOUT 1000 /* ms */
119
120 struct davinci_i2c_dev {
121 struct device *dev;
122 void __iomem *base;
123 struct completion cmd_complete;
124 struct clk *clk;
125 int cmd_err;
126 u8 *buf;
127 size_t buf_len;
128 int irq;
129 int stop;
130 u8 terminate;
131 struct i2c_adapter adapter;
132 #ifdef CONFIG_CPU_FREQ
133 struct notifier_block freq_transition;
134 #endif
135 struct davinci_i2c_platform_data *pdata;
136 };
137
138 /* default platform data to use if not supplied in the platform_device */
139 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
140 .bus_freq = 100,
141 .bus_delay = 0,
142 };
143
144 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
145 int reg, u16 val)
146 {
147 writew_relaxed(val, i2c_dev->base + reg);
148 }
149
150 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
151 {
152 return readw_relaxed(i2c_dev->base + reg);
153 }
154
155 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
156 int val)
157 {
158 u16 w;
159
160 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
161 if (!val) /* put I2C into reset */
162 w &= ~DAVINCI_I2C_MDR_IRS;
163 else /* take I2C out of reset */
164 w |= DAVINCI_I2C_MDR_IRS;
165
166 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
167 }
168
169 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
170 {
171 struct davinci_i2c_platform_data *pdata = dev->pdata;
172 u16 psc;
173 u32 clk;
174 u32 d;
175 u32 clkh;
176 u32 clkl;
177 u32 input_clock = clk_get_rate(dev->clk);
178 struct device_node *of_node = dev->dev->of_node;
179
180 /* NOTE: I2C Clock divider programming info
181 * As per I2C specs the following formulas provide prescaler
182 * and low/high divider values
183 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
184 * module clk
185 *
186 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
187 *
188 * Thus,
189 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
190 *
191 * where if PSC == 0, d = 7,
192 * if PSC == 1, d = 6
193 * if PSC > 1 , d = 5
194 *
195 * Note:
196 * d is always 6 on Keystone I2C controller
197 */
198
199 /*
200 * Both Davinci and current Keystone User Guides recommend a value
201 * between 7MHz and 12MHz. In reality 7MHz module clock doesn't
202 * always produce enough margin between SDA and SCL transitions.
203 * Measurements show that the higher the module clock is, the
204 * bigger is the margin, providing more reliable communication.
205 * So we better target for 12MHz.
206 */
207 psc = (input_clock / 12000000) - 1;
208 if ((input_clock / (psc + 1)) > 12000000)
209 psc++; /* better to run under spec than over */
210 d = (psc >= 2) ? 5 : 7 - psc;
211
212 if (of_node && of_device_is_compatible(of_node, "ti,keystone-i2c"))
213 d = 6;
214
215 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000));
216 /* Avoid driving the bus too fast because of rounding errors above */
217 if (input_clock / (psc + 1) / clk > pdata->bus_freq * 1000)
218 clk++;
219 /*
220 * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at
221 * least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH
222 * to LOW ratio as 1 to 2 is more safe.
223 */
224 if (pdata->bus_freq > 100)
225 clkl = (clk << 1) / 3;
226 else
227 clkl = (clk >> 1);
228 /*
229 * It's not always possible to have 1 to 2 ratio when d=7, so fall back
230 * to minimal possible clkh in this case.
231 *
232 * Note:
233 * CLKH is not allowed to be 0, in this case I2C clock is not generated
234 * at all
235 */
236 if (clk > clkl + d) {
237 clkh = clk - clkl - d;
238 clkl -= d;
239 } else {
240 clkh = 1;
241 clkl = clk - (d << 1);
242 }
243
244 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
245 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
246 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
247
248 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
249 }
250
251 /*
252 * This function configures I2C and brings I2C out of reset.
253 * This function is called during I2C init function. This function
254 * also gets called if I2C encounters any errors.
255 */
256 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
257 {
258 struct davinci_i2c_platform_data *pdata = dev->pdata;
259
260 /* put I2C into reset */
261 davinci_i2c_reset_ctrl(dev, 0);
262
263 /* compute clock dividers */
264 i2c_davinci_calc_clk_dividers(dev);
265
266 /* Respond at reserved "SMBus Host" target address" (and zero);
267 * we seem to have no option to not respond...
268 */
269 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, DAVINCI_I2C_OWN_ADDRESS);
270
271 dev_dbg(dev->dev, "PSC = %d\n",
272 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
273 dev_dbg(dev->dev, "CLKL = %d\n",
274 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
275 dev_dbg(dev->dev, "CLKH = %d\n",
276 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
277 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
278 pdata->bus_freq, pdata->bus_delay);
279
280
281 /* Take the I2C module out of reset: */
282 davinci_i2c_reset_ctrl(dev, 1);
283
284 /* Enable interrupts */
285 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
286
287 return 0;
288 }
289
290 /*
291 * This routine does i2c bus recovery by using i2c_generic_scl_recovery
292 * which is provided by I2C Bus recovery infrastructure.
293 */
294 static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap)
295 {
296 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
297
298 /* Disable interrupts */
299 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0);
300
301 /* put I2C into reset */
302 davinci_i2c_reset_ctrl(dev, 0);
303 }
304
305 static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap)
306 {
307 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
308
309 i2c_davinci_init(dev);
310 }
311
312 static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = {
313 .recover_bus = i2c_generic_scl_recovery,
314 .prepare_recovery = davinci_i2c_prepare_recovery,
315 .unprepare_recovery = davinci_i2c_unprepare_recovery,
316 };
317
318 static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val)
319 {
320 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
321
322 if (val)
323 davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG,
324 DAVINCI_I2C_DSET_PDSET0);
325 else
326 davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG,
327 DAVINCI_I2C_DCLR_PDCLR0);
328 }
329
330 static int davinci_i2c_get_scl(struct i2c_adapter *adap)
331 {
332 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
333 int val;
334
335 /* read the state of SCL */
336 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
337 return val & DAVINCI_I2C_DIN_PDIN0;
338 }
339
340 static int davinci_i2c_get_sda(struct i2c_adapter *adap)
341 {
342 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
343 int val;
344
345 /* read the state of SDA */
346 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
347 return val & DAVINCI_I2C_DIN_PDIN1;
348 }
349
350 static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap)
351 {
352 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
353
354 davinci_i2c_prepare_recovery(adap);
355
356 /* SCL output, SDA input */
357 davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0);
358
359 /* change to GPIO mode */
360 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG,
361 DAVINCI_I2C_FUNC_PFUNC0);
362 }
363
364 static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap)
365 {
366 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
367
368 /* change back to I2C mode */
369 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0);
370
371 davinci_i2c_unprepare_recovery(adap);
372 }
373
374 static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = {
375 .recover_bus = i2c_generic_scl_recovery,
376 .set_scl = davinci_i2c_set_scl,
377 .get_scl = davinci_i2c_get_scl,
378 .get_sda = davinci_i2c_get_sda,
379 .prepare_recovery = davinci_i2c_scl_prepare_recovery,
380 .unprepare_recovery = davinci_i2c_scl_unprepare_recovery,
381 };
382
383 /*
384 * Waiting for bus not busy
385 */
386 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev)
387 {
388 unsigned long timeout = jiffies + dev->adapter.timeout;
389
390 do {
391 if (!(davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB))
392 return 0;
393 schedule_timeout_uninterruptible(1);
394 } while (time_before_eq(jiffies, timeout));
395
396 dev_warn(dev->dev, "timeout waiting for bus ready\n");
397 i2c_recover_bus(&dev->adapter);
398
399 /*
400 * if bus is still "busy" here, it's most probably a HW problem like
401 * short-circuit
402 */
403 if (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB)
404 return -EIO;
405
406 return 0;
407 }
408
409 /*
410 * Low level read/write transaction. This function is called from
411 * i2c_davinci_xfer.
412 */
413 static int
414 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
415 {
416 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
417 struct davinci_i2c_platform_data *pdata = dev->pdata;
418 u32 flag;
419 u16 w;
420 unsigned long time_left;
421
422 if (msg->addr == DAVINCI_I2C_OWN_ADDRESS) {
423 dev_warn(dev->dev, "transfer to own address aborted\n");
424 return -EADDRNOTAVAIL;
425 }
426
427 /* Introduce a delay, required for some boards (e.g Davinci EVM) */
428 if (pdata->bus_delay)
429 udelay(pdata->bus_delay);
430
431 /* set the target address */
432 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
433
434 dev->buf = msg->buf;
435 dev->buf_len = msg->len;
436 dev->stop = stop;
437
438 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
439
440 reinit_completion(&dev->cmd_complete);
441 dev->cmd_err = 0;
442
443 /* Take I2C out of reset and configure it as controller */
444 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
445
446 if (msg->flags & I2C_M_TEN)
447 flag |= DAVINCI_I2C_MDR_XA;
448 if (!(msg->flags & I2C_M_RD))
449 flag |= DAVINCI_I2C_MDR_TRX;
450 if (msg->len == 0)
451 flag |= DAVINCI_I2C_MDR_RM;
452
453 /* Enable receive or transmit interrupts */
454 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
455 if (msg->flags & I2C_M_RD)
456 w |= DAVINCI_I2C_IMR_RRDY;
457 else
458 w |= DAVINCI_I2C_IMR_XRDY;
459 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
460
461 dev->terminate = 0;
462
463 /*
464 * Write mode register first as needed for correct behaviour
465 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
466 * occurring before we have loaded DXR
467 */
468 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
469
470 /*
471 * First byte should be set here, not after interrupt,
472 * because transmit-data-ready interrupt can come before
473 * NACK-interrupt during sending of previous message and
474 * ICDXR may have wrong data
475 * It also saves us one interrupt, slightly faster
476 */
477 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
478 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
479 dev->buf_len--;
480 }
481
482 /* Set STT to begin transmit now DXR is loaded */
483 flag |= DAVINCI_I2C_MDR_STT;
484 if (stop && msg->len != 0)
485 flag |= DAVINCI_I2C_MDR_STP;
486 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
487
488 time_left = wait_for_completion_timeout(&dev->cmd_complete,
489 dev->adapter.timeout);
490 if (!time_left) {
491 i2c_recover_bus(adap);
492 dev->buf_len = 0;
493 return -ETIMEDOUT;
494 }
495 if (dev->buf_len) {
496 /* This should be 0 if all bytes were transferred
497 * or dev->cmd_err denotes an error.
498 */
499 dev_err(dev->dev, "abnormal termination buf_len=%zu\n",
500 dev->buf_len);
501 dev->terminate = 1;
502 wmb();
503 dev->buf_len = 0;
504 return -EREMOTEIO;
505 }
506
507 /* no error */
508 if (likely(!dev->cmd_err))
509 return msg->len;
510
511 /* We have an error */
512 if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
513 i2c_davinci_init(dev);
514 return -EIO;
515 }
516
517 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
518 if (msg->flags & I2C_M_IGNORE_NAK)
519 return msg->len;
520 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
521 w |= DAVINCI_I2C_MDR_STP;
522 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
523 return -EREMOTEIO;
524 }
525 return -EIO;
526 }
527
528 /*
529 * Prepare controller for a transaction and call i2c_davinci_xfer_msg
530 */
531 static int
532 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
533 {
534 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
535 int i;
536 int ret;
537
538 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
539
540 ret = pm_runtime_resume_and_get(dev->dev);
541 if (ret < 0) {
542 dev_err(dev->dev, "Failed to runtime_get device: %d\n", ret);
543 return ret;
544 }
545
546 ret = i2c_davinci_wait_bus_not_busy(dev);
547 if (ret < 0) {
548 dev_warn(dev->dev, "timeout waiting for bus ready\n");
549 goto out;
550 }
551
552 for (i = 0; i < num; i++) {
553 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
554 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
555 ret);
556 if (ret < 0)
557 goto out;
558 }
559
560 ret = num;
561
562 out:
563 pm_runtime_mark_last_busy(dev->dev);
564 pm_runtime_put_autosuspend(dev->dev);
565
566 return ret;
567 }
568
569 static u32 i2c_davinci_func(struct i2c_adapter *adap)
570 {
571 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
572 }
573
574 static void terminate_read(struct davinci_i2c_dev *dev)
575 {
576 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
577 w |= DAVINCI_I2C_MDR_NACK;
578 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
579
580 /* Throw away data */
581 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
582 if (!dev->terminate)
583 dev_err(dev->dev, "RDR IRQ while no data requested\n");
584 }
585 static void terminate_write(struct davinci_i2c_dev *dev)
586 {
587 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
588 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
589 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
590
591 if (!dev->terminate)
592 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
593 }
594
595 /*
596 * Interrupt service routine. This gets called whenever an I2C interrupt
597 * occurs.
598 */
599 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
600 {
601 struct davinci_i2c_dev *dev = dev_id;
602 u32 stat;
603 int count = 0;
604 u16 w;
605
606 if (pm_runtime_suspended(dev->dev))
607 return IRQ_NONE;
608
609 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
610 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
611 if (count++ == 100) {
612 dev_warn(dev->dev, "Too much work in one IRQ\n");
613 break;
614 }
615
616 switch (stat) {
617 case DAVINCI_I2C_IVR_AL:
618 /* Arbitration lost, must retry */
619 dev->cmd_err |= DAVINCI_I2C_STR_AL;
620 dev->buf_len = 0;
621 complete(&dev->cmd_complete);
622 break;
623
624 case DAVINCI_I2C_IVR_NACK:
625 dev->cmd_err |= DAVINCI_I2C_STR_NACK;
626 dev->buf_len = 0;
627 complete(&dev->cmd_complete);
628 break;
629
630 case DAVINCI_I2C_IVR_ARDY:
631 davinci_i2c_write_reg(dev,
632 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
633 if (((dev->buf_len == 0) && (dev->stop != 0)) ||
634 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
635 w = davinci_i2c_read_reg(dev,
636 DAVINCI_I2C_MDR_REG);
637 w |= DAVINCI_I2C_MDR_STP;
638 davinci_i2c_write_reg(dev,
639 DAVINCI_I2C_MDR_REG, w);
640 }
641 complete(&dev->cmd_complete);
642 break;
643
644 case DAVINCI_I2C_IVR_RDR:
645 if (dev->buf_len) {
646 *dev->buf++ =
647 davinci_i2c_read_reg(dev,
648 DAVINCI_I2C_DRR_REG);
649 dev->buf_len--;
650 if (dev->buf_len)
651 continue;
652
653 davinci_i2c_write_reg(dev,
654 DAVINCI_I2C_STR_REG,
655 DAVINCI_I2C_IMR_RRDY);
656 } else {
657 /* signal can terminate transfer */
658 terminate_read(dev);
659 }
660 break;
661
662 case DAVINCI_I2C_IVR_XRDY:
663 if (dev->buf_len) {
664 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
665 *dev->buf++);
666 dev->buf_len--;
667 if (dev->buf_len)
668 continue;
669
670 w = davinci_i2c_read_reg(dev,
671 DAVINCI_I2C_IMR_REG);
672 w &= ~DAVINCI_I2C_IMR_XRDY;
673 davinci_i2c_write_reg(dev,
674 DAVINCI_I2C_IMR_REG,
675 w);
676 } else {
677 /* signal can terminate transfer */
678 terminate_write(dev);
679 }
680 break;
681
682 case DAVINCI_I2C_IVR_SCD:
683 davinci_i2c_write_reg(dev,
684 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
685 complete(&dev->cmd_complete);
686 break;
687
688 case DAVINCI_I2C_IVR_AAS:
689 dev_dbg(dev->dev, "Address as target interrupt\n");
690 break;
691
692 default:
693 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
694 break;
695 }
696 }
697
698 return count ? IRQ_HANDLED : IRQ_NONE;
699 }
700
701 #ifdef CONFIG_CPU_FREQ
702 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
703 unsigned long val, void *data)
704 {
705 struct davinci_i2c_dev *dev;
706
707 dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
708
709 i2c_lock_bus(&dev->adapter, I2C_LOCK_ROOT_ADAPTER);
710 if (val == CPUFREQ_PRECHANGE) {
711 davinci_i2c_reset_ctrl(dev, 0);
712 } else if (val == CPUFREQ_POSTCHANGE) {
713 i2c_davinci_calc_clk_dividers(dev);
714 davinci_i2c_reset_ctrl(dev, 1);
715 }
716 i2c_unlock_bus(&dev->adapter, I2C_LOCK_ROOT_ADAPTER);
717
718 return 0;
719 }
720
721 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
722 {
723 dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
724
725 return cpufreq_register_notifier(&dev->freq_transition,
726 CPUFREQ_TRANSITION_NOTIFIER);
727 }
728
729 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
730 {
731 cpufreq_unregister_notifier(&dev->freq_transition,
732 CPUFREQ_TRANSITION_NOTIFIER);
733 }
734 #else
735 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
736 {
737 return 0;
738 }
739
740 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
741 {
742 }
743 #endif
744
745 static const struct i2c_algorithm i2c_davinci_algo = {
746 .xfer = i2c_davinci_xfer,
747 .functionality = i2c_davinci_func,
748 };
749
750 static const struct of_device_id davinci_i2c_of_match[] = {
751 {.compatible = "ti,davinci-i2c", },
752 {.compatible = "ti,keystone-i2c", },
753 {},
754 };
755 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
756
757 static int davinci_i2c_probe(struct platform_device *pdev)
758 {
759 struct davinci_i2c_dev *dev;
760 struct i2c_adapter *adap;
761 struct i2c_bus_recovery_info *rinfo;
762 int r, irq;
763
764 irq = platform_get_irq(pdev, 0);
765 if (irq < 0)
766 return irq;
767
768 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
769 if (!dev)
770 return -ENOMEM;
771
772 init_completion(&dev->cmd_complete);
773
774 dev->dev = &pdev->dev;
775 dev->irq = irq;
776 dev->pdata = dev_get_platdata(&pdev->dev);
777 platform_set_drvdata(pdev, dev);
778
779 if (!dev->pdata && pdev->dev.of_node) {
780 u32 prop;
781
782 dev->pdata = devm_kzalloc(&pdev->dev,
783 sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
784 if (!dev->pdata)
785 return -ENOMEM;
786
787 memcpy(dev->pdata, &davinci_i2c_platform_data_default,
788 sizeof(struct davinci_i2c_platform_data));
789 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
790 &prop))
791 dev->pdata->bus_freq = prop / 1000;
792
793 dev->pdata->has_pfunc =
794 of_property_read_bool(pdev->dev.of_node,
795 "ti,has-pfunc");
796 } else if (!dev->pdata) {
797 dev->pdata = &davinci_i2c_platform_data_default;
798 }
799
800 dev->clk = devm_clk_get(&pdev->dev, NULL);
801 if (IS_ERR(dev->clk))
802 return PTR_ERR(dev->clk);
803
804 dev->base = devm_platform_ioremap_resource(pdev, 0);
805 if (IS_ERR(dev->base)) {
806 return PTR_ERR(dev->base);
807 }
808
809 pm_runtime_set_autosuspend_delay(dev->dev,
810 DAVINCI_I2C_PM_TIMEOUT);
811 pm_runtime_use_autosuspend(dev->dev);
812
813 pm_runtime_enable(dev->dev);
814
815 r = pm_runtime_resume_and_get(dev->dev);
816 if (r < 0) {
817 dev_err(dev->dev, "failed to runtime_get device: %d\n", r);
818 goto err_pm;
819 }
820
821 i2c_davinci_init(dev);
822
823 r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
824 pdev->name, dev);
825 if (r) {
826 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
827 goto err_unuse_clocks;
828 }
829
830 r = i2c_davinci_cpufreq_register(dev);
831 if (r) {
832 dev_err(&pdev->dev, "failed to register cpufreq\n");
833 goto err_unuse_clocks;
834 }
835
836 adap = &dev->adapter;
837 i2c_set_adapdata(adap, dev);
838 adap->owner = THIS_MODULE;
839 adap->class = I2C_CLASS_DEPRECATED;
840 strscpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
841 adap->algo = &i2c_davinci_algo;
842 adap->dev.parent = &pdev->dev;
843 adap->timeout = DAVINCI_I2C_TIMEOUT;
844 adap->dev.of_node = pdev->dev.of_node;
845
846 if (dev->pdata->has_pfunc)
847 adap->bus_recovery_info = &davinci_i2c_scl_recovery_info;
848 else if (dev->pdata->gpio_recovery) {
849 rinfo = &davinci_i2c_gpio_recovery_info;
850 adap->bus_recovery_info = rinfo;
851 rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl",
852 GPIOD_OUT_HIGH_OPEN_DRAIN);
853 if (IS_ERR(rinfo->scl_gpiod)) {
854 r = PTR_ERR(rinfo->scl_gpiod);
855 goto err_unuse_clocks;
856 }
857 rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
858 if (IS_ERR(rinfo->sda_gpiod)) {
859 r = PTR_ERR(rinfo->sda_gpiod);
860 goto err_unuse_clocks;
861 }
862 }
863
864 adap->nr = pdev->id;
865 r = i2c_add_numbered_adapter(adap);
866 if (r)
867 goto err_unuse_clocks;
868
869 pm_runtime_mark_last_busy(dev->dev);
870 pm_runtime_put_autosuspend(dev->dev);
871
872 return 0;
873
874 err_unuse_clocks:
875 pm_runtime_dont_use_autosuspend(dev->dev);
876 pm_runtime_put_sync(dev->dev);
877 err_pm:
878 pm_runtime_disable(dev->dev);
879
880 return r;
881 }
882
883 static void davinci_i2c_remove(struct platform_device *pdev)
884 {
885 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
886 int ret;
887
888 i2c_davinci_cpufreq_deregister(dev);
889
890 i2c_del_adapter(&dev->adapter);
891
892 ret = pm_runtime_get_sync(&pdev->dev);
893 if (ret < 0)
894 dev_err(&pdev->dev, "Failed to resume device\n");
895 else
896 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
897
898 pm_runtime_dont_use_autosuspend(dev->dev);
899 pm_runtime_put_sync(dev->dev);
900 pm_runtime_disable(dev->dev);
901 }
902
903 static int davinci_i2c_suspend(struct device *dev)
904 {
905 struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev);
906
907 /* put I2C into reset */
908 davinci_i2c_reset_ctrl(i2c_dev, 0);
909
910 return 0;
911 }
912
913 static int davinci_i2c_resume(struct device *dev)
914 {
915 struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev);
916
917 /* take I2C out of reset */
918 davinci_i2c_reset_ctrl(i2c_dev, 1);
919
920 return 0;
921 }
922
923 static const struct dev_pm_ops davinci_i2c_pm = {
924 .suspend = davinci_i2c_suspend,
925 .resume = davinci_i2c_resume,
926 NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
927 pm_runtime_force_resume)
928 };
929
930 static const struct platform_device_id davinci_i2c_driver_ids[] = {
931 { .name = "i2c_davinci", },
932 { /* sentinel */ }
933 };
934 MODULE_DEVICE_TABLE(platform, davinci_i2c_driver_ids);
935
936 static struct platform_driver davinci_i2c_driver = {
937 .probe = davinci_i2c_probe,
938 .remove_new = davinci_i2c_remove,
939 .id_table = davinci_i2c_driver_ids,
940 .driver = {
941 .name = "i2c_davinci",
942 .pm = pm_sleep_ptr(&davinci_i2c_pm),
943 .of_match_table = davinci_i2c_of_match,
944 },
945 };
946
947 /* I2C may be needed to bring up other drivers */
948 static int __init davinci_i2c_init_driver(void)
949 {
950 return platform_driver_register(&davinci_i2c_driver);
951 }
952 subsys_initcall(davinci_i2c_init_driver);
953
954 static void __exit davinci_i2c_exit_driver(void)
955 {
956 platform_driver_unregister(&davinci_i2c_driver);
957 }
958 module_exit(davinci_i2c_exit_driver);
959
960 MODULE_AUTHOR("Texas Instruments India");
961 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
962 MODULE_LICENSE("GPL");
Kernel DRM miscellaneous fixes and cross-tree changes