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drm/tests: hdmi: Fix memory leaks in drm_display_mode_from_cea_vic()
[drm/drm-misc.git] / drivers / i2c / busses / i2c-mv64xxx.c
blob29f94efedf605a499b3be173a6da7f039aea4a55
1 /*
2 * Driver for the i2c controller on the Marvell line of host bridges
3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/mv643xx_i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/property.h>
23 #include <linux/reset.h>
24 #include <linux/io.h>
25 #include <linux/of.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/delay.h>
29
30 #define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1)
31 #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
32 #define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
33
34 #define MV64XXX_I2C_REG_CONTROL_ACK BIT(2)
35 #define MV64XXX_I2C_REG_CONTROL_IFLG BIT(3)
36 #define MV64XXX_I2C_REG_CONTROL_STOP BIT(4)
37 #define MV64XXX_I2C_REG_CONTROL_START BIT(5)
38 #define MV64XXX_I2C_REG_CONTROL_TWSIEN BIT(6)
39 #define MV64XXX_I2C_REG_CONTROL_INTEN BIT(7)
40
41 /* Ctlr status values */
42 #define MV64XXX_I2C_STATUS_BUS_ERR 0x00
43 #define MV64XXX_I2C_STATUS_MAST_START 0x08
44 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
45 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
46 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
47 #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
48 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
49 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
50 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
51 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
52 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
53 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
54 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
55 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
56 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
57 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
58 #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
59
60 /* Register defines (I2C bridge) */
61 #define MV64XXX_I2C_REG_TX_DATA_LO 0xc0
62 #define MV64XXX_I2C_REG_TX_DATA_HI 0xc4
63 #define MV64XXX_I2C_REG_RX_DATA_LO 0xc8
64 #define MV64XXX_I2C_REG_RX_DATA_HI 0xcc
65 #define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0
66 #define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4
67 #define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8
68 #define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC
69 #define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0
70
71 /* Bridge Control values */
72 #define MV64XXX_I2C_BRIDGE_CONTROL_WR BIT(0)
73 #define MV64XXX_I2C_BRIDGE_CONTROL_RD BIT(1)
74 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2
75 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT BIT(12)
76 #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13
77 #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16
78 #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19)
79 #define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START BIT(20)
80
81 /* Bridge Status values */
82 #define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0)
83
84 /* Driver states */
85 enum {
86 MV64XXX_I2C_STATE_INVALID,
87 MV64XXX_I2C_STATE_IDLE,
88 MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
89 MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
90 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
91 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
92 MV64XXX_I2C_STATE_WAITING_FOR_TARGET_ACK,
93 MV64XXX_I2C_STATE_WAITING_FOR_TARGET_DATA,
94 };
95
96 /* Driver actions */
97 enum {
98 MV64XXX_I2C_ACTION_INVALID,
99 MV64XXX_I2C_ACTION_CONTINUE,
100 MV64XXX_I2C_ACTION_SEND_RESTART,
101 MV64XXX_I2C_ACTION_SEND_ADDR_1,
102 MV64XXX_I2C_ACTION_SEND_ADDR_2,
103 MV64XXX_I2C_ACTION_SEND_DATA,
104 MV64XXX_I2C_ACTION_RCV_DATA,
105 MV64XXX_I2C_ACTION_RCV_DATA_STOP,
106 MV64XXX_I2C_ACTION_SEND_STOP,
107 };
108
109 struct mv64xxx_i2c_regs {
110 u8 addr;
111 u8 ext_addr;
112 u8 data;
113 u8 control;
114 u8 status;
115 u8 clock;
116 u8 soft_reset;
117 };
118
119 struct mv64xxx_i2c_data {
120 struct i2c_msg *msgs;
121 int num_msgs;
122 int irq;
123 u32 state;
124 u32 action;
125 u32 aborting;
126 u32 cntl_bits;
127 void __iomem *reg_base;
128 struct mv64xxx_i2c_regs reg_offsets;
129 u32 addr1;
130 u32 addr2;
131 u32 bytes_left;
132 u32 byte_posn;
133 u32 send_stop;
134 u32 block;
135 int rc;
136 u32 freq_m;
137 u32 freq_n;
138 struct clk *clk;
139 struct clk *reg_clk;
140 wait_queue_head_t waitq;
141 spinlock_t lock;
142 struct i2c_msg *msg;
143 struct i2c_adapter adapter;
144 bool offload_enabled;
145 /* 5us delay in order to avoid repeated start timing violation */
146 bool errata_delay;
147 struct reset_control *rstc;
148 bool irq_clear_inverted;
149 /* Clk div is 2 to the power n, not 2 to the power n + 1 */
150 bool clk_n_base_0;
151 struct i2c_bus_recovery_info rinfo;
152 bool atomic;
153 };
154
155 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
156 .addr = 0x00,
157 .ext_addr = 0x10,
158 .data = 0x04,
159 .control = 0x08,
160 .status = 0x0c,
161 .clock = 0x0c,
162 .soft_reset = 0x1c,
163 };
164
165 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
166 .addr = 0x00,
167 .ext_addr = 0x04,
168 .data = 0x08,
169 .control = 0x0c,
170 .status = 0x10,
171 .clock = 0x14,
172 .soft_reset = 0x18,
173 };
174
175 static void
176 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
177 struct i2c_msg *msg)
178 {
179 u32 dir = 0;
180
181 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
182 MV64XXX_I2C_REG_CONTROL_TWSIEN;
183
184 if (!drv_data->atomic)
185 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_INTEN;
186
187 if (msg->flags & I2C_M_RD)
188 dir = 1;
189
190 if (msg->flags & I2C_M_TEN) {
191 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
192 drv_data->addr2 = (u32)msg->addr & 0xff;
193 } else {
194 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
195 drv_data->addr2 = 0;
196 }
197 }
198
199 /*
200 *****************************************************************************
201 *
202 * Finite State Machine & Interrupt Routines
203 *
204 *****************************************************************************
205 */
206
207 /* Reset hardware and initialize FSM */
208 static void
209 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
210 {
211 if (drv_data->offload_enabled) {
212 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
213 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
214 writel(0, drv_data->reg_base +
215 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
216 writel(0, drv_data->reg_base +
217 MV64XXX_I2C_REG_BRIDGE_INTR_MASK);
218 }
219
220 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
221 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
222 drv_data->reg_base + drv_data->reg_offsets.clock);
223 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
224 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
225 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
226 drv_data->reg_base + drv_data->reg_offsets.control);
227
228 if (drv_data->errata_delay)
229 udelay(5);
230
231 drv_data->state = MV64XXX_I2C_STATE_IDLE;
232 }
233
234 static void
235 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
236 {
237 /*
238 * If state is idle, then this is likely the remnants of an old
239 * operation that driver has given up on or the user has killed.
240 * If so, issue the stop condition and go to idle.
241 */
242 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
243 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
244 return;
245 }
246
247 /* The status from the ctlr [mostly] tells us what to do next */
248 switch (status) {
249 /* Start condition interrupt */
250 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
251 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
252 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
253 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
254 break;
255
256 /* Performing a write */
257 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
258 if (drv_data->msg->flags & I2C_M_TEN) {
259 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
260 drv_data->state =
261 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
262 break;
263 }
264 fallthrough;
265 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
266 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
267 if ((drv_data->bytes_left == 0)
268 || (drv_data->aborting
269 && (drv_data->byte_posn != 0))) {
270 if (drv_data->send_stop || drv_data->aborting) {
271 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
272 drv_data->state = MV64XXX_I2C_STATE_IDLE;
273 } else {
274 drv_data->action =
275 MV64XXX_I2C_ACTION_SEND_RESTART;
276 drv_data->state =
277 MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
278 }
279 } else {
280 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
281 drv_data->state =
282 MV64XXX_I2C_STATE_WAITING_FOR_TARGET_ACK;
283 drv_data->bytes_left--;
284 }
285 break;
286
287 /* Performing a read */
288 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
289 if (drv_data->msg->flags & I2C_M_TEN) {
290 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
291 drv_data->state =
292 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
293 break;
294 }
295 fallthrough;
296 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
297 if (drv_data->bytes_left == 0) {
298 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
299 drv_data->state = MV64XXX_I2C_STATE_IDLE;
300 break;
301 }
302 fallthrough;
303 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
304 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
305 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
306 else {
307 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
308 drv_data->bytes_left--;
309 }
310 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_TARGET_DATA;
311
312 if ((drv_data->bytes_left == 1) || drv_data->aborting)
313 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
314 break;
315
316 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
317 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
318 drv_data->state = MV64XXX_I2C_STATE_IDLE;
319 break;
320
321 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
322 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
323 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
324 /* Doesn't seem to be a device at other end */
325 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
326 drv_data->state = MV64XXX_I2C_STATE_IDLE;
327 drv_data->rc = -ENXIO;
328 break;
329
330 default:
331 dev_err(&drv_data->adapter.dev,
332 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
333 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
334 drv_data->state, status, drv_data->msg->addr,
335 drv_data->msg->flags);
336 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
337 mv64xxx_i2c_hw_init(drv_data);
338 i2c_recover_bus(&drv_data->adapter);
339 drv_data->rc = -EAGAIN;
340 }
341 }
342
343 static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
344 {
345 drv_data->msg = drv_data->msgs;
346 drv_data->byte_posn = 0;
347 drv_data->bytes_left = drv_data->msg->len;
348 drv_data->aborting = 0;
349 drv_data->rc = 0;
350
351 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
352 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
353 drv_data->reg_base + drv_data->reg_offsets.control);
354 }
355
356 static void
357 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
358 {
359 switch(drv_data->action) {
360 case MV64XXX_I2C_ACTION_SEND_RESTART:
361 /* We should only get here if we have further messages */
362 BUG_ON(drv_data->num_msgs == 0);
363
364 drv_data->msgs++;
365 drv_data->num_msgs--;
366 mv64xxx_i2c_send_start(drv_data);
367
368 if (drv_data->errata_delay)
369 udelay(5);
370
371 /*
372 * We're never at the start of the message here, and by this
373 * time it's already too late to do any protocol mangling.
374 * Thankfully, do not advertise support for that feature.
375 */
376 drv_data->send_stop = drv_data->num_msgs == 1;
377 break;
378
379 case MV64XXX_I2C_ACTION_CONTINUE:
380 writel(drv_data->cntl_bits,
381 drv_data->reg_base + drv_data->reg_offsets.control);
382 break;
383
384 case MV64XXX_I2C_ACTION_SEND_ADDR_1:
385 writel(drv_data->addr1,
386 drv_data->reg_base + drv_data->reg_offsets.data);
387 writel(drv_data->cntl_bits,
388 drv_data->reg_base + drv_data->reg_offsets.control);
389 break;
390
391 case MV64XXX_I2C_ACTION_SEND_ADDR_2:
392 writel(drv_data->addr2,
393 drv_data->reg_base + drv_data->reg_offsets.data);
394 writel(drv_data->cntl_bits,
395 drv_data->reg_base + drv_data->reg_offsets.control);
396 break;
397
398 case MV64XXX_I2C_ACTION_SEND_DATA:
399 writel(drv_data->msg->buf[drv_data->byte_posn++],
400 drv_data->reg_base + drv_data->reg_offsets.data);
401 writel(drv_data->cntl_bits,
402 drv_data->reg_base + drv_data->reg_offsets.control);
403 break;
404
405 case MV64XXX_I2C_ACTION_RCV_DATA:
406 drv_data->msg->buf[drv_data->byte_posn++] =
407 readl(drv_data->reg_base + drv_data->reg_offsets.data);
408 writel(drv_data->cntl_bits,
409 drv_data->reg_base + drv_data->reg_offsets.control);
410 break;
411
412 case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
413 drv_data->msg->buf[drv_data->byte_posn++] =
414 readl(drv_data->reg_base + drv_data->reg_offsets.data);
415 if (!drv_data->atomic)
416 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
417 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
418 drv_data->reg_base + drv_data->reg_offsets.control);
419 drv_data->block = 0;
420 if (drv_data->errata_delay)
421 udelay(5);
422
423 wake_up(&drv_data->waitq);
424 break;
425
426 case MV64XXX_I2C_ACTION_INVALID:
427 default:
428 dev_err(&drv_data->adapter.dev,
429 "mv64xxx_i2c_do_action: Invalid action: %d\n",
430 drv_data->action);
431 drv_data->rc = -EIO;
432 fallthrough;
433 case MV64XXX_I2C_ACTION_SEND_STOP:
434 if (!drv_data->atomic)
435 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
436 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
437 drv_data->reg_base + drv_data->reg_offsets.control);
438 drv_data->block = 0;
439 wake_up(&drv_data->waitq);
440 break;
441 }
442 }
443
444 static void
445 mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data,
446 struct i2c_msg *msg)
447 {
448 u32 buf[2];
449
450 buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO);
451 buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI);
452
453 memcpy(msg->buf, buf, msg->len);
454 }
455
456 static int
457 mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data)
458 {
459 u32 cause, status;
460
461 cause = readl(drv_data->reg_base +
462 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
463 if (!cause)
464 return IRQ_NONE;
465
466 status = readl(drv_data->reg_base +
467 MV64XXX_I2C_REG_BRIDGE_STATUS);
468
469 if (status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) {
470 drv_data->rc = -EIO;
471 goto out;
472 }
473
474 drv_data->rc = 0;
475
476 /*
477 * Transaction is a one message read transaction, read data
478 * for this message.
479 */
480 if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) {
481 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs);
482 drv_data->msgs++;
483 drv_data->num_msgs--;
484 }
485 /*
486 * Transaction is a two messages write/read transaction, read
487 * data for the second (read) message.
488 */
489 else if (drv_data->num_msgs == 2 &&
490 !(drv_data->msgs[0].flags & I2C_M_RD) &&
491 drv_data->msgs[1].flags & I2C_M_RD) {
492 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1);
493 drv_data->msgs += 2;
494 drv_data->num_msgs -= 2;
495 }
496
497 out:
498 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
499 writel(0, drv_data->reg_base +
500 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
501 drv_data->block = 0;
502
503 wake_up(&drv_data->waitq);
504
505 return IRQ_HANDLED;
506 }
507
508 static irqreturn_t
509 mv64xxx_i2c_intr(int irq, void *dev_id)
510 {
511 struct mv64xxx_i2c_data *drv_data = dev_id;
512 u32 status;
513 irqreturn_t rc = IRQ_NONE;
514
515 spin_lock(&drv_data->lock);
516
517 if (drv_data->offload_enabled)
518 rc = mv64xxx_i2c_intr_offload(drv_data);
519
520 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
521 MV64XXX_I2C_REG_CONTROL_IFLG) {
522 /*
523 * It seems that sometime the controller updates the status
524 * register only after it asserts IFLG in control register.
525 * This may result in weird bugs when in atomic mode. A delay
526 * of 100 ns before reading the status register solves this
527 * issue. This bug does not seem to appear when using
528 * interrupts.
529 */
530 if (drv_data->atomic)
531 ndelay(100);
532
533 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
534 mv64xxx_i2c_fsm(drv_data, status);
535 mv64xxx_i2c_do_action(drv_data);
536
537 if (drv_data->irq_clear_inverted)
538 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
539 drv_data->reg_base + drv_data->reg_offsets.control);
540
541 rc = IRQ_HANDLED;
542 }
543 spin_unlock(&drv_data->lock);
544
545 return rc;
546 }
547
548 /*
549 *****************************************************************************
550 *
551 * I2C Msg Execution Routines
552 *
553 *****************************************************************************
554 */
555 static void
556 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
557 {
558 long time_left;
559 unsigned long flags;
560 char abort = 0;
561
562 time_left = wait_event_timeout(drv_data->waitq,
563 !drv_data->block, drv_data->adapter.timeout);
564
565 spin_lock_irqsave(&drv_data->lock, flags);
566 if (!time_left) { /* Timed out */
567 drv_data->rc = -ETIMEDOUT;
568 abort = 1;
569 } else if (time_left < 0) { /* Interrupted/Error */
570 drv_data->rc = time_left; /* errno value */
571 abort = 1;
572 }
573
574 if (abort && drv_data->block) {
575 drv_data->aborting = 1;
576 spin_unlock_irqrestore(&drv_data->lock, flags);
577
578 time_left = wait_event_timeout(drv_data->waitq,
579 !drv_data->block, drv_data->adapter.timeout);
580
581 if ((time_left <= 0) && drv_data->block) {
582 drv_data->state = MV64XXX_I2C_STATE_IDLE;
583 dev_err(&drv_data->adapter.dev,
584 "mv64xxx: I2C bus locked, block: %d, "
585 "time_left: %d\n", drv_data->block,
586 (int)time_left);
587 mv64xxx_i2c_hw_init(drv_data);
588 i2c_recover_bus(&drv_data->adapter);
589 }
590 } else
591 spin_unlock_irqrestore(&drv_data->lock, flags);
592 }
593
594 static void mv64xxx_i2c_wait_polling(struct mv64xxx_i2c_data *drv_data)
595 {
596 ktime_t timeout = ktime_add_ms(ktime_get(), drv_data->adapter.timeout);
597
598 while (READ_ONCE(drv_data->block) &&
599 ktime_compare(ktime_get(), timeout) < 0) {
600 udelay(5);
601 mv64xxx_i2c_intr(0, drv_data);
602 }
603 }
604
605 static int
606 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
607 int is_last)
608 {
609 unsigned long flags;
610
611 spin_lock_irqsave(&drv_data->lock, flags);
612
613 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
614
615 drv_data->send_stop = is_last;
616 drv_data->block = 1;
617 mv64xxx_i2c_send_start(drv_data);
618 spin_unlock_irqrestore(&drv_data->lock, flags);
619
620 if (!drv_data->atomic)
621 mv64xxx_i2c_wait_for_completion(drv_data);
622 else
623 mv64xxx_i2c_wait_polling(drv_data);
624
625 return drv_data->rc;
626 }
627
628 static void
629 mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data)
630 {
631 struct i2c_msg *msg = drv_data->msgs;
632 u32 buf[2];
633
634 memcpy(buf, msg->buf, msg->len);
635
636 writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
637 writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
638 }
639
640 static int
641 mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data)
642 {
643 struct i2c_msg *msgs = drv_data->msgs;
644 int num = drv_data->num_msgs;
645 unsigned long ctrl_reg;
646 unsigned long flags;
647
648 spin_lock_irqsave(&drv_data->lock, flags);
649
650 /* Build transaction */
651 ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
652 (msgs[0].addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
653
654 if (msgs[0].flags & I2C_M_TEN)
655 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
656
657 /* Single write message transaction */
658 if (num == 1 && !(msgs[0].flags & I2C_M_RD)) {
659 size_t len = msgs[0].len - 1;
660
661 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
662 (len << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT);
663 mv64xxx_i2c_prepare_tx(drv_data);
664 }
665 /* Single read message transaction */
666 else if (num == 1 && msgs[0].flags & I2C_M_RD) {
667 size_t len = msgs[0].len - 1;
668
669 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
670 (len << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT);
671 }
672 /*
673 * Transaction with one write and one read message. This is
674 * guaranteed by the mv64xx_i2c_can_offload() checks.
675 */
676 else if (num == 2) {
677 size_t lentx = msgs[0].len - 1;
678 size_t lenrx = msgs[1].len - 1;
679
680 ctrl_reg |=
681 MV64XXX_I2C_BRIDGE_CONTROL_RD |
682 MV64XXX_I2C_BRIDGE_CONTROL_WR |
683 (lentx << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT) |
684 (lenrx << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT) |
685 MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START;
686 mv64xxx_i2c_prepare_tx(drv_data);
687 }
688
689 /* Execute transaction */
690 drv_data->block = 1;
691 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
692 spin_unlock_irqrestore(&drv_data->lock, flags);
693
694 mv64xxx_i2c_wait_for_completion(drv_data);
695
696 return drv_data->rc;
697 }
698
699 static bool
700 mv64xxx_i2c_valid_offload_sz(struct i2c_msg *msg)
701 {
702 return msg->len <= 8 && msg->len >= 1;
703 }
704
705 static bool
706 mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data)
707 {
708 struct i2c_msg *msgs = drv_data->msgs;
709 int num = drv_data->num_msgs;
710
711 if (!drv_data->offload_enabled)
712 return false;
713
714 /*
715 * We can offload a transaction consisting of a single
716 * message, as long as the message has a length between 1 and
717 * 8 bytes.
718 */
719 if (num == 1 && mv64xxx_i2c_valid_offload_sz(msgs))
720 return true;
721
722 /*
723 * We can offload a transaction consisting of two messages, if
724 * the first is a write and a second is a read, and both have
725 * a length between 1 and 8 bytes.
726 */
727 if (num == 2 &&
728 mv64xxx_i2c_valid_offload_sz(msgs) &&
729 mv64xxx_i2c_valid_offload_sz(msgs + 1) &&
730 !(msgs[0].flags & I2C_M_RD) &&
731 msgs[1].flags & I2C_M_RD)
732 return true;
733
734 return false;
735 }
736
737 /*
738 *****************************************************************************
739 *
740 * I2C Core Support Routines (Interface to higher level I2C code)
741 *
742 *****************************************************************************
743 */
744 static u32
745 mv64xxx_i2c_functionality(struct i2c_adapter *adap)
746 {
747 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
748 }
749
750 static int
751 mv64xxx_i2c_xfer_core(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
752 {
753 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
754 int rc, ret = num;
755
756 rc = pm_runtime_resume_and_get(&adap->dev);
757 if (rc)
758 return rc;
759
760 BUG_ON(drv_data->msgs != NULL);
761 drv_data->msgs = msgs;
762 drv_data->num_msgs = num;
763
764 if (mv64xxx_i2c_can_offload(drv_data) && !drv_data->atomic)
765 rc = mv64xxx_i2c_offload_xfer(drv_data);
766 else
767 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
768
769 if (rc < 0)
770 ret = rc;
771
772 drv_data->num_msgs = 0;
773 drv_data->msgs = NULL;
774
775 pm_runtime_mark_last_busy(&adap->dev);
776 pm_runtime_put_autosuspend(&adap->dev);
777
778 return ret;
779 }
780
781 static int
782 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
783 {
784 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
785
786 drv_data->atomic = 0;
787 return mv64xxx_i2c_xfer_core(adap, msgs, num);
788 }
789
790 static int mv64xxx_i2c_xfer_atomic(struct i2c_adapter *adap,
791 struct i2c_msg msgs[], int num)
792 {
793 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
794
795 drv_data->atomic = 1;
796 return mv64xxx_i2c_xfer_core(adap, msgs, num);
797 }
798
799 static const struct i2c_algorithm mv64xxx_i2c_algo = {
800 .xfer = mv64xxx_i2c_xfer,
801 .xfer_atomic = mv64xxx_i2c_xfer_atomic,
802 .functionality = mv64xxx_i2c_functionality,
803 };
804
805 /*
806 *****************************************************************************
807 *
808 * Driver Interface & Early Init Routines
809 *
810 *****************************************************************************
811 */
812 static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
813 { .compatible = "allwinner,sun4i-a10-i2c", .data = &mv64xxx_i2c_regs_sun4i},
814 { .compatible = "allwinner,sun6i-a31-i2c", .data = &mv64xxx_i2c_regs_sun4i},
815 { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
816 { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
817 { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
818 {}
819 };
820 MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
821
822 #ifdef CONFIG_OF
823 static int
824 mv64xxx_calc_freq(struct mv64xxx_i2c_data *drv_data,
825 const int tclk, const int n, const int m)
826 {
827 if (drv_data->clk_n_base_0)
828 return tclk / (10 * (m + 1) * (1 << n));
829 else
830 return tclk / (10 * (m + 1) * (2 << n));
831 }
832
833 static bool
834 mv64xxx_find_baud_factors(struct mv64xxx_i2c_data *drv_data,
835 const u32 req_freq, const u32 tclk)
836 {
837 int freq, delta, best_delta = INT_MAX;
838 int m, n;
839
840 for (n = 0; n <= 7; n++)
841 for (m = 0; m <= 15; m++) {
842 freq = mv64xxx_calc_freq(drv_data, tclk, n, m);
843 delta = req_freq - freq;
844 if (delta >= 0 && delta < best_delta) {
845 drv_data->freq_m = m;
846 drv_data->freq_n = n;
847 best_delta = delta;
848 }
849 if (best_delta == 0)
850 return true;
851 }
852 if (best_delta == INT_MAX)
853 return false;
854 return true;
855 }
856
857 static int
858 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
859 struct device *dev)
860 {
861 const struct mv64xxx_i2c_regs *data;
862 struct device_node *np = dev->of_node;
863 u32 bus_freq, tclk;
864 int rc = 0;
865
866 /* CLK is mandatory when using DT to describe the i2c bus. We
867 * need to know tclk in order to calculate bus clock
868 * factors.
869 */
870 if (!drv_data->clk) {
871 rc = -ENODEV;
872 goto out;
873 }
874 tclk = clk_get_rate(drv_data->clk);
875
876 if (of_property_read_u32(np, "clock-frequency", &bus_freq))
877 bus_freq = I2C_MAX_STANDARD_MODE_FREQ; /* 100kHz by default */
878
879 if (of_device_is_compatible(np, "allwinner,sun4i-a10-i2c") ||
880 of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
881 drv_data->clk_n_base_0 = true;
882
883 if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) {
884 rc = -EINVAL;
885 goto out;
886 }
887
888 drv_data->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
889 if (IS_ERR(drv_data->rstc)) {
890 rc = PTR_ERR(drv_data->rstc);
891 goto out;
892 }
893
894 /* Its not yet defined how timeouts will be specified in device tree.
895 * So hard code the value to 1 second.
896 */
897 drv_data->adapter.timeout = HZ;
898
899 data = device_get_match_data(dev);
900 if (!data)
901 return -ENODEV;
902
903 memcpy(&drv_data->reg_offsets, data, sizeof(drv_data->reg_offsets));
904
905 /*
906 * For controllers embedded in new SoCs activate the
907 * Transaction Generator support and the errata fix.
908 */
909 if (of_device_is_compatible(np, "marvell,mv78230-i2c")) {
910 drv_data->offload_enabled = true;
911 /* The delay is only needed in standard mode (100kHz) */
912 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
913 drv_data->errata_delay = true;
914 }
915
916 if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
917 drv_data->offload_enabled = false;
918 /* The delay is only needed in standard mode (100kHz) */
919 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
920 drv_data->errata_delay = true;
921 }
922
923 if (of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
924 drv_data->irq_clear_inverted = true;
925
926 out:
927 return rc;
928 }
929 #else /* CONFIG_OF */
930 static int
931 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
932 struct device *dev)
933 {
934 return -ENODEV;
935 }
936 #endif /* CONFIG_OF */
937
938 static int mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data *drv_data,
939 struct device *dev)
940 {
941 struct i2c_bus_recovery_info *rinfo = &drv_data->rinfo;
942
943 rinfo->pinctrl = devm_pinctrl_get(dev);
944 if (IS_ERR(rinfo->pinctrl)) {
945 if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER)
946 return -EPROBE_DEFER;
947 dev_info(dev, "can't get pinctrl, bus recovery not supported\n");
948 return PTR_ERR(rinfo->pinctrl);
949 } else if (!rinfo->pinctrl) {
950 return -ENODEV;
951 }
952
953 drv_data->adapter.bus_recovery_info = rinfo;
954 return 0;
955 }
956
957 static int
958 mv64xxx_i2c_runtime_suspend(struct device *dev)
959 {
960 struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
961
962 reset_control_assert(drv_data->rstc);
963 clk_disable_unprepare(drv_data->reg_clk);
964 clk_disable_unprepare(drv_data->clk);
965
966 return 0;
967 }
968
969 static int
970 mv64xxx_i2c_runtime_resume(struct device *dev)
971 {
972 struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
973
974 clk_prepare_enable(drv_data->clk);
975 clk_prepare_enable(drv_data->reg_clk);
976 reset_control_reset(drv_data->rstc);
977
978 mv64xxx_i2c_hw_init(drv_data);
979
980 return 0;
981 }
982
983 static int
984 mv64xxx_i2c_probe(struct platform_device *pd)
985 {
986 struct mv64xxx_i2c_data *drv_data;
987 struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev);
988 int rc;
989
990 if ((!pdata && !pd->dev.of_node))
991 return -ENODEV;
992
993 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
994 GFP_KERNEL);
995 if (!drv_data)
996 return -ENOMEM;
997
998 drv_data->reg_base = devm_platform_ioremap_resource(pd, 0);
999 if (IS_ERR(drv_data->reg_base))
1000 return PTR_ERR(drv_data->reg_base);
1001
1002 strscpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
1003 sizeof(drv_data->adapter.name));
1004
1005 init_waitqueue_head(&drv_data->waitq);
1006 spin_lock_init(&drv_data->lock);
1007
1008 /* Not all platforms have clocks */
1009 drv_data->clk = devm_clk_get(&pd->dev, NULL);
1010 if (IS_ERR(drv_data->clk)) {
1011 if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER)
1012 return -EPROBE_DEFER;
1013 drv_data->clk = NULL;
1014 }
1015
1016 drv_data->reg_clk = devm_clk_get(&pd->dev, "reg");
1017 if (IS_ERR(drv_data->reg_clk)) {
1018 if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER)
1019 return -EPROBE_DEFER;
1020 drv_data->reg_clk = NULL;
1021 }
1022
1023 drv_data->irq = platform_get_irq(pd, 0);
1024 if (drv_data->irq < 0)
1025 return drv_data->irq;
1026
1027 if (pdata) {
1028 drv_data->freq_m = pdata->freq_m;
1029 drv_data->freq_n = pdata->freq_n;
1030 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
1031 drv_data->offload_enabled = false;
1032 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
1033 } else if (pd->dev.of_node) {
1034 rc = mv64xxx_of_config(drv_data, &pd->dev);
1035 if (rc)
1036 return rc;
1037 }
1038
1039 rc = mv64xxx_i2c_init_recovery_info(drv_data, &pd->dev);
1040 if (rc == -EPROBE_DEFER)
1041 return rc;
1042
1043 drv_data->adapter.dev.parent = &pd->dev;
1044 drv_data->adapter.algo = &mv64xxx_i2c_algo;
1045 drv_data->adapter.owner = THIS_MODULE;
1046 drv_data->adapter.class = I2C_CLASS_DEPRECATED;
1047 drv_data->adapter.nr = pd->id;
1048 drv_data->adapter.dev.of_node = pd->dev.of_node;
1049 platform_set_drvdata(pd, drv_data);
1050 i2c_set_adapdata(&drv_data->adapter, drv_data);
1051
1052 pm_runtime_set_autosuspend_delay(&pd->dev, MSEC_PER_SEC);
1053 pm_runtime_use_autosuspend(&pd->dev);
1054 pm_runtime_enable(&pd->dev);
1055 if (!pm_runtime_enabled(&pd->dev)) {
1056 rc = mv64xxx_i2c_runtime_resume(&pd->dev);
1057 if (rc)
1058 goto exit_disable_pm;
1059 }
1060
1061 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
1062 MV64XXX_I2C_CTLR_NAME, drv_data);
1063 if (rc) {
1064 dev_err(&drv_data->adapter.dev,
1065 "mv64xxx: Can't register intr handler irq%d: %d\n",
1066 drv_data->irq, rc);
1067 goto exit_disable_pm;
1068 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
1069 dev_err(&drv_data->adapter.dev,
1070 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
1071 goto exit_free_irq;
1072 }
1073
1074 return 0;
1075
1076 exit_free_irq:
1077 free_irq(drv_data->irq, drv_data);
1078 exit_disable_pm:
1079 pm_runtime_disable(&pd->dev);
1080 if (!pm_runtime_status_suspended(&pd->dev))
1081 mv64xxx_i2c_runtime_suspend(&pd->dev);
1082
1083 return rc;
1084 }
1085
1086 static void
1087 mv64xxx_i2c_remove(struct platform_device *pd)
1088 {
1089 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(pd);
1090
1091 i2c_del_adapter(&drv_data->adapter);
1092 free_irq(drv_data->irq, drv_data);
1093 pm_runtime_disable(&pd->dev);
1094 if (!pm_runtime_status_suspended(&pd->dev))
1095 mv64xxx_i2c_runtime_suspend(&pd->dev);
1096 }
1097
1098 static const struct dev_pm_ops mv64xxx_i2c_pm_ops = {
1099 SET_RUNTIME_PM_OPS(mv64xxx_i2c_runtime_suspend,
1100 mv64xxx_i2c_runtime_resume, NULL)
1101 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1102 pm_runtime_force_resume)
1103 };
1104
1105 static struct platform_driver mv64xxx_i2c_driver = {
1106 .probe = mv64xxx_i2c_probe,
1107 .remove_new = mv64xxx_i2c_remove,
1108 .driver = {
1109 .name = MV64XXX_I2C_CTLR_NAME,
1110 .pm = &mv64xxx_i2c_pm_ops,
1111 .of_match_table = mv64xxx_i2c_of_match_table,
1112 },
1113 };
1114
1115 module_platform_driver(mv64xxx_i2c_driver);
1116
1117 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
1118 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
1119 MODULE_LICENSE("GPL");
Kernel DRM miscellaneous fixes and cross-tree changes