drivers/iio/adc/aspeed_adc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Aspeed AST2400/2500/2600 ADC
   4  *
   5  * Copyright (C) 2017 Google, Inc.
   6  * Copyright (C) 2021 Aspeed Technology Inc.
   7  *
   8  * ADC clock formula:
   9  * Ast2400/Ast2500:
  10  * clock period = period of PCLK * 2 * (ADC0C[31:17] + 1) * (ADC0C[9:0] + 1)
  11  * Ast2600:
  12  * clock period = period of PCLK * 2 * (ADC0C[15:0] + 1)
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/err.h>
  18 #include <linux/errno.h>
  19 #include <linux/io.h>
  20 #include <linux/module.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/reset.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/types.h>
  27 #include <linux/bitfield.h>
  28 #include <linux/regmap.h>
  29 #include <linux/mfd/syscon.h>
  30
  31 #include <linux/iio/iio.h>
  32 #include <linux/iio/driver.h>
  33 #include <linux/iopoll.h>
  34
  35 #define ASPEED_RESOLUTION_BITS          10
  36 #define ASPEED_CLOCKS_PER_SAMPLE        12
  37
  38 #define ASPEED_REG_ENGINE_CONTROL       0x00
  39 #define ASPEED_REG_INTERRUPT_CONTROL    0x04
  40 #define ASPEED_REG_VGA_DETECT_CONTROL   0x08
  41 #define ASPEED_REG_CLOCK_CONTROL        0x0C
  42 #define ASPEED_REG_COMPENSATION_TRIM    0xC4
  43 /*
  44  * The register offset between 0xC8~0xCC can be read and won't affect the
  45  * hardware logic in each version of ADC.
  46  */
  47 #define ASPEED_REG_MAX                  0xD0
  48
  49 #define ASPEED_ADC_ENGINE_ENABLE                BIT(0)
  50 #define ASPEED_ADC_OP_MODE                      GENMASK(3, 1)
  51 #define ASPEED_ADC_OP_MODE_PWR_DOWN             0
  52 #define ASPEED_ADC_OP_MODE_STANDBY              1
  53 #define ASPEED_ADC_OP_MODE_NORMAL               7
  54 #define ASPEED_ADC_CTRL_COMPENSATION            BIT(4)
  55 #define ASPEED_ADC_AUTO_COMPENSATION            BIT(5)
  56 /*
  57  * Bit 6 determines not only the reference voltage range but also the dividing
  58  * circuit for battery sensing.
  59  */
  60 #define ASPEED_ADC_REF_VOLTAGE                  GENMASK(7, 6)
  61 #define ASPEED_ADC_REF_VOLTAGE_2500mV           0
  62 #define ASPEED_ADC_REF_VOLTAGE_1200mV           1
  63 #define ASPEED_ADC_REF_VOLTAGE_EXT_HIGH         2
  64 #define ASPEED_ADC_REF_VOLTAGE_EXT_LOW          3
  65 #define ASPEED_ADC_BAT_SENSING_DIV              BIT(6)
  66 #define ASPEED_ADC_BAT_SENSING_DIV_2_3          0
  67 #define ASPEED_ADC_BAT_SENSING_DIV_1_3          1
  68 #define ASPEED_ADC_CTRL_INIT_RDY                BIT(8)
  69 #define ASPEED_ADC_CH7_MODE                     BIT(12)
  70 #define ASPEED_ADC_CH7_NORMAL                   0
  71 #define ASPEED_ADC_CH7_BAT                      1
  72 #define ASPEED_ADC_BAT_SENSING_ENABLE           BIT(13)
  73 #define ASPEED_ADC_CTRL_CHANNEL                 GENMASK(31, 16)
  74 #define ASPEED_ADC_CTRL_CHANNEL_ENABLE(ch)      FIELD_PREP(ASPEED_ADC_CTRL_CHANNEL, BIT(ch))
  75
  76 #define ASPEED_ADC_INIT_POLLING_TIME    500
  77 #define ASPEED_ADC_INIT_TIMEOUT         500000
  78 /*
  79  * When the sampling rate is too high, the ADC may not have enough charging
  80  * time, resulting in a low voltage value. Thus, the default uses a slow
  81  * sampling rate for most use cases.
  82  */
  83 #define ASPEED_ADC_DEF_SAMPLING_RATE    65000
  84
  85 struct aspeed_adc_trim_locate {
  86         const unsigned int offset;
  87         const unsigned int field;
  88 };
  89
  90 struct aspeed_adc_model_data {
  91         const char *model_name;
  92         unsigned int min_sampling_rate; // Hz
  93         unsigned int max_sampling_rate; // Hz
  94         unsigned int vref_fixed_mv;
  95         bool wait_init_sequence;
  96         bool need_prescaler;
  97         bool bat_sense_sup;
  98         u8 scaler_bit_width;
  99         unsigned int num_channels;
 100         const struct aspeed_adc_trim_locate *trim_locate;
 101 };
 102
 103 struct adc_gain {
 104         u8 mult;
 105         u8 div;
 106 };
 107
 108 struct aspeed_adc_data {
 109         struct device           *dev;
 110         const struct aspeed_adc_model_data *model_data;
 111         void __iomem            *base;
 112         spinlock_t              clk_lock;
 113         struct clk_hw           *fixed_div_clk;
 114         struct clk_hw           *clk_prescaler;
 115         struct clk_hw           *clk_scaler;
 116         struct reset_control    *rst;
 117         int                     vref_mv;
 118         u32                     sample_period_ns;
 119         int                     cv;
 120         bool                    battery_sensing;
 121         struct adc_gain         battery_mode_gain;
 122 };
 123
 124 #define ASPEED_CHAN(_idx, _data_reg_addr) {                     \
 125         .type = IIO_VOLTAGE,                                    \
 126         .indexed = 1,                                           \
 127         .channel = (_idx),                                      \
 128         .address = (_data_reg_addr),                            \
 129         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 130         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |  \
 131                                 BIT(IIO_CHAN_INFO_SAMP_FREQ) |  \
 132                                 BIT(IIO_CHAN_INFO_OFFSET),      \
 133 }
 134
 135 static const struct iio_chan_spec aspeed_adc_iio_channels[] = {
 136         ASPEED_CHAN(0, 0x10),
 137         ASPEED_CHAN(1, 0x12),
 138         ASPEED_CHAN(2, 0x14),
 139         ASPEED_CHAN(3, 0x16),
 140         ASPEED_CHAN(4, 0x18),
 141         ASPEED_CHAN(5, 0x1A),
 142         ASPEED_CHAN(6, 0x1C),
 143         ASPEED_CHAN(7, 0x1E),
 144         ASPEED_CHAN(8, 0x20),
 145         ASPEED_CHAN(9, 0x22),
 146         ASPEED_CHAN(10, 0x24),
 147         ASPEED_CHAN(11, 0x26),
 148         ASPEED_CHAN(12, 0x28),
 149         ASPEED_CHAN(13, 0x2A),
 150         ASPEED_CHAN(14, 0x2C),
 151         ASPEED_CHAN(15, 0x2E),
 152 };
 153
 154 #define ASPEED_BAT_CHAN(_idx, _data_reg_addr) {                                 \
 155                 .type = IIO_VOLTAGE,                                            \
 156                 .indexed = 1,                                                   \
 157                 .channel = (_idx),                                              \
 158                 .address = (_data_reg_addr),                                    \
 159                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |                  \
 160                                       BIT(IIO_CHAN_INFO_OFFSET),                \
 161                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |          \
 162                                             BIT(IIO_CHAN_INFO_SAMP_FREQ),       \
 163 }
 164 static const struct iio_chan_spec aspeed_adc_iio_bat_channels[] = {
 165         ASPEED_CHAN(0, 0x10),
 166         ASPEED_CHAN(1, 0x12),
 167         ASPEED_CHAN(2, 0x14),
 168         ASPEED_CHAN(3, 0x16),
 169         ASPEED_CHAN(4, 0x18),
 170         ASPEED_CHAN(5, 0x1A),
 171         ASPEED_CHAN(6, 0x1C),
 172         ASPEED_BAT_CHAN(7, 0x1E),
 173 };
 174
 175 static int aspeed_adc_set_trim_data(struct iio_dev *indio_dev)
 176 {
 177         struct device_node *syscon;
 178         struct regmap *scu;
 179         u32 scu_otp, trimming_val;
 180         struct aspeed_adc_data *data = iio_priv(indio_dev);
 181
 182         syscon = of_find_node_by_name(NULL, "syscon");
 183         if (syscon == NULL) {
 184                 dev_warn(data->dev, "Couldn't find syscon node\n");
 185                 return -EOPNOTSUPP;
 186         }
 187         scu = syscon_node_to_regmap(syscon);
 188         of_node_put(syscon);
 189         if (IS_ERR(scu)) {
 190                 dev_warn(data->dev, "Failed to get syscon regmap\n");
 191                 return -EOPNOTSUPP;
 192         }
 193         if (data->model_data->trim_locate) {
 194                 if (regmap_read(scu, data->model_data->trim_locate->offset,
 195                                 &scu_otp)) {
 196                         dev_warn(data->dev,
 197                                  "Failed to get adc trimming data\n");
 198                         trimming_val = 0x8;
 199                 } else {
 200                         trimming_val =
 201                                 ((scu_otp) &
 202                                  (data->model_data->trim_locate->field)) >>
 203                                 __ffs(data->model_data->trim_locate->field);
 204                         if (!trimming_val)
 205                                 trimming_val = 0x8;
 206                 }
 207                 dev_dbg(data->dev,
 208                         "trimming val = %d, offset = %08x, fields = %08x\n",
 209                         trimming_val, data->model_data->trim_locate->offset,
 210                         data->model_data->trim_locate->field);
 211                 writel(trimming_val, data->base + ASPEED_REG_COMPENSATION_TRIM);
 212         }
 213         return 0;
 214 }
 215
 216 static int aspeed_adc_compensation(struct iio_dev *indio_dev)
 217 {
 218         struct aspeed_adc_data *data = iio_priv(indio_dev);
 219         u32 index, adc_raw = 0;
 220         u32 adc_engine_control_reg_val;
 221
 222         adc_engine_control_reg_val =
 223                 readl(data->base + ASPEED_REG_ENGINE_CONTROL);
 224         adc_engine_control_reg_val &= ~ASPEED_ADC_OP_MODE;
 225         adc_engine_control_reg_val |=
 226                 (FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) |
 227                  ASPEED_ADC_ENGINE_ENABLE);
 228         /*
 229          * Enable compensating sensing:
 230          * After that, the input voltage of ADC will force to half of the reference
 231          * voltage. So the expected reading raw data will become half of the max
 232          * value. We can get compensating value = 0x200 - ADC read raw value.
 233          * It is recommended to average at least 10 samples to get a final CV.
 234          */
 235         writel(adc_engine_control_reg_val | ASPEED_ADC_CTRL_COMPENSATION |
 236                        ASPEED_ADC_CTRL_CHANNEL_ENABLE(0),
 237                data->base + ASPEED_REG_ENGINE_CONTROL);
 238         /*
 239          * After enable compensating sensing mode need to wait some time for ADC stable
 240          * Experiment result is 1ms.
 241          */
 242         mdelay(1);
 243
 244         for (index = 0; index < 16; index++) {
 245                 /*
 246                  * Waiting for the sampling period ensures that the value acquired
 247                  * is fresh each time.
 248                  */
 249                 ndelay(data->sample_period_ns);
 250                 adc_raw += readw(data->base + aspeed_adc_iio_channels[0].address);
 251         }
 252         adc_raw >>= 4;
 253         data->cv = BIT(ASPEED_RESOLUTION_BITS - 1) - adc_raw;
 254         writel(adc_engine_control_reg_val,
 255                data->base + ASPEED_REG_ENGINE_CONTROL);
 256         dev_dbg(data->dev, "Compensating value = %d\n", data->cv);
 257
 258         return 0;
 259 }
 260
 261 static int aspeed_adc_set_sampling_rate(struct iio_dev *indio_dev, u32 rate)
 262 {
 263         struct aspeed_adc_data *data = iio_priv(indio_dev);
 264
 265         if (rate < data->model_data->min_sampling_rate ||
 266             rate > data->model_data->max_sampling_rate)
 267                 return -EINVAL;
 268         /* Each sampling needs 12 clocks to convert.*/
 269         clk_set_rate(data->clk_scaler->clk, rate * ASPEED_CLOCKS_PER_SAMPLE);
 270         rate = clk_get_rate(data->clk_scaler->clk);
 271         data->sample_period_ns = DIV_ROUND_UP_ULL(
 272                 (u64)NSEC_PER_SEC * ASPEED_CLOCKS_PER_SAMPLE, rate);
 273         dev_dbg(data->dev, "Adc clock = %d sample period = %d ns", rate,
 274                 data->sample_period_ns);
 275
 276         return 0;
 277 }
 278
 279 static int aspeed_adc_read_raw(struct iio_dev *indio_dev,
 280                                struct iio_chan_spec const *chan,
 281                                int *val, int *val2, long mask)
 282 {
 283         struct aspeed_adc_data *data = iio_priv(indio_dev);
 284         u32 adc_engine_control_reg_val;
 285
 286         switch (mask) {
 287         case IIO_CHAN_INFO_RAW:
 288                 if (data->battery_sensing && chan->channel == 7) {
 289                         adc_engine_control_reg_val =
 290                                 readl(data->base + ASPEED_REG_ENGINE_CONTROL);
 291                         writel(adc_engine_control_reg_val |
 292                                        FIELD_PREP(ASPEED_ADC_CH7_MODE,
 293                                                   ASPEED_ADC_CH7_BAT) |
 294                                        ASPEED_ADC_BAT_SENSING_ENABLE,
 295                                data->base + ASPEED_REG_ENGINE_CONTROL);
 296                         /*
 297                          * After enable battery sensing mode need to wait some time for adc stable
 298                          * Experiment result is 1ms.
 299                          */
 300                         mdelay(1);
 301                         *val = readw(data->base + chan->address);
 302                         *val = (*val * data->battery_mode_gain.mult) /
 303                                data->battery_mode_gain.div;
 304                         /* Restore control register value */
 305                         writel(adc_engine_control_reg_val,
 306                                data->base + ASPEED_REG_ENGINE_CONTROL);
 307                 } else
 308                         *val = readw(data->base + chan->address);
 309                 return IIO_VAL_INT;
 310
 311         case IIO_CHAN_INFO_OFFSET:
 312                 if (data->battery_sensing && chan->channel == 7)
 313                         *val = (data->cv * data->battery_mode_gain.mult) /
 314                                data->battery_mode_gain.div;
 315                 else
 316                         *val = data->cv;
 317                 return IIO_VAL_INT;
 318
 319         case IIO_CHAN_INFO_SCALE:
 320                 *val = data->vref_mv;
 321                 *val2 = ASPEED_RESOLUTION_BITS;
 322                 return IIO_VAL_FRACTIONAL_LOG2;
 323
 324         case IIO_CHAN_INFO_SAMP_FREQ:
 325                 *val = clk_get_rate(data->clk_scaler->clk) /
 326                                 ASPEED_CLOCKS_PER_SAMPLE;
 327                 return IIO_VAL_INT;
 328
 329         default:
 330                 return -EINVAL;
 331         }
 332 }
 333
 334 static int aspeed_adc_write_raw(struct iio_dev *indio_dev,
 335                                 struct iio_chan_spec const *chan,
 336                                 int val, int val2, long mask)
 337 {
 338         switch (mask) {
 339         case IIO_CHAN_INFO_SAMP_FREQ:
 340                 return aspeed_adc_set_sampling_rate(indio_dev, val);
 341
 342         case IIO_CHAN_INFO_SCALE:
 343         case IIO_CHAN_INFO_RAW:
 344                 /*
 345                  * Technically, these could be written but the only reasons
 346                  * for doing so seem better handled in userspace.  EPERM is
 347                  * returned to signal this is a policy choice rather than a
 348                  * hardware limitation.
 349                  */
 350                 return -EPERM;
 351
 352         default:
 353                 return -EINVAL;
 354         }
 355 }
 356
 357 static int aspeed_adc_reg_access(struct iio_dev *indio_dev,
 358                                  unsigned int reg, unsigned int writeval,
 359                                  unsigned int *readval)
 360 {
 361         struct aspeed_adc_data *data = iio_priv(indio_dev);
 362
 363         if (!readval || reg % 4 || reg > ASPEED_REG_MAX)
 364                 return -EINVAL;
 365
 366         *readval = readl(data->base + reg);
 367
 368         return 0;
 369 }
 370
 371 static const struct iio_info aspeed_adc_iio_info = {
 372         .read_raw = aspeed_adc_read_raw,
 373         .write_raw = aspeed_adc_write_raw,
 374         .debugfs_reg_access = aspeed_adc_reg_access,
 375 };
 376
 377 static void aspeed_adc_unregister_fixed_divider(void *data)
 378 {
 379         struct clk_hw *clk = data;
 380
 381         clk_hw_unregister_fixed_factor(clk);
 382 }
 383
 384 static void aspeed_adc_reset_assert(void *data)
 385 {
 386         struct reset_control *rst = data;
 387
 388         reset_control_assert(rst);
 389 }
 390
 391 static void aspeed_adc_clk_disable_unprepare(void *data)
 392 {
 393         struct clk *clk = data;
 394
 395         clk_disable_unprepare(clk);
 396 }
 397
 398 static void aspeed_adc_power_down(void *data)
 399 {
 400         struct aspeed_adc_data *priv_data = data;
 401
 402         writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN),
 403                priv_data->base + ASPEED_REG_ENGINE_CONTROL);
 404 }
 405
 406 static int aspeed_adc_vref_config(struct iio_dev *indio_dev)
 407 {
 408         struct aspeed_adc_data *data = iio_priv(indio_dev);
 409         int ret;
 410         u32 adc_engine_control_reg_val;
 411
 412         if (data->model_data->vref_fixed_mv) {
 413                 data->vref_mv = data->model_data->vref_fixed_mv;
 414                 return 0;
 415         }
 416         adc_engine_control_reg_val =
 417                 readl(data->base + ASPEED_REG_ENGINE_CONTROL);
 418
 419         ret = devm_regulator_get_enable_read_voltage(data->dev, "vref");
 420         if (ret < 0 && ret != -ENODEV)
 421                 return ret;
 422
 423         if (ret != -ENODEV) {
 424                 data->vref_mv = ret / 1000;
 425
 426                 if ((data->vref_mv >= 1550) && (data->vref_mv <= 2700))
 427                         writel(adc_engine_control_reg_val |
 428                                 FIELD_PREP(
 429                                         ASPEED_ADC_REF_VOLTAGE,
 430                                         ASPEED_ADC_REF_VOLTAGE_EXT_HIGH),
 431                         data->base + ASPEED_REG_ENGINE_CONTROL);
 432                 else if ((data->vref_mv >= 900) && (data->vref_mv <= 1650))
 433                         writel(adc_engine_control_reg_val |
 434                                 FIELD_PREP(
 435                                         ASPEED_ADC_REF_VOLTAGE,
 436                                         ASPEED_ADC_REF_VOLTAGE_EXT_LOW),
 437                         data->base + ASPEED_REG_ENGINE_CONTROL);
 438                 else {
 439                         dev_err(data->dev, "Regulator voltage %d not support",
 440                                 data->vref_mv);
 441                         return -EOPNOTSUPP;
 442                 }
 443         } else {
 444                 data->vref_mv = 2500000;
 445                 of_property_read_u32(data->dev->of_node,
 446                                      "aspeed,int-vref-microvolt",
 447                                      &data->vref_mv);
 448                 /* Conversion from uV to mV */
 449                 data->vref_mv /= 1000;
 450                 if (data->vref_mv == 2500)
 451                         writel(adc_engine_control_reg_val |
 452                                 FIELD_PREP(ASPEED_ADC_REF_VOLTAGE,
 453                                                 ASPEED_ADC_REF_VOLTAGE_2500mV),
 454                         data->base + ASPEED_REG_ENGINE_CONTROL);
 455                 else if (data->vref_mv == 1200)
 456                         writel(adc_engine_control_reg_val |
 457                                 FIELD_PREP(ASPEED_ADC_REF_VOLTAGE,
 458                                                 ASPEED_ADC_REF_VOLTAGE_1200mV),
 459                         data->base + ASPEED_REG_ENGINE_CONTROL);
 460                 else {
 461                         dev_err(data->dev, "Voltage %d not support", data->vref_mv);
 462                         return -EOPNOTSUPP;
 463                 }
 464         }
 465
 466         return 0;
 467 }
 468
 469 static int aspeed_adc_probe(struct platform_device *pdev)
 470 {
 471         struct iio_dev *indio_dev;
 472         struct aspeed_adc_data *data;
 473         int ret;
 474         u32 adc_engine_control_reg_val;
 475         unsigned long scaler_flags = 0;
 476         char clk_name[32], clk_parent_name[32];
 477
 478         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data));
 479         if (!indio_dev)
 480                 return -ENOMEM;
 481
 482         data = iio_priv(indio_dev);
 483         data->dev = &pdev->dev;
 484         data->model_data = of_device_get_match_data(&pdev->dev);
 485         platform_set_drvdata(pdev, indio_dev);
 486
 487         data->base = devm_platform_ioremap_resource(pdev, 0);
 488         if (IS_ERR(data->base))
 489                 return PTR_ERR(data->base);
 490
 491         /* Register ADC clock prescaler with source specified by device tree. */
 492         spin_lock_init(&data->clk_lock);
 493         snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), "%s",
 494                  of_clk_get_parent_name(pdev->dev.of_node, 0));
 495         snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-fixed-div",
 496                  data->model_data->model_name);
 497         data->fixed_div_clk = clk_hw_register_fixed_factor(
 498                 &pdev->dev, clk_name, clk_parent_name, 0, 1, 2);
 499         if (IS_ERR(data->fixed_div_clk))
 500                 return PTR_ERR(data->fixed_div_clk);
 501
 502         ret = devm_add_action_or_reset(data->dev,
 503                                        aspeed_adc_unregister_fixed_divider,
 504                                        data->fixed_div_clk);
 505         if (ret)
 506                 return ret;
 507         snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), clk_name);
 508
 509         if (data->model_data->need_prescaler) {
 510                 snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-prescaler",
 511                          data->model_data->model_name);
 512                 data->clk_prescaler = devm_clk_hw_register_divider(
 513                         &pdev->dev, clk_name, clk_parent_name, 0,
 514                         data->base + ASPEED_REG_CLOCK_CONTROL, 17, 15, 0,
 515                         &data->clk_lock);
 516                 if (IS_ERR(data->clk_prescaler))
 517                         return PTR_ERR(data->clk_prescaler);
 518                 snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name),
 519                          clk_name);
 520                 scaler_flags = CLK_SET_RATE_PARENT;
 521         }
 522         /*
 523          * Register ADC clock scaler downstream from the prescaler. Allow rate
 524          * setting to adjust the prescaler as well.
 525          */
 526         snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-scaler",
 527                  data->model_data->model_name);
 528         data->clk_scaler = devm_clk_hw_register_divider(
 529                 &pdev->dev, clk_name, clk_parent_name, scaler_flags,
 530                 data->base + ASPEED_REG_CLOCK_CONTROL, 0,
 531                 data->model_data->scaler_bit_width,
 532                 data->model_data->need_prescaler ? CLK_DIVIDER_ONE_BASED : 0,
 533                 &data->clk_lock);
 534         if (IS_ERR(data->clk_scaler))
 535                 return PTR_ERR(data->clk_scaler);
 536
 537         data->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
 538         if (IS_ERR(data->rst)) {
 539                 dev_err(&pdev->dev,
 540                         "invalid or missing reset controller device tree entry");
 541                 return PTR_ERR(data->rst);
 542         }
 543         reset_control_deassert(data->rst);
 544
 545         ret = devm_add_action_or_reset(data->dev, aspeed_adc_reset_assert,
 546                                        data->rst);
 547         if (ret)
 548                 return ret;
 549
 550         ret = aspeed_adc_vref_config(indio_dev);
 551         if (ret)
 552                 return ret;
 553
 554         ret = aspeed_adc_set_trim_data(indio_dev);
 555         if (ret)
 556                 return ret;
 557
 558         if (of_property_present(data->dev->of_node, "aspeed,battery-sensing")) {
 559                 if (data->model_data->bat_sense_sup) {
 560                         data->battery_sensing = 1;
 561                         if (readl(data->base + ASPEED_REG_ENGINE_CONTROL) &
 562                             ASPEED_ADC_BAT_SENSING_DIV) {
 563                                 data->battery_mode_gain.mult = 3;
 564                                 data->battery_mode_gain.div = 1;
 565                         } else {
 566                                 data->battery_mode_gain.mult = 3;
 567                                 data->battery_mode_gain.div = 2;
 568                         }
 569                 } else
 570                         dev_warn(&pdev->dev,
 571                                  "Failed to enable battery-sensing mode\n");
 572         }
 573
 574         ret = clk_prepare_enable(data->clk_scaler->clk);
 575         if (ret)
 576                 return ret;
 577         ret = devm_add_action_or_reset(data->dev,
 578                                        aspeed_adc_clk_disable_unprepare,
 579                                        data->clk_scaler->clk);
 580         if (ret)
 581                 return ret;
 582         ret = aspeed_adc_set_sampling_rate(indio_dev,
 583                                            ASPEED_ADC_DEF_SAMPLING_RATE);
 584         if (ret)
 585                 return ret;
 586
 587         adc_engine_control_reg_val =
 588                 readl(data->base + ASPEED_REG_ENGINE_CONTROL);
 589         adc_engine_control_reg_val |=
 590                 FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) |
 591                 ASPEED_ADC_ENGINE_ENABLE;
 592         /* Enable engine in normal mode. */
 593         writel(adc_engine_control_reg_val,
 594                data->base + ASPEED_REG_ENGINE_CONTROL);
 595
 596         ret = devm_add_action_or_reset(data->dev, aspeed_adc_power_down,
 597                                         data);
 598         if (ret)
 599                 return ret;
 600
 601         if (data->model_data->wait_init_sequence) {
 602                 /* Wait for initial sequence complete. */
 603                 ret = readl_poll_timeout(data->base + ASPEED_REG_ENGINE_CONTROL,
 604                                          adc_engine_control_reg_val,
 605                                          adc_engine_control_reg_val &
 606                                          ASPEED_ADC_CTRL_INIT_RDY,
 607                                          ASPEED_ADC_INIT_POLLING_TIME,
 608                                          ASPEED_ADC_INIT_TIMEOUT);
 609                 if (ret)
 610                         return ret;
 611         }
 612
 613         aspeed_adc_compensation(indio_dev);
 614         /* Start all channels in normal mode. */
 615         adc_engine_control_reg_val =
 616                 readl(data->base + ASPEED_REG_ENGINE_CONTROL);
 617         adc_engine_control_reg_val |= ASPEED_ADC_CTRL_CHANNEL;
 618         writel(adc_engine_control_reg_val,
 619                data->base + ASPEED_REG_ENGINE_CONTROL);
 620
 621         indio_dev->name = data->model_data->model_name;
 622         indio_dev->info = &aspeed_adc_iio_info;
 623         indio_dev->modes = INDIO_DIRECT_MODE;
 624         indio_dev->channels = data->battery_sensing ?
 625                                             aspeed_adc_iio_bat_channels :
 626                                             aspeed_adc_iio_channels;
 627         indio_dev->num_channels = data->model_data->num_channels;
 628
 629         ret = devm_iio_device_register(data->dev, indio_dev);
 630         return ret;
 631 }
 632
 633 static const struct aspeed_adc_trim_locate ast2500_adc_trim = {
 634         .offset = 0x154,
 635         .field = GENMASK(31, 28),
 636 };
 637
 638 static const struct aspeed_adc_trim_locate ast2600_adc0_trim = {
 639         .offset = 0x5d0,
 640         .field = GENMASK(3, 0),
 641 };
 642
 643 static const struct aspeed_adc_trim_locate ast2600_adc1_trim = {
 644         .offset = 0x5d0,
 645         .field = GENMASK(7, 4),
 646 };
 647
 648 static const struct aspeed_adc_model_data ast2400_model_data = {
 649         .model_name = "ast2400-adc",
 650         .vref_fixed_mv = 2500,
 651         .min_sampling_rate = 10000,
 652         .max_sampling_rate = 500000,
 653         .need_prescaler = true,
 654         .scaler_bit_width = 10,
 655         .num_channels = 16,
 656 };
 657
 658 static const struct aspeed_adc_model_data ast2500_model_data = {
 659         .model_name = "ast2500-adc",
 660         .vref_fixed_mv = 1800,
 661         .min_sampling_rate = 1,
 662         .max_sampling_rate = 1000000,
 663         .wait_init_sequence = true,
 664         .need_prescaler = true,
 665         .scaler_bit_width = 10,
 666         .num_channels = 16,
 667         .trim_locate = &ast2500_adc_trim,
 668 };
 669
 670 static const struct aspeed_adc_model_data ast2600_adc0_model_data = {
 671         .model_name = "ast2600-adc0",
 672         .min_sampling_rate = 10000,
 673         .max_sampling_rate = 500000,
 674         .wait_init_sequence = true,
 675         .bat_sense_sup = true,
 676         .scaler_bit_width = 16,
 677         .num_channels = 8,
 678         .trim_locate = &ast2600_adc0_trim,
 679 };
 680
 681 static const struct aspeed_adc_model_data ast2600_adc1_model_data = {
 682         .model_name = "ast2600-adc1",
 683         .min_sampling_rate = 10000,
 684         .max_sampling_rate = 500000,
 685         .wait_init_sequence = true,
 686         .bat_sense_sup = true,
 687         .scaler_bit_width = 16,
 688         .num_channels = 8,
 689         .trim_locate = &ast2600_adc1_trim,
 690 };
 691
 692 static const struct of_device_id aspeed_adc_matches[] = {
 693         { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data },
 694         { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data },
 695         { .compatible = "aspeed,ast2600-adc0", .data = &ast2600_adc0_model_data },
 696         { .compatible = "aspeed,ast2600-adc1", .data = &ast2600_adc1_model_data },
 697         { }
 698 };
 699 MODULE_DEVICE_TABLE(of, aspeed_adc_matches);
 700
 701 static struct platform_driver aspeed_adc_driver = {
 702         .probe = aspeed_adc_probe,
 703         .driver = {
 704                 .name = KBUILD_MODNAME,
 705                 .of_match_table = aspeed_adc_matches,
 706         }
 707 };
 708
 709 module_platform_driver(aspeed_adc_driver);
 710
 711 MODULE_AUTHOR("Rick Altherr <raltherr@google.com>");
 712 MODULE_DESCRIPTION("Aspeed AST2400/2500/2600 ADC Driver");
 713 MODULE_LICENSE("GPL");