drivers/scsi/be2iscsi/be_main.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright 2017 Broadcom. All Rights Reserved.
   4  * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries.
   5  *
   6  * Contact Information:
   7  * linux-drivers@broadcom.com
   8  */
   9
  10 #ifndef _BEISCSI_MAIN_
  11 #define _BEISCSI_MAIN_
  12
  13 #include <linux/kernel.h>
  14 #include <linux/pci.h>
  15 #include <linux/if_ether.h>
  16 #include <linux/in.h>
  17 #include <linux/ctype.h>
  18 #include <linux/module.h>
  19 #include <scsi/scsi.h>
  20 #include <scsi/scsi_cmnd.h>
  21 #include <scsi/scsi_device.h>
  22 #include <scsi/scsi_host.h>
  23 #include <scsi/iscsi_proto.h>
  24 #include <scsi/libiscsi.h>
  25 #include <scsi/scsi_transport_iscsi.h>
  26
  27 #define DRV_NAME                "be2iscsi"
  28 #define BUILD_STR               "11.4.0.1"
  29 #define BE_NAME                 "Emulex OneConnect" \
  30                                 "Open-iSCSI Driver version" BUILD_STR
  31 #define DRV_DESC                BE_NAME " " "Driver"
  32
  33 #define BE_VENDOR_ID            0x19A2
  34 #define ELX_VENDOR_ID           0x10DF
  35 /* DEVICE ID's for BE2 */
  36 #define BE_DEVICE_ID1           0x212
  37 #define OC_DEVICE_ID1           0x702
  38 #define OC_DEVICE_ID2           0x703
  39
  40 /* DEVICE ID's for BE3 */
  41 #define BE_DEVICE_ID2           0x222
  42 #define OC_DEVICE_ID3           0x712
  43
  44 /* DEVICE ID for SKH */
  45 #define OC_SKH_ID1              0x722
  46
  47 #define BE2_IO_DEPTH            1024
  48 #define BE2_MAX_SESSIONS        256
  49 #define BE2_TMFS                16
  50 #define BE2_NOPOUT_REQ          16
  51 #define BE2_SGE                 32
  52 #define BE2_DEFPDU_HDR_SZ       64
  53 #define BE2_DEFPDU_DATA_SZ      8192
  54 #define BE2_MAX_NUM_CQ_PROC     512
  55
  56 #define MAX_CPUS                64U
  57 #define BEISCSI_MAX_NUM_CPUS    7
  58
  59 #define BEISCSI_VER_STRLEN 32
  60
  61 #define BEISCSI_SGLIST_ELEMENTS 30
  62
  63 /**
  64  * BE_INVLDT_CMD_TBL_SZ is 128 which is total number commands that can
  65  * be invalidated at a time, consider it before changing the value of
  66  * BEISCSI_CMD_PER_LUN.
  67  */
  68 #define BEISCSI_CMD_PER_LUN     128     /* scsi_host->cmd_per_lun */
  69 #define BEISCSI_MAX_SECTORS     1024    /* scsi_host->max_sectors */
  70 #define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
  71
  72 #define BEISCSI_MAX_CMD_LEN     16      /* scsi_host->max_cmd_len */
  73 #define BEISCSI_NUM_MAX_LUN     256     /* scsi_host->max_lun */
  74 #define BEISCSI_MAX_FRAGS_INIT  192
  75
  76 #define BE_SENSE_INFO_SIZE              258
  77 #define BE_ISCSI_PDU_HEADER_SIZE        64
  78 #define BE_MIN_MEM_SIZE                 16384
  79 #define MAX_CMD_SZ                      65536
  80 #define IIOC_SCSI_DATA                  0x05    /* Write Operation */
  81
  82 /**
  83  * hardware needs the async PDU buffers to be posted in multiples of 8
  84  * So have atleast 8 of them by default
  85  */
  86
  87 #define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num)    \
  88         (phwi->phwi_ctxt->pasync_ctx[ulp_num])
  89
  90 /********* Memory BAR register ************/
  91 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET      0xfc
  92 /**
  93  * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
  94  * Disable" may still globally block interrupts in addition to individual
  95  * interrupt masks; a mechanism for the device driver to block all interrupts
  96  * atomically without having to arbitrate for the PCI Interrupt Disable bit
  97  * with the OS.
  98  */
  99 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK      (1 << 29)       /* bit 29 */
 100
 101 /********* ISR0 Register offset **********/
 102 #define CEV_ISR0_OFFSET                         0xC18
 103 #define CEV_ISR_SIZE                            4
 104
 105 /**
 106  * Macros for reading/writing a protection domain or CSR registers
 107  * in BladeEngine.
 108  */
 109
 110 #define DB_TXULP0_OFFSET 0x40
 111 #define DB_RXULP0_OFFSET 0xA0
 112 /********* Event Q door bell *************/
 113 #define DB_EQ_OFFSET                    DB_CQ_OFFSET
 114 #define DB_EQ_RING_ID_LOW_MASK          0x1FF   /* bits 0 - 8 */
 115 /* Clear the interrupt for this eq */
 116 #define DB_EQ_CLR_SHIFT                 (9)     /* bit 9 */
 117 /* Must be 1 */
 118 #define DB_EQ_EVNT_SHIFT                (10)    /* bit 10 */
 119 /* Higher Order EQ_ID bit */
 120 #define DB_EQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
 121 #define DB_EQ_HIGH_SET_SHIFT    11
 122 #define DB_EQ_HIGH_FEILD_SHIFT  9
 123 /* Number of event entries processed */
 124 #define DB_EQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 125 /* Rearm bit */
 126 #define DB_EQ_REARM_SHIFT               (29)    /* bit 29 */
 127
 128 /********* Compl Q door bell *************/
 129 #define DB_CQ_OFFSET                    0x120
 130 #define DB_CQ_RING_ID_LOW_MASK          0x3FF   /* bits 0 - 9 */
 131 /* Higher Order CQ_ID bit */
 132 #define DB_CQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
 133 #define DB_CQ_HIGH_SET_SHIFT    11
 134 #define DB_CQ_HIGH_FEILD_SHIFT  10
 135
 136 /* Number of event entries processed */
 137 #define DB_CQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 138 /* Rearm bit */
 139 #define DB_CQ_REARM_SHIFT               (29)    /* bit 29 */
 140
 141 #define GET_HWI_CONTROLLER_WS(pc)       (pc->phwi_ctrlr)
 142 #define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
 143                 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
 144 #define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
 145                 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
 146
 147 #define PAGES_REQUIRED(x) \
 148         ((x < PAGE_SIZE) ? 1 :  ((x + PAGE_SIZE - 1) / PAGE_SIZE))
 149
 150 #define MEM_DESCR_OFFSET 8
 151 #define BEISCSI_DEFQ_HDR 1
 152 #define BEISCSI_DEFQ_DATA 0
 153 enum be_mem_enum {
 154         HWI_MEM_ADDN_CONTEXT,
 155         HWI_MEM_WRB,
 156         HWI_MEM_WRBH,
 157         HWI_MEM_SGLH,
 158         HWI_MEM_SGE,
 159         HWI_MEM_TEMPLATE_HDR_ULP0,
 160         HWI_MEM_ASYNC_HEADER_BUF_ULP0,  /* 6 */
 161         HWI_MEM_ASYNC_DATA_BUF_ULP0,
 162         HWI_MEM_ASYNC_HEADER_RING_ULP0,
 163         HWI_MEM_ASYNC_DATA_RING_ULP0,
 164         HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
 165         HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
 166         HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
 167         HWI_MEM_TEMPLATE_HDR_ULP1,
 168         HWI_MEM_ASYNC_HEADER_BUF_ULP1,  /* 14 */
 169         HWI_MEM_ASYNC_DATA_BUF_ULP1,
 170         HWI_MEM_ASYNC_HEADER_RING_ULP1,
 171         HWI_MEM_ASYNC_DATA_RING_ULP1,
 172         HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
 173         HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
 174         HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
 175         ISCSI_MEM_GLOBAL_HEADER,
 176         SE_MEM_MAX
 177 };
 178
 179 struct be_bus_address32 {
 180         unsigned int address_lo;
 181         unsigned int address_hi;
 182 };
 183
 184 struct be_bus_address64 {
 185         unsigned long long address;
 186 };
 187
 188 struct be_bus_address {
 189         union {
 190                 struct be_bus_address32 a32;
 191                 struct be_bus_address64 a64;
 192         } u;
 193 };
 194
 195 struct mem_array {
 196         struct be_bus_address bus_address;      /* Bus address of location */
 197         void *virtual_address;          /* virtual address to the location */
 198         unsigned int size;              /* Size required by memory block */
 199 };
 200
 201 struct be_mem_descriptor {
 202         unsigned int size_in_bytes;     /* Size required by memory block */
 203         unsigned int num_elements;
 204         struct mem_array *mem_array;
 205 };
 206
 207 struct sgl_handle {
 208         unsigned int sgl_index;
 209         unsigned int type;
 210         unsigned int cid;
 211         struct iscsi_task *task;
 212         struct iscsi_sge *pfrag;
 213 };
 214
 215 struct hba_parameters {
 216         unsigned int ios_per_ctrl;
 217         unsigned int cxns_per_ctrl;
 218         unsigned int icds_per_ctrl;
 219         unsigned int num_sge_per_io;
 220         unsigned int defpdu_hdr_sz;
 221         unsigned int defpdu_data_sz;
 222         unsigned int num_cq_entries;
 223         unsigned int num_eq_entries;
 224         unsigned int wrbs_per_cxn;
 225         unsigned int hwi_ws_sz;
 226 };
 227
 228 #define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
 229         (phwi_ctrlr->wrb_context[cri].ulp_num)
 230 struct hwi_wrb_context {
 231         spinlock_t wrb_lock;
 232         struct wrb_handle **pwrb_handle_base;
 233         struct wrb_handle **pwrb_handle_basestd;
 234         struct iscsi_wrb *plast_wrb;
 235         unsigned short alloc_index;
 236         unsigned short free_index;
 237         unsigned short wrb_handles_available;
 238         unsigned short cid;
 239         uint8_t ulp_num;        /* ULP to which CID binded */
 240         uint32_t doorbell_offset;
 241 };
 242
 243 struct ulp_cid_info {
 244         unsigned short *cid_array;
 245         unsigned short avlbl_cids;
 246         unsigned short cid_alloc;
 247         unsigned short cid_free;
 248 };
 249
 250 #include "be.h"
 251 #define chip_be2(phba)      (phba->generation == BE_GEN2)
 252 #define chip_be3_r(phba)    (phba->generation == BE_GEN3)
 253 #define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
 254
 255 #define BEISCSI_ULP0    0
 256 #define BEISCSI_ULP1    1
 257 #define BEISCSI_ULP_COUNT   2
 258 #define BEISCSI_ULP0_LOADED 0x01
 259 #define BEISCSI_ULP1_LOADED 0x02
 260
 261 #define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \
 262         (((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids)
 263 #define BEISCSI_ULP0_AVLBL_CID(phba) \
 264         BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0)
 265 #define BEISCSI_ULP1_AVLBL_CID(phba) \
 266         BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1)
 267
 268 struct beiscsi_hba {
 269         struct hba_parameters params;
 270         struct hwi_controller *phwi_ctrlr;
 271         unsigned int mem_req[SE_MEM_MAX];
 272         /* PCI BAR mapped addresses */
 273         u8 __iomem *csr_va;     /* CSR */
 274         u8 __iomem *db_va;      /* Door  Bell  */
 275         u8 __iomem *pci_va;     /* PCI Config */
 276         /* PCI representation of our HBA */
 277         struct pci_dev *pcidev;
 278         unsigned int num_cpus;
 279         unsigned int nxt_cqid;
 280         char *msi_name[MAX_CPUS];
 281         struct be_mem_descriptor *init_mem;
 282
 283         unsigned short io_sgl_alloc_index;
 284         unsigned short io_sgl_free_index;
 285         unsigned short io_sgl_hndl_avbl;
 286         struct sgl_handle **io_sgl_hndl_base;
 287
 288         unsigned short eh_sgl_alloc_index;
 289         unsigned short eh_sgl_free_index;
 290         unsigned short eh_sgl_hndl_avbl;
 291         struct sgl_handle **eh_sgl_hndl_base;
 292         spinlock_t io_sgl_lock;
 293         spinlock_t mgmt_sgl_lock;
 294         spinlock_t async_pdu_lock;
 295         struct list_head hba_queue;
 296 #define BE_MAX_SESSION 2048
 297 #define BE_INVALID_CID 0xffff
 298 #define BE_SET_CID_TO_CRI(cri_index, cid) \
 299                           (phba->cid_to_cri_map[cid] = cri_index)
 300 #define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
 301         unsigned short cid_to_cri_map[BE_MAX_SESSION];
 302         struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT];
 303         struct iscsi_endpoint **ep_array;
 304         struct beiscsi_conn **conn_table;
 305         struct Scsi_Host *shost;
 306         struct iscsi_iface *ipv4_iface;
 307         struct iscsi_iface *ipv6_iface;
 308         struct {
 309                 /**
 310                  * group together since they are used most frequently
 311                  * for cid to cri conversion
 312                  */
 313 #define BEISCSI_PHYS_PORT_MAX   4
 314                 unsigned int phys_port;
 315                 /* valid values of phys_port id are 0, 1, 2, 3 */
 316                 unsigned int eqid_count;
 317                 unsigned int cqid_count;
 318                 unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
 319 #define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
 320                 (phba->fw_config.iscsi_cid_count[ulp_num])
 321                 unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
 322                 unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
 323                 unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
 324                 unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
 325                 unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
 326
 327                 unsigned short iscsi_features;
 328                 uint16_t dual_ulp_aware;
 329                 unsigned long ulp_supported;
 330         } fw_config;
 331
 332         unsigned long state;
 333 #define BEISCSI_HBA_ONLINE      0
 334 #define BEISCSI_HBA_LINK_UP     1
 335 #define BEISCSI_HBA_BOOT_FOUND  2
 336 #define BEISCSI_HBA_BOOT_WORK   3
 337 #define BEISCSI_HBA_UER_SUPP    4
 338 #define BEISCSI_HBA_PCI_ERR     5
 339 #define BEISCSI_HBA_FW_TIMEOUT  6
 340 #define BEISCSI_HBA_IN_UE       7
 341 #define BEISCSI_HBA_IN_TPE      8
 342
 343 /* error bits */
 344 #define BEISCSI_HBA_IN_ERR      ((1 << BEISCSI_HBA_PCI_ERR) | \
 345                                  (1 << BEISCSI_HBA_FW_TIMEOUT) | \
 346                                  (1 << BEISCSI_HBA_IN_UE) | \
 347                                  (1 << BEISCSI_HBA_IN_TPE))
 348
 349         u8 optic_state;
 350         struct delayed_work eqd_update;
 351         /* update EQ delay timer every 1000ms */
 352 #define BEISCSI_EQD_UPDATE_INTERVAL     1000
 353         struct timer_list hw_check;
 354         /* check for UE every 1000ms */
 355 #define BEISCSI_UE_DETECT_INTERVAL      1000
 356         u32 ue2rp;
 357         struct delayed_work recover_port;
 358         struct work_struct sess_work;
 359
 360         bool mac_addr_set;
 361         u8 mac_address[ETH_ALEN];
 362         u8 port_name;
 363         u8 port_speed;
 364         char fw_ver_str[BEISCSI_VER_STRLEN];
 365         struct workqueue_struct *wq;    /* The actuak work queue */
 366         struct be_ctrl_info ctrl;
 367         unsigned int generation;
 368         unsigned int interface_handle;
 369
 370         struct be_aic_obj aic_obj[MAX_CPUS];
 371         unsigned int attr_log_enable;
 372         int (*iotask_fn)(struct iscsi_task *,
 373                         struct scatterlist *sg,
 374                         uint32_t num_sg, uint32_t xferlen,
 375                         uint32_t writedir);
 376         struct boot_struct {
 377                 int retry;
 378                 unsigned int tag;
 379                 unsigned int s_handle;
 380                 struct be_dma_mem nonemb_cmd;
 381                 enum {
 382                         BEISCSI_BOOT_REOPEN_SESS = 1,
 383                         BEISCSI_BOOT_GET_SHANDLE,
 384                         BEISCSI_BOOT_GET_SINFO,
 385                         BEISCSI_BOOT_LOGOUT_SESS,
 386                         BEISCSI_BOOT_CREATE_KSET,
 387                 } action;
 388                 struct mgmt_session_info boot_sess;
 389                 struct iscsi_boot_kset *boot_kset;
 390         } boot_struct;
 391         struct work_struct boot_work;
 392 };
 393
 394 #define beiscsi_hba_in_error(phba) ((phba)->state & BEISCSI_HBA_IN_ERR)
 395 #define beiscsi_hba_is_online(phba) \
 396         (!beiscsi_hba_in_error((phba)) && \
 397          test_bit(BEISCSI_HBA_ONLINE, &phba->state))
 398
 399 struct beiscsi_session {
 400         struct dma_pool *bhs_pool;
 401 };
 402
 403 /**
 404  * struct beiscsi_conn - iscsi connection structure
 405  */
 406 struct beiscsi_conn {
 407         struct iscsi_conn *conn;
 408         struct beiscsi_hba *phba;
 409         u32 exp_statsn;
 410         u32 doorbell_offset;
 411         u32 beiscsi_conn_cid;
 412         struct beiscsi_endpoint *ep;
 413         unsigned short login_in_progress;
 414         struct wrb_handle *plogin_wrb_handle;
 415         struct sgl_handle *plogin_sgl_handle;
 416         struct beiscsi_session *beiscsi_sess;
 417         struct iscsi_task *task;
 418 };
 419
 420 /* This structure is used by the chip */
 421 struct pdu_data_out {
 422         u32 dw[12];
 423 };
 424 /**
 425  * Pseudo amap definition in which each bit of the actual structure is defined
 426  * as a byte: used to calculate offset/shift/mask of each field
 427  */
 428 struct amap_pdu_data_out {
 429         u8 opcode[6];           /* opcode */
 430         u8 rsvd0[2];            /* should be 0 */
 431         u8 rsvd1[7];
 432         u8 final_bit;           /* F bit */
 433         u8 rsvd2[16];
 434         u8 ahs_length[8];       /* no AHS */
 435         u8 data_len_hi[8];
 436         u8 data_len_lo[16];     /* DataSegmentLength */
 437         u8 lun[64];
 438         u8 itt[32];             /* ITT; initiator task tag */
 439         u8 ttt[32];             /* TTT; valid for R2T or 0xffffffff */
 440         u8 rsvd3[32];
 441         u8 exp_stat_sn[32];
 442         u8 rsvd4[32];
 443         u8 data_sn[32];
 444         u8 buffer_offset[32];
 445         u8 rsvd5[32];
 446 };
 447
 448 struct be_cmd_bhs {
 449         struct iscsi_scsi_req iscsi_hdr;
 450         unsigned char pad1[16];
 451         struct pdu_data_out iscsi_data_pdu;
 452         unsigned char pad2[BE_SENSE_INFO_SIZE -
 453                         sizeof(struct pdu_data_out)];
 454 };
 455
 456 struct beiscsi_io_task {
 457         struct wrb_handle *pwrb_handle;
 458         struct sgl_handle *psgl_handle;
 459         struct beiscsi_conn *conn;
 460         struct scsi_cmnd *scsi_cmnd;
 461         int num_sg;
 462         struct hwi_wrb_context *pwrb_context;
 463         itt_t libiscsi_itt;
 464         struct be_cmd_bhs *cmd_bhs;
 465         struct be_bus_address bhs_pa;
 466         unsigned short bhs_len;
 467         dma_addr_t mtask_addr;
 468         uint32_t mtask_data_count;
 469         uint8_t wrb_type;
 470 };
 471
 472 struct be_nonio_bhs {
 473         struct iscsi_hdr iscsi_hdr;
 474         unsigned char pad1[16];
 475         struct pdu_data_out iscsi_data_pdu;
 476         unsigned char pad2[BE_SENSE_INFO_SIZE -
 477                         sizeof(struct pdu_data_out)];
 478 };
 479
 480 struct be_status_bhs {
 481         struct iscsi_scsi_req iscsi_hdr;
 482         unsigned char pad1[16];
 483         /**
 484          * The plus 2 below is to hold the sense info length that gets
 485          * DMA'ed by RxULP
 486          */
 487         unsigned char sense_info[BE_SENSE_INFO_SIZE];
 488 };
 489
 490 struct iscsi_sge {
 491         u32 dw[4];
 492 };
 493
 494 /**
 495  * Pseudo amap definition in which each bit of the actual structure is defined
 496  * as a byte: used to calculate offset/shift/mask of each field
 497  */
 498 struct amap_iscsi_sge {
 499         u8 addr_hi[32];
 500         u8 addr_lo[32];
 501         u8 sge_offset[22];      /* DWORD 2 */
 502         u8 rsvd0[9];            /* DWORD 2 */
 503         u8 last_sge;            /* DWORD 2 */
 504         u8 len[17];             /* DWORD 3 */
 505         u8 rsvd1[15];           /* DWORD 3 */
 506 };
 507
 508 struct beiscsi_offload_params {
 509         u32 dw[6];
 510 };
 511
 512 #define OFFLD_PARAMS_ERL        0x00000003
 513 #define OFFLD_PARAMS_DDE        0x00000004
 514 #define OFFLD_PARAMS_HDE        0x00000008
 515 #define OFFLD_PARAMS_IR2T       0x00000010
 516 #define OFFLD_PARAMS_IMD        0x00000020
 517 #define OFFLD_PARAMS_DATA_SEQ_INORDER   0x00000040
 518 #define OFFLD_PARAMS_PDU_SEQ_INORDER    0x00000080
 519 #define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
 520
 521 /**
 522  * Pseudo amap definition in which each bit of the actual structure is defined
 523  * as a byte: used to calculate offset/shift/mask of each field
 524  */
 525 struct amap_beiscsi_offload_params {
 526         u8 max_burst_length[32];
 527         u8 max_send_data_segment_length[32];
 528         u8 first_burst_length[32];
 529         u8 erl[2];
 530         u8 dde[1];
 531         u8 hde[1];
 532         u8 ir2t[1];
 533         u8 imd[1];
 534         u8 data_seq_inorder[1];
 535         u8 pdu_seq_inorder[1];
 536         u8 max_r2t[16];
 537         u8 pad[8];
 538         u8 exp_statsn[32];
 539         u8 max_recv_data_segment_length[32];
 540 };
 541
 542 struct hd_async_handle {
 543         struct list_head link;
 544         struct be_bus_address pa;
 545         void *pbuffer;
 546         u32 buffer_len;
 547         u16 index;
 548         u16 cri;
 549         u8 is_header;
 550         u8 is_final;
 551         u8 in_use;
 552 };
 553
 554 #define BEISCSI_ASYNC_HDQ_SIZE(phba, ulp) \
 555         (BEISCSI_GET_CID_COUNT((phba), (ulp)) * 2)
 556
 557 /**
 558  * This has list of async PDUs that are waiting to be processed.
 559  * Buffers live in this list for a brief duration before they get
 560  * processed and posted back to hardware.
 561  * Note that we don't really need one cri_wait_queue per async_entry.
 562  * We need one cri_wait_queue per CRI. Its easier to manage if this
 563  * is tagged along with the async_entry.
 564  */
 565 struct hd_async_entry {
 566         struct cri_wait_queue {
 567                 unsigned short hdr_len;
 568                 unsigned int bytes_received;
 569                 unsigned int bytes_needed;
 570                 struct list_head list;
 571         } wq;
 572         /* handles posted to FW resides here */
 573         struct hd_async_handle *header;
 574         struct hd_async_handle *data;
 575 };
 576
 577 struct hd_async_buf_context {
 578         struct be_bus_address pa_base;
 579         void *va_base;
 580         void *ring_base;
 581         struct hd_async_handle *handle_base;
 582         u32 buffer_size;
 583         u16 pi;
 584 };
 585
 586 /**
 587  * hd_async_context is declared for each ULP supporting iSCSI function.
 588  */
 589 struct hd_async_context {
 590         struct hd_async_buf_context async_header;
 591         struct hd_async_buf_context async_data;
 592         u16 num_entries;
 593         /**
 594          * When unsol PDU is in, it needs to be chained till all the bytes are
 595          * received and then processing is done. hd_async_entry is created
 596          * based on the cid_count for each ULP. When unsol PDU comes in based
 597          * on the conn_id it needs to be added to the correct async_entry wq.
 598          * Below defined cid_to_async_cri_map is used to reterive the
 599          * async_cri_map for a particular connection.
 600          *
 601          * This array is initialized after beiscsi_create_wrb_rings returns.
 602          *
 603          * - this method takes more memory space, fixed to 2K
 604          * - any support for connections greater than this the array size needs
 605          * to be incremented
 606          */
 607 #define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
 608         unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
 609         /**
 610          * This is a variable size array. Don`t add anything after this field!!
 611          */
 612         struct hd_async_entry *async_entry;
 613 };
 614
 615 struct i_t_dpdu_cqe {
 616         u32 dw[4];
 617 } __packed;
 618
 619 /**
 620  * Pseudo amap definition in which each bit of the actual structure is defined
 621  * as a byte: used to calculate offset/shift/mask of each field
 622  */
 623 struct amap_i_t_dpdu_cqe {
 624         u8 db_addr_hi[32];
 625         u8 db_addr_lo[32];
 626         u8 code[6];
 627         u8 cid[10];
 628         u8 dpl[16];
 629         u8 index[16];
 630         u8 num_cons[10];
 631         u8 rsvd0[4];
 632         u8 final;
 633         u8 valid;
 634 } __packed;
 635
 636 struct amap_i_t_dpdu_cqe_v2 {
 637         u8 db_addr_hi[32];  /* DWORD 0 */
 638         u8 db_addr_lo[32];  /* DWORD 1 */
 639         u8 code[6]; /* DWORD 2 */
 640         u8 num_cons; /* DWORD 2*/
 641         u8 rsvd0[8]; /* DWORD 2 */
 642         u8 dpl[17]; /* DWORD 2 */
 643         u8 index[16]; /* DWORD 3 */
 644         u8 cid[13]; /* DWORD 3 */
 645         u8 rsvd1; /* DWORD 3 */
 646         u8 final; /* DWORD 3 */
 647         u8 valid; /* DWORD 3 */
 648 } __packed;
 649
 650 #define CQE_VALID_MASK  0x80000000
 651 #define CQE_CODE_MASK   0x0000003F
 652 #define CQE_CID_MASK    0x0000FFC0
 653
 654 #define EQE_VALID_MASK          0x00000001
 655 #define EQE_MAJORCODE_MASK      0x0000000E
 656 #define EQE_RESID_MASK          0xFFFF0000
 657
 658 struct be_eq_entry {
 659         u32 dw[1];
 660 } __packed;
 661
 662 /**
 663  * Pseudo amap definition in which each bit of the actual structure is defined
 664  * as a byte: used to calculate offset/shift/mask of each field
 665  */
 666 struct amap_eq_entry {
 667         u8 valid;               /* DWORD 0 */
 668         u8 major_code[3];       /* DWORD 0 */
 669         u8 minor_code[12];      /* DWORD 0 */
 670         u8 resource_id[16];     /* DWORD 0 */
 671
 672 } __packed;
 673
 674 struct cq_db {
 675         u32 dw[1];
 676 } __packed;
 677
 678 /**
 679  * Pseudo amap definition in which each bit of the actual structure is defined
 680  * as a byte: used to calculate offset/shift/mask of each field
 681  */
 682 struct amap_cq_db {
 683         u8 qid[10];
 684         u8 event[1];
 685         u8 rsvd0[5];
 686         u8 num_popped[13];
 687         u8 rearm[1];
 688         u8 rsvd1[2];
 689 } __packed;
 690
 691 void beiscsi_process_eq(struct beiscsi_hba *phba);
 692
 693 struct iscsi_wrb {
 694         u32 dw[16];
 695 } __packed;
 696
 697 #define WRB_TYPE_MASK 0xF0000000
 698 #define SKH_WRB_TYPE_OFFSET 27
 699 #define BE_WRB_TYPE_OFFSET  28
 700
 701 #define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
 702                 (pwrb->dw[0] |= (wrb_type << type_offset))
 703
 704 /**
 705  * Pseudo amap definition in which each bit of the actual structure is defined
 706  * as a byte: used to calculate offset/shift/mask of each field
 707  */
 708 struct amap_iscsi_wrb {
 709         u8 lun[14];             /* DWORD 0 */
 710         u8 lt;                  /* DWORD 0 */
 711         u8 invld;               /* DWORD 0 */
 712         u8 wrb_idx[8];          /* DWORD 0 */
 713         u8 dsp;                 /* DWORD 0 */
 714         u8 dmsg;                /* DWORD 0 */
 715         u8 undr_run;            /* DWORD 0 */
 716         u8 over_run;            /* DWORD 0 */
 717         u8 type[4];             /* DWORD 0 */
 718         u8 ptr2nextwrb[8];      /* DWORD 1 */
 719         u8 r2t_exp_dtl[24];     /* DWORD 1 */
 720         u8 sgl_icd_idx[12];     /* DWORD 2 */
 721         u8 rsvd0[20];           /* DWORD 2 */
 722         u8 exp_data_sn[32];     /* DWORD 3 */
 723         u8 iscsi_bhs_addr_hi[32];       /* DWORD 4 */
 724         u8 iscsi_bhs_addr_lo[32];       /* DWORD 5 */
 725         u8 cmdsn_itt[32];       /* DWORD 6 */
 726         u8 dif_ref_tag[32];     /* DWORD 7 */
 727         u8 sge0_addr_hi[32];    /* DWORD 8 */
 728         u8 sge0_addr_lo[32];    /* DWORD 9  */
 729         u8 sge0_offset[22];     /* DWORD 10 */
 730         u8 pbs;                 /* DWORD 10 */
 731         u8 dif_mode[2];         /* DWORD 10 */
 732         u8 rsvd1[6];            /* DWORD 10 */
 733         u8 sge0_last;           /* DWORD 10 */
 734         u8 sge0_len[17];        /* DWORD 11 */
 735         u8 dif_meta_tag[14];    /* DWORD 11 */
 736         u8 sge0_in_ddr;         /* DWORD 11 */
 737         u8 sge1_addr_hi[32];    /* DWORD 12 */
 738         u8 sge1_addr_lo[32];    /* DWORD 13 */
 739         u8 sge1_r2t_offset[22]; /* DWORD 14 */
 740         u8 rsvd2[9];            /* DWORD 14 */
 741         u8 sge1_last;           /* DWORD 14 */
 742         u8 sge1_len[17];        /* DWORD 15 */
 743         u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
 744         u8 rsvd3[2];            /* DWORD 15 */
 745         u8 sge1_in_ddr;         /* DWORD 15 */
 746
 747 } __packed;
 748
 749 struct amap_iscsi_wrb_v2 {
 750         u8 r2t_exp_dtl[25]; /* DWORD 0 */
 751         u8 rsvd0[2];    /* DWORD 0*/
 752         u8 type[5];     /* DWORD 0 */
 753         u8 ptr2nextwrb[8];  /* DWORD 1 */
 754         u8 wrb_idx[8];      /* DWORD 1 */
 755         u8 lun[16];     /* DWORD 1 */
 756         u8 sgl_idx[16]; /* DWORD 2 */
 757         u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
 758         u8 exp_data_sn[32]; /* DWORD 3 */
 759         u8 iscsi_bhs_addr_hi[32];   /* DWORD 4 */
 760         u8 iscsi_bhs_addr_lo[32];   /* DWORD 5 */
 761         u8 cq_id[16];   /* DWORD 6 */
 762         u8 rsvd1[16];   /* DWORD 6 */
 763         u8 cmdsn_itt[32];   /* DWORD 7 */
 764         u8 sge0_addr_hi[32];    /* DWORD 8 */
 765         u8 sge0_addr_lo[32];    /* DWORD 9 */
 766         u8 sge0_offset[24]; /* DWORD 10 */
 767         u8 rsvd2[7];    /* DWORD 10 */
 768         u8 sge0_last;   /* DWORD 10 */
 769         u8 sge0_len[17];    /* DWORD 11 */
 770         u8 rsvd3[7];    /* DWORD 11 */
 771         u8 diff_enbl;   /* DWORD 11 */
 772         u8 u_run;       /* DWORD 11 */
 773         u8 o_run;       /* DWORD 11 */
 774         u8 invld;     /* DWORD 11 */
 775         u8 dsp;         /* DWORD 11 */
 776         u8 dmsg;        /* DWORD 11 */
 777         u8 rsvd4;       /* DWORD 11 */
 778         u8 lt;          /* DWORD 11 */
 779         u8 sge1_addr_hi[32];    /* DWORD 12 */
 780         u8 sge1_addr_lo[32];    /* DWORD 13 */
 781         u8 sge1_r2t_offset[24]; /* DWORD 14 */
 782         u8 rsvd5[7];    /* DWORD 14 */
 783         u8 sge1_last;   /* DWORD 14 */
 784         u8 sge1_len[17];    /* DWORD 15 */
 785         u8 rsvd6[15];   /* DWORD 15 */
 786 } __packed;
 787
 788
 789 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
 790                                      struct hwi_wrb_context **pcontext);
 791 void
 792 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
 793
 794 void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
 795                                      struct iscsi_task *task);
 796
 797 void hwi_ring_cq_db(struct beiscsi_hba *phba,
 798                      unsigned int id, unsigned int num_processed,
 799                      unsigned char rearm);
 800
 801 unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget);
 802 void beiscsi_process_mcc_cq(struct beiscsi_hba *phba);
 803
 804 struct pdu_nop_out {
 805         u32 dw[12];
 806 };
 807
 808 /**
 809  * Pseudo amap definition in which each bit of the actual structure is defined
 810  * as a byte: used to calculate offset/shift/mask of each field
 811  */
 812 struct amap_pdu_nop_out {
 813         u8 opcode[6];           /* opcode 0x00 */
 814         u8 i_bit;               /* I Bit */
 815         u8 x_bit;               /* reserved; should be 0 */
 816         u8 fp_bit_filler1[7];
 817         u8 f_bit;               /* always 1 */
 818         u8 reserved1[16];
 819         u8 ahs_length[8];       /* no AHS */
 820         u8 data_len_hi[8];
 821         u8 data_len_lo[16];     /* DataSegmentLength */
 822         u8 lun[64];
 823         u8 itt[32];             /* initiator id for ping or 0xffffffff */
 824         u8 ttt[32];             /* target id for ping or 0xffffffff */
 825         u8 cmd_sn[32];
 826         u8 exp_stat_sn[32];
 827         u8 reserved5[128];
 828 };
 829
 830 #define PDUBASE_OPCODE_MASK     0x0000003F
 831 #define PDUBASE_DATALENHI_MASK  0x0000FF00
 832 #define PDUBASE_DATALENLO_MASK  0xFFFF0000
 833
 834 struct pdu_base {
 835         u32 dw[16];
 836 } __packed;
 837
 838 /**
 839  * Pseudo amap definition in which each bit of the actual structure is defined
 840  * as a byte: used to calculate offset/shift/mask of each field
 841  */
 842 struct amap_pdu_base {
 843         u8 opcode[6];
 844         u8 i_bit;               /* immediate bit */
 845         u8 x_bit;               /* reserved, always 0 */
 846         u8 reserved1[24];       /* opcode-specific fields */
 847         u8 ahs_length[8];       /* length units is 4 byte words */
 848         u8 data_len_hi[8];
 849         u8 data_len_lo[16];     /* DatasegmentLength */
 850         u8 lun[64];             /* lun or opcode-specific fields */
 851         u8 itt[32];             /* initiator task tag */
 852         u8 reserved4[224];
 853 };
 854
 855 struct iscsi_target_context_update_wrb {
 856         u32 dw[16];
 857 } __packed;
 858
 859 /**
 860  * Pseudo amap definition in which each bit of the actual structure is defined
 861  * as a byte: used to calculate offset/shift/mask of each field
 862  */
 863 #define BE_TGT_CTX_UPDT_CMD 0x07
 864 struct amap_iscsi_target_context_update_wrb {
 865         u8 lun[14];             /* DWORD 0 */
 866         u8 lt;                  /* DWORD 0 */
 867         u8 invld;               /* DWORD 0 */
 868         u8 wrb_idx[8];          /* DWORD 0 */
 869         u8 dsp;                 /* DWORD 0 */
 870         u8 dmsg;                /* DWORD 0 */
 871         u8 undr_run;            /* DWORD 0 */
 872         u8 over_run;            /* DWORD 0 */
 873         u8 type[4];             /* DWORD 0 */
 874         u8 ptr2nextwrb[8];      /* DWORD 1 */
 875         u8 max_burst_length[19];        /* DWORD 1 */
 876         u8 rsvd0[5];            /* DWORD 1 */
 877         u8 rsvd1[15];           /* DWORD 2 */
 878         u8 max_send_data_segment_length[17];    /* DWORD 2 */
 879         u8 first_burst_length[14];      /* DWORD 3 */
 880         u8 rsvd2[2];            /* DWORD 3 */
 881         u8 tx_wrbindex_drv_msg[8];      /* DWORD 3 */
 882         u8 rsvd3[5];            /* DWORD 3 */
 883         u8 session_state[3];    /* DWORD 3 */
 884         u8 rsvd4[16];           /* DWORD 4 */
 885         u8 tx_jumbo;            /* DWORD 4 */
 886         u8 hde;                 /* DWORD 4 */
 887         u8 dde;                 /* DWORD 4 */
 888         u8 erl[2];              /* DWORD 4 */
 889         u8 domain_id[5];                /* DWORD 4 */
 890         u8 mode;                /* DWORD 4 */
 891         u8 imd;                 /* DWORD 4 */
 892         u8 ir2t;                /* DWORD 4 */
 893         u8 notpredblq[2];       /* DWORD 4 */
 894         u8 compltonack;         /* DWORD 4 */
 895         u8 stat_sn[32];         /* DWORD 5 */
 896         u8 pad_buffer_addr_hi[32];      /* DWORD 6 */
 897         u8 pad_buffer_addr_lo[32];      /* DWORD 7 */
 898         u8 pad_addr_hi[32];     /* DWORD 8 */
 899         u8 pad_addr_lo[32];     /* DWORD 9 */
 900         u8 rsvd5[32];           /* DWORD 10 */
 901         u8 rsvd6[32];           /* DWORD 11 */
 902         u8 rsvd7[32];           /* DWORD 12 */
 903         u8 rsvd8[32];           /* DWORD 13 */
 904         u8 rsvd9[32];           /* DWORD 14 */
 905         u8 rsvd10[32];          /* DWORD 15 */
 906
 907 } __packed;
 908
 909 #define BEISCSI_MAX_RECV_DATASEG_LEN    (64 * 1024)
 910 #define BEISCSI_MAX_CXNS    1
 911 struct amap_iscsi_target_context_update_wrb_v2 {
 912         u8 max_burst_length[24];    /* DWORD 0 */
 913         u8 rsvd0[3];    /* DWORD 0 */
 914         u8 type[5];     /* DWORD 0 */
 915         u8 ptr2nextwrb[8];  /* DWORD 1 */
 916         u8 wrb_idx[8];      /* DWORD 1 */
 917         u8 rsvd1[16];       /* DWORD 1 */
 918         u8 max_send_data_segment_length[24];    /* DWORD 2 */
 919         u8 rsvd2[8];    /* DWORD 2 */
 920         u8 first_burst_length[24]; /* DWORD 3 */
 921         u8 rsvd3[8]; /* DOWRD 3 */
 922         u8 max_r2t[16]; /* DWORD 4 */
 923         u8 rsvd4;       /* DWORD 4 */
 924         u8 hde;         /* DWORD 4 */
 925         u8 dde;         /* DWORD 4 */
 926         u8 erl[2];      /* DWORD 4 */
 927         u8 rsvd5[6];    /* DWORD 4 */
 928         u8 imd;         /* DWORD 4 */
 929         u8 ir2t;        /* DWORD 4 */
 930         u8 rsvd6[3];    /* DWORD 4 */
 931         u8 stat_sn[32];     /* DWORD 5 */
 932         u8 rsvd7[32];   /* DWORD 6 */
 933         u8 rsvd8[32];   /* DWORD 7 */
 934         u8 max_recv_dataseg_len[24];    /* DWORD 8 */
 935         u8 rsvd9[8]; /* DWORD 8 */
 936         u8 rsvd10[32];   /* DWORD 9 */
 937         u8 rsvd11[32];   /* DWORD 10 */
 938         u8 max_cxns[16]; /* DWORD 11 */
 939         u8 rsvd12[11]; /* DWORD  11*/
 940         u8 invld; /* DWORD 11 */
 941         u8 rsvd13;/* DWORD 11*/
 942         u8 dmsg; /* DWORD 11 */
 943         u8 data_seq_inorder; /* DWORD 11 */
 944         u8 pdu_seq_inorder; /* DWORD 11 */
 945         u8 rsvd14[32]; /*DWORD 12 */
 946         u8 rsvd15[32]; /* DWORD 13 */
 947         u8 rsvd16[32]; /* DWORD 14 */
 948         u8 rsvd17[32]; /* DWORD 15 */
 949 } __packed;
 950
 951
 952 struct be_ring {
 953         u32 pages;              /* queue size in pages */
 954         u32 id;                 /* queue id assigned by beklib */
 955         u32 num;                /* number of elements in queue */
 956         u32 cidx;               /* consumer index */
 957         u32 pidx;               /* producer index -- not used by most rings */
 958         u32 item_size;          /* size in bytes of one object */
 959         u8 ulp_num;     /* ULP to which CID binded */
 960         u16 register_set;
 961         u16 doorbell_format;
 962         u32 doorbell_offset;
 963
 964         void *va;               /* The virtual address of the ring.  This
 965                                  * should be last to allow 32 & 64 bit debugger
 966                                  * extensions to work.
 967                                  */
 968 };
 969
 970 struct hwi_controller {
 971         struct hwi_wrb_context *wrb_context;
 972         struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
 973         struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
 974         struct hwi_context_memory *phwi_ctxt;
 975 };
 976
 977 enum hwh_type_enum {
 978         HWH_TYPE_IO = 1,
 979         HWH_TYPE_LOGOUT = 2,
 980         HWH_TYPE_TMF = 3,
 981         HWH_TYPE_NOP = 4,
 982         HWH_TYPE_IO_RD = 5,
 983         HWH_TYPE_LOGIN = 11,
 984         HWH_TYPE_INVALID = 0xFFFFFFFF
 985 };
 986
 987 struct wrb_handle {
 988         unsigned short wrb_index;
 989         struct iscsi_task *pio_handle;
 990         struct iscsi_wrb *pwrb;
 991 };
 992
 993 struct hwi_context_memory {
 994         struct be_eq_obj be_eq[MAX_CPUS];
 995         struct be_queue_info be_cq[MAX_CPUS - 1];
 996
 997         struct be_queue_info *be_wrbq;
 998         /**
 999          * Create array of ULP number for below entries as DEFQ
1000          * will be created for both ULP if iSCSI Protocol is
1001          * loaded on both ULP.
1002          */
1003         struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
1004         struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
1005         struct hd_async_context *pasync_ctx[BEISCSI_ULP_COUNT];
1006 };
1007
1008 void beiscsi_start_boot_work(struct beiscsi_hba *phba, unsigned int s_handle);
1009
1010 /* Logging related definitions */
1011 #define BEISCSI_LOG_INIT        0x0001  /* Initialization events */
1012 #define BEISCSI_LOG_MBOX        0x0002  /* Mailbox Events */
1013 #define BEISCSI_LOG_MISC        0x0004  /* Miscllaneous Events */
1014 #define BEISCSI_LOG_EH          0x0008  /* Error Handler */
1015 #define BEISCSI_LOG_IO          0x0010  /* IO Code Path */
1016 #define BEISCSI_LOG_CONFIG      0x0020  /* CONFIG Code Path */
1017 #define BEISCSI_LOG_ISCSI       0x0040  /* SCSI/iSCSI Protocol related Logs */
1018
1019 #define __beiscsi_log(phba, level, fmt, arg...) \
1020         shost_printk(level, phba->shost, fmt, __LINE__, ##arg)
1021
1022 #define beiscsi_log(phba, level, mask, fmt, arg...) \
1023 do { \
1024         uint32_t log_value = phba->attr_log_enable; \
1025                 if (((mask) & log_value) || (level[1] <= '3')) \
1026                         __beiscsi_log(phba, level, fmt, ##arg); \
1027 } while (0);
1028
1029 #endif