1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2016 Imagination Technologies
4 * Author: Marcin Nowakowski <marcin.nowakowski@mips.com>
7 #ifndef __PROBES_COMMON_H
8 #define __PROBES_COMMON_H
12 int __insn_is_compact_branch(union mips_instruction insn
);
14 static inline int __insn_has_delay_slot(const union mips_instruction insn
)
16 switch (insn
.i_format
.opcode
) {
18 * jr and jalr are in r_format format.
21 switch (insn
.r_format
.func
) {
29 * This group contains:
30 * bltz_op, bgez_op, bltzl_op, bgezl_op,
31 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
34 switch (insn
.i_format
.rt
) {
49 * These are unconditional and in j_format.
57 case blez_op
: /* not really i_format */
64 * And now the FPA/cp1 branch instructions.
67 #ifdef CONFIG_CPU_CAVIUM_OCTEON
68 case lwc2_op
: /* This is bbit0 on Octeon */
69 case ldc2_op
: /* This is bbit032 on Octeon */
70 case swc2_op
: /* This is bbit1 on Octeon */
71 case sdc2_op
: /* This is bbit132 on Octeon */
79 #endif /* __PROBES_COMMON_H */