include/fx2regs.h

   1 // Copyright (C) 2009 Ubixum, Inc.
   2 //
   3 // This library is free software; you can redistribute it and/or
   4 // modify it under the terms of the GNU Lesser General Public
   5 // License as published by the Free Software Foundation; either
   6 // version 2.1 of the License, or (at your option) any later version.
   7 //
   8 // This library is distributed in the hope that it will be useful,
   9 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11 // Lesser General Public License for more details.
  12 //
  13 // You should have received a copy of the GNU Lesser General Public
  14 // License along with this library; if not, write to the Free Software
  15 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
  16
  17 /*! \file
  18  *
  19  * This is the basic header/register file for working with the cypress fx2
  20  * (cyc768013) and variants 8051 chipset.  It contains the special function
  21  * register definitions as well as the special configuration registers
  22  * addresses.
  23  *
  24  * The TRM for the fx2 chip contains the full documentation for what each of
  25  * these registers do.
  26  *
  27  * */
  28
  29
  30 /** \mainpage FX2LIB Documentation
  31  *  \verbinclude README
  32  **/
  33
  34 /** \example fw.c
  35  * The firmware framework allows for easily beginning a new firware project.
  36  **/
  37
  38 #ifndef FX2REGS_H
  39 #define FX2REGS_H
  40
  41 #include "fx2types.h"
  42
  43 __xdata __at(0xE400) volatile BYTE GPIF_WAVE_DATA;
  44 __xdata __at(0xE480) volatile BYTE RES_WAVEDATA_END;
  45
  46 // General Configuration
  47
  48 __xdata __at(0xE600) volatile BYTE CPUCS;  ///< Control & Status
  49 __xdata __at(0xE601) volatile BYTE IFCONFIG;  ///< Interface Configuration
  50 __xdata __at(0xE602) volatile BYTE PINFLAGSAB;  ///< FIFO FLAGA and FLAGB Assignments
  51 __xdata __at(0xE603) volatile BYTE PINFLAGSCD;  ///< FIFO FLAGC and FLAGD Assignments
  52 __xdata __at(0xE604) volatile BYTE FIFORESET;  ///< Restore FIFOS to default state
  53 __xdata __at(0xE605) volatile BYTE BREAKPT;  ///< Breakpoint
  54 __xdata __at(0xE606) volatile BYTE BPADDRH;  ///< Breakpoint Address H
  55 __xdata __at(0xE607) volatile BYTE BPADDRL;  ///< Breakpoint Address L
  56 __xdata __at(0xE608) volatile BYTE UART230;  ///< 230 Kbaud clock for T0,T1,T2
  57 __xdata __at(0xE609) volatile BYTE FIFOPINPOLAR;  ///< FIFO polarities
  58 __xdata __at(0xE60A) volatile BYTE REVID;  ///< Chip Revision
  59 __xdata __at(0xE60B) volatile BYTE REVCTL;  ///< Chip Revision Control
  60
  61 // Endpoint Configuration
  62
  63 __xdata __at(0xE610) volatile BYTE EP1OUTCFG;  ///< Endpoint 1-OUT Configuration
  64 __xdata __at(0xE611) volatile BYTE EP1INCFG;  ///< Endpoint 1-IN Configuration
  65 __xdata __at(0xE612) volatile BYTE EP2CFG;  ///< Endpoint 2 Configuration
  66 __xdata __at(0xE613) volatile BYTE EP4CFG;  ///< Endpoint 4 Configuration
  67 __xdata __at(0xE614) volatile BYTE EP6CFG;  ///< Endpoint 6 Configuration
  68 __xdata __at(0xE615) volatile BYTE EP8CFG;  ///< Endpoint 8 Configuration
  69 __xdata __at(0xE618) volatile BYTE EP2FIFOCFG;  ///< Endpoint 2 FIFO configuration
  70 __xdata __at(0xE619) volatile BYTE EP4FIFOCFG;  ///< Endpoint 4 FIFO configuration
  71 __xdata __at(0xE61A) volatile BYTE EP6FIFOCFG;  ///< Endpoint 6 FIFO configuration
  72 __xdata __at(0xE61B) volatile BYTE EP8FIFOCFG;  ///< Endpoint 8 FIFO configuration
  73 __xdata __at(0xE620) volatile BYTE EP2AUTOINLENH;  ///< Endpoint 2 Packet Length H (IN only)
  74 __xdata __at(0xE621) volatile BYTE EP2AUTOINLENL;  ///< Endpoint 2 Packet Length L (IN only)
  75 __xdata __at(0xE622) volatile BYTE EP4AUTOINLENH;  ///< Endpoint 4 Packet Length H (IN only)
  76 __xdata __at(0xE623) volatile BYTE EP4AUTOINLENL;  ///< Endpoint 4 Packet Length L (IN only)
  77 __xdata __at(0xE624) volatile BYTE EP6AUTOINLENH;  ///< Endpoint 6 Packet Length H (IN only)
  78 __xdata __at(0xE625) volatile BYTE EP6AUTOINLENL;  ///< Endpoint 6 Packet Length L (IN only)
  79 __xdata __at(0xE626) volatile BYTE EP8AUTOINLENH;  ///< Endpoint 8 Packet Length H (IN only)
  80 __xdata __at(0xE627) volatile BYTE EP8AUTOINLENL;  ///< Endpoint 8 Packet Length L (IN only)
  81 __xdata __at(0xE630) volatile BYTE EP2FIFOPFH;  ///< EP2 Programmable Flag trigger H
  82 __xdata __at(0xE631) volatile BYTE EP2FIFOPFL;  ///< EP2 Programmable Flag trigger L
  83 __xdata __at(0xE632) volatile BYTE EP4FIFOPFH;  ///< EP4 Programmable Flag trigger H
  84 __xdata __at(0xE633) volatile BYTE EP4FIFOPFL;  ///< EP4 Programmable Flag trigger L
  85 __xdata __at(0xE634) volatile BYTE EP6FIFOPFH;  ///< EP6 Programmable Flag trigger H
  86 __xdata __at(0xE635) volatile BYTE EP6FIFOPFL;  ///< EP6 Programmable Flag trigger L
  87 __xdata __at(0xE636) volatile BYTE EP8FIFOPFH;  ///< EP8 Programmable Flag trigger H
  88 __xdata __at(0xE637) volatile BYTE EP8FIFOPFL;  ///< EP8 Programmable Flag trigger L
  89 __xdata __at(0xE640) volatile BYTE EP2ISOINPKTS;  ///< EP2 (if ISO) IN Packets per frame (1-3)
  90 __xdata __at(0xE641) volatile BYTE EP4ISOINPKTS;  ///< EP4 (if ISO) IN Packets per frame (1-3)
  91 __xdata __at(0xE642) volatile BYTE EP6ISOINPKTS;  ///< EP6 (if ISO) IN Packets per frame (1-3)
  92 __xdata __at(0xE643) volatile BYTE EP8ISOINPKTS;  ///< EP8 (if ISO) IN Packets per frame (1-3)
  93 __xdata __at(0xE648) volatile BYTE INPKTEND;  ///< Force IN Packet End
  94 __xdata __at(0xE649) volatile BYTE OUTPKTEND;  ///< Force OUT Packet End
  95
  96 // Interrupts
  97
  98 __xdata __at(0xE650) volatile BYTE EP2FIFOIE;  ///< Endpoint 2 Flag Interrupt Enable
  99 __xdata __at(0xE651) volatile BYTE EP2FIFOIRQ;  ///< Endpoint 2 Flag Interrupt Request
 100 __xdata __at(0xE652) volatile BYTE EP4FIFOIE;  ///< Endpoint 4 Flag Interrupt Enable
 101 __xdata __at(0xE653) volatile BYTE EP4FIFOIRQ;  ///< Endpoint 4 Flag Interrupt Request
 102 __xdata __at(0xE654) volatile BYTE EP6FIFOIE;  ///< Endpoint 6 Flag Interrupt Enable
 103 __xdata __at(0xE655) volatile BYTE EP6FIFOIRQ;  ///< Endpoint 6 Flag Interrupt Request
 104 __xdata __at(0xE656) volatile BYTE EP8FIFOIE;  ///< Endpoint 8 Flag Interrupt Enable
 105 __xdata __at(0xE657) volatile BYTE EP8FIFOIRQ;  ///< Endpoint 8 Flag Interrupt Request
 106 __xdata __at(0xE658) volatile BYTE IBNIE;  ///< IN-BULK-NAK Interrupt Enable
 107 __xdata __at(0xE659) volatile BYTE IBNIRQ;  ///< IN-BULK-NAK interrupt Request
 108 __xdata __at(0xE65A) volatile BYTE NAKIE;  ///< Endpoint Ping NAK interrupt Enable
 109 __xdata __at(0xE65B) volatile BYTE NAKIRQ;  ///< Endpoint Ping NAK interrupt Request
 110 __xdata __at(0xE65C) volatile BYTE USBIE;  ///< USB Int Enables
 111 __xdata __at(0xE65D) volatile BYTE USBIRQ;  ///< USB Interrupt Requests
 112 __xdata __at(0xE65E) volatile BYTE EPIE;  ///< Endpoint Interrupt Enables
 113 __xdata __at(0xE65F) volatile BYTE EPIRQ;  ///< Endpoint Interrupt Requests
 114 __xdata __at(0xE660) volatile BYTE GPIFIE;  ///< GPIF Interrupt Enable
 115 __xdata __at(0xE661) volatile BYTE GPIFIRQ;  ///< GPIF Interrupt Request
 116 __xdata __at(0xE662) volatile BYTE USBERRIE;  ///< USB Error Interrupt Enables
 117 __xdata __at(0xE663) volatile BYTE USBERRIRQ;  ///< USB Error Interrupt Requests
 118 __xdata __at(0xE664) volatile BYTE ERRCNTLIM;  ///< USB Error counter and limit
 119 __xdata __at(0xE665) volatile BYTE CLRERRCNT;  ///< Clear Error Counter EC[3..0]
 120 __xdata __at(0xE666) volatile BYTE INT2IVEC;  ///< Interupt 2 (USB) Autovector
 121 __xdata __at(0xE667) volatile BYTE INT4IVEC;  ///< Interupt 4 (FIFOS & GPIF) Autovector
 122 __xdata __at(0xE668) volatile BYTE INTSETUP;  ///< Interrupt 2&4 Setup
 123
 124 // Input/Output
 125
 126 __xdata __at(0xE670) volatile BYTE PORTACFG;  ///< I/O PORTA Alternate Configuration
 127 __xdata __at(0xE671) volatile BYTE PORTCCFG;  ///< I/O PORTC Alternate Configuration
 128 __xdata __at(0xE672) volatile BYTE PORTECFG;  ///< I/O PORTE Alternate Configuration
 129 __xdata __at(0xE678) volatile BYTE I2CS;  ///< Control & Status
 130 __xdata __at(0xE679) volatile BYTE I2DAT;  ///< Data
 131 __xdata __at(0xE67A) volatile BYTE I2CTL;  ///< I2C Control
 132 __xdata __at(0xE67B) volatile BYTE XAUTODAT1;  ///< Autoptr1 MOVX access
 133 __xdata __at(0xE67C) volatile BYTE XAUTODAT2;  ///< Autoptr2 MOVX access
 134
 135 #define EXTAUTODAT1 XAUTODAT1
 136 #define EXTAUTODAT2 XAUTODAT2
 137
 138 // USB Control
 139
 140 __xdata __at(0xE680) volatile BYTE USBCS;  ///< USB Control & Status
 141 __xdata __at(0xE681) volatile BYTE SUSPEND;  ///< Put chip into suspend
 142 __xdata __at(0xE682) volatile BYTE WAKEUPCS;  ///< Wakeup source and polarity
 143 __xdata __at(0xE683) volatile BYTE TOGCTL;  ///< Toggle Control
 144 __xdata __at(0xE684) volatile BYTE USBFRAMEH;  ///< USB Frame count H
 145 __xdata __at(0xE685) volatile BYTE USBFRAMEL;  ///< USB Frame count L
 146 __xdata __at(0xE686) volatile BYTE MICROFRAME;  ///< Microframe count, 0-7
 147 __xdata __at(0xE687) volatile BYTE FNADDR;  ///< USB Function address
 148
 149 // Endpoints
 150
 151 __xdata __at(0xE68A) volatile BYTE EP0BCH;  ///< Endpoint 0 Byte Count H
 152 __xdata __at(0xE68B) volatile BYTE EP0BCL;  ///< Endpoint 0 Byte Count L
 153 __xdata __at(0xE68D) volatile BYTE EP1OUTBC;  ///< Endpoint 1 OUT Byte Count
 154 __xdata __at(0xE68F) volatile BYTE EP1INBC;  ///< Endpoint 1 IN Byte Count
 155 __xdata __at(0xE690) volatile BYTE EP2BCH;  ///< Endpoint 2 Byte Count H
 156 __xdata __at(0xE691) volatile BYTE EP2BCL;  ///< Endpoint 2 Byte Count L
 157 __xdata __at(0xE694) volatile BYTE EP4BCH;  ///< Endpoint 4 Byte Count H
 158 __xdata __at(0xE695) volatile BYTE EP4BCL;  ///< Endpoint 4 Byte Count L
 159 __xdata __at(0xE698) volatile BYTE EP6BCH;  ///< Endpoint 6 Byte Count H
 160 __xdata __at(0xE699) volatile BYTE EP6BCL;  ///< Endpoint 6 Byte Count L
 161 __xdata __at(0xE69C) volatile BYTE EP8BCH;  ///< Endpoint 8 Byte Count H
 162 __xdata __at(0xE69D) volatile BYTE EP8BCL;  ///< Endpoint 8 Byte Count L
 163 __xdata __at(0xE6A0) volatile BYTE EP0CS;  ///< Endpoint  Control and Status
 164 __xdata __at(0xE6A1) volatile BYTE EP1OUTCS;  ///< Endpoint 1 OUT Control and Status
 165 __xdata __at(0xE6A2) volatile BYTE EP1INCS;  ///< Endpoint 1 IN Control and Status
 166 __xdata __at(0xE6A3) volatile BYTE EP2CS;  ///< Endpoint 2 Control and Status
 167 __xdata __at(0xE6A4) volatile BYTE EP4CS;  ///< Endpoint 4 Control and Status
 168 __xdata __at(0xE6A5) volatile BYTE EP6CS;  ///< Endpoint 6 Control and Status
 169 __xdata __at(0xE6A6) volatile BYTE EP8CS;  ///< Endpoint 8 Control and Status
 170 __xdata __at(0xE6A7) volatile BYTE EP2FIFOFLGS;  ///< Endpoint 2 Flags
 171 __xdata __at(0xE6A8) volatile BYTE EP4FIFOFLGS;  ///< Endpoint 4 Flags
 172 __xdata __at(0xE6A9) volatile BYTE EP6FIFOFLGS;  ///< Endpoint 6 Flags
 173 __xdata __at(0xE6AA) volatile BYTE EP8FIFOFLGS;  ///< Endpoint 8 Flags
 174 __xdata __at(0xE6AB) volatile BYTE EP2FIFOBCH;  ///< EP2 FIFO total byte count H
 175 __xdata __at(0xE6AC) volatile BYTE EP2FIFOBCL;  ///< EP2 FIFO total byte count L
 176 __xdata __at(0xE6AD) volatile BYTE EP4FIFOBCH;  ///< EP4 FIFO total byte count H
 177 __xdata __at(0xE6AE) volatile BYTE EP4FIFOBCL;  ///< EP4 FIFO total byte count L
 178 __xdata __at(0xE6AF) volatile BYTE EP6FIFOBCH;  ///< EP6 FIFO total byte count H
 179 __xdata __at(0xE6B0) volatile BYTE EP6FIFOBCL;  ///< EP6 FIFO total byte count L
 180 __xdata __at(0xE6B1) volatile BYTE EP8FIFOBCH;  ///< EP8 FIFO total byte count H
 181 __xdata __at(0xE6B2) volatile BYTE EP8FIFOBCL;  ///< EP8 FIFO total byte count L
 182 __xdata __at(0xE6B3) volatile BYTE SUDPTRH;  ///< Setup Data Pointer high address byte
 183 __xdata __at(0xE6B4) volatile BYTE SUDPTRL;  ///< Setup Data Pointer low address byte
 184 __xdata __at(0xE6B5) volatile BYTE SUDPTRCTL;  ///< Setup Data Pointer Auto Mode
 185 __xdata __at(0xE6B8) volatile BYTE SETUPDAT[8];  ///< 8 bytes of SETUP data
 186
 187 // GPIF
 188
 189 __xdata __at(0xE6C0) volatile BYTE GPIFWFSELECT;  ///< Waveform Selector
 190 __xdata __at(0xE6C1) volatile BYTE GPIFIDLECS;  ///< GPIF Done, GPIF IDLE drive mode
 191 __xdata __at(0xE6C2) volatile BYTE GPIFIDLECTL;  ///< Inactive Bus, CTL states
 192 __xdata __at(0xE6C3) volatile BYTE GPIFCTLCFG;  ///< CTL OUT pin drive
 193 __xdata __at(0xE6C4) volatile BYTE GPIFADRH;  ///< GPIF Address H
 194 __xdata __at(0xE6C5) volatile BYTE GPIFADRL;  ///< GPIF Address L
 195
 196 __xdata __at(0xE6CE) volatile BYTE GPIFTCB3;  ///< GPIF Transaction Count Byte 3
 197 __xdata __at(0xE6CF) volatile BYTE GPIFTCB2;  ///< GPIF Transaction Count Byte 2
 198 __xdata __at(0xE6D0) volatile BYTE GPIFTCB1;  ///< GPIF Transaction Count Byte 1
 199 __xdata __at(0xE6D1) volatile BYTE GPIFTCB0;  ///< GPIF Transaction Count Byte 0
 200
 201 __xdata __at(0xE6D2) volatile BYTE EP2GPIFFLGSEL;  ///< EP2 GPIF Flag select
 202 __xdata __at(0xE6D3) volatile BYTE EP2GPIFPFSTOP;  ///< Stop GPIF EP2 transaction on prog. flag
 203 __xdata __at(0xE6D4) volatile BYTE EP2GPIFTRIG;  ///< EP2 FIFO Trigger
 204 __xdata __at(0xE6DA) volatile BYTE EP4GPIFFLGSEL;  ///< EP4 GPIF Flag select
 205 __xdata __at(0xE6DB) volatile BYTE EP4GPIFPFSTOP;  ///< Stop GPIF EP4 transaction on prog. flag
 206 __xdata __at(0xE6DC) volatile BYTE EP4GPIFTRIG;  ///< EP4 FIFO Trigger
 207 __xdata __at(0xE6E2) volatile BYTE EP6GPIFFLGSEL;  ///< EP6 GPIF Flag select
 208 __xdata __at(0xE6E3) volatile BYTE EP6GPIFPFSTOP;  ///< Stop GPIF EP6 transaction on prog. flag
 209 __xdata __at(0xE6E4) volatile BYTE EP6GPIFTRIG;  ///< EP6 FIFO Trigger
 210 __xdata __at(0xE6EA) volatile BYTE EP8GPIFFLGSEL;  ///< EP8 GPIF Flag select
 211 __xdata __at(0xE6EB) volatile BYTE EP8GPIFPFSTOP;  ///< Stop GPIF EP8 transaction on prog. flag
 212 __xdata __at(0xE6EC) volatile BYTE EP8GPIFTRIG;  ///< EP8 FIFO Trigger
 213 __xdata __at(0xE6F0) volatile BYTE XGPIFSGLDATH;  ///< GPIF Data H (16-bit mode only)
 214 __xdata __at(0xE6F1) volatile BYTE XGPIFSGLDATLX;  ///< Read/Write GPIF Data L & trigger transac
 215 __xdata __at(0xE6F2) volatile BYTE XGPIFSGLDATLNOX;  ///< Read GPIF Data L, no transac trigger
 216 __xdata __at(0xE6F3) volatile BYTE GPIFREADYCFG;  ///< Internal RDY,Sync/Async, RDY5CFG
 217 __xdata __at(0xE6F4) volatile BYTE GPIFREADYSTAT;  ///< RDY pin states
 218 __xdata __at(0xE6F5) volatile BYTE GPIFABORT;  ///< Abort GPIF cycles
 219
 220 // UDMA
 221
 222 __xdata __at(0xE6C6) volatile BYTE FLOWSTATE; ///<Defines GPIF flow state
 223 __xdata __at(0xE6C7) volatile BYTE FLOWLOGIC; ///<Defines flow/hold decision criteria
 224 __xdata __at(0xE6C8) volatile BYTE FLOWEQ0CTL; ///<CTL states during active flow state
 225 __xdata __at(0xE6C9) volatile BYTE FLOWEQ1CTL; ///<CTL states during hold flow state
 226 __xdata __at(0xE6CA) volatile BYTE FLOWHOLDOFF;
 227 __xdata __at(0xE6CB) volatile BYTE FLOWSTB; ///<CTL/RDY Signal to use as master data strobe
 228 __xdata __at(0xE6CC) volatile BYTE FLOWSTBEDGE; ///<Defines active master strobe edge
 229 __xdata __at(0xE6CD) volatile BYTE FLOWSTBHPERIOD; ///<Half Period of output master strobe
 230 __xdata __at(0xE60C) volatile BYTE GPIFHOLDAMOUNT; ///<Data delay shift
 231 __xdata __at(0xE67D) volatile BYTE UDMACRCH; ///<CRC Upper byte
 232 __xdata __at(0xE67E) volatile BYTE UDMACRCL; ///<CRC Lower byte
 233 __xdata __at(0xE67F) volatile BYTE UDMACRCQUAL; ///<UDMA In only, host terminated use only
 234
 235 // Endpoint Buffers
 236
 237 __xdata __at(0xE740) volatile BYTE EP0BUF[64];  ///< EP0 IN-OUT buffer
 238 __xdata __at(0xE780) volatile BYTE EP1OUTBUF[64];  ///< EP1-OUT buffer
 239 __xdata __at(0xE7C0) volatile BYTE EP1INBUF[64];  ///< EP1-IN buffer
 240 __xdata __at(0xF000) volatile BYTE EP2FIFOBUF[1024];  ///< 512/1024-byte EP2 buffer (IN or OUT)
 241 __xdata __at(0xF400) volatile BYTE EP4FIFOBUF[1024];  ///< 512 byte EP4 buffer (IN or OUT)
 242 __xdata __at(0xF800) volatile BYTE EP6FIFOBUF[1024];  ///< 512/1024-byte EP6 buffer (IN or OUT)
 243 __xdata __at(0xFC00) volatile BYTE EP8FIFOBUF[1024];  ///< 512 byte EP8 buffer (IN or OUT)
 244
 245 // Error Correction Code (ECC) Registers (FX2LP/FX1 only)
 246
 247 __xdata __at(0xE628) volatile BYTE ECCCFG;  ///< ECC Configuration
 248 __xdata __at(0xE629) volatile BYTE ECCRESET;  ///< ECC Reset
 249 __xdata __at(0xE62A) volatile BYTE ECC1B0;  ///< ECC1 Byte 0
 250 __xdata __at(0xE62B) volatile BYTE ECC1B1;  ///< ECC1 Byte 1
 251 __xdata __at(0xE62C) volatile BYTE ECC1B2;  ///< ECC1 Byte 2
 252 __xdata __at(0xE62D) volatile BYTE ECC2B0;  ///< ECC2 Byte 0
 253 __xdata __at(0xE62E) volatile BYTE ECC2B1;  ///< ECC2 Byte 1
 254 __xdata __at(0xE62F) volatile BYTE ECC2B2;  ///< ECC2 Byte 2
 255
 256 // Feature Registers  (FX2LP/FX1 only)
 257 __xdata __at(0xE50D) volatile BYTE GPCR2;  ///< Chip Features
 258
 259 /**
 260  * SFRs below
 261  *  According to TRM 15.2, only rows 0 and 8 of the SFRs are bit addressible
 262  *  row 0: IOA, IOB, IOC, IOD, SCON1, PSW, ACC, B
 263  *  row 8: TCON, SCON0, IE, IP, T2CON, IECON, EIE, EIP
 264  *
 265  *  All others have to move a byte to the SRF address
 266  **/
 267
 268 __sfr __at(0x80) IOA;
 269          /*  IOA  */
 270          __sbit __at(0x80 + 0) PA0;
 271          __sbit __at(0x80 + 1) PA1;
 272          __sbit __at(0x80 + 2) PA2;
 273          __sbit __at(0x80 + 3) PA3;
 274          __sbit __at(0x80 + 4) PA4;
 275          __sbit __at(0x80 + 5) PA5;
 276          __sbit __at(0x80 + 6) PA6;
 277          __sbit __at(0x80 + 7) PA7;
 278 __sfr __at(0x81) SP;
 279 __sfr __at(0x82) DPL;
 280 __sfr __at(0x83) DPH;
 281 __sfr __at(0x84) DPL1;
 282 __sfr __at(0x85) DPH1;
 283 __sfr __at(0x86) DPS;
 284 __sfr __at(0x87) PCON;
 285 __sfr __at(0x88) TCON;
 286          /*  TCON  */
 287          __sbit __at(0x88+0) IT0;
 288          __sbit __at(0x88+1) IE0;
 289          __sbit __at(0x88+2) IT1;
 290          __sbit __at(0x88+3) IE1;
 291          __sbit __at(0x88+4) TR0;
 292          __sbit __at(0x88+5) TF0;
 293          __sbit __at(0x88+6) TR1;
 294          __sbit __at(0x88+7) TF1;
 295 __sfr __at(0x89) TMOD;
 296 __sfr __at(0x8A) TL0;
 297 __sfr __at(0x8B) TL1;
 298 __sfr __at(0x8C) TH0;
 299 __sfr __at(0x8D) TH1;
 300 __sfr __at(0x8E) CKCON;
 301 __sfr __at(0x90) IOB;
 302          /*  IOB  */
 303          __sbit __at(0x90 + 0) PB0;
 304          __sbit __at(0x90 + 1) PB1;
 305          __sbit __at(0x90 + 2) PB2;
 306          __sbit __at(0x90 + 3) PB3;
 307          __sbit __at(0x90 + 4) PB4;
 308          __sbit __at(0x90 + 5) PB5;
 309          __sbit __at(0x90 + 6) PB6;
 310          __sbit __at(0x90 + 7) PB7;
 311 __sfr __at(0x91) EXIF;
 312
 313 //__sfr __at(0x92) MPAGE;
 314 __sfr __at(0x92) _XPAGE; // same as MPAGE for pdata __sfr access w/ sdcc
 315 __sfr __at(0x98) SCON0;
 316          /*  SCON0  */
 317          __sbit __at(0x98+0) RI;
 318          __sbit __at(0x98+1) TI;
 319          __sbit __at(0x98+2) RB8;
 320          __sbit __at(0x98+3) TB8;
 321          __sbit __at(0x98+4) REN;
 322          __sbit __at(0x98+5) SM2;
 323          __sbit __at(0x98+6) SM1;
 324          __sbit __at(0x98+7) SM0;
 325 __sfr __at(0x99) SBUF0;
 326
 327 __sfr __at(0x9A) AUTOPTRH1;
 328 __sfr __at(0x9B) AUTOPTRL1;
 329 __sfr __at(0x9D) AUTOPTRH2;
 330 __sfr __at(0x9E) AUTOPTRL2;
 331
 332 __sfr __at(0xA0) IOC;
 333          /*  IOC  */
 334          __sbit __at(0xA0 + 0) PC0;
 335          __sbit __at(0xA0 + 1) PC1;
 336          __sbit __at(0xA0 + 2) PC2;
 337          __sbit __at(0xA0 + 3) PC3;
 338          __sbit __at(0xA0 + 4) PC4;
 339          __sbit __at(0xA0 + 5) PC5;
 340          __sbit __at(0xA0 + 6) PC6;
 341          __sbit __at(0xA0 + 7) PC7;
 342 __sfr __at(0xA1) INT2CLR;
 343 __sfr __at(0xA2) INT4CLR;
 344
 345 __sfr __at(0xA8) IE;
 346          /*  IE  */
 347          __sbit __at(0xA8+0) EX0;
 348          __sbit __at(0xA8+1) ET0;
 349          __sbit __at(0xA8+2) EX1;
 350          __sbit __at(0xA8+3) ET1;
 351          __sbit __at(0xA8+4) ES0;
 352          __sbit __at(0xA8+5) ET2;
 353          __sbit __at(0xA8+6) ES1;
 354          __sbit __at(0xA8+7) EA;
 355
 356 __sfr __at(0xAA) EP2468STAT;
 357 __sfr __at(0xAB) EP24FIFOFLGS;
 358 __sfr __at(0xAC) EP68FIFOFLGS;
 359 __sfr __at(0xAF) AUTOPTRSETUP;
 360 __sfr __at(0xB0) IOD;
 361          /*  IOD  */
 362          __sbit __at(0xB0 + 0) PD0;
 363          __sbit __at(0xB0 + 1) PD1;
 364          __sbit __at(0xB0 + 2) PD2;
 365          __sbit __at(0xB0 + 3) PD3;
 366          __sbit __at(0xB0 + 4) PD4;
 367          __sbit __at(0xB0 + 5) PD5;
 368          __sbit __at(0xB0 + 6) PD6;
 369          __sbit __at(0xB0 + 7) PD7;
 370 __sfr __at(0xB1) IOE;
 371 __sfr __at(0xB2) OEA;
 372 __sfr __at(0xB3) OEB;
 373 __sfr __at(0xB4) OEC;
 374 __sfr __at(0xB5) OED;
 375 __sfr __at(0xB6) OEE;
 376
 377 __sfr __at(0xB8) IP;
 378          /*  IP  */
 379          __sbit __at(0xB8+0) PX0;
 380          __sbit __at(0xB8+1) PT0;
 381          __sbit __at(0xB8+2) PX1;
 382          __sbit __at(0xB8+3) PT1;
 383          __sbit __at(0xB8+4) PS0;
 384          __sbit __at(0xB8+5) PT2;
 385          __sbit __at(0xB8+6) PS1;
 386
 387 __sfr __at(0xBA) EP01STAT;
 388 __sfr __at(0xBB) GPIFTRIG;
 389
 390 __sfr __at(0xBD) GPIFSGLDATH;
 391 __sfr __at(0xBE) GPIFSGLDATLX;
 392 __sfr __at(0xBF) GPIFSGLDATLNOX;
 393
 394 __sfr __at(0xC0) SCON1;
 395          /*  SCON1  */
 396          __sbit __at(0xC0+0) RI1;
 397          __sbit __at(0xC0+1) TI1;
 398          __sbit __at(0xC0+2) RB81;
 399          __sbit __at(0xC0+3) TB81;
 400          __sbit __at(0xC0+4) REN1;
 401          __sbit __at(0xC0+5) SM21;
 402          __sbit __at(0xC0+6) SM11;
 403          __sbit __at(0xC0+7) SM01;
 404 __sfr __at(0xC1) SBUF1;
 405 __sfr __at(0xC8) T2CON;
 406          /*  T2CON  */
 407          __sbit __at(0xC8+0) CP_RL2;
 408          __sbit __at(0xC8+1) C_T2;
 409          __sbit __at(0xC8+2) TR2;
 410          __sbit __at(0xC8+3) EXEN2;
 411          __sbit __at(0xC8+4) TCLK;
 412          __sbit __at(0xC8+5) RCLK;
 413          __sbit __at(0xC8+6) EXF2;
 414          __sbit __at(0xC8+7) TF2;
 415 __sfr __at(0xCA) RCAP2L;
 416 __sfr __at(0xCB) RCAP2H;
 417 __sfr __at(0xCC) TL2;
 418 __sfr __at(0xCD) TH2;
 419 __sfr __at(0xD0) PSW;
 420          /*  PSW  */
 421          __sbit __at(0xD0+0) P;
 422          __sbit __at(0xD0+1) FL;
 423          __sbit __at(0xD0+2) OV;
 424          __sbit __at(0xD0+3) RS0;
 425          __sbit __at(0xD0+4) RS1;
 426          __sbit __at(0xD0+5) F0;
 427          __sbit __at(0xD0+6) AC;
 428          __sbit __at(0xD0+7) CY;
 429 __sfr __at(0xD8) EICON; // Was WDCON in DS80C320; Bit Values differ from Reg320
 430          /*  EICON  */
 431          __sbit __at(0xD8+3) INT6;
 432          __sbit __at(0xD8+4) RESI;
 433          __sbit __at(0xD8+5) ERESI;
 434          __sbit __at(0xD8+7) SMOD1;
 435 __sfr __at(0xE0) ACC;
 436 __sfr __at(0xE8) EIE; // EIE Bit Values differ from Reg320
 437          /*  EIE  */
 438          __sbit __at(0xE8+0) EUSB;
 439          __sbit __at(0xE8+1) EI2C;
 440          __sbit __at(0xE8+2) EIEX4;
 441          __sbit __at(0xE8+3) EIEX5;
 442          __sbit __at(0xE8+4) EIEX6;
 443 __sfr __at(0xF0) B;
 444 __sfr __at(0xF8) EIP; // EIP Bit Values differ from Reg320
 445          /*  EIP  */
 446          __sbit __at(0xF8+0) PUSB;
 447          __sbit __at(0xF8+1) PI2C;
 448          __sbit __at(0xF8+2) EIPX4;
 449          __sbit __at(0xF8+3) EIPX5;
 450          __sbit __at(0xF8+4) EIPX6;
 451
 452
 453 /* CPU Control & Status Register (CPUCS) */
 454 #define bmPRTCSTB    bmBIT5
 455 #define bmCLKSPD     (bmBIT4 | bmBIT3)
 456 #define bmCLKSPD1    bmBIT4
 457 #define bmCLKSPD0    bmBIT3
 458 #define bmCLKINV     bmBIT2
 459 #define bmCLKOE      bmBIT1
 460 #define bm8051RES    bmBIT0
 461 /* Port Alternate Configuration Registers */
 462 /* Port A (PORTACFG) */
 463 #define bmFLAGD      bmBIT7
 464 #define bmSLCS       bmBIT6
 465 #define bmINT1       bmBIT1
 466 #define bmINT0       bmBIT0
 467 /* Port C (PORTCCFG) */
 468 #define bmGPIFA7     bmBIT7
 469 #define bmGPIFA6     bmBIT6
 470 #define bmGPIFA5     bmBIT5
 471 #define bmGPIFA4     bmBIT4
 472 #define bmGPIFA3     bmBIT3
 473 #define bmGPIFA2     bmBIT2
 474 #define bmGPIFA1     bmBIT1
 475 #define bmGPIFA0     bmBIT0
 476 /* Port E (PORTECFG) */
 477 #define bmGPIFA8     bmBIT7
 478 #define bmT2EX       bmBIT6
 479 #define bmINT6       bmBIT5
 480 #define bmRXD1OUT    bmBIT4
 481 #define bmRXD0OUT    bmBIT3
 482 #define bmT2OUT      bmBIT2
 483 #define bmT1OUT      bmBIT1
 484 #define bmT0OUT      bmBIT0
 485
 486 /* I2C Control & Status Register (I2CS) */
 487 #define bmSTART      bmBIT7
 488 #define bmSTOP       bmBIT6
 489 #define bmLASTRD     bmBIT5
 490 #define bmID         (bmBIT4 | bmBIT3)
 491 #define bmBERR       bmBIT2
 492 #define bmACK        bmBIT1
 493 #define bmDONE       bmBIT0
 494 /* I2C Control Register (I2CTL) */
 495 #define bmSTOPIE     bmBIT1
 496 #define bm400KHZ     bmBIT0
 497 /* Interrupt 2 (USB) Autovector Register (INT2IVEC) */
 498 #define bmIV4        bmBIT6
 499 #define bmIV3        bmBIT5
 500 #define bmIV2        bmBIT4
 501 #define bmIV1        bmBIT3
 502 #define bmIV0        bmBIT2
 503 /* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */
 504 #define bmEP0ACK     bmBIT6
 505 #define bmHSGRANT    bmBIT5
 506 #define bmURES       bmBIT4
 507 #define bmSUSP       bmBIT3
 508 #define bmSUTOK      bmBIT2
 509 #define bmSOF        bmBIT1
 510 #define bmSUDAV      bmBIT0
 511 /* USBERRIE/IRQ */
 512 #define bmERRLIMIT  bmBIT0
 513 #define bmISOEP2    bmBIT4
 514 #define bmISOEP4    bmBIT5
 515 #define bmISOEP6    bmBIT6
 516 #define bmISOEP8    bmBIT7
 517
 518 /* Endpoint Interrupt & Enable Registers (EPIE/EPIRQ) */
 519 #define bmEP0IN     bmBIT0
 520 #define bmEP0OUT    bmBIT1
 521 #define bmEP1IN     bmBIT2
 522 #define bmEP1OUT    bmBIT3
 523 #define bmEP2       bmBIT4
 524 #define bmEP4       bmBIT5
 525 #define bmEP6       bmBIT6
 526 #define bmEP8       bmBIT7
 527 /* Breakpoint register (BREAKPT) */
 528 #define bmBREAK      bmBIT3
 529 #define bmBPPULSE    bmBIT2
 530 #define bmBPEN       bmBIT1
 531 /* Interrupt 2 & 4 Setup (INTSETUP) */
 532 #define bmAV2EN      bmBIT3
 533 #define INT4IN       bmBIT1
 534 #define bmAV4EN      bmBIT0
 535 /* USB Control & Status Register (USBCS) */
 536 #define bmHSM        bmBIT7
 537 #define bmDISCON     bmBIT3
 538 #define bmNOSYNSOF   bmBIT2
 539 #define bmRENUM      bmBIT1
 540 #define bmSIGRESUME  bmBIT0
 541 /* Wakeup Control and Status Register (WAKEUPCS) */
 542 #define bmWU2        bmBIT7
 543 #define bmWU         bmBIT6
 544 #define bmWU2POL     bmBIT5
 545 #define bmWUPOL      bmBIT4
 546 #define bmDPEN       bmBIT2
 547 #define bmWU2EN      bmBIT1
 548 #define bmWUEN       bmBIT0
 549 /* End Point 0 Control & Status Register (EP0CS) */
 550 #define bmHSNAK      bmBIT7
 551 /* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */
 552 #define bmEPBUSY     bmBIT1
 553 #define bmEPSTALL    bmBIT0
 554 /* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */
 555 #define bmNPAK       (bmBIT6 | bmBIT5 | bmBIT4)
 556 #define bmEPFULL     bmBIT3
 557 #define bmEPEMPTY    bmBIT2
 558 /* Endpoint Status (EP2468STAT) SFR bits */
 559 #define bmEP8FULL    bmBIT7
 560 #define bmEP8EMPTY   bmBIT6
 561 #define bmEP6FULL    bmBIT5
 562 #define bmEP6EMPTY   bmBIT4
 563 #define bmEP4FULL    bmBIT3
 564 #define bmEP4EMPTY   bmBIT2
 565 #define bmEP2FULL    bmBIT1
 566 #define bmEP2EMPTY   bmBIT0
 567 /* Endpoint Config (EP[2468]CFG) */
 568 #define bmVALID     bmBIT7
 569 #define bmDIR       bmBIT6
 570 #define bmTYPE      (bmBIT4|bmBIT5)
 571 #define bmTYPE1     bmBIT5
 572 #define bmTYPE0     bmBIT4
 573 #define bmSIZE      bmBIT3
 574 /* Endpoint Config (EP[24]CFG) */
 575 #define bmBUF       (bmBIT0|bmBIT1)
 576 #define bmBUF1      bmBIT1
 577 #define bmBUF0      bmBIT0
 578 /* SETUP Data Pointer Auto Mode (SUDPTRCTL) */
 579 #define bmSDPAUTO    bmBIT0
 580 /* Endpoint Data Toggle Control (TOGCTL) */
 581 #define bmQUERYTOGGLE  bmBIT7
 582 #define bmSETTOGGLE    bmBIT6
 583 #define bmRESETTOGGLE  bmBIT5
 584 #define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
 585 /* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */
 586 #define bmEP8IBN     bmBIT5
 587 #define bmEP6IBN     bmBIT4
 588 #define bmEP4IBN     bmBIT3
 589 #define bmEP2IBN     bmBIT2
 590 #define bmEP1IBN     bmBIT1
 591 #define bmEP0IBN     bmBIT0
 592
 593 /* PING-NAK enable and request bits (NAKIE/NAKIRQ) */
 594 #define bmEP8PING     bmBIT7
 595 #define bmEP6PING     bmBIT6
 596 #define bmEP4PING     bmBIT5
 597 #define bmEP2PING     bmBIT4
 598 #define bmEP1PING     bmBIT3
 599 #define bmEP0PING     bmBIT2
 600 #define bmIBN         bmBIT0
 601
 602 /* Interface Configuration bits (IFCONFIG) */
 603 #define bmIFCLKSRC    bmBIT7
 604 #define bm3048MHZ     bmBIT6
 605 #define bmIFCLKOE     bmBIT5
 606 #define bmIFCLKPOL    bmBIT4
 607 #define bmASYNC       bmBIT3
 608 #define bmGSTATE      bmBIT2
 609 #define bmIFCFG1      bmBIT1
 610 #define bmIFCFG0      bmBIT0
 611 #define bmIFCFGMASK   (bmIFCFG0 | bmIFCFG1)
 612 #define bmIFGPIF      bmIFCFG1
 613
 614 /* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */
 615 #define bmINFM       bmBIT6
 616 #define bmOEP        bmBIT5
 617 #define bmAUTOOUT    bmBIT4
 618 #define bmAUTOIN     bmBIT3
 619 #define bmZEROLENIN  bmBIT2
 620 #define bmWORDWIDE   bmBIT0
 621
 622 /* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specidic
 623    features */
 624 #define bmNOAUTOARM    bmBIT1
 625 #define bmSKIPCOMMIT   bmBIT0
 626
 627 /* Fifo Reset bits (FIFORESET) */
 628 #define bmNAKALL       bmBIT7
 629
 630 /* Chip Feature Register (GPCR2) */
 631 #define bmFULLSPEEDONLY    bmBIT4
 632
 633 /* EP 01 status (EP01STAT) */
 634 #define bmEP1INBSY      bmBIT2
 635 #define bmEP1OUTBSY     bmBIT1
 636 #define bmEP0BSY        bmBIT0
 637
 638 #endif   /* FX2REGS_H */