[RISC-V][PR target/118146] Fix ICE for unsupported modes

[RISC-V][PR target/118146] Fix ICE for unsupported modes

There's some special case code in the risc-v move expander to try and optimize
cases where the source is a subreg of a vector and the destination is a scalar
mode.

The code works fine except when we have no support for the given mode. ie HF or
BF when those extensions aren't enabled.  We'll end up tripping an assert in
that case when we should have just let standard expansion do its thing.

Tested in my system for rv32 and rv64, but I'll wait for the pre-commit tester
to render a verdict before moving forward.

	PR target/118146
gcc/
	* config/riscv/riscv.cc (riscv_legitimize_move): Handle subreg
	of vector source better to avoid ICE.

gcc/testsuite
	* gcc.target/riscv/pr118146-1.c: New test.
	* gcc.target/riscv/pr118146-2.c: New test.