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15 <h1 class="sectionedit809"><a name="vvp_simulation_engine" id="vvp_simulation_engine">VVP Simulation Engine</a></h1>
18 * Copyright (c) 2001 Stephen Williams (steve@icarus.com)
19 *
21 */
23 VVP SIMULATION ENGINE
25 The VVP simulator takes as input source code not unlike assembly
26 language for a conventional processor. It is intended to be machine
27 generated code emitted by other tools, including the Icarus Verilog
28 compiler, so the syntax, though readable, is not necessarily
29 convenient for humans.
32 GENERAL FORMAT
34 The source file is a collection of statements. Each statement may have
35 a label, an opcode, and operands that depend on the opcode. For some
36 opcodes, the label is optional (or meaningless) and for others it is
37 required.
39 Every statement is terminated by a semicolon. The semicolon is also
40 the start of a comment line, so you can put comment text after the
41 semicolon that terminates a statement. Like so:
43 Label .functor and, 0x5a, x, y ; This is a comment.
45 The semicolon is required, whether the comment is there or not.
47 Statements may span multiple lines, as long as there is no text (other
48 then the first character of a label) in the first column of the
49 continuation line.
51 HEADER SYNTAX
53 Before any other non-commentary code starts, the source may contain
54 some header statements. These are used for passing parameters or
55 global details from the compiler to the vvp run-time. In all cases,
56 the header statement starts with a left-justified keyword.
60 This header statement names a vpi module that vvp should load before
61 the rest of the program is compiled. The compiler looks in the
63 dynamic load them.
67 This header statement specifies the time precision of a single tick of
68 the simulation clock. This is mostly used for display (and VPI)
69 purposes, because the engine itself does not care about units. The
70 compiler scales time values ahead of time.
72 The value is the size of a simulation tick in seconds, and is
74 nanosecond. If the record is left out, then the precision is taken to
75 be +0.
77 LABELS AND SYMBOLS
79 Labels and symbols consist of the characters:
81 a-z
82 A-Z
84 .$_<>
87 are easily distinguished from keywords and numbers. A Label is a
88 symbol that starts a statement. If a label is present in a statement,
89 it must start in the first text column. This is how the lexical
90 analyzer distinguishes a label from a symbol. If a symbol is present
91 in a statement, it is in the operand. Opcodes of statements must be a
92 keyword.
94 Symbols are references to labels. It is not necessary for a label to
95 be declared before its use in a symbol, but it must be declared
96 eventually. When symbols refer to functors, the symbol represents the
97 vvp_ipoint_t pointer to the output. (Inputs cannot, and need not, be
98 references symbolically.)
100 If the functor is part of a vector, then the symbol is the
101 vvp_ipoint_t for the first functor. The [] operator can then be used
102 to reference a functor other then the first in the vector.
104 There are some special symbols that in certain contexts have special
105 meanings. As inputs to functors, the symbols "C<0>", "C<1>", "C<x>"
109 SCOPE STATEMENTS:
112 PARAMETER STATEMENTS:
114 Parameters are named constants within a scope. These parameters have a
115 type and value, and also a label so that they can be referenced as VPI
116 objects.
118 The syntax of a parameter is:
124 following:
126 real -- The parameter has a real value
127 string -- The parameter has a string value
129 -- The parameter is a vector, with specified
131 unsigned.
133 The value, then, is appropriate for the data type. For example:
138 FUNCTOR STATEMENTS:
140 A functor statement is a statement that uses the ``.functor''
141 opcode. Functors are the basic structural units of a simulation, and
142 include a type (in the form of a truth table) and up to four inputs. A
143 label is required for functors.
145 The general syntax of a functor is:
149 The symbol list is 4 names of labels of other functors. These connect
150 inputs of the functor of the statement to the output of other
152 type selects the truth lookup table to use for the functor
153 implementation. Most of the core gate types have built in tables.
155 The initial values of all the inputs and the output is x. Any other
157 symbols, then the inputs are initialized to the specified bit value,
158 and if this causes the output to be something other then x, a
159 propagation event is created to be executed at the start of run time.
161 The strengths of inputs are ignored by functors, and the output has
162 fixed drive0 and drive1 strengths. So strength information is
163 typically lost as it passes through functors.
165 Almost all of the structural aspects of a simulation can be
166 represented by functors, which perform the very basic task of
167 combining up to four inputs down to one output.
169 - MUXZ
171 Q | A B S n/a
172 --+-------------
173 A | * * 0
174 B | * * 1
177 DFF STATEMENTS:
179 The Verilog language itself does not have a DFF primitive, but post
180 synthesis readily creates DFF devices that are best simulated with a
181 common device. Thus, there is the DFF statement to create DFF devices:
188 type of datum at all. The device will transfer the input to the output
190 asynchronous input that is immediately stored and transferred to the
191 output when data arrives here. This is useful for implementing
192 asynchronous set/clear functions.
194 UDP STATEMENTS:
196 A UDP statement either defines a User Defined Primitive, or
197 instantiates a previously defined UDP by creating a UDP functor. A
198 UDP functor has as many inputs as the UDP definition requires.
200 UDPs come in sequential and combinatorial flavors. Sequential UDPs
201 carry an output state and can respond to edges at the inputs. The
202 output of combinatorial UDPs is a function of its current inputs
203 only.
205 The function of a UDP is defined via a table. The rows of the table
206 are strings which describe input states or edges, and the new output
207 state. Combinatorial UDPs require one character for each input, and
208 one character at the end for the output state. Sequential UDPs need
209 an additional char for the current state, which is the first char of
210 the row.
212 Any input transition or the new state must match at most one row (or
213 all matches must provide the same output state). If no row matches,
219 An input or current output state can be
229 For Sequential UDPs, at most one input state specification may be
230 replaced by an edge specification. Valid edges are:
240 A combinatorial UDP is defined like this:
242 <type> .udp/comb "<name>", <number>, "<row0>", "<row1>", ... ;
246 need an additional initialization value:
248 <type> .udp/sequ "<name>", <number>, <init>, "<row0>", "<row1>", ... ;
254 A UDP functor instance is created so:
260 input of the UDP.
263 VARIABLE STATEMENTS:
265 A variable is a bit vector that can be written by behavioral code (so
266 has no structural input) and propagates its output to a functor. The
267 general syntax of a variable is:
274 sake of VPI code that might access it. The variable is placed in the
275 current scope. The variable also has a width, defined by the indices
276 for the most significant and lest significant bits. If the indices are
277 equal (normally 0) the vector has width of one. If the width is greater
278 then one, a contiguous array of functors is created and the value of
279 the label is the address of the least significant bit.
281 A variable does not take inputs, since its value is set behaviorally
282 by assignment events. It does have output, though, and its output is
283 propagated into the net of functors in the usual way.
285 A variable gets its value by assignments from procedural code: %set
286 and %assign. These instructions write values to the port-0 input. From
287 there, the value is held.
289 Behavioral code can also invoke %cassign/v statements that work like
290 %set/v, but instead write to port-1 of the variable node. Writes to
291 port-1 of a variable activate continuous assign mode, where the values
292 written to port-0 are ignored. The continuous assign mode remains
295 Behavioral code may also invoke %force/v statements that write to port-2
296 to invoke force mode. This overrides continuous assign mode until a
299 NET STATEMENTS:
301 A net is similar to a variable, except that a thread cannot write to
302 it (unless it uses a force) and it is given a different VPI type
303 code. The syntax of a .net statement is also similar to but not
304 exactly the same as the .var statement:
314 Like a .var statement, the .net statement creates a VPI object with
315 the basename and dimensions given as parameters. The symbol is a
316 functor that feeds into the vector of the net, and the vpiHandle
317 holds references to that functor.
319 The input of a .net is replicated to its output. In this sense, it
320 acts like a diode. The purpose of this node is to hold various VPI
321 and event trappings. The .net and .net8 nodes are vector types. They
322 both may represent wires, but the .net8 nodes preserve strength values
323 that arrive through them, while .net nodes reduce strength values to
324 4-value logic. The .net8 nodes should only be used when strength
325 information really is possible.
328 represents. This label does not map to a functor, so only references
329 that know they want to access .nets are able to locate the symbol. In
330 particular, this includes behavioral %load and %wait instructions. The
331 references to net and reg objects are done through the .net label
332 instead of a general functor symbol. The instruction stores the
333 functor pointer, though.
335 The .alias statements do not create new nodes, but instead create net
336 names that are aliases of an existing node. This handles special cases
337 where a net has different names, possibly in different scopes.
339 MEMORY STATEMENTS:
341 Memories are arrays of words, each word a vvp_vector4_t vector of the
342 same width. The memory is canonically addressed as a 1-dimensional
343 array of words, although indices are stored with the memory for
344 calculating a canonical address from a multi-dimensional address.
347 connecting a read port to an existing memory, and (3) initializing the
348 memory's contents.
354 allowed for multidimensional indexing. This statement creates the
355 memory array and makes it available to procedural code.
357 Procedural access to the memory references the memory as single array
358 of words, with the base address==0, and the last address the size (in
359 words) of the memory -1. It is up to the compiler to convert Verilog
360 index sets to a canonical address. The multi-dimensional index set is
361 available for VPI use.
363 Structural read access is implemented in terms of address and data
364 ports. The addresses applied to the address port are expected to be
365 in canonical form.
367 A read port is a functor that takes a single input, the read address,
368 and outputs the word value at the given (canonical) address.
375 Any address input change, or any change in the addressed memory
376 contents, is immediately propagated to the port output.
378 A write port is a superset of a read port. It is a 4-input functor
379 that accepts the word address, an event input, a write enable input,
380 and the data input.
382 <label> .mem/port <memid>, <address>, <event>, <we>, <data> ;
386 port. For asynchronous transparent write operation, connect
390 There is no Verilog construct that calls for a structural write port
391 to a memory, but synthesis may ask for lpm_ram_d[pq] objects.
393 To initialize a memory, use:
398 address (canonical) of the first word to be initialized. The start
399 address allows multiple statements be used to initialize words of a
400 memory.
402 The values are one per word.
404 Procedural access to the memory employs an index register to address a
405 bit location in the memory, via the commands:
411 The memory bit is addressed by index register 3. The value of
413 word occupies a multiple of four bits.
416 EVENT STATEMENTS
418 Threads need to interact with the functors of a netlist synchronously,
419 as well as asynchronously. There are cases where the web of functors
420 needs to wake up a waiting thread. The web of functors signals threads
421 through .event objects, that are declared like so:
427 This event statement declares an object that a %wait instruction
428 can take as an operand. When a thread executes a %wait, it puts
429 itself in the notification list of the event and suspends. The
434 string, then this is a named event which receives events by the %set
435 instruction instead of from the output of a functor.
437 If the event has inputs (a requirement unless it is a named event)
438 then it has up to 4 symbols that address functors. The event then
439 detects the appropriate edge on any of the inputs and signals when the
440 event is true. Normally (in Verilog) a posedge or negedge event only
441 watches a single bit, so the generated code would only include a
442 single symbol for the addressed bit. However, if there are several
443 events of the same edge in an event OR expression, the compiler may
444 combine up to 4 into a single event.
446 If many more events need to be combined together (for example due to
447 an event or expression in the Verilog) then this form can be used:
451 In this case, the symbols list all the events that are to be combined
452 to trigger this event. Only one of the input events needs to trigger
453 to make this one go.
456 RESOLVER STATEMENTS:
458 Resolver statements are strength-aware functors with 4 inputs, but
459 their job typically is to calculate a resolved output using strength
460 resolution. The type of the functor is used to select a specific
461 resolution function.
467 The output from the resolver is vvp_vector8_t value. That is, the
468 result is a vector with strength included.
471 PART SELECT STATEMENTS:
473 Part select statements are functors with three inputs. They take in at
474 port-0 a vector, and output a selected (likely smaller) part of that
475 vector. The other inputs specify what those parts are, as a canonical
476 bit number, and a width. Normally, those bits are constant values.
482 The input is typically a .reg or .net, but can be any vector node in
483 the netlist.
485 The .part/pv variation is the inverse of the .part version, in that
486 the output is actually written to a *part* of the output. The node
487 uses special part-select-write functions to propagate a part of a
489 that part is written to. Destination nodes use this value to check
490 further output widths.
492 The .part/v variation takes a vector (or long) input on port-1 as the
493 base of the part select. Thus, the part select can move around.
495 PART CONCATENATION STATEMENTS:
497 The opposite of the part select statement is the part concatenation
498 statement. The .concat statement is a functor node that takes at input
499 vector values and produces a single vector output that is the
500 concatenation of all the inputs.
505 expected widths of all the inputs. These widths are needed to figure
506 the positions of the input vectors in the generated output, and are
507 listed in order LSB to MSB. The inputs themselves are also listed LSB
508 to MSB, with the LSB vector input coming through port-0 of the real
509 functor.
511 The initial output value is (W+X+Y+Z) bits of 'bx. As input values are
512 propagated, the bits are placed in the correct place in the output
513 vector value, and a new output value is propagated.
516 REPEAT VECTOR STATEMENTS:
518 The repeat vector statement is similar to the concatenation statement,
519 expect that the input is repeated a constant number of times. The
520 format of the repeat vector statement is:
526 vector value is repeated to make the output width. The input width is
529 REDUCTION LOGIC
531 The reduction logic statements take in a single vector, and propagate
532 a single bit.
541 the device has a single input, which is a vector of any width. The
542 device performs the logic on all the bits of the vector (a la Verilog)
543 and produces and propagates a single bit width vector.
545 EXPANSION LOGIC
547 Sign extension nodes are the opposite of reduction logic, in that they
548 take a narrow vector, or single bit, and pad it out to a wider
549 vector.
553 The .expand/s node takes an input symbol and sign-extends it to the
554 given width.
556 FORCE STATEMENTS (old method - remove me):
558 A force statement creates functors that represent a Verilog force
559 statement.
566 There will be as many force functors as there are symbols in the
569 To activate and deactivate a force on a single bit, use:
576 being forced.
578 FORCE STATEMENTS (new method - implement me):
580 A %force instruction, as described in the .var section, forces a
581 constant value onto a .var or .net, and the matching %release releases
582 that value. However, there are times when the value of a functor
583 (i.e. another .net) needs to be forced onto a .var or .net. For this
584 task, the %force/link instruction exists:
591 will automatically drive values to the force port of the destination
592 node. The matching %release/link instruction removes the link (a
593 %release is still needed) to the destination. The %release/link
594 releases the last %force/link, no matter where the link is from. A new
595 %force/link will remove a previous link.
597 The instructions:
602 are the same concept, but for the continuous assign port.
604 STRUCTURAL ARITHMETIC STATEMENTS:
606 The various Verilog arithmetic operators (+-*/%) are available to
607 structural contexts as two-input functors that take in vectors. All of
608 these operators take two inputs and generate a fixed width output. The
609 input vectors will be padded if needed to get the desired output width.
617 In all cases, there are no width limits, so long as the width is
618 fixed.
620 NOTE: The .arith/mult inputs are not necessarily the width of the
621 output. I have not decided how to handle this.
623 These devices support .s and .r suffixes. The .s means the node is a
624 signed vector device, the .r a real valued device.
626 STRUCTURAL COMPARE STATEMENTS:
628 The arithmetic statements handle various arithmetic operators that
629 have wide outputs, but the comparators have single bit output, so they
630 are implemented a bit differently. The syntax, however, is very
631 similar:
642 Whereas the arithmetic statements generate an output the width of
645 comparisons. (Equality doesn't need to care about sign.)
648 STRUCTURAL SHIFTER STATEMENTS:
650 Variable shifts in structural context are implemented with .shift
651 statements:
656 The shifter has a width that defines the vector width of the output, a
658 that is the amount to shift. The vectors that come from port 0 are the
659 data to be shifted and must have exactly the width of the output. The
660 input to port 1 is the amount to shift.
663 STRUCTURAL FUNCTION CALLS:
665 The .ufunc statement defines a call to a user defined function.
667 <label> .ufunc <flabel>, <wid>, <isymbols> ( <psymbols> ) <rsymbol> ;
670 function implementation. This is code that the simulator will branch
671 to.
676 function. These are points in the net, and the ufunc device watches
677 these nets for input changes.
681 the function. The ufunc performs an assignment to these variables
682 before calling the function.
685 result will be found when the function code ends. This value is picked
686 up and propagated to the output of the functor.
688 THREAD STATEMENTS:
690 Thread statements create the initial threads for a simulation. These
691 represent the initial and always blocks, and possibly other causes to
692 create threads at startup.
696 This statement creates a thread with a starting address at the
699 addressed instruction.
702 thread. Supported flags are:
704 $push -- Cause the thread to be pushed in the scheduler. This
705 only effects startup (time 0) by arranging for pushed
706 threads to be started before non-pushed threads. This
707 is useful for resolving time-0 races.
709 * Threads in general
711 Thread statements create the initial threads of a design. These
713 Verilog, and possibly some other synthetic threads for various
714 purposes. It is also possible to create transient threads from
715 behavioral code. These are needed to support such constructs as
716 fork/join, named blocks and task activation.
718 A transient thread is created with a %fork instruction. When a
719 transient thread is created this way, the operand to the %fork gives
720 the starting address, and the new thread is said to be a child of the
721 forking thread. The children of a thread are pushed onto a stack of
722 children. A thread can have only one direct child.
724 A transient thread is reaped with a %join instruction. %join waits for
725 the top thread in the stack of children to complete, then
726 continues. It is an error to %join when there are no children.
728 As you can see, the transient thread in VVP is a cross between a
729 conventional thread and a function call. In fact, there is no %call
730 instruction in vvp, the job is accomplished with %fork/%join in the
731 caller and %end in the callee. The %fork, then is simply a
732 generalization of a function call, where the caller does not
733 necessarily wait for the callee.
735 For all the behavior of threads and thread parentage to work
736 correctly, all %fork statements must have a corresponding %join in the
737 parent, and %end in the child. Without this proper matching, the
738 hierarchical relationships can get confused. The behavior of erroneous
739 code is undefined.
741 * Thread Context
743 The context of a thread is all the local data that only that thread
744 can address. The local data is broken into two addresses spaces: bit
745 memory and word memory.
748 addressed in strips of arbitrary length. For example, an 8-bit value
752 manufacture complex values elsewhere.
754 The word memory is a region of tagged words. The value in each word
755 may be native long or real. These words have a distinct address space
756 from the bits.
758 * Threads and scopes
760 The Verilog ``disable'' statement deserves some special mention
761 because of how it interacts with threads. In particular, threads
762 throughout the design can affect (end) other threads in the design
763 using the disable statement.
765 In Verilog, the operand to the disable statement is the name of a
766 scope. The behavior of the disable is to cause all threads executing
767 in the scope to end. Termination of a thread includes all the children
768 of the thread. In vvp, all threads are in a scope, so this is how the
769 disable gains access to the desired thread.
771 It is obvious how initial/always thread join a scope. They become part
772 of the scope simply by being declared after a .scope declaration. (See
773 vvp.txt for .scope declarations.) The .thread statement placed in the
774 assembly source after a .scope statement causes the thread to join the
775 named scope.
777 Transient threads join a scope that is the operand to the %fork
778 instruction. The scope is referenced by name, and the thread created
779 by the fork atomically joins that scope. Once the transient thread
780 joins the scope, it stays there until it ends. Threads never change
781 scopes, not even transient threads.
783 TRUTH TABLES
785 The logic that a functor represents is expressed as a truth table. The
786 functor has four inputs and one output. Each input and output has one
788 represent them. So the input of the functor is 8 bits, and the output
791 small enough that the table should take less space then the code to
792 implement the logic.
794 To implement the truth table, we need to assign 2-bit encodings for
795 the 4-value signals. I choose, pseudo-randomly, the following
796 encoding:
805 so:
806 332211
809 pairs in the 8-bit byte are the output:
813 A complete truth table, then is described as 64 8-bit bytes.
815 The vvp engine includes truth tables for the primitive gate types, so
816 none needs to be given by the programmer. It is sufficient to name the
817 type to get that truth table.
820 EXECUTABLE INSTRUCTIONS
822 Threads run executable code, much like a processor executes machine
823 code. VVP has a variety of opcodes for executable instructions. All of
825 space. Labels attached to executable instructions get assigned the
826 address of the instruction, and can be the target of %jmp instructions
827 and starting points for threads.
829 The opcodes.txt file has a more detailed description of all the
830 various instructions.
833 THE RELATIONSHIP BETWEEN FUNCTORS, THREADS AND EVENTS
835 Given the above summary of the major components of vvp, some
836 description of their relationship is warranted. Functors provide a
837 structural description of the design (so far as it can be described
838 structurally) and these functors run independently of the threads. In
839 particular, when an input to a functor is set, it calculates a new
840 output value; and if that output is different from the existing
841 output, a propagation event is created. Functor output is calculated
842 by truth table lookup, without the aid of threads.
844 Propagation events are one of three kinds of events in vvp. They are
845 scheduled to execute at some time, and they simply point to the functor
846 that is to have its output propagated. When the event expires, the
847 output of the referenced functor is propagated to all the inputs that
848 it is connected to, and those functors in turn create new events if
849 needed.
851 Assignment events (the second of three types of events) are created
853 executed (a %assign in vvp) an assign event is created, which includes
854 the vvp_ipoint_t pointer to the functor input to receive the value,
855 as well as the value. These are distinct from propagation events because:
857 a) There is no functor that has as its output the value to be
858 assigned (this is how values get into the functor net in
859 the first place), and
861 b) This allows for behavioral code to create waveforms of
862 arbitrary length that feed into a variable. Verilog allows
863 this of non-blocking assignments, but not of gate outputs.
865 The last type of event is the thread schedule event. This event simply
866 points to a thread to be executed. Threads are made up of a virtual
867 processor with a program counter and some private storage. Threads
868 can execute %assign instructions to create assignment events, and can
869 execute %set instructions to do blocking assignments. Threads can also
870 use %load to read the output of functors.
872 The core event scheduler takes these three kinds of events and calls
873 the right kind of code to cause things to happen in the design. If the
874 event is a propagate or assignment event, the network of functors is
875 tickled; if the event is a thread schedule, then a thread is run. The
876 implementation of the event queue is not important, but currently is
877 implemented as a ``skip list''. That is, it is a sorted singly linked
878 list with skip pointers that skip over delta-time events.
880 The functor net and the threads are distinct. They communicate through
881 thread instructions %set, %assign, %waitfor and %load. So far as a thread
882 is concerned, the functor net is a blob of structure that it pokes and
883 prods via certain functor access instructions.
886 VVP COMPILATION AND EXECUTION
888 The vvp program operates in a few steps:
890 1) Initialization
891 Data structures are cleared to empty, and tables are
892 readied for compilation.
894 2) Compilation
895 The input file is read and compiled. Symbol tables are
896 build up as needed, objects are allocated and linked
897 together.
899 3) Cleanup
900 Symbol tables and other resources used only for
901 compilation are released to reduce the memory
902 footprint.
904 4) Simulation
905 Event simulation is run.
908 The initialization step is performed by the compile_init() function in
909 compile.cc. This function in turn calls all the *_init() functions in
910 other parts of the source that need initialization for compile. All
913 Compilation is controlled by the parser, it parse.y. As the parser
914 reads and parses input, the compilation proceeds in the rules by
915 calling various compile_* functions. All these functions live in the
916 compile.cc file. Compilation calls other sections of the code as
917 needed.
919 When the parser completes compilation, compile_cleanup() is called to
920 finish the compilation process. Unresolved references are completed,
921 then all the symbol tables and other compile-time-only resources are
922 released. Once compile_cleanup() returns, there is no more use for the
923 parser for the function in compile.cc.
925 After cleanup, the simulation is started. This is done by executing
926 the schedule_simulate() function. This does any final setup and starts
927 the simulation running and the event queue running.
930 HOW TO GET FROM THERE TO HERE
932 The vvp simulation engine is designed to be able to take as input a
933 compiled form of Verilog. That implies that there is a compiler that
934 compiles Verilog into a form that the vvp engine can read.
937 * Boolean logic gates
939 Gates like AND, OR and NAND are implemented simply and obviously by
940 functor statements. Any logic up to 4 inputs can be implemented with a
941 single functor. For example:
943 and gate (out, i1, i2, i3);
945 becomes:
947 gate .functor and, i1, i2, i3;
949 Notice the first parameter of the .functor is the type. The type
950 includes a truth table that describes the output with a given
951 input. If the gate is wider then four inputs, then cascade
952 functors. For example:
954 and gate (out, i1, i2, i3, i4, i5, i6, i7, i8);
956 becomes:
958 gate.0 .functor and, i1, i2, i3, i4;
959 gate.1 .functor and, i5, i6, i7, i8;
963 * reg and other variables
965 Reg and integer are cases of what Verilog calls ``variables.''
966 Variables are, simply put, things that behavioral code can assign
967 to. These are not the same as ``nets,'' which include wires and the
968 like.
970 Each bit of a variable is created by a ``.var'' statement. For example:
972 reg a;
974 becomes:
979 * named events
981 Events in general are implemented as functors, but named events in
982 particular have no inputs and only the event output. The way to
983 generate code for these is like so:
987 This creates a functor and makes it into a mode-2 functor. Then the
989 generated. This is sufficient to trigger the event.
991 /*
992 * Copyright (c) 2001 Stephen Williams (steve@icarus.com)
993 *
994 * This source code is free software; you can redistribute it
995 * and/or modify it in source code form under the terms of the GNU
996 * General Public License as published by the Free Software
997 * Foundation; either version 2 of the License, or (at your option)
998 * any later version.
999 *
1000 * This program is distributed in the hope that it will be useful,
1001 * but WITHOUT ANY WARRANTY; without even the implied warranty of
1002 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1003 * GNU General Public License for more details.
1004 *
1005 * You should have received a copy of the GNU General Public License
1006 * along with this program; if not, write to the Free Software
1008 */</pre>
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