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verilog: add sv_maps iterators
[ghdl-vlg.git] / testsuite / synth / issue2266 / testsuite.sh
blobde76174915bff6e48a224acb570675ba9ea0db1e
1 #! /bin/sh
2
3 . ../../testenv.sh
4
5 GHDL_FLAGS=--std=08
6
7 synth_only reproducer
8
9 echo "Test successful"
Experimental work