verilog: add sv_maps iterators
[ghdl-vlg.git] / testsuite / synth / lib01 / testsuite.sh
bloba24d25f2fc08a56498e05b2131eaaf3f55af5fc1
1 #! /bin/sh
3 . ../../testenv.sh
5 analyze --work=mylib and2.vhdl
6 analyze and3.vhdl tb_and3.vhdl
7 elab_simulate tb_and3
8 clean
9 clean mylib
11 synth --work=work and3.vhdl --work=mylib and2.vhdl --work=work -e and3 > syn_and3.vhdl
12 analyze --work=mylib and2.vhdl
13 analyze syn_and3.vhdl tb_and3.vhdl
14 elab_simulate tb_and3
15 clean
16 clean mylib
18 echo "Test successful"