testsuite/synth/synth128/test.vhdl

   1 library ieee;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 entity test is
   6   port (
   7     resb:               in std_logic;
   8     clk_FF:             in std_logic;
   9     ADD_FF:             in unsigned(1 downto 0);
  10     CONFIG:             in std_logic;
  11     D_FF:               in std_logic;
  12     WE:                 in std_logic;
  13     EN_signal:          out std_logic
  14     );
  15 end test;
  16
  17 architecture test_a of test is
  18 signal Q_FF: std_logic_vector(0 to 1);
  19 begin
  20     process(resb, clk_FF)
  21     begin
  22         if resb = '0' then
  23             Q_FF <= "00";
  24         elsif clk_FF'event and clk_FF = '1' then
  25                 if WE = '1' then
  26                         Q_FF(to_integer(ADD_FF)) <= D_FF;
  27                 end if;
  28         end if;
  29      end process;
  30
  31     process(CONFIG, Q_FF)
  32     begin
  33         if CONFIG = '1'  then
  34             EN_signal <=  Q_FF(0);
  35          else
  36             EN_signal <= '0';
  37          end if;
  38       end process;
  39 end;