sysdeps/powerpc/fpu/fenv_libc.h

   1 /* Internal libc stuff for floating point environment routines.
   2    Copyright (C) 1997, 2006, 2008, 2009 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, write to the Free
  17    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  18    02111-1307 USA.  */
  19
  20 #ifndef _FENV_LIBC_H
  21 #define _FENV_LIBC_H    1
  22
  23 #include <fenv.h>
  24 #include <ldsodefs.h>
  25 #include <sysdep.h>
  26
  27 libm_hidden_proto (__fe_nomask_env)
  28
  29 /* The sticky bits in the FPSCR indicating exceptions have occurred.  */
  30 #define FPSCR_STICKY_BITS ((FE_ALL_EXCEPT | FE_ALL_INVALID) & ~FE_INVALID)
  31
  32 /* Equivalent to fegetenv, but returns a fenv_t instead of taking a
  33    pointer.  */
  34 #define fegetenv_register() \
  35         ({ fenv_t env; asm volatile ("mffs %0" : "=f" (env)); env; })
  36
  37 /* Equivalent to fesetenv, but takes a fenv_t instead of a pointer.  */
  38 #define fesetenv_register(env) \
  39         do { \
  40           double d = (env); \
  41           if(GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
  42             asm volatile (".machine push; " \
  43                           ".machine \"power6\"; " \
  44                           "mtfsf 0xff,%0,1,0; " \
  45                           ".machine pop" : : "f" (d)); \
  46           else \
  47             asm volatile ("mtfsf 0xff,%0" : : "f" (d)); \
  48         } while(0)
  49
  50 /* This very handy macro:
  51    - Sets the rounding mode to 'round to nearest';
  52    - Sets the processor into IEEE mode; and
  53    - Prevents exceptions from being raised for inexact results.
  54    These things happen to be exactly what you need for typical elementary
  55    functions.  */
  56 #define relax_fenv_state() \
  57         do { \
  58            if (GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
  59              asm (".machine push; .machine \"power6\"; " \
  60                   "mtfsfi 7,0,1; .machine pop"); \
  61            asm ("mtfsfi 7,0"); \
  62         } while(0)
  63
  64 /* Set/clear a particular FPSCR bit (for instance,
  65    reset_fpscr_bit(FPSCR_VE);
  66    prevents INVALID exceptions from being raised).  */
  67 #define set_fpscr_bit(x) asm volatile ("mtfsb1 %0" : : "i"(x))
  68 #define reset_fpscr_bit(x) asm volatile ("mtfsb0 %0" : : "i"(x))
  69
  70 typedef union
  71 {
  72   fenv_t fenv;
  73   unsigned int l[2];
  74 } fenv_union_t;
  75
  76
  77 static inline int
  78 __fegetround (void)
  79 {
  80   int result;
  81   asm volatile ("mcrfs 7,7\n\t"
  82                 "mfcr  %0" : "=r"(result) : : "cr7");
  83   return result & 3;
  84 }
  85 #define fegetround() __fegetround()
  86
  87 static inline int
  88 __fesetround (int round)
  89 {
  90   if ((unsigned int) round < 2)
  91     {
  92        asm volatile ("mtfsb0 30");
  93        if ((unsigned int) round == 0)
  94          asm volatile ("mtfsb0 31");
  95        else
  96          asm volatile ("mtfsb1 31");
  97     }
  98   else
  99     {
 100        asm volatile ("mtfsb1 30");
 101        if ((unsigned int) round == 2)
 102          asm volatile ("mtfsb0 31");
 103        else
 104          asm volatile ("mtfsb1 31");
 105     }
 106
 107   return 0;
 108 }
 109 #define fesetround(mode) __fesetround(mode)
 110
 111 /* Definitions of all the FPSCR bit numbers */
 112 enum {
 113   FPSCR_FX = 0,    /* exception summary */
 114   FPSCR_FEX,       /* enabled exception summary */
 115   FPSCR_VX,        /* invalid operation summary */
 116   FPSCR_OX,        /* overflow */
 117   FPSCR_UX,        /* underflow */
 118   FPSCR_ZX,        /* zero divide */
 119   FPSCR_XX,        /* inexact */
 120   FPSCR_VXSNAN,    /* invalid operation for SNaN */
 121   FPSCR_VXISI,     /* invalid operation for Inf-Inf */
 122   FPSCR_VXIDI,     /* invalid operation for Inf/Inf */
 123   FPSCR_VXZDZ,     /* invalid operation for 0/0 */
 124   FPSCR_VXIMZ,     /* invalid operation for Inf*0 */
 125   FPSCR_VXVC,      /* invalid operation for invalid compare */
 126   FPSCR_FR,        /* fraction rounded [fraction was incremented by round] */
 127   FPSCR_FI,        /* fraction inexact */
 128   FPSCR_FPRF_C,    /* result class descriptor */
 129   FPSCR_FPRF_FL,   /* result less than (usually, less than 0) */
 130   FPSCR_FPRF_FG,   /* result greater than */
 131   FPSCR_FPRF_FE,   /* result equal to */
 132   FPSCR_FPRF_FU,   /* result unordered */
 133   FPSCR_20,        /* reserved */
 134   FPSCR_VXSOFT,    /* invalid operation set by software */
 135   FPSCR_VXSQRT,    /* invalid operation for square root */
 136   FPSCR_VXCVI,     /* invalid operation for invalid integer convert */
 137   FPSCR_VE,        /* invalid operation exception enable */
 138   FPSCR_OE,        /* overflow exception enable */
 139   FPSCR_UE,        /* underflow exception enable */
 140   FPSCR_ZE,        /* zero divide exception enable */
 141   FPSCR_XE,        /* inexact exception enable */
 142 #ifdef _ARCH_PWR6
 143   FPSCR_29,        /* Reserved in ISA 2.05  */
 144 #else
 145   FPSCR_NI         /* non-IEEE mode (typically, no denormalised numbers) */
 146 #endif /* _ARCH_PWR6 */
 147   /* the remaining two least-significant bits keep the rounding mode */
 148 };
 149
 150 #ifdef _ARCH_PWR6
 151   /* Not supported in ISA 2.05.  Provided for source compat only.  */
 152 # define FPSCR_NI 29
 153 #endif /* _ARCH_PWR6 */
 154
 155 /* This operation (i) sets the appropriate FPSCR bits for its
 156    parameter, (ii) converts SNaN to the corresponding NaN, and (iii)
 157    otherwise passes its parameter through unchanged (in particular, -0
 158    and +0 stay as they were).  The `obvious' way to do this is optimised
 159    out by gcc.  */
 160 #define f_wash(x) \
 161    ({ double d; asm volatile ("fmul %0,%1,%2" \
 162                               : "=f"(d) \
 163                               : "f" (x), "f"((float)1.0)); d; })
 164 #define f_washf(x) \
 165    ({ float f; asm volatile ("fmuls %0,%1,%2" \
 166                              : "=f"(f) \
 167                              : "f" (x), "f"((float)1.0)); f; })
 168
 169 #endif /* fenv_libc.h */