src/drivers/net/igb/igb_82575.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 FILE_LICENCE ( GPL2_ONLY );
  29
  30 #ifndef _IGB_82575_H_
  31 #define _IGB_82575_H_
  32
  33 #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
  34                                      (ID_LED_DEF1_DEF2 <<  8) | \
  35                                      (ID_LED_DEF1_DEF2 <<  4) | \
  36                                      (ID_LED_OFF1_ON2))
  37 /*
  38  * Receive Address Register Count
  39  * Number of high/low register pairs in the RAR.  The RAR (Receive Address
  40  * Registers) holds the directed and multicast addresses that we monitor.
  41  * These entries are also used for MAC-based filtering.
  42  */
  43 /*
  44  * For 82576, there are an additional set of RARs that begin at an offset
  45  * separate from the first set of RARs.
  46  */
  47 #define E1000_RAR_ENTRIES_82575   16
  48 #define E1000_RAR_ENTRIES_82576   24
  49
  50 struct e1000_adv_data_desc {
  51         __le64 buffer_addr;    /* Address of the descriptor's data buffer */
  52         union {
  53                 u32 data;
  54                 struct {
  55                         u32 datalen :16; /* Data buffer length */
  56                         u32 rsvd    :4;
  57                         u32 dtyp    :4;  /* Descriptor type */
  58                         u32 dcmd    :8;  /* Descriptor command */
  59                 } config;
  60         } lower;
  61         union {
  62                 u32 data;
  63                 struct {
  64                         u32 status  :4;  /* Descriptor status */
  65                         u32 idx     :4;
  66                         u32 popts   :6;  /* Packet Options */
  67                         u32 paylen  :18; /* Payload length */
  68                 } options;
  69         } upper;
  70 };
  71
  72 #define E1000_TXD_DTYP_ADV_C    0x2  /* Advanced Context Descriptor */
  73 #define E1000_TXD_DTYP_ADV_D    0x3  /* Advanced Data Descriptor */
  74 #define E1000_ADV_TXD_CMD_DEXT  0x20 /* Descriptor extension (0 = legacy) */
  75 #define E1000_ADV_TUCMD_IPV4    0x2  /* IP Packet Type: 1=IPv4 */
  76 #define E1000_ADV_TUCMD_IPV6    0x0  /* IP Packet Type: 0=IPv6 */
  77 #define E1000_ADV_TUCMD_L4T_UDP 0x0  /* L4 Packet TYPE of UDP */
  78 #define E1000_ADV_TUCMD_L4T_TCP 0x4  /* L4 Packet TYPE of TCP */
  79 #define E1000_ADV_TUCMD_MKRREQ  0x10 /* Indicates markers are required */
  80 #define E1000_ADV_DCMD_EOP      0x1  /* End of Packet */
  81 #define E1000_ADV_DCMD_IFCS     0x2  /* Insert FCS (Ethernet CRC) */
  82 #define E1000_ADV_DCMD_RS       0x8  /* Report Status */
  83 #define E1000_ADV_DCMD_VLE      0x40 /* Add VLAN tag */
  84 #define E1000_ADV_DCMD_TSE      0x80 /* TCP Seg enable */
  85 /* Extended Device Control */
  86 #define E1000_CTRL_EXT_NSICR    0x00000001 /* Disable Intr Clear all on read */
  87
  88 struct e1000_adv_context_desc {
  89         union {
  90                 u32 ip_config;
  91                 struct {
  92                         u32 iplen    :9;
  93                         u32 maclen   :7;
  94                         u32 vlan_tag :16;
  95                 } fields;
  96         } ip_setup;
  97         u32 seq_num;
  98         union {
  99                 u64 l4_config;
 100                 struct {
 101                         u32 mkrloc :9;
 102                         u32 tucmd  :11;
 103                         u32 dtyp   :4;
 104                         u32 adv    :8;
 105                         u32 rsvd   :4;
 106                         u32 idx    :4;
 107                         u32 l4len  :8;
 108                         u32 mss    :16;
 109                 } fields;
 110         } l4_setup;
 111 };
 112
 113 /* SRRCTL bit definitions */
 114 #define E1000_SRRCTL_BSIZEPKT_SHIFT                     10 /* Shift _right_ */
 115 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK                  0x00000F00
 116 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT                 2  /* Shift _left_ */
 117 #define E1000_SRRCTL_DESCTYPE_LEGACY                    0x00000000
 118 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF                0x02000000
 119 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT                 0x04000000
 120 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS          0x0A000000
 121 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION           0x06000000
 122 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
 123 #define E1000_SRRCTL_DESCTYPE_MASK                      0x0E000000
 124 #define E1000_SRRCTL_DROP_EN                            0x80000000
 125
 126 #define E1000_SRRCTL_BSIZEPKT_MASK      0x0000007F
 127 #define E1000_SRRCTL_BSIZEHDR_MASK      0x00003F00
 128
 129 #define E1000_TX_HEAD_WB_ENABLE   0x1
 130 #define E1000_TX_SEQNUM_WB_ENABLE 0x2
 131
 132 #define E1000_MRQC_ENABLE_RSS_4Q            0x00000002
 133 #define E1000_MRQC_ENABLE_VMDQ              0x00000003
 134 #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q       0x00000005
 135 #define E1000_MRQC_RSS_FIELD_IPV4_UDP       0x00400000
 136 #define E1000_MRQC_RSS_FIELD_IPV6_UDP       0x00800000
 137 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX    0x01000000
 138
 139 #define E1000_VMRCTL_MIRROR_PORT_SHIFT      8
 140 #define E1000_VMRCTL_MIRROR_DSTPORT_MASK    (7 << E1000_VMRCTL_MIRROR_PORT_SHIFT)
 141 #define E1000_VMRCTL_POOL_MIRROR_ENABLE     (1 << 0)
 142 #define E1000_VMRCTL_UPLINK_MIRROR_ENABLE   (1 << 1)
 143 #define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2)
 144
 145 #define E1000_EICR_TX_QUEUE ( \
 146     E1000_EICR_TX_QUEUE0 |    \
 147     E1000_EICR_TX_QUEUE1 |    \
 148     E1000_EICR_TX_QUEUE2 |    \
 149     E1000_EICR_TX_QUEUE3)
 150
 151 #define E1000_EICR_RX_QUEUE ( \
 152     E1000_EICR_RX_QUEUE0 |    \
 153     E1000_EICR_RX_QUEUE1 |    \
 154     E1000_EICR_RX_QUEUE2 |    \
 155     E1000_EICR_RX_QUEUE3)
 156
 157 #define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
 158 #define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
 159
 160 #define EIMS_ENABLE_MASK ( \
 161     E1000_EIMS_RX_QUEUE  | \
 162     E1000_EIMS_TX_QUEUE  | \
 163     E1000_EIMS_TCP_TIMER | \
 164     E1000_EIMS_OTHER)
 165
 166 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
 167 #define E1000_IMIR_PORT_IM_EN     0x00010000  /* TCP port enable */
 168 #define E1000_IMIR_PORT_BP        0x00020000  /* TCP port check bypass */
 169 #define E1000_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
 170 #define E1000_IMIREXT_CTRL_URG    0x00002000  /* Check URG bit in header */
 171 #define E1000_IMIREXT_CTRL_ACK    0x00004000  /* Check ACK bit in header */
 172 #define E1000_IMIREXT_CTRL_PSH    0x00008000  /* Check PSH bit in header */
 173 #define E1000_IMIREXT_CTRL_RST    0x00010000  /* Check RST bit in header */
 174 #define E1000_IMIREXT_CTRL_SYN    0x00020000  /* Check SYN bit in header */
 175 #define E1000_IMIREXT_CTRL_FIN    0x00040000  /* Check FIN bit in header */
 176 #define E1000_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of ctrl bits */
 177
 178 /* Receive Descriptor - Advanced */
 179 union e1000_adv_rx_desc {
 180         struct {
 181                 __le64 pkt_addr;             /* Packet buffer address */
 182                 __le64 hdr_addr;             /* Header buffer address */
 183         } read;
 184         struct {
 185                 struct {
 186                         union {
 187                                 __le32 data;
 188                                 struct {
 189                                         __le16 pkt_info; /*RSS type, Pkt type*/
 190                                         __le16 hdr_info; /* Split Header,
 191                                                           * header buffer len*/
 192                                 } hs_rss;
 193                         } lo_dword;
 194                         union {
 195                                 __le32 rss;          /* RSS Hash */
 196                                 struct {
 197                                         __le16 ip_id;    /* IP id */
 198                                         __le16 csum;     /* Packet Checksum */
 199                                 } csum_ip;
 200                         } hi_dword;
 201                 } lower;
 202                 struct {
 203                         __le32 status_error;     /* ext status/error */
 204                         __le16 length;           /* Packet length */
 205                         __le16 vlan;             /* VLAN tag */
 206                 } upper;
 207         } wb;  /* writeback */
 208 };
 209
 210 #define E1000_RXDADV_RSSTYPE_MASK        0x0000000F
 211 #define E1000_RXDADV_RSSTYPE_SHIFT       12
 212 #define E1000_RXDADV_HDRBUFLEN_MASK      0x7FE0
 213 #define E1000_RXDADV_HDRBUFLEN_SHIFT     5
 214 #define E1000_RXDADV_SPLITHEADER_EN      0x00001000
 215 #define E1000_RXDADV_SPH                 0x8000
 216 #define E1000_RXDADV_STAT_TS             0x10000 /* Pkt was time stamped */
 217 #define E1000_RXDADV_ERR_HBO             0x00800000
 218
 219 /* RSS Hash results */
 220 #define E1000_RXDADV_RSSTYPE_NONE        0x00000000
 221 #define E1000_RXDADV_RSSTYPE_IPV4_TCP    0x00000001
 222 #define E1000_RXDADV_RSSTYPE_IPV4        0x00000002
 223 #define E1000_RXDADV_RSSTYPE_IPV6_TCP    0x00000003
 224 #define E1000_RXDADV_RSSTYPE_IPV6_EX     0x00000004
 225 #define E1000_RXDADV_RSSTYPE_IPV6        0x00000005
 226 #define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
 227 #define E1000_RXDADV_RSSTYPE_IPV4_UDP    0x00000007
 228 #define E1000_RXDADV_RSSTYPE_IPV6_UDP    0x00000008
 229 #define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
 230
 231 /* RSS Packet Types as indicated in the receive descriptor */
 232 #define E1000_RXDADV_PKTTYPE_NONE        0x00000000
 233 #define E1000_RXDADV_PKTTYPE_IPV4        0x00000010 /* IPV4 hdr present */
 234 #define E1000_RXDADV_PKTTYPE_IPV4_EX     0x00000020 /* IPV4 hdr + extensions */
 235 #define E1000_RXDADV_PKTTYPE_IPV6        0x00000040 /* IPV6 hdr present */
 236 #define E1000_RXDADV_PKTTYPE_IPV6_EX     0x00000080 /* IPV6 hdr + extensions */
 237 #define E1000_RXDADV_PKTTYPE_TCP         0x00000100 /* TCP hdr present */
 238 #define E1000_RXDADV_PKTTYPE_UDP         0x00000200 /* UDP hdr present */
 239 #define E1000_RXDADV_PKTTYPE_SCTP        0x00000400 /* SCTP hdr present */
 240 #define E1000_RXDADV_PKTTYPE_NFS         0x00000800 /* NFS hdr present */
 241
 242 #define E1000_RXDADV_PKTTYPE_IPSEC_ESP   0x00001000 /* IPSec ESP */
 243 #define E1000_RXDADV_PKTTYPE_IPSEC_AH    0x00002000 /* IPSec AH */
 244 #define E1000_RXDADV_PKTTYPE_LINKSEC     0x00004000 /* LinkSec Encap */
 245 #define E1000_RXDADV_PKTTYPE_ETQF        0x00008000 /* PKTTYPE is ETQF index */
 246 #define E1000_RXDADV_PKTTYPE_ETQF_MASK   0x00000070 /* ETQF has 8 indices */
 247 #define E1000_RXDADV_PKTTYPE_ETQF_SHIFT  4          /* Right-shift 4 bits */
 248
 249 /* LinkSec results */
 250 /* Security Processing bit Indication */
 251 #define E1000_RXDADV_LNKSEC_STATUS_SECP         0x00020000
 252 #define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK      0x18000000
 253 #define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH   0x08000000
 254 #define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR  0x10000000
 255 #define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG       0x18000000
 256
 257 #define E1000_RXDADV_IPSEC_STATUS_SECP          0x00020000
 258 #define E1000_RXDADV_IPSEC_ERROR_BIT_MASK       0x18000000
 259 #define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL       0x08000000
 260 #define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH         0x10000000
 261 #define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED  0x18000000
 262
 263 /* Transmit Descriptor - Advanced */
 264 union e1000_adv_tx_desc {
 265         struct {
 266                 __le64 buffer_addr;    /* Address of descriptor's data buf */
 267                 __le32 cmd_type_len;
 268                 __le32 olinfo_status;
 269         } read;
 270         struct {
 271                 __le64 rsvd;       /* Reserved */
 272                 __le32 nxtseq_seed;
 273                 __le32 status;
 274         } wb;
 275 };
 276
 277 /* Adv Transmit Descriptor Config Masks */
 278 #define E1000_ADVTXD_DTYP_CTXT    0x00200000 /* Advanced Context Descriptor */
 279 #define E1000_ADVTXD_DTYP_DATA    0x00300000 /* Advanced Data Descriptor */
 280 #define E1000_ADVTXD_DCMD_EOP     0x01000000 /* End of Packet */
 281 #define E1000_ADVTXD_DCMD_IFCS    0x02000000 /* Insert FCS (Ethernet CRC) */
 282 #define E1000_ADVTXD_DCMD_RS      0x08000000 /* Report Status */
 283 #define E1000_ADVTXD_DCMD_DDTYP_ISCSI  0x10000000 /* DDP hdr type or iSCSI */
 284 #define E1000_ADVTXD_DCMD_DEXT    0x20000000 /* Descriptor extension (1=Adv) */
 285 #define E1000_ADVTXD_DCMD_VLE     0x40000000 /* VLAN pkt enable */
 286 #define E1000_ADVTXD_DCMD_TSE     0x80000000 /* TCP Seg enable */
 287 #define E1000_ADVTXD_MAC_LINKSEC  0x00040000 /* Apply LinkSec on packet */
 288 #define E1000_ADVTXD_MAC_TSTAMP   0x00080000 /* IEEE1588 Timestamp packet */
 289 #define E1000_ADVTXD_STAT_SN_CRC  0x00000002 /* NXTSEQ/SEED present in WB */
 290 #define E1000_ADVTXD_IDX_SHIFT    4  /* Adv desc Index shift */
 291 #define E1000_ADVTXD_POPTS_ISCO_1ST  0x00000000 /* 1st TSO of iSCSI PDU */
 292 #define E1000_ADVTXD_POPTS_ISCO_MDL  0x00000800 /* Middle TSO of iSCSI PDU */
 293 #define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
 294 #define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/
 295 #define E1000_ADVTXD_POPTS_IPSEC     0x00000400 /* IPSec offload request */
 296 #define E1000_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */
 297
 298 /* Context descriptors */
 299 struct e1000_adv_tx_context_desc {
 300         __le32 vlan_macip_lens;
 301         __le32 seqnum_seed;
 302         __le32 type_tucmd_mlhl;
 303         __le32 mss_l4len_idx;
 304 };
 305
 306 #define E1000_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
 307 #define E1000_ADVTXD_VLAN_SHIFT     16  /* Adv ctxt vlan tag shift */
 308 #define E1000_ADVTXD_TUCMD_IPV4    0x00000400  /* IP Packet Type: 1=IPv4 */
 309 #define E1000_ADVTXD_TUCMD_IPV6    0x00000000  /* IP Packet Type: 0=IPv6 */
 310 #define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000  /* L4 Packet TYPE of UDP */
 311 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800  /* L4 Packet TYPE of TCP */
 312 #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000  /* L4 Packet TYPE of SCTP */
 313 #define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP    0x00002000 /* IPSec Type ESP */
 314 /* IPSec Encrypt Enable for ESP */
 315 #define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN  0x00004000
 316 #define E1000_ADVTXD_TUCMD_MKRREQ  0x00002000 /* Req requires Markers and CRC */
 317 #define E1000_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
 318 #define E1000_ADVTXD_MSS_SHIFT      16  /* Adv ctxt MSS shift */
 319 /* Adv ctxt IPSec SA IDX mask */
 320 #define E1000_ADVTXD_IPSEC_SA_INDEX_MASK     0x000000FF
 321 /* Adv ctxt IPSec ESP len mask */
 322 #define E1000_ADVTXD_IPSEC_ESP_LEN_MASK      0x000000FF
 323
 324 /* Additional Transmit Descriptor Control definitions */
 325 #define E1000_TXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
 326 #define E1000_TXDCTL_SWFLSH        0x04000000 /* Tx Desc. write-back flushing */
 327 /* Tx Queue Arbitration Priority 0=low, 1=high */
 328 #define E1000_TXDCTL_PRIORITY      0x08000000
 329
 330 /* Additional Receive Descriptor Control definitions */
 331 #define E1000_RXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Rx Queue */
 332 #define E1000_RXDCTL_SWFLSH        0x04000000 /* Rx Desc. write-back flushing */
 333
 334 /* Direct Cache Access (DCA) definitions */
 335 #define E1000_DCA_CTRL_DCA_ENABLE  0x00000000 /* DCA Enable */
 336 #define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
 337
 338 #define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
 339 #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
 340
 341 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
 342 #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
 343 #define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
 344 #define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
 345
 346 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
 347 #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
 348 #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
 349
 350 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
 351 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
 352 #define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */
 353 #define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */
 354
 355 /* Additional interrupt register bit definitions */
 356 #define E1000_ICR_LSECPNS       0x00000020          /* PN threshold - server */
 357 #define E1000_IMS_LSECPNS       E1000_ICR_LSECPNS   /* PN threshold - server */
 358 #define E1000_ICS_LSECPNS       E1000_ICR_LSECPNS   /* PN threshold - server */
 359
 360 /* ETQF register bit definitions */
 361 #define E1000_ETQF_FILTER_ENABLE   (1 << 26)
 362 #define E1000_ETQF_IMM_INT         (1 << 29)
 363 #define E1000_ETQF_1588            (1 << 30)
 364 #define E1000_ETQF_QUEUE_ENABLE    (1 << 31)
 365 /*
 366  * ETQF filter list: one static filter per filter consumer. This is
 367  *                   to avoid filter collisions later. Add new filters
 368  *                   here!!
 369  *
 370  * Current filters:
 371  *    EAPOL 802.1x (0x888e): Filter 0
 372  */
 373 #define E1000_ETQF_FILTER_EAPOL          0
 374
 375 #define E1000_FTQF_VF_BP               0x00008000
 376 #define E1000_FTQF_1588_TIME_STAMP     0x08000000
 377 #define E1000_FTQF_MASK                0xF0000000
 378 #define E1000_FTQF_MASK_PROTO_BP       0x10000000
 379 #define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000
 380 #define E1000_FTQF_MASK_DEST_ADDR_BP   0x40000000
 381 #define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
 382
 383 #define E1000_NVM_APME_82575          0x0400
 384 #define MAX_NUM_VFS                   8
 385
 386 #define E1000_DTXSWC_MAC_SPOOF_MASK   0x000000FF /* Per VF MAC spoof control */
 387 #define E1000_DTXSWC_VLAN_SPOOF_MASK  0x0000FF00 /* Per VF VLAN spoof control */
 388 #define E1000_DTXSWC_LLE_MASK         0x00FF0000 /* Per VF Local LB enables */
 389 #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
 390 #define E1000_DTXSWC_LLE_SHIFT        16
 391 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31)  /* global VF LB enable */
 392
 393 /* Easy defines for setting default pool, would normally be left a zero */
 394 #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
 395 #define E1000_VT_CTL_DEFAULT_POOL_MASK  (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
 396
 397 /* Other useful VMD_CTL register defines */
 398 #define E1000_VT_CTL_IGNORE_MAC         (1 << 28)
 399 #define E1000_VT_CTL_DISABLE_DEF_POOL   (1 << 29)
 400 #define E1000_VT_CTL_VM_REPL_EN         (1 << 30)
 401
 402 /* Per VM Offload register setup */
 403 #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
 404 #define E1000_VMOLR_LPE        0x00010000 /* Accept Long packet */
 405 #define E1000_VMOLR_RSSE       0x00020000 /* Enable RSS */
 406 #define E1000_VMOLR_AUPE       0x01000000 /* Accept untagged packets */
 407 #define E1000_VMOLR_ROMPE      0x02000000 /* Accept overflow multicast */
 408 #define E1000_VMOLR_ROPE       0x04000000 /* Accept overflow unicast */
 409 #define E1000_VMOLR_BAM        0x08000000 /* Accept Broadcast packets */
 410 #define E1000_VMOLR_MPME       0x10000000 /* Multicast promiscuous mode */
 411 #define E1000_VMOLR_STRVLAN    0x40000000 /* Vlan stripping enable */
 412 #define E1000_VMOLR_STRCRC     0x80000000 /* CRC stripping enable */
 413
 414 #define E1000_VLVF_ARRAY_SIZE     32
 415 #define E1000_VLVF_VLANID_MASK    0x00000FFF
 416 #define E1000_VLVF_POOLSEL_SHIFT  12
 417 #define E1000_VLVF_POOLSEL_MASK   (0xFF << E1000_VLVF_POOLSEL_SHIFT)
 418 #define E1000_VLVF_LVLAN          0x00100000
 419 #define E1000_VLVF_VLANID_ENABLE  0x80000000
 420
 421 #define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
 422
 423 #define E1000_IOVCTL 0x05BBC
 424 #define E1000_IOVCTL_REUSE_VFQ 0x00000001
 425
 426 #define E1000_RPLOLR_STRVLAN   0x40000000
 427 #define E1000_RPLOLR_STRCRC    0x80000000
 428
 429 #define E1000_DTXCTL_8023LL     0x0004
 430 #define E1000_DTXCTL_VLAN_ADDED 0x0008
 431 #define E1000_DTXCTL_OOS_ENABLE 0x0010
 432 #define E1000_DTXCTL_MDP_EN     0x0020
 433 #define E1000_DTXCTL_SPOOF_INT  0x0040
 434
 435 #define ALL_QUEUES   0xFFFF
 436
 437 /* RX packet buffer size defines */
 438 #define E1000_RXPBS_SIZE_MASK_82576  0x0000007F
 439 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
 440 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);
 441
 442 #endif /* _IGB_82575_H_ */