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Remove deprecation of pci_bar_size()
[gpxe.git] / src / include / gpxe / pci.h
blobb5c417c9e118163656b456366b175cb440f6ed4b
1 #ifndef _GPXE_PCI_H
2 #define _GPXE_PCI_H
3
4 /*
5 * Support for NE2000 PCI clones added David Monro June 1997
6 * Generalised for other PCI NICs by Ken Yap July 1997
7 * PCI support rewritten by Michael Brown 2006
8 *
9 * Most of this is taken from /usr/src/linux/include/linux/pci.h.
10 */
11
12 /*
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2, or (at
16 * your option) any later version.
17 */
18
19 #include <stdint.h>
20 #include <gpxe/device.h>
21 #include <gpxe/tables.h>
22 #include <pci_io.h>
23 #include "pci_ids.h"
24
25 /*
26 * PCI constants
27 *
28 */
29
30 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
31 #define PCI_COMMAND_MEM 0x2 /* Enable response in mem space */
32 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
33 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
34 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
35 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
36 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
37 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
38 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
39 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
40 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
41
42
43 #define PCI_VENDOR_ID 0x00 /* 16 bits */
44 #define PCI_DEVICE_ID 0x02 /* 16 bits */
45 #define PCI_COMMAND 0x04 /* 16 bits */
46
47 #define PCI_STATUS 0x06 /* 16 bits */
48 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
49 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
50 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
51 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
52 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
53 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
54 #define PCI_STATUS_DEVSEL_FAST 0x000
55 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
56 #define PCI_STATUS_DEVSEL_SLOW 0x400
57 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
58 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
59 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
60 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
61 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
62
63 #define PCI_REVISION 0x08 /* 8 bits */
64 #define PCI_REVISION_ID 0x08 /* 8 bits */
65 #define PCI_CLASS_REVISION 0x08 /* 32 bits */
66 #define PCI_CLASS_CODE 0x0b /* 8 bits */
67 #define PCI_SUBCLASS_CODE 0x0a /* 8 bits */
68 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
69 #define PCI_HEADER_TYPE_NORMAL 0
70 #define PCI_HEADER_TYPE_BRIDGE 1
71 #define PCI_HEADER_TYPE_CARDBUS 2
72
73
74 /* Header type 0 (normal devices) */
75 #define PCI_CARDBUS_CIS 0x28
76 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
77 #define PCI_SUBSYSTEM_ID 0x2e
78
79 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
80 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits */
81 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits */
82 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
83 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
84 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
85
86 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
87 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
88 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
89
90 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
91 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
92 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
93 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
94 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0f)
95 #define PCI_BASE_ADDRESS_IO_MASK (~0x03)
96 #define PCI_ROM_ADDRESS 0x30 /* 32 bits */
97 #define PCI_ROM_ADDRESS_ENABLE 0x01 /* Write 1 to enable ROM,
98 bits 31..11 are address,
99 10..2 are reserved */
100
101 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
102
103 #define PCI_INTERRUPT_LINE 0x3c /* IRQ number (0-15) */
104 #define PCI_INTERRUPT_PIN 0x3d /* IRQ pin on PCI bus (A-D) */
105
106 /* Header type 1 (PCI-to-PCI bridges) */
107 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
108 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
109 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
110 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
111 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
112 #define PCI_IO_LIMIT 0x1d
113 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
114 #define PCI_IO_RANGE_TYPE_16 0x00
115 #define PCI_IO_RANGE_TYPE_32 0x01
116 #define PCI_IO_RANGE_MASK ~0x0f
117 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
118 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
119 #define PCI_MEMORY_LIMIT 0x22
120 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
121 #define PCI_MEMORY_RANGE_MASK ~0x0f
122 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
123 #define PCI_PREF_MEMORY_LIMIT 0x26
124 #define PCI_PREF_RANGE_TYPE_MASK 0x0f
125 #define PCI_PREF_RANGE_TYPE_32 0x00
126 #define PCI_PREF_RANGE_TYPE_64 0x01
127 #define PCI_PREF_RANGE_MASK ~0x0f
128 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
129 #define PCI_PREF_LIMIT_UPPER32 0x2c
130 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
131 #define PCI_IO_LIMIT_UPPER16 0x32
132 /* 0x34 same as for htype 0 */
133 /* 0x35-0x3b is reserved */
134 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
135 /* 0x3c-0x3d are same as for htype 0 */
136 #define PCI_BRIDGE_CONTROL 0x3e
137 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
138 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
139 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
140 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
141 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
142 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
143 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
144
145 #define PCI_CB_CAPABILITY_LIST 0x14
146
147 /* Capability lists */
148
149 #define PCI_CAP_LIST_ID 0 /* Capability ID */
150 #define PCI_CAP_ID_PM 0x01 /* Power Management */
151 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
152 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
153 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
154 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
155 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
156 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
157 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
158 #define PCI_CAP_SIZEOF 4
159
160 /* Power Management Registers */
161
162 #define PCI_PM_PMC 2 /* PM Capabilities Register */
163 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
164 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
165 #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
166 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
167 #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
168 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
169 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
170 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
171 #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
172 #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
173 #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
174 #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
175 #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
176 #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
177 #define PCI_PM_CTRL 4 /* PM control and status register */
178 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
179 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
180 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
181 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
182 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
183 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
184 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
185 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
186 #define PCI_PM_DATA_REGISTER 7 /* (??) */
187 #define PCI_PM_SIZEOF 8
188
189 /* AGP registers */
190
191 #define PCI_AGP_VERSION 2 /* BCD version number */
192 #define PCI_AGP_RFU 3 /* Rest of capability flags */
193 #define PCI_AGP_STATUS 4 /* Status register */
194 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
195 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
196 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
197 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
198 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
199 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
200 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
201 #define PCI_AGP_COMMAND 8 /* Control register */
202 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
203 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
204 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
205 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
206 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
207 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
208 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
209 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
210 #define PCI_AGP_SIZEOF 12
211
212 /* Slot Identification */
213
214 #define PCI_SID_ESR 2 /* Expansion Slot Register */
215 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
216 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
217 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
218
219 /* Message Signalled Interrupts registers */
220
221 #define PCI_MSI_FLAGS 2 /* Various flags */
222 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
223 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
224 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
225 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
226 #define PCI_MSI_RFU 3 /* Rest of capability flags */
227 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
228 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
229 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
230 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
231
232 /** A PCI device ID list entry */
233 struct pci_device_id {
234 /** Name */
235 const char *name;
236 /** PCI vendor ID */
237 uint16_t vendor;
238 /** PCI device ID */
239 uint16_t device;
240 };
241
242 /** Match-anything ID */
243 #define PCI_ANY_ID 0xffff
244
245 /** A PCI device */
246 struct pci_device {
247 /** Generic device */
248 struct device dev;
249 /** Memory base
250 *
251 * This is the physical address of the first valid memory BAR.
252 */
253 unsigned long membase;
254 /**
255 * I/O address
256 *
257 * This is the physical address of the first valid I/O BAR.
258 */
259 unsigned long ioaddr;
260 /** Vendor ID */
261 uint16_t vendor;
262 /** Device ID */
263 uint16_t device;
264 /** Device class */
265 uint32_t class;
266 /** Interrupt number */
267 uint8_t irq;
268 /** Bus number */
269 uint8_t bus;
270 /** Device and function number */
271 uint8_t devfn;
272 /** Driver for this device */
273 struct pci_driver *driver;
274 /** Driver-private data
275 *
276 * Use pci_set_drvdata() and pci_get_drvdata() to access this
277 * field.
278 */
279 void *priv;
280 /** Driver name */
281 const char *driver_name;
282 };
283
284 /** A PCI driver */
285 struct pci_driver {
286 /** PCI ID table */
287 struct pci_device_id *ids;
288 /** Number of entries in PCI ID table */
289 unsigned int id_count;
290 /**
291 * Probe device
292 *
293 * @v pci PCI device
294 * @v id Matching entry in ID table
295 * @ret rc Return status code
296 */
297 int ( * probe ) ( struct pci_device *pci,
298 const struct pci_device_id *id );
299 /**
300 * Remove device
301 *
302 * @v pci PCI device
303 */
304 void ( * remove ) ( struct pci_device *pci );
305 };
306
307 /** Declare a PCI driver */
308 #define __pci_driver __table ( struct pci_driver, pci_drivers, 01 )
309
310 #define PCI_DEVFN( slot, func ) ( ( (slot) << 3 ) | (func) )
311 #define PCI_SLOT( devfn ) ( ( (devfn) >> 3 ) & 0x1f )
312 #define PCI_FUNC( devfn ) ( (devfn) & 0x07 )
313 #define PCI_BUSDEVFN( bus, devfn ) ( ( (bus) << 8 ) | (devfn) )
314
315 #define PCI_BASE_CLASS( class ) ( (class) >> 16 )
316 #define PCI_SUB_CLASS( class ) ( ( (class) >> 8 ) & 0xff )
317 #define PCI_PROG_INTF( class ) ( (class) & 0xff )
318
319 /*
320 * PCI_ROM is used to build up entries in a struct pci_id array. It
321 * is also parsed by parserom.pl to generate Makefile rules and files
322 * for rom-o-matic.
323 */
324 #define PCI_ROM( _vendor, _device, _name, _description ) { \
325 .vendor = _vendor, \
326 .device = _device, \
327 .name = _name, \
328 }
329
330 extern void adjust_pci_device ( struct pci_device *pci );
331 extern unsigned long pci_bar_start ( struct pci_device *pci,
332 unsigned int reg );
333 extern int pci_find_capability ( struct pci_device *pci, int capability );
334 extern unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg );
335
336 /**
337 * Set PCI driver-private data
338 *
339 * @v pci PCI device
340 * @v priv Private data
341 */
342 static inline void pci_set_drvdata ( struct pci_device *pci, void *priv ) {
343 pci->priv = priv;
344 }
345
346 /**
347 * Get PCI driver-private data
348 *
349 * @v pci PCI device
350 * @ret priv Private data
351 */
352 static inline void * pci_get_drvdata ( struct pci_device *pci ) {
353 return pci->priv;
354 }
355
356 #endif /* _GPXE_PCI_H */
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