src/add-ons/kernel/drivers/network/rtl8169/hardware.h

   1 /* Realtek RTL8169 Family Driver
   2  * Copyright (C) 2004 Marcus Overhagen <marcus@overhagen.de>. All rights reserved.
   3  *
   4  * Permission to use, copy, modify and distribute this software and its
   5  * documentation for any purpose and without fee is hereby granted, provided
   6  * that the above copyright notice appear in all copies, and that both the
   7  * copyright notice and this permission notice appear in supporting documentation.
   8  *
   9  * Marcus Overhagen makes no representations about the suitability of this software
  10  * for any purpose. It is provided "as is" without express or implied warranty.
  11  *
  12  * MARCUS OVERHAGEN DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING
  13  * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL MARCUS
  14  * OVERHAGEN BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
  15  * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  17  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19 #ifndef __HARDWARE_H
  20 #define __HARDWARE_H
  21
  22 #define PCI_PCICMD_IOS  0x01
  23 #define PCI_PCICMD_MSE  0x02
  24 #define PCI_PCICMD_BME  0x04
  25
  26 typedef struct {
  27         uint32 stat_len;
  28         uint32 vlan;
  29         uint32 buf_low;         // must be 8 byte aligned
  30         uint32 buf_high;
  31 } _PACKED buf_desc;
  32
  33 enum {
  34         TX_DESC_OWN                     = 0x80000000,
  35         TX_DESC_EOR                     = 0x40000000,
  36         TX_DESC_FS                      = 0x20000000,
  37         TX_DESC_LS                      = 0x10000000,
  38         TX_DESC_LEN_MASK        = 0x00003fff,
  39 };
  40
  41 enum {
  42         RX_DESC_OWN                     = 0x80000000,
  43         RX_DESC_EOR                     = 0x40000000,
  44         RX_DESC_FS                      = 0x20000000,
  45         RX_DESC_LS                      = 0x10000000,
  46         RX_DESC_MAR                     = 0x08000000,
  47         RX_DESC_PAM                     = 0x04000000,
  48         RX_DESC_BAR                     = 0x02000000,
  49         RX_DESC_BOVF            = 0x01000000,
  50         RX_DESC_FOVF            = 0x00800000,
  51         RX_DESC_RWT                     = 0x00400000,
  52         RX_DESC_RES                     = 0x00200000,
  53         RX_DESC_RUNT            = 0x00100000,
  54         RX_DESC_CRC                     = 0x00080000,
  55         RX_DESC_LEN_MASK        = 0x00003fff,
  56 };
  57
  58 enum {
  59         REG_TNPDS_LOW           = 0x20,
  60         REG_TNPDS_HIGH          = 0x24,
  61         REG_THPDS_LOW           = 0x28,
  62         REG_THPDS_HIGH          = 0x2c,
  63         REG_RDSAR_LOW           = 0xe4,
  64         REG_RDSAR_HIGH          = 0xe8,
  65
  66         REG_CR                          = 0x37, // 8 bit
  67         REG_TPPOLL                      = 0x38, // 8 bit
  68
  69         REG_INT_MASK            = 0x3c, // 16 bit
  70         REG_INT_STAT            = 0x3e, // 16 bit
  71
  72         REG_TX_CONFIG           = 0x40,
  73         REG_RX_CONFIG           = 0x44,
  74
  75         REG_9346CR                      = 0x50, // 8 bit
  76         REG_CONFIG0                     = 0x51, // 8 bit
  77         REG_CONFIG1                     = 0x52, // 8 bit
  78         REG_CONFIG2                     = 0x53, // 8 bit
  79         REG_CONFIG3                     = 0x54, // 8 bit
  80         REG_CONFIG4                     = 0x55, // 8 bit
  81         REG_CONFIG5                     = 0x56, // 8 bit
  82
  83
  84         REG_PHYAR                       = 0x60,
  85         REG_TBICSR                      = 0x64,
  86         REG_PHY_STAT            = 0x6c, // 8bit
  87
  88 };
  89
  90 // for REG_CR
  91 enum {
  92         CR_RST  = 0x10,
  93         CR_RE   = 0x08,
  94         CR_TE   = 0x04,
  95 };
  96
  97 // for REG_TPPOLL
  98 enum {
  99         TPPOLL_HPQ              = 0x80,
 100         TPPOLL_NPQ              = 0x40,
 101         TPPOLL_FSWINT   = 0x01,
 102 };
 103
 104 // for REG_INT_MASK and REG_INT_STAT
 105 enum {
 106         INT_SERR        = 0x8000,
 107         INT_TimeOut     = 0x4000,
 108         INT_SwInt       = 0x0100,
 109         INT_TDU         = 0x0080,
 110         INT_FOVW        = 0x0040,
 111         INT_PUN         = 0x0020,
 112         INT_RDU         = 0x0010,
 113         INT_TER         = 0x0008,
 114         INT_TOK         = 0x0004,
 115         INT_RER         = 0x0002,
 116         INT_ROK         = 0x0001,
 117 };
 118
 119 // for REG_PHY_STAT
 120 enum {
 121         PHY_STAT_EnTBI          = 0x80,
 122         PHY_STAT_TxFlow         = 0x40,
 123         PHY_STAT_RxFlow         = 0x20,
 124         PHY_STAT_1000MF         = 0x10,
 125         PHY_STAT_100M           = 0x08,
 126         PHY_STAT_10M            = 0x04,
 127         PHY_STAT_LinkSts        = 0x02,
 128         PHY_STAT_FullDup        = 0x01,
 129 };
 130
 131 // for REG_TBICSR
 132 enum {
 133         TBICSR_ResetTBI         = 0x80000000,
 134         TBICSR_TBILoopBack      = 0x40000000,
 135         TBICSR_TBINWEn          = 0x20000000,
 136         TBICSR_TBIReNW          = 0x10000000,
 137         TBICSR_TBILinkOk        = 0x02000000,
 138         TBICSR_NWComplete       = 0x01000000,
 139 };
 140
 141 // for REG_RX_CONFIG
 142 enum {
 143         RX_CONFIG_MulERINT              = 0x01000000,
 144         RX_CONFIG_RER8                  = 0x00010000,
 145         RX_CONFIG_AcceptErr             = 0x00000020,
 146         RX_CONFIG_AcceptRunt    = 0x00000010,
 147         RX_CONFIG_AcceptBroad   = 0x00000008,
 148         RX_CONFIG_AcceptMulti   = 0x00000004,
 149         RX_CONFIG_AcceptMyPhys  = 0x00000002,
 150         RX_CONFIG_AcceptAllPhys = 0x00000001,
 151         RX_CONFIG_MASK                  = 0xfe7e1880, // XXX should be 0xfefe1880 but Realtek driver clears the undocumented bit 23
 152         RC_CONFIG_RXFTH_Shift   = 13,
 153         RC_CONFIG_MAXDMA_Shift  = 8,
 154 };
 155
 156 #endif