src/add-ons/kernel/drivers/network/sis900/sis900.h

   1 /*
   2  * Copyright (c) 2001-2007 pinc Software. All Rights Reserved.
   3  * Distributed under the terms of the MIT license.
   4  */
   5 #ifndef SIS900_H
   6 #define SIS900_H
   7
   8 /*! SiS 900 driver/chip specific definitions */
   9
  10 #include <ether_driver.h>
  11
  12 #include <KernelExport.h>
  13 #include <PCI.h>
  14
  15
  16 #define VENDOR_ID_SiS           0x1039
  17 #define DEVICE_ID_SiS900        0x900
  18
  19 #define DEVICE_ID_SiS_ISA_BRIDGE 0x0008
  20
  21 enum SiS_revisions {
  22         SiS900_REVISION_B                       = 0x03,
  23         SiS900_REVISION_SiS630A         = 0x80,
  24         SiS900_REVISION_SiS630E         = 0x81,
  25         SiS900_REVISION_SiS630S         = 0x82,
  26         SiS900_REVISION_SiS630EA1       = 0x83,
  27         SiS900_REVISION_SiS630ET        = 0x84,
  28         SiS900_REVISION_SiS635A         = 0x90,
  29         SiS900_REVISION_SiS96x          = 0x91,
  30 };
  31
  32 #define DEVICE_NAME "sis900"
  33 #define DEVICE_DRIVERNAME "net/" DEVICE_NAME
  34
  35
  36 /***************************** Buffer & Buffer Descriptors *****************************/
  37
  38 struct buffer_desc {
  39         uint32  link;
  40         uint32  status;
  41         uint32  buffer;
  42 };
  43
  44 enum SiS900_buffer_desc_bits {
  45         SiS900_DESCR_OWN                        = 0x80000000,
  46         SiS900_DESCR_MORE                       = 0x40000000,
  47         SiS900_DESCR_INTR                       = 0x20000000,
  48         SiS900_DESCR_SUPPRESS_CRC       = 0x10000000,
  49         SiS900_DESCR_OK                         = 0x08000000,
  50
  51         SiS900_DESCR_Tx_ABORT           = 0x04000000,
  52         SiS900_DESCR_Tx_UNDERRUN        = 0x02000000,
  53         SiS900_DESCR_Tx_CRS                     = 0x01000000,
  54         SiS900_DESCR_Tx_DEFERRED        = 0x00800000,
  55         SiS900_DESCR_Tx_EXC_DEFERRED    = 0x00400000,
  56         SiS900_DESCR_Tx_OOW_COLLISION   = 0x00200000,
  57         SiS900_DESCR_Tx_EXC_COLLISIONS  = 0x00100000,
  58
  59         SiS900_DESCR_Rx_ABORT           = 0x04000000,
  60         SiS900_DESCR_Rx_OVERRUN         = 0x02000000,
  61         SiS900_DESCR_Rx_DESTCLASS0      = 0x01000000,
  62         SiS900_DESCR_Rx_DESTCLASS1      = 0x00800000,
  63         SiS900_DESCR_Rx_LONG_PACKET     = 0x00400000,
  64         SiS900_DESCR_Rx_RUNT_PACKET     = 0x00200000,
  65         SiS900_DESCR_Rx_INVALID_SYM     = 0x00100000,
  66         SiS900_DESCR_Rx_CRC_ERROR       = 0x00080000,
  67         SiS900_DESCR_Rx_FRAME_ALIGN     = 0x00040000,
  68         SiS900_DESCR_Rx_LOOPBACK        = 0x00020000,
  69         SiS900_DESCR_Rx_COLLISION       = 0x00010000,
  70 };
  71
  72 #define SiS900_DESCR_SIZE_MASK 0x0fff
  73
  74 #define NUM_Rx_DESCR 32
  75 #define NUM_Tx_DESCR 16
  76
  77 #define NUM_Rx_MASK (NUM_Rx_DESCR - 1)
  78 #define NUM_Tx_MASK (NUM_Tx_DESCR - 1)
  79
  80
  81 #define MAX_FRAME_SIZE  1514
  82 #define BUFFER_SIZE     2048
  83 #define CRC_SIZE 4
  84
  85
  86 /***************************** Private Device Data *****************************/
  87
  88 struct sis_info {
  89         timer                   timer;
  90         uint32                  cookieMagic;
  91         area_id                 thisArea;
  92         uint32                  id;
  93         spinlock                lock;
  94         pci_info                *pciInfo;
  95         volatile addr_t registers;
  96         ether_address_t address;
  97         volatile int32  blockFlag;
  98
  99         struct mii_phy  *firstPHY;
 100         struct mii_phy  *currentPHY;
 101         uint16                  phy;
 102         bool                    autoNegotiationComplete;
 103         bool                    link;
 104         bool                    full_duplex;
 105         uint16                  speed;
 106         uint16                  fixedMode;
 107
 108         // receive data
 109         volatile struct buffer_desc rxDescriptor[NUM_Rx_DESCR];
 110         volatile char   *rxBuffer[NUM_Rx_DESCR];
 111         area_id                 rxArea;
 112         sem_id                  rxSem;
 113         spinlock                rxSpinlock;
 114         int32                   rxLock;
 115         int16                   rxCurrent;
 116         int16                   rxInterruptIndex;
 117         int16                   rxFree;
 118
 119         // transmit data
 120         volatile struct buffer_desc txDescriptor[NUM_Tx_DESCR];
 121         volatile char   *txBuffer[NUM_Tx_DESCR];
 122         area_id                 txArea;
 123         sem_id                  txSem;
 124         spinlock                txSpinlock;
 125         int32                   txLock;
 126         int16                   txCurrent;
 127         int16                   txInterruptIndex;
 128         int16                   txSent;
 129 };
 130
 131 #define SiS_COOKIE_MAGIC 's900'
 132 #define SiS_FREE_COOKIE_MAGIC 's9fr'
 133
 134 enum link_modes {
 135         LINK_HALF_DUPLEX        = 0x0100,
 136         LINK_FULL_DUPLEX        = 0x0200,
 137         LINK_DUPLEX_MASK        = 0xff00,
 138
 139         LINK_SPEED_HOME         = 1,
 140         LINK_SPEED_10_MBIT      = 10,
 141         LINK_SPEED_100_MBIT     = 100,
 142         LINK_SPEED_DEFAULT      = LINK_SPEED_100_MBIT,
 143         LINK_SPEED_MASK         = 0x00ff
 144 };
 145
 146 /***************************** Media Access Control *****************************/
 147
 148 enum SiS900_MAC_registers {
 149         SiS900_MAC_COMMAND                      = 0x00,
 150         SiS900_MAC_CONFIG                       = 0x04,
 151         SiS900_MAC_EEPROM_ACCESS        = 0x08,
 152         SiS900_MAC_PCI_TEST                     = 0x0c,
 153         SiS900_MAC_INTR_STATUS          = 0x10,
 154         SiS900_MAC_INTR_MASK            = 0x14,
 155         SiS900_MAC_INTR_ENABLE          = 0x18,
 156         SiS900_MAC_PHY_ACCESS           = 0x1c,
 157         SiS900_MAC_Tx_DESCR                     = 0x20,
 158         SiS900_MAC_Tx_CONFIG            = 0x24,
 159         /* reserved 0x28 - 0x2c */
 160         SiS900_MAC_Rx_DESCR                     = 0x30,
 161         SiS900_MAC_Rx_CONFIG            = 0x34,
 162         SiS900_MAC_FLOW_CONTROL         = 0x38,
 163         /* reserved 0x3c - 0x44 */
 164         SiS900_MAC_Rx_FILTER_CONTROL    = 0x48,
 165         SiS900_MAC_Rx_FILTER_DATA       = 0x4c,
 166         /* reserved 0x50 - 0xac */
 167         SiS900_MAC_WAKEUP_CONTROL       = 0xb0,
 168         SiS900_MAC_WAKEUP_EVENT         = 0xb4
 169         /* reserved, wake-up registers */
 170 };
 171
 172 enum SiS900_MAC_commands {
 173         SiS900_MAC_CMD_RESET            = 0x0100,
 174         SiS900_MAC_CMD_Rx_RESET         = 0x0020,
 175         SiS900_MAC_CMD_Tx_RESET         = 0x0010,
 176         SiS900_MAC_CMD_Rx_DISABLE       = 0x0008,
 177         SiS900_MAC_CMD_Rx_ENABLE        = 0x0004,
 178         SiS900_MAC_CMD_Tx_DISABLE       = 0x0002,
 179         SiS900_MAC_CMD_Tx_ENABLE        = 0x0001
 180 };
 181
 182 enum SiS900_MAC_configuration_bits {
 183         SiS900_MAC_CONFIG_BIG_ENDIAN                    = 0x00000001,
 184         SiS900_MAC_CONFIG_EXCESSIVE_DEFERRAL    = 0x00000010,
 185         SiS900_MAC_CONFIG_EDB_MASTER                    = 0x00002000,
 186 };
 187
 188 enum SiS900_MAC_rxfilter {
 189         SiS900_RxF_ENABLE                               = 0x80000000,
 190         SiS900_RxF_ACCEPT_ALL_BROADCAST = 0x40000000,
 191         SiS900_RxF_ACCEPT_ALL_MULTICAST = 0x20000000,
 192         SiS900_RxF_ACCEPT_ALL_ADDRESSES = 0x10000000
 193 };
 194
 195 #define SiS900_Rx_FILTER_ADDRESS_SHIFT 16
 196
 197 enum SiS900_MAC_txconfig {
 198         SiS900_Tx_CS_IGNORE             = 0x80000000,
 199         SiS900_Tx_HB_IGNORE             = 0x40000000,
 200         SiS900_Tx_MAC_LOOPBACK  = 0x20000000,
 201         SiS900_Tx_AUTO_PADDING  = 0x10000000
 202 };
 203
 204 #define SiS900_DMA_SHIFT        20
 205 #define SiS900_Tx_FILL_THRES                    (16 << 8)       /* 1/4 of FIFO */
 206 #define SiS900_Tx_100_MBIT_DRAIN_THRES  48                      /* 3/4 */
 207 #define SiS900_Tx_10_MBIT_DRAIN_THRES   16      //      32      /* 1/2 */
 208
 209 enum SiS900_MAC_rxconfig {
 210         SiS900_Rx_ACCEPT_ERROR_PACKETS  = 0x80000000,
 211         SiS900_Rx_ACCEPT_RUNT_PACKETS   = 0x40000000,
 212         SiS900_Rx_ACCEPT_Tx_PACKETS             = 0x10000000,
 213         SiS900_Rx_ACCEPT_JABBER_PACKETS = 0x08000000
 214 };
 215
 216 #define SiS900_Rx_100_MBIT_DRAIN_THRES  32                      /* 1/2 of FIFO */
 217 #define SiS900_Rx_10_MBIT_DRAIN_THRES   48                      /* 3/4 */
 218
 219 enum SiS900_MAC_wakeup {
 220         SiS900_WAKEUP_LINK_ON   = 0x02,
 221         SiS900_WAKEUP_LINK_LOSS = 0x01
 222 };
 223
 224 enum SiS900_MAC_interrupts {
 225         SiS900_INTR_WAKEUP_EVENT                = 0x10000000,
 226         SiS900_INTR_Tx_RESET_COMPLETE   = 0x02000000,
 227         SiS900_INTR_Rx_RESET_COMPLETE   = 0x01000000,
 228         SiS900_INTR_Rx_STATUS_OVERRUN   = 0x00010000,
 229         SiS900_INTR_Tx_UNDERRUN                 = 0x00000400,
 230         SiS900_INTR_Tx_IDLE                             = 0x00000200,
 231         SiS900_INTR_Tx_ERROR                    = 0x00000100,
 232         SiS900_INTR_Tx_DESCRIPTION              = 0x00000080,
 233         SiS900_INTR_Tx_OK                               = 0x00000040,
 234         SiS900_INTR_Rx_OVERRUN                  = 0x00000020,
 235         SiS900_INTR_Rx_IDLE                             = 0x00000010,
 236         SiS900_INTR_Rx_EARLY_THRESHOLD  = 0x00000008,
 237         SiS900_INTR_Rx_ERROR                    = 0x00000004,
 238         SiS900_INTR_Rx_DESCRIPTION              = 0x00000002,
 239         SiS900_INTR_Rx_OK                               = 0x00000001
 240 };
 241
 242 /***************************** EEPROM *****************************/
 243
 244 enum SiS900_EEPROM_bits {
 245         SiS900_EEPROM_SELECT    = 0x08,
 246         SiS900_EEPROM_CLOCK             = 0x04,
 247         SiS900_EEPROM_DATA_OUT  = 0x02,
 248         SiS900_EEPROM_DATA_IN   = 0x01
 249 };
 250
 251 // the EEPROM definitions are taken from linux' sis900 driver header
 252 enum SiS900_EEPROM_address {
 253         SiS900_EEPROM_SIGNATURE         = 0x00,
 254         SiS900_EEPROM_VENDOR_ID         = 0x02,
 255         SiS900_EEPROM_DEVICE_ID         = 0x03,
 256         SiS900_EEPROM_MAC_ADDRESS       = 0x08,
 257         SiS900_EEPROM_CHECKSUM          = 0x0b
 258 };
 259
 260 enum SiS900_EEPROM_commands {
 261         SiS900_EEPROM_CMD_READ = 0x0180
 262 };
 263
 264 enum SiS96x_EEPROM_command {
 265         SiS96x_EEPROM_CMD_REQ   = 0x00000400,
 266         SiS96x_EEPROM_CMD_DONE  = 0x00000200,
 267         SiS96x_EEPROM_CMD_GRANT = 0x00000100
 268 };
 269
 270 /***************************** Media Independent Interface *****************************/
 271
 272 struct mii_phy {
 273         struct mii_phy *next;
 274         uint16  id0,id1;
 275         uint16  address;
 276         uint8   types;
 277 };
 278
 279 enum SiS900_MII_bits {
 280 //      SiS900_MII_WRITE        = 0x00,
 281 //      SiS900_MII_READ         = 0x20,
 282 //      SiS900_MII_ACCESS       = 0x10
 283         SiS900_MII_MDC          = 0x40,
 284         SiS900_MII_MDDIR        = 0x20,
 285         SiS900_MII_MDIO         = 0x10,
 286 };
 287
 288 enum SiS900_MII_address {
 289         // standard registers
 290         MII_CONTROL             = 0x00,
 291         MII_STATUS              = 0x01,
 292         MII_PHY_ID0             = 0x02,
 293         MII_PHY_ID1             = 0x03,
 294         MII_AUTONEG_ADV                         = 0x04,
 295         MII_AUTONEG_LINK_PARTNER        = 0x05,
 296         MII_AUTONEG_EXT                         = 0x06,
 297
 298         // SiS900 specific registers
 299         MII_CONFIG1             = 0x10,
 300         MII_CONFIG2             = 0x11,
 301         MII_LINK_STATUS = 0x12,
 302         MII_MASK                = 0x13,
 303         MII_RESERVED    = 0x14
 304 };
 305
 306 enum MII_control {
 307         MII_CONTROL_RESET                       = 0x8000,
 308         MII_CONTROL_RESET_AUTONEG       = 0x0200,
 309         MII_CONTROL_AUTO                        = 0x1000,
 310         MII_CONTROL_FULL_DUPLEX         = 0x0100,
 311         MII_CONTROL_ISOLATE                     = 0x0400
 312 };
 313
 314 enum SiS900_MII_commands {
 315         MII_CMD_READ            = 0x6000,
 316         MII_CMD_WRITE           = 0x5002,
 317
 318         MII_PHY_SHIFT           = 7,
 319         MII_REG_SHIFT           = 2,
 320 };
 321
 322 enum MII_status_bits {
 323         MII_STATUS_EXT                  = 0x0001,
 324         MII_STATUS_JAB                  = 0x0002,
 325         MII_STATUS_LINK                 = 0x0004,
 326         MII_STATUS_CAN_AUTO             = 0x0008,
 327         MII_STATUS_FAULT                = 0x0010,
 328         MII_STATUS_AUTO_DONE    = 0x0020,
 329         MII_STATUS_CAN_T                = 0x0800,
 330         MII_STATUS_CAN_T_FDX    = 0x1000,
 331         MII_STATUS_CAN_TX               = 0x2000,
 332         MII_STATUS_CAN_TX_FDX   = 0x4000,
 333         MII_STATUS_CAN_T4               = 0x8000
 334 };
 335
 336 enum MII_auto_negotiation {
 337         // taken from the linux sis900.h header file
 338         MII_NWAY_NODE_SEL       = 0x001f,
 339         MII_NWAY_CSMA_CD        = 0x0001,
 340         MII_NWAY_T                      = 0x0020,
 341         MII_NWAY_T_FDX          = 0x0040,
 342         MII_NWAY_TX                     = 0x0080,
 343         MII_NWAY_TX_FDX         = 0x0100,
 344         MII_NWAY_T4                     = 0x0200,
 345         MII_NWAY_PAUSE          = 0x0400,
 346         MII_NWAY_RF                     = 0x2000,
 347         MII_NWAY_ACK            = 0x4000,
 348         MII_NWAY_NP                     = 0x8000
 349 };
 350
 351
 352 enum SiS900_MII_link_status {
 353         MII_LINK_FAIL                   = 0x4000,
 354         MII_LINK_100_MBIT               = 0x0080,
 355         MII_LINK_FULL_DUPLEX    = 0x0040
 356 };
 357
 358 #define SiS900_MII_REGISTER_SHIFT       6
 359 #define SiS900_MII_DATA_SHIFT           16
 360
 361
 362 /***************************** Misc. & Prototypes *****************************/
 363
 364 #define HACK(x) ;
 365
 366 #ifdef EXCESSIVE_DEBUG
 367 #       define TRACE(x) dprintf x
 368         extern int bug(const char *, ...);
 369 #elif defined(DEBUG)
 370 #       define TRACE(x) dprintf x
 371 #else
 372 #       define TRACE(x) ;
 373 #endif
 374
 375 #define ROUND_TO_PAGE_SIZE(x) (((x) + (B_PAGE_SIZE) - 1) & ~((B_PAGE_SIZE) - 1))
 376
 377 // chip specific network functions
 378 extern int32 sis900_interrupt(void *data);
 379 extern void     sis900_disableInterrupts(struct sis_info *info);
 380 extern void     sis900_enableInterrupts(struct sis_info *info);
 381
 382 extern int32 sis900_timer(timer *t);
 383 extern status_t sis900_initPHYs(struct sis_info *info);
 384 extern void sis900_checkMode(struct sis_info *info);
 385 extern bool sis900_getMACAddress(struct sis_info *info);
 386 extern status_t sis900_reset(struct sis_info *info);
 387
 388 extern void sis900_setPromiscuous(struct sis_info *info, bool on);
 389 extern void sis900_setRxFilter(struct sis_info *info);
 390
 391 extern void sis900_deleteRings(struct sis_info *info);
 392 extern status_t sis900_createRings(struct sis_info *info);
 393
 394
 395 #endif /* SIS900_H */