src/add-ons/kernel/drivers/network/vlance/vlance.h

   1 /*
   2  * Copyright 2006, Hideyuki Abe. All rights reserved.
   3  * Distributed under the terms of the MIT License.
   4  */
   5 #ifndef VLANCE_H
   6 #define VLANCE_H
   7
   8
   9 #include <SupportDefs.h>
  10
  11
  12 /* PCnet/PCI definitions */
  13
  14 /* I/O mapping */
  15 #define PCNET_APROM_OFFSET      (0x00UL)
  16 #define PCNET_RDP_OFFSET        (0x10UL)
  17 #define PCNET_RAP_OFFSET        (0x14UL)
  18 #define PCNET_RST_OFFSET        (0x18UL)
  19 #define PCNET_BDP_OFFSET        (0x1cUL)
  20
  21 /* CSR register numbers */
  22 #define PCNET_CSR_STATUS        (  0)
  23 #define PCNET_CSR_IADDR0        (  1)
  24 #define PCNET_CSR_IADDR1        (  2)
  25 #define PCNET_CSR_IMSK          (  3)
  26 #define PCNET_CSR_FTR           (  4)
  27 #define PCNET_CSR_EXTCNT        (  5)
  28 #define PCNET_CSR_LADRF0        (  8)
  29 #define PCNET_CSR_LADRF1        (  9)
  30 #define PCNET_CSR_LADRF2        ( 10)
  31 #define PCNET_CSR_LADRF3        ( 11)
  32 #define PCNET_CSR_PADR0         ( 12)
  33 #define PCNET_CSR_PADR1         ( 13)
  34 #define PCNET_CSR_PADR2         ( 14)
  35 #define PCNET_CSR_MODE          ( 15)
  36 #define PCNET_CSR_BADRL         ( 24)
  37 #define PCNET_CSR_BADRH         ( 25)
  38 #define PCNET_CSR_BADXL         ( 30)
  39 #define PCNET_CSR_BADXH         ( 31)
  40 #define PCNET_CSR_POLLINT       ( 47)
  41 #define PCNET_CSR_RCVRL         ( 76)
  42 #define PCNET_CSR_XMTRL         ( 78)
  43 #define PCNET_CSR_DMABAT        ( 82)
  44 #define PCNET_CSR_MERRTO        (100)
  45 #define PCNET_CSR_MFC           (112)
  46 #define PCNET_CSR_RCC           (114)
  47 #define PCNET_CSR_RCVALGN       (122)
  48
  49 /* BCR register numbers */
  50 #define PCNET_BCR_MC            (  2)
  51 #define PCNET_BCR_LNKST         (  4)
  52 #define PCNET_BCR_LED1          (  5)
  53 #define PCNET_BCR_LED2          (  6)
  54 #define PCNET_BCR_LED3          (  7)
  55 #define PCNET_BCR_FDC           (  9)
  56 #define PCNET_BCR_BSBC          ( 18)
  57 #define PCNET_BCR_SWS           ( 20)
  58
  59 /* Receive Descriptor (Little-Endian ordering) */
  60 typedef union recv_desc {
  61         uint32 rmd[4];
  62         struct {
  63                 uint32 rbadr;
  64                 int16 bcnt;
  65                 uint16 status;
  66                 uint32 mcnt;
  67                 uint32 rsvd;
  68         } s;
  69 } recv_desc_t;
  70
  71 /* Transmit Descriptor (Little-Endian ordering) */
  72 typedef union trns_desc {
  73         uint32 tmd[4];
  74         struct {
  75                 uint32 tbadr;
  76                 int16 bcnt;
  77                 uint16 status;
  78                 uint32 misc;
  79                 uint32 rsvd;
  80         } s;
  81 } trns_desc_t;
  82
  83 /* Initialization Block (Little-Endian ordering) */
  84 typedef union init_block {
  85         uint32 iblk[7];
  86         struct {
  87                 uint32 mode;
  88                 uint8 padr[8];
  89                 uint32 ladr[2];
  90                 uint32 rdra;
  91                 uint32 tdra;
  92         } s;
  93 } init_block_t;
  94
  95 #endif  /* VLANCE_H */