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btrfs: [] on the end of a struct field is a variable length array.
[haiku.git] / headers / private / graphics / intel_extreme / intel_extreme.h
blob1c79b5752775eb559166e13d6b3871700e390552
1 /*
2 * Copyright 2006-2016, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 * Axel Dörfler, axeld@pinc-software.de
7 * Alexander von Gluck, kallisti5@unixzen.com
8 */
9 #ifndef INTEL_EXTREME_H
10 #define INTEL_EXTREME_H
11
12
13 #include "lock.h"
14
15 #include <Accelerant.h>
16 #include <Drivers.h>
17 #include <PCI.h>
18
19 #include <edid.h>
20
21
22 #define VENDOR_ID_INTEL 0x8086
23
24 #define INTEL_FAMILY_MASK 0x00ff0000
25 #define INTEL_GROUP_MASK 0x00fffff0
26 #define INTEL_MODEL_MASK 0x00ffffff
27 #define INTEL_TYPE_MASK 0x0000000f
28 // families
29 #define INTEL_FAMILY_7xx 0x00010000 // First Gen
30 #define INTEL_FAMILY_8xx 0x00020000 // Second Gen
31 #define INTEL_FAMILY_9xx 0x00040000 // Third Gen +
32 #define INTEL_FAMILY_SER5 0x00080000 // Intel5 Series
33 #define INTEL_FAMILY_POVR 0x00100000 // PowerVR (uugh)
34 #define INTEL_FAMILY_SOC0 0x00200000 // Atom SOC
35 #define INTEL_FAMILY_LAKE 0x00400000 // Intel Lakes
36 // groups
37 #define INTEL_GROUP_83x (INTEL_FAMILY_8xx | 0x0010)
38 #define INTEL_GROUP_85x (INTEL_FAMILY_8xx | 0x0020)
39 #define INTEL_GROUP_91x (INTEL_FAMILY_9xx | 0x0010)
40 #define INTEL_GROUP_94x (INTEL_FAMILY_9xx | 0x0020)
41 #define INTEL_GROUP_96x (INTEL_FAMILY_9xx | 0x0040)
42 #define INTEL_GROUP_Gxx (INTEL_FAMILY_9xx | 0x0080)
43 #define INTEL_GROUP_G4x (INTEL_FAMILY_9xx | 0x0100)
44 #define INTEL_GROUP_PIN (INTEL_FAMILY_9xx | 0x0200) // PineView
45 #define INTEL_GROUP_ILK (INTEL_FAMILY_SER5 | 0x0010) // IronLake
46 #define INTEL_GROUP_SNB (INTEL_FAMILY_SER5 | 0x0020) // SandyBridge
47 #define INTEL_GROUP_IVB (INTEL_FAMILY_SER5 | 0x0040) // IvyBridge
48 #define INTEL_GROUP_HAS (INTEL_FAMILY_SER5 | 0x0080) // Haswell
49 #define INTEL_GROUP_SLT (INTEL_FAMILY_POVR | 0x0010) // Saltwell
50 #define INTEL_GROUP_FSM (INTEL_FAMILY_POVR | 0x0020) // Fu.Silvermont
51 #define INTEL_GROUP_VLV (INTEL_FAMILY_SOC0 | 0x0010) // ValleyView
52 #define INTEL_GROUP_CHV (INTEL_FAMILY_SOC0 | 0x0020) // CherryView
53 #define INTEL_GROUP_BDW (INTEL_FAMILY_SOC0 | 0x0040) // Broadwell
54 #define INTEL_GROUP_SKY (INTEL_FAMILY_LAKE | 0x0010) // SkyLake
55 #define INTEL_GROUP_KBY (INTEL_FAMILY_LAKE | 0x0020) // KabyLake
56 // models
57 #define INTEL_TYPE_SERVER 0x0004
58 #define INTEL_TYPE_MOBILE 0x0008
59 #define INTEL_MODEL_915 (INTEL_GROUP_91x)
60 #define INTEL_MODEL_915M (INTEL_GROUP_91x | INTEL_TYPE_MOBILE)
61 #define INTEL_MODEL_945 (INTEL_GROUP_94x)
62 #define INTEL_MODEL_945M (INTEL_GROUP_94x | INTEL_TYPE_MOBILE)
63 #define INTEL_MODEL_965 (INTEL_GROUP_96x)
64 #define INTEL_MODEL_965M (INTEL_GROUP_96x | INTEL_TYPE_MOBILE)
65 #define INTEL_MODEL_G33 (INTEL_GROUP_Gxx)
66 #define INTEL_MODEL_G45 (INTEL_GROUP_G4x)
67 #define INTEL_MODEL_GM45 (INTEL_GROUP_G4x | INTEL_TYPE_MOBILE)
68 #define INTEL_MODEL_PINE (INTEL_GROUP_PIN)
69 #define INTEL_MODEL_PINEM (INTEL_GROUP_PIN | INTEL_TYPE_MOBILE)
70 #define INTEL_MODEL_ILKG (INTEL_GROUP_ILK)
71 #define INTEL_MODEL_ILKGM (INTEL_GROUP_ILK | INTEL_TYPE_MOBILE)
72 #define INTEL_MODEL_SNBG (INTEL_GROUP_SNB)
73 #define INTEL_MODEL_SNBGM (INTEL_GROUP_SNB | INTEL_TYPE_MOBILE)
74 #define INTEL_MODEL_SNBGS (INTEL_GROUP_SNB | INTEL_TYPE_SERVER)
75 #define INTEL_MODEL_IVBG (INTEL_GROUP_IVB)
76 #define INTEL_MODEL_IVBGM (INTEL_GROUP_IVB | INTEL_TYPE_MOBILE)
77 #define INTEL_MODEL_IVBGS (INTEL_GROUP_IVB | INTEL_TYPE_SERVER)
78 #define INTEL_MODEL_HAS (INTEL_GROUP_HAS)
79 #define INTEL_MODEL_HASM (INTEL_GROUP_HAS | INTEL_TYPE_MOBILE)
80 #define INTEL_MODEL_VLV (INTEL_GROUP_VLV)
81 #define INTEL_MODEL_VLVM (INTEL_GROUP_VLV | INTEL_TYPE_MOBILE)
82 #define INTEL_MODEL_BDW (INTEL_GROUP_BDW)
83 #define INTEL_MODEL_BDWM (INTEL_GROUP_BDW | INTEL_TYPE_MOBILE)
84 #define INTEL_MODEL_SKY (INTEL_GROUP_SKY)
85 #define INTEL_MODEL_SKYM (INTEL_GROUP_SKY | INTEL_TYPE_MOBILE)
86 #define INTEL_MODEL_SKYS (INTEL_GROUP_SKY | INTEL_TYPE_SERVER)
87
88 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
89 #define INTEL_PCH_IBX_DEVICE_ID 0x3b00
90 #define INTEL_PCH_CPT_DEVICE_ID 0x1c00
91 #define INTEL_PCH_PPT_DEVICE_ID 0x1e00
92 #define INTEL_PCH_LPT_DEVICE_ID 0x8c00
93 #define INTEL_PCH_LPT_LP_DEVICE_ID 0x9c00 /* Wildcat Point */
94 #define INTEL_PCH_SPT_DEVICE_ID 0xa100
95 #define INTEL_PCH_SPT_LP_DEVICE_ID 0x9d00
96 #define INTEL_PCH_P2X_DEVICE_ID 0x7100
97 #define INTEL_PCH_P3X_DEVICE_ID 0x7000
98
99 // ValleyView MMIO offset
100 #define VLV_DISPLAY_BASE 0x180000
101
102 #define DEVICE_NAME "intel_extreme"
103 #define INTEL_ACCELERANT_NAME "intel_extreme.accelerant"
104
105 // We encode the register block into the value and extract/translate it when
106 // actually accessing.
107 #define REGISTER_BLOCK_COUNT 6
108 #define REGISTER_BLOCK_SHIFT 24
109 #define REGISTER_BLOCK_MASK 0xff000000
110 #define REGISTER_REGISTER_MASK 0x00ffffff
111 #define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT)
112 #define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK)
113
114 #define REGS_FLAT (0 << REGISTER_BLOCK_SHIFT)
115 #define REGS_NORTH_SHARED (1 << REGISTER_BLOCK_SHIFT)
116 #define REGS_NORTH_PIPE_AND_PORT (2 << REGISTER_BLOCK_SHIFT)
117 #define REGS_NORTH_PLANE_CONTROL (3 << REGISTER_BLOCK_SHIFT)
118 #define REGS_SOUTH_SHARED (4 << REGISTER_BLOCK_SHIFT)
119 #define REGS_SOUTH_TRANSCODER_PORT (5 << REGISTER_BLOCK_SHIFT)
120
121 // register blocks for (G)MCH/ICH based platforms
122 #define MCH_SHARED_REGISTER_BASE 0x00000
123 #define MCH_PIPE_AND_PORT_REGISTER_BASE 0x60000
124 #define MCH_PLANE_CONTROL_REGISTER_BASE 0x70000
125
126 #define ICH_SHARED_REGISTER_BASE 0x00000
127 #define ICH_PORT_REGISTER_BASE 0x60000
128
129 // PCH - Platform Control Hub - Some hardware moves from a MCH/ICH based
130 // setup to a PCH based one, that means anything that used to communicate via
131 // (G)MCH registers needs to use different ones on PCH based platforms
132 // (Ironlake, SandyBridge, IvyBridge, Some Haswell).
133 #define PCH_NORTH_SHARED_REGISTER_BASE 0x40000
134 #define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE 0x60000
135 #define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE 0x70000
136 #define PCH_SOUTH_SHARED_REGISTER_BASE 0xc0000
137 #define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE 0xe0000
138
139
140 struct DeviceType {
141 uint32 type;
142
143 DeviceType(int t)
144 {
145 type = t;
146 }
147
148 DeviceType& operator=(int t)
149 {
150 type = t;
151 return *this;
152 }
153
154 bool InFamily(uint32 family) const
155 {
156 return (type & INTEL_FAMILY_MASK) == family;
157 }
158
159 bool InGroup(uint32 group) const
160 {
161 return (type & INTEL_GROUP_MASK) == group;
162 }
163
164 bool IsModel(uint32 model) const
165 {
166 return (type & INTEL_MODEL_MASK) == model;
167 }
168
169 bool IsMobile() const
170 {
171 return (type & INTEL_TYPE_MASK) == INTEL_TYPE_MOBILE;
172 }
173
174 bool SupportsHDMI() const
175 {
176 return InGroup(INTEL_GROUP_G4x) || InFamily(INTEL_FAMILY_SER5)
177 || InFamily(INTEL_FAMILY_SOC0);
178 }
179
180 bool HasDDI() const
181 {
182 // Intel Digital Display Interface
183 return InGroup(INTEL_GROUP_HAS) || (Generation() >= 8);
184 }
185
186 int Generation() const
187 {
188 if (InFamily(INTEL_FAMILY_7xx))
189 return 1;
190 if (InFamily(INTEL_FAMILY_8xx))
191 return 2;
192 if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x)
193 || IsModel(INTEL_MODEL_G33) || InGroup(INTEL_GROUP_PIN))
194 return 3;
195 if (InFamily(INTEL_FAMILY_9xx))
196 return 4;
197 if (InGroup(INTEL_GROUP_ILK))
198 return 5;
199 if (InGroup(INTEL_GROUP_SNB))
200 return 6;
201 if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_VLV))
202 return 7;
203 if (InGroup(INTEL_GROUP_CHV) || InGroup(INTEL_GROUP_BDW))
204 return 8;
205 if (InFamily(INTEL_FAMILY_LAKE))
206 return 9;
207
208 // Generation 0 means somethins is wrong :-)
209 return 0;
210 }
211 };
212
213 enum pch_info {
214 INTEL_PCH_NONE = 0, // No PCH present
215 INTEL_PCH_IBX, // Ibexpeak
216 INTEL_PCH_CPT, // Cougarpoint
217 INTEL_PCH_LPT, // Lynxpoint
218 INTEL_PCH_SPT, // Sunrisepoint
219 INTEL_PCH_NOP
220 };
221
222 // info about PLL on graphics card
223 struct pll_info {
224 uint32 reference_frequency;
225 uint32 max_frequency;
226 uint32 min_frequency;
227 uint32 divisor_register;
228 };
229
230 struct ring_buffer {
231 struct lock lock;
232 uint32 register_base;
233 uint32 offset;
234 uint32 size;
235 uint32 position;
236 uint32 space_left;
237 uint8* base;
238 };
239
240 struct overlay_registers;
241
242 struct intel_shared_info {
243 area_id mode_list_area; // area containing display mode list
244 uint32 mode_count;
245
246 display_mode panel_mode; // VBIOS VBT panel mode
247 uint32 bytes_per_row;
248 uint32 bits_per_pixel;
249 uint32 dpms_mode;
250
251 area_id registers_area; // area of memory mapped registers
252 uint32 register_blocks[REGISTER_BLOCK_COUNT];
253
254 uint8* status_page;
255 phys_addr_t physical_status_page;
256 uint8* graphics_memory;
257 phys_addr_t physical_graphics_memory;
258 uint32 graphics_memory_size;
259
260 addr_t frame_buffer;
261 uint32 frame_buffer_offset;
262
263 uint32 fdi_link_frequency; // In Mhz
264
265 bool got_vbt;
266 bool single_head_locked;
267
268 struct lock accelerant_lock;
269 struct lock engine_lock;
270
271 ring_buffer primary_ring_buffer;
272
273 int32 overlay_channel_used;
274 bool overlay_active;
275 uintptr_t overlay_token;
276 phys_addr_t physical_overlay_registers;
277 uint32 overlay_offset;
278
279 bool hardware_cursor_enabled;
280 sem_id vblank_sem;
281
282 uint8* cursor_memory;
283 phys_addr_t physical_cursor_memory;
284 uint32 cursor_buffer_offset;
285 uint32 cursor_format;
286 bool cursor_visible;
287 uint16 cursor_hot_x;
288 uint16 cursor_hot_y;
289
290 DeviceType device_type;
291 char device_identifier[32];
292 struct pll_info pll_info;
293
294 enum pch_info pch_info;
295
296 edid1_info vesa_edid_info;
297 bool has_vesa_edid_info;
298 };
299
300 enum pipe_index {
301 INTEL_PIPE_ANY,
302 INTEL_PIPE_A,
303 INTEL_PIPE_B
304 };
305
306 //----------------- ioctl() interface ----------------
307
308 // magic code for ioctls
309 #define INTEL_PRIVATE_DATA_MAGIC 'itic'
310
311 // list ioctls
312 enum {
313 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
314
315 INTEL_GET_DEVICE_NAME,
316 INTEL_ALLOCATE_GRAPHICS_MEMORY,
317 INTEL_FREE_GRAPHICS_MEMORY
318 };
319
320 // retrieve the area_id of the kernel/accelerant shared info
321 struct intel_get_private_data {
322 uint32 magic; // magic number
323 area_id shared_info_area;
324 };
325
326 // allocate graphics memory
327 struct intel_allocate_graphics_memory {
328 uint32 magic;
329 uint32 size;
330 uint32 alignment;
331 uint32 flags;
332 addr_t buffer_base;
333 };
334
335 // free graphics memory
336 struct intel_free_graphics_memory {
337 uint32 magic;
338 addr_t buffer_base;
339 };
340
341 //----------------------------------------------------------
342 // Register definitions, taken from X driver
343
344 // PCI bridge memory management
345 #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // i830+
346
347 // GGC - (G)MCH Graphics Control Register
348 #define MEMORY_CONTROL_ENABLED 0x0004
349 #define MEMORY_MASK 0x0001
350 #define STOLEN_MEMORY_MASK 0x00f0
351 #define i965_GTT_MASK 0x000e
352 #define G33_GTT_MASK 0x0300
353 #define G4X_GTT_MASK 0x0f00 // GGMS (GSM Memory Size) mask
354
355 // models i830 and up
356 #define i830_LOCAL_MEMORY_ONLY 0x10
357 #define i830_STOLEN_512K 0x20
358 #define i830_STOLEN_1M 0x30
359 #define i830_STOLEN_8M 0x40
360 #define i830_FRAME_BUFFER_64M 0x01
361 #define i830_FRAME_BUFFER_128M 0x00
362
363 // models i855 and up
364 #define i855_STOLEN_MEMORY_1M 0x10
365 #define i855_STOLEN_MEMORY_4M 0x20
366 #define i855_STOLEN_MEMORY_8M 0x30
367 #define i855_STOLEN_MEMORY_16M 0x40
368 #define i855_STOLEN_MEMORY_32M 0x50
369 #define i855_STOLEN_MEMORY_48M 0x60
370 #define i855_STOLEN_MEMORY_64M 0x70
371 #define i855_STOLEN_MEMORY_128M 0x80
372 #define i855_STOLEN_MEMORY_256M 0x90
373
374 #define G4X_STOLEN_MEMORY_96MB 0xa0 // GMS - Graphics Mode Select
375 #define G4X_STOLEN_MEMORY_160MB 0xb0
376 #define G4X_STOLEN_MEMORY_224MB 0xc0
377 #define G4X_STOLEN_MEMORY_352MB 0xd0
378
379 // SandyBridge (SNB)
380
381 #define SNB_GRAPHICS_MEMORY_CONTROL 0x50
382
383 #define SNB_STOLEN_MEMORY_MASK 0xf8
384 #define SNB_STOLEN_MEMORY_32MB (1 << 3)
385 #define SNB_STOLEN_MEMORY_64MB (2 << 3)
386 #define SNB_STOLEN_MEMORY_96MB (3 << 3)
387 #define SNB_STOLEN_MEMORY_128MB (4 << 3)
388 #define SNB_STOLEN_MEMORY_160MB (5 << 3)
389 #define SNB_STOLEN_MEMORY_192MB (6 << 3)
390 #define SNB_STOLEN_MEMORY_224MB (7 << 3)
391 #define SNB_STOLEN_MEMORY_256MB (8 << 3)
392 #define SNB_STOLEN_MEMORY_288MB (9 << 3)
393 #define SNB_STOLEN_MEMORY_320MB (10 << 3)
394 #define SNB_STOLEN_MEMORY_352MB (11 << 3)
395 #define SNB_STOLEN_MEMORY_384MB (12 << 3)
396 #define SNB_STOLEN_MEMORY_416MB (13 << 3)
397 #define SNB_STOLEN_MEMORY_448MB (14 << 3)
398 #define SNB_STOLEN_MEMORY_480MB (15 << 3)
399 #define SNB_STOLEN_MEMORY_512MB (16 << 3)
400
401 #define SNB_GTT_SIZE_MASK (3 << 8)
402 #define SNB_GTT_SIZE_NONE (0 << 8)
403 #define SNB_GTT_SIZE_1MB (1 << 8)
404 #define SNB_GTT_SIZE_2MB (2 << 8)
405
406 // graphics page translation table
407 #define INTEL_PAGE_TABLE_CONTROL 0x02020
408 #define PAGE_TABLE_ENABLED 0x00000001
409 #define INTEL_PAGE_TABLE_ERROR 0x02024
410 #define INTEL_HARDWARE_STATUS_PAGE 0x02080
411 #define i915_GTT_BASE 0x1c
412 #define i830_GTT_BASE 0x10000 // (- 0x2ffff)
413 #define i830_GTT_SIZE 0x20000
414 #define i965_GTT_BASE 0x80000 // (- 0xfffff)
415 #define i965_GTT_SIZE 0x80000
416 #define i965_GTT_128K (2 << 1)
417 #define i965_GTT_256K (1 << 1)
418 #define i965_GTT_512K (0 << 1)
419 #define G33_GTT_1M (1 << 8)
420 #define G33_GTT_2M (2 << 8)
421 #define G4X_GTT_NONE 0x000 // GGMS - GSM Memory Size
422 #define G4X_GTT_1M_NO_IVT 0x100 // no Intel Virtualization Tech.
423 #define G4X_GTT_2M_NO_IVT 0x300
424 #define G4X_GTT_2M_IVT 0x900 // with Intel Virt. Tech.
425 #define G4X_GTT_3M_IVT 0xa00
426 #define G4X_GTT_4M_IVT 0xb00
427
428
429 #define GTT_ENTRY_VALID 0x01
430 #define GTT_ENTRY_LOCAL_MEMORY 0x02
431 #define GTT_PAGE_SHIFT 12
432
433
434 // ring buffer
435 #define INTEL_PRIMARY_RING_BUFFER 0x02030
436 #define INTEL_SECONDARY_RING_BUFFER_0 0x02100
437 #define INTEL_SECONDARY_RING_BUFFER_1 0x02110
438 // offsets for the ring buffer base registers above
439 #define RING_BUFFER_TAIL 0x0
440 #define RING_BUFFER_HEAD 0x4
441 #define RING_BUFFER_START 0x8
442 #define RING_BUFFER_CONTROL 0xc
443 #define INTEL_RING_BUFFER_SIZE_MASK 0x001ff000
444 #define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc
445 #define INTEL_RING_BUFFER_ENABLED 1
446
447 // interrupts
448 #define INTEL_INTERRUPT_ENABLED 0x020a0
449 #define INTEL_INTERRUPT_IDENTITY 0x020a4
450 #define INTEL_INTERRUPT_MASK 0x020a8
451 #define INTEL_INTERRUPT_STATUS 0x020ac
452 #define INTERRUPT_VBLANK_PIPEA (1 << 7)
453 #define INTERRUPT_VBLANK_PIPEB (1 << 5)
454
455 // PCH interrupts
456 #define PCH_INTERRUPT_STATUS 0x44000
457 #define PCH_INTERRUPT_MASK 0x44004
458 #define PCH_INTERRUPT_IDENTITY 0x44008
459 #define PCH_INTERRUPT_ENABLED 0x4400c
460
461 #define PCH_INTERRUPT_VBLANK_PIPEA (1 << 0)
462 #define PCH_INTERRUPT_VBLANK_PIPEB (1 << 5)
463 #define PCH_INTERRUPT_VBLANK_PIPEC (1 << 10)
464
465 // SandyBridge had only two pipes, and things were shuffled aroud again with
466 // the introduction of pipe C.
467 #define PCH_INTERRUPT_VBLANK_PIPEA_SNB (1 << 7)
468 #define PCH_INTERRUPT_VBLANK_PIPEB_SNB (1 << 15)
469 #define PCH_INTERRUPT_GLOBAL_SNB (1 << 31)
470
471 // graphics port control
472 #define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31)
473 #define DISPLAY_MONITOR_PIPE_B (1UL << 30)
474 #define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15)
475 #define DISPLAY_MONITOR_MODE_MASK (3UL << 10)
476 #define DISPLAY_MONITOR_ON 0
477 #define DISPLAY_MONITOR_SUSPEND (1UL << 10)
478 #define DISPLAY_MONITOR_STAND_BY (2UL << 10)
479 #define DISPLAY_MONITOR_OFF (3UL << 10)
480 #define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3)
481 #define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3)
482 #define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3)
483 #define DISPLAY_MONITOR_PORT_DETECTED (1UL << 2) // TMDS/DisplayPort only
484
485 #define LVDS_POST2_RATE_SLOW 14 // PLL Divisors
486 #define LVDS_POST2_RATE_FAST 7
487 #define LVDS_B0B3_POWER_MASK (3UL << 2)
488 #define LVDS_B0B3_POWER_UP (3UL << 2)
489 #define LVDS_CLKB_POWER_MASK (3UL << 4)
490 #define LVDS_CLKB_POWER_UP (3UL << 4)
491 #define LVDS_A3_POWER_MASK (3UL << 6)
492 #define LVDS_A3_POWER_UP (3UL << 6)
493 #define LVDS_A0A2_CLKA_POWER_UP (3UL << 8)
494 #define LVDS_BORDER_ENABLE (1UL << 15)
495 #define LVDS_HSYNC_POLARITY (1UL << 20)
496 #define LVDS_VSYNC_POLARITY (1UL << 21)
497 #define LVDS_18BIT_DITHER (1UL << 25)
498 #define LVDS_PORT_EN (1UL << 31)
499
500 // PLL flags
501 #define DISPLAY_PLL_ENABLED (1UL << 31)
502 #define DISPLAY_PLL_2X_CLOCK (1UL << 30)
503 #define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29)
504 #define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28)
505 #define DISPLAY_PLL_MODE_NORMAL (1UL << 26)
506 #define DISPLAY_PLL_MODE_LVDS (2UL << 26)
507 #define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24)
508 #define DISPLAY_PLL_DIVIDE_4X (1UL << 23)
509 #define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21)
510 #define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000
511 #define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000
512 #define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK 0x00ff8000
513 #define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16
514 #define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT 15
515 #define DISPLAY_PLL_DIVISOR_1 (1UL << 8)
516 #define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000
517 #define DISPLAY_PLL_IGD_N_DIVISOR_MASK 0x00ff0000
518 #define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00
519 #define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f
520 #define DISPLAY_PLL_IGD_M2_DIVISOR_MASK 0x000000ff
521 #define DISPLAY_PLL_N_DIVISOR_SHIFT 16
522 #define DISPLAY_PLL_M1_DIVISOR_SHIFT 8
523 #define DISPLAY_PLL_M2_DIVISOR_SHIFT 0
524 #define DISPLAY_PLL_PULSE_PHASE_SHIFT 9
525
526 // display
527
528 #define INTEL_DISPLAY_OFFSET 0x1000
529
530 #define INTEL_DISPLAY_A_HTOTAL (0x0000 | REGS_NORTH_PIPE_AND_PORT)
531 #define INTEL_DISPLAY_A_HBLANK (0x0004 | REGS_NORTH_PIPE_AND_PORT)
532 #define INTEL_DISPLAY_A_HSYNC (0x0008 | REGS_NORTH_PIPE_AND_PORT)
533 #define INTEL_DISPLAY_A_VTOTAL (0x000c | REGS_NORTH_PIPE_AND_PORT)
534 #define INTEL_DISPLAY_A_VBLANK (0x0010 | REGS_NORTH_PIPE_AND_PORT)
535 #define INTEL_DISPLAY_A_VSYNC (0x0014 | REGS_NORTH_PIPE_AND_PORT)
536 #define INTEL_DISPLAY_B_HTOTAL (0x1000 | REGS_NORTH_PIPE_AND_PORT)
537 #define INTEL_DISPLAY_B_HBLANK (0x1004 | REGS_NORTH_PIPE_AND_PORT)
538 #define INTEL_DISPLAY_B_HSYNC (0x1008 | REGS_NORTH_PIPE_AND_PORT)
539 #define INTEL_DISPLAY_B_VTOTAL (0x100c | REGS_NORTH_PIPE_AND_PORT)
540 #define INTEL_DISPLAY_B_VBLANK (0x1010 | REGS_NORTH_PIPE_AND_PORT)
541 #define INTEL_DISPLAY_B_VSYNC (0x1014 | REGS_NORTH_PIPE_AND_PORT)
542
543 #define INTEL_DISPLAY_A_IMAGE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT)
544 #define INTEL_DISPLAY_B_IMAGE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT)
545
546 // Cougar Point transcoder pipe selection
547 #define PORT_TRANS_A_SEL_CPT 0
548 #define PORT_TRANS_B_SEL_CPT (1<<29)
549 #define PORT_TRANS_C_SEL_CPT (2<<29)
550 #define PORT_TRANS_SEL_MASK (3<<29)
551
552 // on PCH we also have to set the transcoder
553 #define INTEL_TRANSCODER_A_HTOTAL (0x0000 | REGS_SOUTH_TRANSCODER_PORT)
554 #define INTEL_TRANSCODER_A_HBLANK (0x0004 | REGS_SOUTH_TRANSCODER_PORT)
555 #define INTEL_TRANSCODER_A_HSYNC (0x0008 | REGS_SOUTH_TRANSCODER_PORT)
556 #define INTEL_TRANSCODER_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT)
557 #define INTEL_TRANSCODER_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT)
558 #define INTEL_TRANSCODER_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT)
559 #define INTEL_TRANSCODER_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT)
560 #define INTEL_TRANSCODER_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT)
561 #define INTEL_TRANSCODER_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT)
562 #define INTEL_TRANSCODER_B_VTOTAL (0x100c | REGS_SOUTH_TRANSCODER_PORT)
563 #define INTEL_TRANSCODER_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT)
564 #define INTEL_TRANSCODER_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT)
565
566 #define INTEL_TRANSCODER_A_IMAGE_SIZE (0x001c | REGS_SOUTH_TRANSCODER_PORT)
567 #define INTEL_TRANSCODER_B_IMAGE_SIZE (0x101c | REGS_SOUTH_TRANSCODER_PORT)
568
569 // TODO: Is there consolidation that could happen here with digital ports?
570
571 #define INTEL_ANALOG_PORT (0x1100 | REGS_SOUTH_TRANSCODER_PORT)
572 #define INTEL_DIGITAL_PORT_A (0x1120 | REGS_SOUTH_TRANSCODER_PORT)
573 #define INTEL_DIGITAL_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT)
574 #define INTEL_DIGITAL_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT)
575 #define INTEL_DIGITAL_LVDS_PORT (0x1180 | REGS_SOUTH_TRANSCODER_PORT)
576
577 #define INTEL_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT)
578 #define INTEL_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT)
579
580 #define PCH_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT)
581 #define PCH_HDMI_PORT_C (0x1150 | REGS_SOUTH_TRANSCODER_PORT)
582 #define PCH_HDMI_PORT_D (0x1160 | REGS_SOUTH_TRANSCODER_PORT)
583
584 #define GEN4_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT)
585 #define GEN4_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT)
586 #define CHV_HDMI_PORT_D (0x116C | REGS_SOUTH_TRANSCODER_PORT)
587
588 // DDI Buffer Control (This replaces DP on Haswell+)
589 #define DDI_BUF_CTL_A (0x4000 | REGS_NORTH_PIPE_AND_PORT)
590 #define DDI_BUF_CTL_B (0x4100 | REGS_NORTH_PIPE_AND_PORT)
591 #define DDI_BUF_CTL_C (0x4200 | REGS_NORTH_PIPE_AND_PORT)
592 #define DDI_BUF_CTL_D (0x4300 | REGS_NORTH_PIPE_AND_PORT)
593 #define DDI_BUF_CTL_E (0x4400 | REGS_NORTH_PIPE_AND_PORT)
594 #define DDI_BUF_CTL_ENABLE (1 << 31)
595 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
596 #define DDI_BUF_EMP_MASK (0xf << 24)
597 #define DDI_BUF_PORT_REVERSAL (1 << 16)
598 #define DDI_BUF_IS_IDLE (1 << 7)
599 #define DDI_A_4_LANES (1 << 4)
600 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
601 #define DDI_INIT_DISPLAY_DETECTED (1 << 0)
602
603 // DP_A always @ 6xxxx, DP_B-DP_D move with PCH
604 #define INTEL_DISPLAY_PORT_A (0x4000 | REGS_NORTH_PIPE_AND_PORT)
605 #define INTEL_DISPLAY_PORT_B (0x4100 | REGS_SOUTH_TRANSCODER_PORT)
606 #define INTEL_DISPLAY_PORT_C (0x4200 | REGS_SOUTH_TRANSCODER_PORT)
607 #define INTEL_DISPLAY_PORT_D (0x4300 | REGS_SOUTH_TRANSCODER_PORT)
608
609 // Unless you're a damn Valley/CherryView unicorn :-(
610 #define VLV_DISPLAY_PORT_B (VLV_DISPLAY_BASE + 0x64100)
611 #define VLV_DISPLAY_PORT_C (VLV_DISPLAY_BASE + 0x64200)
612 #define CHV_DISPLAY_PORT_D (VLV_DISPLAY_BASE + 0x64300)
613
614 // DP AUX channels
615 #define INTEL_DP_AUX_CTL_A (0x4010 | REGS_NORTH_PIPE_AND_PORT)
616 #define INTEL_DP_AUX_CTL_B (0x4110 | REGS_SOUTH_TRANSCODER_PORT)
617 #define INTEL_DP_AUX_CTL_C (0x4210 | REGS_SOUTH_TRANSCODER_PORT)
618 #define INTEL_DP_AUX_CTL_D (0x4310 | REGS_SOUTH_TRANSCODER_PORT)
619
620 #define VLV_DP_AUX_CTL_B (VLV_DISPLAY_BASE + 0x64110)
621 #define VLV_DP_AUX_CTL_C (VLV_DISPLAY_BASE + 0x64210)
622 #define CHV_DP_AUX_CTL_D (VLV_DISPLAY_BASE + 0x64310)
623
624 #define INTEL_DP_AUX_CTL_BUSY (1 << 31)
625 #define INTEL_DP_AUX_CTL_DONE (1 << 30)
626 #define INTEL_DP_AUX_CTL_INTERRUPT (1 << 29)
627 #define INTEL_DP_AUX_CTL_TIMEOUT_ERROR (1 << 28)
628 #define INTEL_DP_AUX_CTL_TIMEOUT_400us (0 << 26)
629 #define INTEL_DP_AUX_CTL_TIMEOUT_600us (1 << 26)
630 #define INTEL_DP_AUX_CTL_TIMEOUT_800us (2 << 26)
631 #define INTEL_DP_AUX_CTL_TIMEOUT_1600us (3 << 26)
632 #define INTEL_DP_AUX_CTL_TIMEOUT_MASK (3 << 26)
633 #define INTEL_DP_AUX_CTL_RECEIVE_ERROR (1 << 25)
634 #define INTEL_DP_AUX_CTL_MSG_SIZE_MASK (0x1f << 20)
635 #define INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT 20
636 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16)
637 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_SHIFT 16
638 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
639 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_SHIFT 0
640 #define INTEL_DP_AUX_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
641
642 // planes
643 #define INTEL_PIPE_ENABLED (1UL << 31)
644 #define INTEL_PIPE_CONTROL 0x0008
645 #define INTEL_PIPE_STATUS 0x0024
646
647 #define INTEL_PLANE_OFFSET 0x1000
648
649 #define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL)
650 #define INTEL_DISPLAY_B_PIPE_CONTROL (0x1008 | REGS_NORTH_PLANE_CONTROL)
651 #define INTEL_DISPLAY_A_PIPE_STATUS (0x0024 | REGS_NORTH_PLANE_CONTROL)
652 #define INTEL_DISPLAY_B_PIPE_STATUS (0x1024 | REGS_NORTH_PLANE_CONTROL)
653
654 #define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17)
655 #define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1)
656
657 #define INTEL_DISPLAY_A_CONTROL (0x0180 | REGS_NORTH_PLANE_CONTROL)
658 #define INTEL_DISPLAY_A_BASE (0x0184 | REGS_NORTH_PLANE_CONTROL)
659 #define INTEL_DISPLAY_A_BYTES_PER_ROW (0x0188 | REGS_NORTH_PLANE_CONTROL)
660 #define INTEL_DISPLAY_A_POS (0x018c | REGS_NORTH_PLANE_CONTROL)
661 // reserved on A
662 #define INTEL_DISPLAY_A_PIPE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL)
663 #define INTEL_DISPLAY_A_SURFACE (0x019c | REGS_NORTH_PLANE_CONTROL)
664 // i965 and up only
665
666 #define INTEL_DISPLAY_B_CONTROL (0x1180 | REGS_NORTH_PLANE_CONTROL)
667 #define INTEL_DISPLAY_B_BASE (0x1184 | REGS_NORTH_PLANE_CONTROL)
668 #define INTEL_DISPLAY_B_BYTES_PER_ROW (0x1188 | REGS_NORTH_PLANE_CONTROL)
669 #define INTEL_DISPLAY_B_POS (0x118c | REGS_NORTH_PLANE_CONTROL)
670 #define INTEL_DISPLAY_B_PIPE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL)
671 #define INTEL_DISPLAY_B_SURFACE (0x119c | REGS_NORTH_PLANE_CONTROL)
672 // i965 and up only
673
674 // INTEL_DISPLAY_A_CONTROL source pixel format
675 #define DISPLAY_CONTROL_ENABLED (1UL << 31)
676 #define DISPLAY_CONTROL_GAMMA (1UL << 30)
677 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26)
678 #define DISPLAY_CONTROL_CMAP8 (2UL << 26)
679 #define DISPLAY_CONTROL_RGB15 (4UL << 26)
680 #define DISPLAY_CONTROL_RGB16 (5UL << 26)
681 #define DISPLAY_CONTROL_RGB32 (6UL << 26)
682
683 // INTEL_DISPLAY_A_PIPE_CONTROL ILK+
684 #define INTEL_PIPE_DITHER_TYPE_MASK (0x0000000c)
685 #define INTEL_PIPE_DITHER_TYPE_SP (0 << 2)
686 #define INTEL_PIPE_DITHER_TYPE_ST1 (1 << 2)
687 #define INTEL_PIPE_DITHER_TYPE_ST2 (2 << 2)
688 #define INTEL_PIPE_DITHER_TYPE_TEMP (3 << 2)
689 #define INTEL_PIPE_DITHER_EN (1 << 4)
690 #define INTEL_PIPE_8BPC (0 << 5)
691 #define INTEL_PIPE_10BPC (1 << 5)
692 #define INTEL_PIPE_6BPC (2 << 5)
693 #define INTEL_PIPE_12BPC (3 << 5)
694 #define INTEL_PIPE_PROGRESSIVE (0 << 21)
695
696 // cursors
697 #define INTEL_CURSOR_CONTROL (0x0080 | REGS_NORTH_PLANE_CONTROL)
698 #define INTEL_CURSOR_BASE (0x0084 | REGS_NORTH_PLANE_CONTROL)
699 #define INTEL_CURSOR_POSITION (0x0088 | REGS_NORTH_PLANE_CONTROL)
700 #define INTEL_CURSOR_PALETTE (0x0090 | REGS_NORTH_PLANE_CONTROL)
701 // (- 0x009f)
702 #define INTEL_CURSOR_SIZE (0x00a0 | REGS_NORTH_PLANE_CONTROL)
703 #define CURSOR_ENABLED (1UL << 31)
704 #define CURSOR_FORMAT_2_COLORS (0UL << 24)
705 #define CURSOR_FORMAT_3_COLORS (1UL << 24)
706 #define CURSOR_FORMAT_4_COLORS (2UL << 24)
707 #define CURSOR_FORMAT_ARGB (4UL << 24)
708 #define CURSOR_FORMAT_XRGB (5UL << 24)
709 #define CURSOR_POSITION_NEGATIVE 0x8000
710 #define CURSOR_POSITION_MASK 0x3fff
711
712 // palette registers
713 #define INTEL_DISPLAY_A_PALETTE (0xa000 | REGS_NORTH_SHARED)
714 #define INTEL_DISPLAY_B_PALETTE (0xa800 | REGS_NORTH_SHARED)
715
716 // PLL registers
717 #define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED)
718 #define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED)
719 #define CHV_DISPLAY_C_PLL (0x6030 | REGS_SOUTH_SHARED)
720
721 // Ironlake PCH reference clk control
722 #define PCH_DREF_CONTROL (0x6200 | REGS_SOUTH_SHARED)
723 #define DREF_CONTROL_MASK 0x7fc3
724 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
725 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
726 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
727 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
728 #define DREF_SSC_SOURCE_DISABLE (0 << 11)
729 #define DREF_SSC_SOURCE_ENABLE (2 << 11)
730 #define DREF_SSC_SOURCE_MASK (3 << 11)
731 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
732 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
733 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
734 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
735 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
736 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
737 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
738 #define DREF_SSC4_DOWNSPREAD (0 << 6)
739 #define DREF_SSC4_CENTERSPREAD (1 << 6)
740 #define DREF_SSC1_DISABLE (0 << 1)
741 #define DREF_SSC1_ENABLE (1 << 1)
742 #define DREF_SSC4_DISABLE (0 << 0)
743 #define DREF_SSC4_ENABLE (1 << 0)
744
745 // Multiplier Divisor
746 #define INTEL_DISPLAY_A_PLL_MD (0x601C | REGS_SOUTH_SHARED)
747 #define INTEL_DISPLAY_B_PLL_MD (0x6020 | REGS_SOUTH_SHARED)
748 #define CHV_DISPLAY_B_PLL_MD (0x603C | REGS_SOUTH_SHARED)
749
750 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED)
751 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 (0x6044 | REGS_SOUTH_SHARED)
752 #define INTEL_DISPLAY_B_PLL_DIVISOR_0 (0x6048 | REGS_SOUTH_SHARED)
753 #define INTEL_DISPLAY_B_PLL_DIVISOR_1 (0x604c | REGS_SOUTH_SHARED)
754
755 // i2c
756 #define INTEL_I2C_IO_A (0x5010 | REGS_SOUTH_SHARED)
757 #define INTEL_I2C_IO_B (0x5014 | REGS_SOUTH_SHARED)
758 #define INTEL_I2C_IO_C (0x5018 | REGS_SOUTH_SHARED)
759 #define INTEL_I2C_IO_D (0x501c | REGS_SOUTH_SHARED)
760 #define INTEL_I2C_IO_E (0x5020 | REGS_SOUTH_SHARED)
761 #define INTEL_I2C_IO_F (0x5024 | REGS_SOUTH_SHARED)
762 #define INTEL_I2C_IO_G (0x5028 | REGS_SOUTH_SHARED)
763 #define INTEL_I2C_IO_H (0x502c | REGS_SOUTH_SHARED)
764
765 #define I2C_CLOCK_DIRECTION_MASK (1 << 0)
766 #define I2C_CLOCK_DIRECTION_OUT (1 << 1)
767 #define I2C_CLOCK_VALUE_MASK (1 << 2)
768 #define I2C_CLOCK_VALUE_OUT (1 << 3)
769 #define I2C_CLOCK_VALUE_IN (1 << 4)
770 #define I2C_DATA_DIRECTION_MASK (1 << 8)
771 #define I2C_DATA_DIRECTION_OUT (1 << 9)
772 #define I2C_DATA_VALUE_MASK (1 << 10)
773 #define I2C_DATA_VALUE_OUT (1 << 11)
774 #define I2C_DATA_VALUE_IN (1 << 12)
775 #define I2C_RESERVED ((1 << 13) | (1 << 5))
776
777 // TODO: on IronLake this is in the north shared block at 0x41000
778 #define INTEL_VGA_DISPLAY_CONTROL (0x1400 | REGS_NORTH_PLANE_CONTROL)
779 #define VGA_DISPLAY_DISABLED (1UL << 31)
780
781 // LVDS panel
782 #define INTEL_PANEL_STATUS (0x1200 | REGS_NORTH_PIPE_AND_PORT)
783 #define INTEL_PANEL_CONTROL (0x1204 | REGS_NORTH_PIPE_AND_PORT)
784 #define INTEL_PANEL_FIT_CONTROL (0x1230 | REGS_NORTH_PIPE_AND_PORT)
785 #define INTEL_PANEL_FIT_RATIOS (0x1234 | REGS_NORTH_PIPE_AND_PORT)
786
787 // LVDS on IronLake and up
788 #define PCH_PANEL_STATUS (0x7200 | REGS_SOUTH_SHARED)
789 #define PCH_PANEL_CONTROL (0x7204 | REGS_SOUTH_SHARED)
790 #define PCH_PANEL_ON_DELAYS (0x7208 | REGS_SOUTH_SHARED)
791 #define PCH_PANEL_OFF_DELAYS (0x720c | REGS_SOUTH_SHARED)
792 #define PCH_PANEL_DIVISOR (0x7210 | REGS_SOUTH_SHARED)
793 #define PCH_LVDS_DETECTED (1 << 1)
794
795 #define PANEL_STATUS_POWER_ON (1UL << 31)
796 #define PANEL_CONTROL_POWER_TARGET_OFF (0UL << 0)
797 #define PANEL_CONTROL_POWER_TARGET_ON (1UL << 0)
798 #define PANEL_CONTROL_POWER_TARGET_RST (1UL << 1)
799 #define PANEL_REGISTER_UNLOCK (0xabcd << 16)
800
801 // PCH_PANEL_ON_DELAYS
802 #define PANEL_DELAY_PORT_SELECT_MASK (3 << 30)
803 #define PANEL_DELAY_PORT_SELECT_LVDS (0 << 30)
804 #define PANEL_DELAY_PORT_SELECT_DPA (1 << 30)
805 #define PANEL_DELAY_PORT_SELECT_DPC (2 << 30)
806 #define PANEL_DELAY_PORT_SELECT_DPD (3 << 30)
807
808 // PCH_PANEL_DIVISOR
809 #define PANEL_DIVISOR_REFERENCE_DIV_MASK 0xffffff00
810 #define PANEL_DIVISOR_REFERENCE_DIV_SHIFT 8
811 #define PANEL_DIVISOR_POW_CYCLE_DLY_MASK 0x1f
812 #define PANEL_DIVISOR_POW_CYCLE_DLY_SHIFT 0x1f
813
814 // Backlight control registers
815 #define PCH_BLC_PWM_CTL2 (0x8250 | REGS_NORTH_SHARED)
816 #define PCH_BLC_PWM_CTL (0x8254 | REGS_NORTH_SHARED)
817 #define PCH_SBLC_PWM_CTL2 (0x8254 | REGS_SOUTH_SHARED)
818
819 #define MCH_BLC_PWM_CTL (0x1254 | REGS_NORTH_PIPE_AND_PORT)
820
821 // ring buffer commands
822
823 #define COMMAND_NOOP 0x00
824 #define COMMAND_WAIT_FOR_EVENT (0x03 << 23)
825 #define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16)
826
827 #define COMMAND_FLUSH (0x04 << 23)
828
829 // overlay flip
830 #define COMMAND_OVERLAY_FLIP (0x11 << 23)
831 #define COMMAND_OVERLAY_CONTINUE (0 << 21)
832 #define COMMAND_OVERLAY_ON (1 << 21)
833 #define COMMAND_OVERLAY_OFF (2 << 21)
834 #define OVERLAY_UPDATE_COEFFICIENTS 0x1
835
836 // 2D acceleration
837 #define XY_COMMAND_SOURCE_BLIT 0x54c00006
838 #define XY_COMMAND_COLOR_BLIT 0x54000004
839 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007
840 #define XY_COMMAND_SCANLINE_BLIT 0x49400001
841 #define COMMAND_COLOR_BLIT 0x50000003
842 #define COMMAND_BLIT_RGBA 0x00300000
843
844 #define COMMAND_MODE_SOLID_PATTERN 0x80
845 #define COMMAND_MODE_CMAP8 0x00
846 #define COMMAND_MODE_RGB15 0x02
847 #define COMMAND_MODE_RGB16 0x01
848 #define COMMAND_MODE_RGB32 0x03
849
850 // overlay
851 #define INTEL_OVERLAY_UPDATE 0x30000
852 #define INTEL_OVERLAY_TEST 0x30004
853 #define INTEL_OVERLAY_STATUS 0x30008
854 #define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c
855 #define INTEL_OVERLAY_GAMMA_5 0x30010
856 #define INTEL_OVERLAY_GAMMA_4 0x30014
857 #define INTEL_OVERLAY_GAMMA_3 0x30018
858 #define INTEL_OVERLAY_GAMMA_2 0x3001c
859 #define INTEL_OVERLAY_GAMMA_1 0x30020
860 #define INTEL_OVERLAY_GAMMA_0 0x30024
861
862 // FDI - Flexible Display Interface, the interface between the (CPU-internal)
863 // GPU and the PCH display outputs. Proprietary interface, based on DisplayPort
864 // though, so similar link training and all...
865 // There's an FDI transmitter (TX) on the CPU and an FDI receiver (RX) on the
866 // PCH for each display pipe.
867 // FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to
868 // transcoder B, so we have the same mapping as with the display pipes.
869 #define PCH_FDI_RX_BASE_REGISTER 0xf0000
870 #define PCH_FDI_RX_PIPE_OFFSET 0x01000
871 #define PCH_FDI_RX_CONTROL 0x00c
872 #define PCH_FDI_RX_MISC 0x010
873 #define PCH_FDI_RX_IIR 0x014
874 #define PCH_FDI_RX_IMR 0x018
875
876 #define FDI_RX_ENABLE (1 << 31)
877 #define FDI_RX_PLL_ENABLED (1 << 13)
878
879 // FDI_tX interrupt register
880 #define FDI_RX_INTER_LANE_ALIGN (1 << 10)
881 #define FDI_RX_SYMBOL_LOCK (1 << 9)
882 #define FDI_RX_BIT_LOCK (1 << 8)
883 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7)
884 #define FDI_RX_FS_CODE_ERR (1 << 6)
885 #define FDI_RX_FE_CODE_ERR (1 << 5)
886 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4)
887 #define FDI_RX_HDCP_LINK_FAIL (1 << 3)
888 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2)
889 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1)
890 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0)
891
892 #define FDI_FS_ERRC_ENABLE (1 << 27)
893 #define FDI_FE_ERRC_ENABLE (1 << 26)
894
895 #define PCH_FDI_RX_TRANS_UNIT_SIZE_1 0x30
896 #define PCH_FDI_RX_TRANS_UNIT_SIZE_2 0x38
897 #define FDI_RX_TRANS_UNIT_SIZE(x) ((x - 1) << 25)
898 #define FDI_RX_TRANS_UNIT_MASK 0x7e000000
899
900 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6)
901 #define FDI_RX_CLOCK_MASK (1 << 4)
902 #define FDI_RX_CLOCK_RAW (0 << 4)
903 #define FDI_RX_CLOCK_PCD (1 << 4)
904
905 // FDI RX MISC
906 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26)
907 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26)
908 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24)
909 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24)
910 #define FDI_RX_TP1_TO_TP2_48 (2 << 20)
911 #define FDI_RX_TP1_TO_TP2_64 (3 << 20)
912 #define FDI_RX_FDI_DELAY_90 (0x90 << 0)
913
914 #define PCH_FDI_TX_BASE_REGISTER 0x60000
915 #define PCH_FDI_TX_PIPE_OFFSET 0x01000
916 #define PCH_FDI_TX_CONTROL 0x100
917 #define FDI_TX_ENABLE (1 << 31)
918 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28)
919 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28)
920 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28)
921 #define FDI_LINK_TRAIN_NONE (3 << 28)
922 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25)
923 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25)
924 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25)
925 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25)
926 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
927 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
928 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
929 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
930
931 // SNB A stepping
932 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
933 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
934 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
935 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x00 << 22)
936
937 // SNB B stepping
938 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x00 << 22)
939 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22)
940 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22)
941 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22)
942 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22)
943 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18)
944 #define FDI_TX_PLL_ENABLED (1 << 14)
945
946 #define FDI_DP_PORT_WIDTH_SHIFT 19
947 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
948 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
949
950 #define FDI_PLL_BIOS_0 0x46000
951 #define FDI_PLL_FB_CLOCK_MASK 0xff
952 #define FDI_PLL_BIOS_1 0x46004
953 #define FDI_PLL_BIOS_2 0x46008
954
955 #define FDI_AUTO_TRAINING (1 << 10)
956 #define FDI_AUTO_TRAIN_DONE (1 << 1)
957
958 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8)
959 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8)
960 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8)
961 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8)
962 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8)
963
964 // IvyBridge changes it up because... they hate developers?
965 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8)
966 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8)
967 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8)
968 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8)
969
970 #define PCH_FDI_RXA_CHICKEN (0x200c | REGS_SOUTH_SHARED)
971 #define PCH_FDI_RXB_CHICKEN (0x2010 | REGS_SOUTH_SHARED)
972 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0)
973 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1)
974
975 // CPU Panel Fitters - These are for IronLake and up and are the CPU internal
976 // panel fitters.
977 #define PCH_PANEL_FITTER_BASE_REGISTER 0x68000
978 #define PCH_PANEL_FITTER_PIPE_OFFSET 0x00800
979
980 #define PCH_PANEL_FITTER_WINDOW_POS 0x70
981 #define PCH_PANEL_FITTER_WINDOW_SIZE 0x74
982 #define PCH_PANEL_FITTER_CONTROL 0x80
983 #define PCH_PANEL_FITTER_V_SCALE 0x84
984 #define PCH_PANEL_FITTER_H_SCALE 0x90
985
986 #define PANEL_FITTER_ENABLED (1 << 31)
987 #define PANEL_FITTER_FILTER_MASK (3 << 23)
988
989 struct overlay_scale {
990 uint32 _reserved0 : 3;
991 uint32 horizontal_scale_fraction : 12;
992 uint32 _reserved1 : 1;
993 uint32 horizontal_downscale_factor : 3;
994 uint32 _reserved2 : 1;
995 uint32 vertical_scale_fraction : 12;
996 };
997
998 #define OVERLAY_FORMAT_RGB15 0x2
999 #define OVERLAY_FORMAT_RGB16 0x3
1000 #define OVERLAY_FORMAT_RGB32 0x1
1001 #define OVERLAY_FORMAT_YCbCr422 0x8
1002 #define OVERLAY_FORMAT_YCbCr411 0x9
1003 #define OVERLAY_FORMAT_YCbCr420 0xc
1004
1005 #define OVERLAY_MIRROR_NORMAL 0x0
1006 #define OVERLAY_MIRROR_HORIZONTAL 0x1
1007 #define OVERLAY_MIRROR_VERTICAL 0x2
1008
1009 // The real overlay registers are written to using an update buffer
1010
1011 struct overlay_registers {
1012 uint32 buffer_rgb0;
1013 uint32 buffer_rgb1;
1014 uint32 buffer_u0;
1015 uint32 buffer_v0;
1016 uint32 buffer_u1;
1017 uint32 buffer_v1;
1018 // (0x18) OSTRIDE - overlay stride
1019 uint16 stride_rgb;
1020 uint16 stride_uv;
1021 // (0x1c) YRGB_VPH - Y/RGB vertical phase
1022 uint16 vertical_phase0_rgb;
1023 uint16 vertical_phase1_rgb;
1024 // (0x20) UV_VPH - UV vertical phase
1025 uint16 vertical_phase0_uv;
1026 uint16 vertical_phase1_uv;
1027 // (0x24) HORZ_PH - horizontal phase
1028 uint16 horizontal_phase_rgb;
1029 uint16 horizontal_phase_uv;
1030 // (0x28) INIT_PHS - initial phase shift
1031 uint32 initial_vertical_phase0_shift_rgb0 : 4;
1032 uint32 initial_vertical_phase1_shift_rgb0 : 4;
1033 uint32 initial_horizontal_phase_shift_rgb0 : 4;
1034 uint32 initial_vertical_phase0_shift_uv : 4;
1035 uint32 initial_vertical_phase1_shift_uv : 4;
1036 uint32 initial_horizontal_phase_shift_uv : 4;
1037 uint32 _reserved0 : 8;
1038 // (0x2c) DWINPOS - destination window position
1039 uint16 window_left;
1040 uint16 window_top;
1041 // (0x30) DWINSZ - destination window size
1042 uint16 window_width;
1043 uint16 window_height;
1044 // (0x34) SWIDTH - source width
1045 uint16 source_width_rgb;
1046 uint16 source_width_uv;
1047 // (0x38) SWITDHSW - source width in 8 byte steps
1048 uint16 source_bytes_per_row_rgb;
1049 uint16 source_bytes_per_row_uv;
1050 uint16 source_height_rgb;
1051 uint16 source_height_uv;
1052 overlay_scale scale_rgb;
1053 overlay_scale scale_uv;
1054 // (0x48) OCLRC0 - overlay color correction 0
1055 uint32 brightness_correction : 8; // signed, -128 to 127
1056 uint32 _reserved1 : 10;
1057 uint32 contrast_correction : 9; // fixed point: 3.6 bits
1058 uint32 _reserved2 : 5;
1059 // (0x4c) OCLRC1 - overlay color correction 1
1060 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits
1061 uint32 _reserved3 : 6;
1062 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits
1063 uint32 _reserved4 : 5;
1064 // (0x50) DCLRKV - destination color key value
1065 uint32 color_key_blue : 8;
1066 uint32 color_key_green : 8;
1067 uint32 color_key_red : 8;
1068 uint32 _reserved5 : 8;
1069 // (0x54) DCLRKM - destination color key mask
1070 uint32 color_key_mask_blue : 8;
1071 uint32 color_key_mask_green : 8;
1072 uint32 color_key_mask_red : 8;
1073 uint32 _reserved6 : 7;
1074 uint32 color_key_enabled : 1;
1075 // (0x58) SCHRKVH - source chroma key high value
1076 uint32 source_chroma_key_high_red : 8;
1077 uint32 source_chroma_key_high_blue : 8;
1078 uint32 source_chroma_key_high_green : 8;
1079 uint32 _reserved7 : 8;
1080 // (0x5c) SCHRKVL - source chroma key low value
1081 uint32 source_chroma_key_low_red : 8;
1082 uint32 source_chroma_key_low_blue : 8;
1083 uint32 source_chroma_key_low_green : 8;
1084 uint32 _reserved8 : 8;
1085 // (0x60) SCHRKEN - source chroma key enable
1086 uint32 _reserved9 : 24;
1087 uint32 source_chroma_key_red_enabled : 1;
1088 uint32 source_chroma_key_blue_enabled : 1;
1089 uint32 source_chroma_key_green_enabled : 1;
1090 uint32 _reserved10 : 5;
1091 // (0x64) OCONFIG - overlay configuration
1092 uint32 _reserved11 : 3;
1093 uint32 color_control_output_mode : 1;
1094 uint32 yuv_to_rgb_bypass : 1;
1095 uint32 _reserved12 : 11;
1096 uint32 gamma2_enabled : 1;
1097 uint32 _reserved13 : 1;
1098 uint32 select_pipe : 1;
1099 uint32 slot_time : 8;
1100 uint32 _reserved14 : 5;
1101 // (0x68) OCOMD - overlay command
1102 uint32 overlay_enabled : 1;
1103 uint32 active_field : 1;
1104 uint32 active_buffer : 2;
1105 uint32 test_mode : 1;
1106 uint32 buffer_field_mode : 1;
1107 uint32 _reserved15 : 1;
1108 uint32 tv_flip_field_enabled : 1;
1109 uint32 _reserved16 : 1;
1110 uint32 tv_flip_field_parity : 1;
1111 uint32 source_format : 4;
1112 uint32 ycbcr422_order : 2;
1113 uint32 _reserved18 : 1;
1114 uint32 mirroring_mode : 2;
1115 uint32 _reserved19 : 13;
1116
1117 uint32 _reserved20;
1118
1119 uint32 start_0y;
1120 uint32 start_1y;
1121 uint32 start_0u;
1122 uint32 start_0v;
1123 uint32 start_1u;
1124 uint32 start_1v;
1125 uint32 _reserved21[6];
1126 #if 0
1127 // (0x70) AWINPOS - alpha blend window position
1128 uint32 awinpos;
1129 // (0x74) AWINSZ - alpha blend window size
1130 uint32 awinsz;
1131
1132 uint32 _reserved21[10];
1133 #endif
1134
1135 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough,
1136 // the next two registers switch the usual Y/RGB vs. UV order)
1137 uint16 horizontal_scale_uv;
1138 uint16 horizontal_scale_rgb;
1139 // (0xa4) UVSCALEV - vertical downscale
1140 uint16 vertical_scale_uv;
1141 uint16 vertical_scale_rgb;
1142
1143 uint32 _reserved22[86];
1144
1145 // (0x200) polyphase filter coefficients
1146 uint16 vertical_coefficients_rgb[128];
1147 uint16 horizontal_coefficients_rgb[128];
1148
1149 uint32 _reserved23[64];
1150
1151 // (0x500)
1152 uint16 vertical_coefficients_uv[128];
1153 uint16 horizontal_coefficients_uv[128];
1154 };
1155
1156 // i965 overlay support is currently realized using its 3D hardware
1157 #define INTEL_i965_OVERLAY_STATE_SIZE 36864
1158 #define INTEL_i965_3D_CONTEXT_SIZE 32768
1159
1160 inline bool
1161 intel_uses_physical_overlay(intel_shared_info &info)
1162 {
1163 return !info.device_type.InGroup(INTEL_GROUP_Gxx);
1164 }
1165
1166
1167 struct hardware_status {
1168 uint32 interrupt_status_register;
1169 uint32 _reserved0[3];
1170 void* primary_ring_head_storage;
1171 uint32 _reserved1[3];
1172 void* secondary_ring_0_head_storage;
1173 void* secondary_ring_1_head_storage;
1174 uint32 _reserved2[2];
1175 void* binning_head_storage;
1176 uint32 _reserved3[3];
1177 uint32 store[1008];
1178 };
1179
1180 #endif /* INTEL_EXTREME_H */
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