headers/private/graphics/radeon/cp_regs.h

   1 /*
   2         Copyright (c) 2002, Thomas Kurschel
   3
   4
   5         Part of Radeon driver
   6
   7         Command Processor registers
   8 */
   9
  10 #ifndef _CP_REGS_H
  11 #define _CP_REGS_H
  12
  13
  14 #define RADEON_SCRATCH_REG0             0x15e0
  15 #define RADEON_SCRATCH_REG1             0x15e4
  16 #define RADEON_SCRATCH_REG2             0x15e8
  17 #define RADEON_SCRATCH_REG3             0x15ec
  18 #define RADEON_SCRATCH_REG4             0x15f0
  19 #define RADEON_SCRATCH_REG5             0x15f4
  20 #define RADEON_SCRATCH_UMSK             0x0770
  21 #define RADEON_SCRATCH_ADDR             0x0774
  22
  23 /* Registers for CP and Microcode Engine */
  24 #define RADEON_CP_ME_RAM_ADDR               0x07d4
  25 #define RADEON_CP_ME_RAM_RADDR              0x07d8
  26 #define RADEON_CP_ME_RAM_DATAH              0x07dc
  27 #define RADEON_CP_ME_RAM_DATAL              0x07e0
  28
  29 #define RADEON_CP_RB_BASE                   0x0700
  30 #define RADEON_CP_RB_CNTL                   0x0704
  31 #define RADEON_CP_RB_RPTR_ADDR              0x070c
  32 #define RADEON_CP_RB_RPTR                   0x0710
  33 #define RADEON_CP_RB_WPTR                   0x0714
  34
  35 #define RADEON_CP_IB_BASE                   0x0738
  36 #define RADEON_CP_IB_BUFSZ                  0x073c
  37
  38 #define RADEON_CP_CSQ_CNTL                  0x0740
  39 #       define RADEON_CSQ_CNT_PRIMARY_MASK  (0xff << 0)
  40 #       define RADEON_CSQ_PRIDIS_INDDIS     (0    << 28)
  41 #       define RADEON_CSQ_PRIPIO_INDDIS     (1    << 28)
  42 #       define RADEON_CSQ_PRIBM_INDDIS      (2    << 28)
  43 #       define RADEON_CSQ_PRIPIO_INDBM      (3    << 28)
  44 #       define RADEON_CSQ_PRIBM_INDBM       (4    << 28)
  45 #       define RADEON_CSQ_PRIPIO_INDPIO     (15   << 28)
  46 #define RADEON_CP_STAT                                          0x07c0
  47 #define RADEON_CP_CSQ_STAT                  0x07f8
  48 #       define RADEON_CSQ_RPTR_PRIMARY_MASK  (0xff <<  0)
  49 #       define RADEON_CSQ_WPTR_PRIMARY_MASK  (0xff <<  8)
  50 #       define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16)
  51 #       define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24)
  52 #define RADEON_CP_CSQ_ADDR                  0x07f0
  53 #define RADEON_CP_CSQ_DATA                  0x07f4
  54 #define RADEON_CP_CSQ_APER_PRIMARY          0x1000
  55 #define RADEON_CP_CSQ_APER_INDIRECT         0x1300
  56
  57 #define RADEON_CP_RB_WPTR_DELAY             0x0718
  58 #       define RADEON_PRE_WRITE_TIMER_SHIFT      0
  59 #       define RADEON_PRE_WRITE_LIMIT_SHIFT     23
  60
  61 /* CP packet types */
  62 #define RADEON_CP_PACKET0                           0x00000000
  63 #define RADEON_CP_PACKET1                           0x40000000
  64 #define RADEON_CP_PACKET2                           0x80000000
  65 #define RADEON_CP_PACKET3                           0xC0000000
  66 #       define RADEON_CP_PACKET_MASK                0xC0000000
  67 #       define RADEON_CP_PACKET_COUNT_MASK          0x3fff0000
  68 #       define RADEON_CP_PACKET_MAX_DWORDS          (1 << 12)
  69 #       define RADEON_CP_PACKET0_REG_MASK           0x000007ff
  70 #       define RADEON_CP_PACKET1_REG0_MASK          0x000007ff
  71 #       define RADEON_CP_PACKET1_REG1_MASK          0x003ff800
  72
  73 #define RADEON_CP_PACKET0_ONE_REG_WR                0x00008000
  74
  75 #define RADEON_CP_PACKET3_NOP                       0xC0001000
  76 #define RADEON_CP_PACKET3_NEXT_CHAR                 0xC0001900
  77 #define RADEON_CP_PACKET3_PLY_NEXTSCAN              0xC0001D00
  78 #define RADEON_CP_PACKET3_SET_SCISSORS              0xC0001E00
  79 #define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM     0xC0002300
  80 #define RADEON_CP_PACKET3_LOAD_MICROCODE            0xC0002400
  81 #define RADEON_CP_PACKET3_3D_RNDR_GEN_PRIM          0xC0002500
  82 #define RADEON_CP_PACKET3_WAIT_FOR_IDLE             0xC0002600
  83 #define RADEON_CP_PACKET3_3D_DRAW_VBUF              0xC0002800
  84 #define RADEON_CP_PACKET3_3D_DRAW_IMMD              0xC0002900
  85 #define RADEON_CP_PACKET3_3D_DRAW_INDX              0xC0002A00
  86 #define RADEON_CP_PACKET3_LOAD_PALETTE              0xC0002C00
  87 #define RADEON_CP_PACKET3_3D_LOAD_VBPNTR            0xC0002F00
  88 #define RADEON_CP_PACKET3_3D_CLEAR_ZMASK            0xC0003200
  89 #define RADEON_CP_PACKET3_CNTL_PAINT                0xC0009100
  90 #define RADEON_CP_PACKET3_CNTL_BITBLT               0xC0009200
  91 #define RADEON_CP_PACKET3_CNTL_SMALLTEXT            0xC0009300
  92 #define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT         0xC0009400
  93 #define RADEON_CP_PACKET3_CNTL_POLYLINE             0xC0009500
  94 #define RADEON_CP_PACKET3_CNTL_POLYSCANLINES        0xC0009800
  95 #define RADEON_CP_PACKET3_CNTL_PAINT_MULTI          0xC0009A00
  96 #define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI         0xC0009B00
  97 #define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT         0xC0009C00
  98
  99
 100 #define RADEON_ISYNC_CNTL               0x1724
 101 #       define RADEON_ISYNC_ANY2D_IDLE3D        (1 << 0)
 102 #       define RADEON_ISYNC_ANY3D_IDLE2D        (1 << 1)
 103 #       define RADEON_ISYNC_TRIG2D_IDLE3D       (1 << 2)
 104 #       define RADEON_ISYNC_TRIG3D_IDLE2D       (1 << 3)
 105 #       define RADEON_ISYNC_WAIT_IDLEGUI        (1 << 4)
 106 #       define RADEON_ISYNC_CPSCRATCH_IDLEGUI   (1 << 5)
 107
 108
 109 #define CP_PACKET0( reg, n )                                            \
 110         (RADEON_CP_PACKET0 | (((n) - 1) << 16) | ((reg) >> 2))
 111
 112
 113 #endif