headers/private/graphics/via/DriverInterface.h

   1 /*
   2         Copyright 1999, Be Incorporated.   All Rights Reserved.
   3         This file may be used under the terms of the Be Sample Code License.
   4
   5         Other authors:
   6         Mark Watson;
   7         Apsed;
   8         Rudolf Cornelissen 10/2002-1/2016.
   9 */
  10
  11 #ifndef DRIVERINTERFACE_H
  12 #define DRIVERINTERFACE_H
  13
  14 #include <Accelerant.h>
  15 #include "video_overlay.h"
  16 #include <Drivers.h>
  17 #include <PCI.h>
  18 #include <OS.h>
  19 #include "AGP.h"
  20
  21 #define DRIVER_PREFIX "via"
  22
  23 /*
  24         Internal driver state (also for sharing info between driver and accelerant)
  25 */
  26 #if defined(__cplusplus)
  27 extern "C" {
  28 #endif
  29
  30 typedef struct {
  31         sem_id  sem;
  32         int32   ben;
  33 } benaphore;
  34
  35 #define INIT_BEN(x)             x.sem = create_sem(0, "NV "#x" benaphore");  x.ben = 0;
  36 #define AQUIRE_BEN(x)   if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem);
  37 #define RELEASE_BEN(x)  if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem);
  38 #define DELETE_BEN(x)   delete_sem(x.sem);
  39
  40
  41 #define VIA_PRIVATE_DATA_MAGIC  0x0009 /* a private driver rev, of sorts */
  42
  43 /*dualhead extensions to flags*/
  44 #define DUALHEAD_OFF (0<<6)
  45 #define DUALHEAD_CLONE (1<<6)
  46 #define DUALHEAD_ON (2<<6)
  47 #define DUALHEAD_SWITCH (3<<6)
  48 #define DUALHEAD_BITS (3<<6)
  49 #define DUALHEAD_CAPABLE (1<<8)
  50 #define TV_BITS (3<<9)
  51 #define TV_MON (0<<9
  52 #define TV_PAL (1<<9)
  53 #define TV_NTSC (2<<9)
  54 #define TV_CAPABLE (1<<11)
  55 #define TV_VIDEO (1<<12)
  56
  57 #define SKD_MOVE_CURSOR    0x00000001
  58 #define SKD_PROGRAM_CLUT   0x00000002
  59 #define SKD_SET_START_ADDR 0x00000004
  60 #define SKD_SET_CURSOR     0x00000008
  61 #define SKD_HANDLER_INSTALLED 0x80000000
  62
  63 enum {
  64         ENG_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
  65         ENG_GET_PCI,
  66         ENG_SET_PCI,
  67         ENG_DEVICE_NAME,
  68         ENG_RUN_INTERRUPTS,
  69         ENG_GET_NTH_AGP_INFO,
  70         ENG_ENABLE_AGP,
  71         ENG_ISA_OUT,
  72         ENG_ISA_IN
  73 };
  74
  75 /* max. number of overlay buffers */
  76 #define MAXBUFFERS 3
  77
  78 /* internal used info on overlay buffers */
  79 typedef struct
  80 {
  81         uint16 slopspace;
  82         uint32 size;
  83 } int_buf_info;
  84
  85 typedef struct settings {  // apsed, see comments in skel.settings
  86         // for driver
  87         char   accelerant[B_FILE_NAME_LENGTH];
  88         bool   dumprom;
  89         // for accelerant
  90         uint32 logmask;
  91         uint32 memory;
  92         bool   usebios;
  93         bool   hardcursor;
  94         bool   switchhead;
  95         bool   force_pci;
  96         bool   unhide_fw;
  97         bool   pgm_panel;
  98 } settings;
  99
 100 /* card info - information gathered from PINS (and other sources) */
 101 enum
 102 {       // card_type in order of date of VIA chip design (fixme: check order)
 103         VT3122 = 0,
 104         VT3022,
 105         VT7205,
 106         VT3205,
 107         VT3108,
 108         VT3204NC,
 109         NV04,
 110         NV05,
 111         NV05M64,
 112         NV06,
 113         NV10,
 114         NV11,
 115         NV11M,
 116         NV15,
 117         NV17,
 118         NV17M,
 119         NV18,
 120         NV18M,
 121         NV20,
 122         NV25,
 123         NV28,
 124         NV30,
 125         NV31,
 126         NV34,
 127         NV35,
 128         NV36,
 129         NV38,
 130         NV40,
 131         NV41,
 132         NV43,
 133         NV45
 134 };
 135 enum
 136 {       // card_arch in order of date of VIA chip design
 137         CLE266 = 0,
 138         KM400,
 139         K8M800,
 140         NV04A,
 141         NV10A,
 142         NV20A,
 143         NV30A,
 144         NV40A
 145 };
 146 enum
 147 {       // tvout_chip_type in order of capability (more or less)
 148         NONE = 0,
 149         CH7003,
 150         CH7004,
 151         CH7005,
 152         CH7006,
 153         CH7007,
 154         CH7008,
 155         SAA7102,
 156         SAA7103,
 157         SAA7104,
 158         SAA7105,
 159         BT868,
 160         BT869,
 161         CX25870,
 162         CX25871,
 163         NVIDIA
 164 };
 165
 166
 167 /*shared info*/
 168 typedef struct {
 169   /*a few ID things*/
 170         uint16  vendor_id;      /* PCI vendor ID, from pci_info */
 171         uint16  device_id;      /* PCI device ID, from pci_info */
 172         uint8   revision;       /* PCI device revsion, from pci_info */
 173         uint8   bus;            /* PCI bus number, from pci_info */
 174         uint8   device;         /* PCI device number on bus, from pci_info */
 175         uint8   function;       /* PCI function number in device, from pci_info */
 176
 177   /* bug workaround for 4.5.0 */
 178         uint32 use_clone_bugfix;        /*for 4.5.0, cloning of physical memory does not work*/
 179         uint32 * clone_bugfix_regs;
 180
 181   /*memory mappings*/
 182         area_id regs_area;      /* Kernel's area_id for the memory mapped registers.
 183                                                         It will be cloned into the accelerant's address
 184                                                         space. */
 185
 186         area_id fb_area;        /* Frame buffer's area_id.  The addresses are shared with all teams. */
 187         area_id pseudo_dma_area;        /* Pseudo dma area_id. Shared by all teams. */
 188         area_id dma_buffer_area;        /* Area assigned for dma*/
 189
 190         void    *framebuffer;           /* As viewed from virtual memory */
 191         void    *framebuffer_pci;       /* As viewed from the PCI bus (for DMA) */
 192
 193         void    *pseudo_dma;            /* As viewed from virtual memory */
 194
 195         void    *dma_buffer;            /* buffer for dma*/
 196         void    *dma_buffer_pci;        /* buffer for dma - from PCI bus*/
 197
 198   /*screenmode list*/
 199         area_id mode_area;              /* Contains the list of display modes the driver supports */
 200         uint32  mode_count;             /* Number of display modes in the list */
 201
 202   /*flags - used by driver*/
 203         uint32 flags;
 204
 205   /*vblank semaphore*/
 206         sem_id  vblank;                 /* The vertical blank semaphore. Ownership will be
 207                                                 transfered to the team opening the device first */
 208   /*cursor information*/
 209         struct {
 210                 uint16  hot_x;          /* Cursor hot spot. The top left corner of the cursor */
 211                 uint16  hot_y;          /* is 0,0 */
 212                 uint16  x;              /* The location of the cursor hot spot on the */
 213                 uint16  y;              /* desktop */
 214                 uint16  width;          /* Width and height of the cursor shape (always 16!) */
 215                 uint16  height;
 216                 bool    is_visible;     /* Is the cursor currently displayed? */
 217                 bool    dh_right;       /* Is cursor on right side of stretched screen? */
 218         } cursor;
 219
 220   /*colour lookup table*/
 221         uint8   color_data[3 * 256];    /* Colour lookup table - as used by DAC */
 222
 223   /*more display mode stuff*/
 224         display_mode dm;                /* current display mode configuration: head1 */
 225         display_mode dm2;               /* current display mode configuration: head2 */
 226         bool acc_mode;                  /* signals (non)accelerated mode */
 227         bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */
 228         bool crtc_switch_mode;  /* signals dualhead switch mode if panels are used */
 229
 230   /*frame buffer config - for BDirectScreen*/
 231         frame_buffer_config fbc;        /* bytes_per_row and start of frame buffer: head1 */
 232         frame_buffer_config fbc2;       /* bytes_per_row and start of frame buffer: head2 */
 233
 234   /*acceleration engine*/
 235         struct {
 236                 uint32          count;          /* last dwgsync slot used */
 237                 uint32          last_idle;      /* last dwgsync slot we *know* the engine was idle after */
 238                 benaphore       lock;           /* for serializing access to the acceleration engine */
 239         } engine;
 240
 241         struct
 242         {
 243                 /* specialised registers for card initialisation read from NV BIOS (pins) */
 244
 245                 /* general card information */
 246                 uint32 card_type;           /* see card_type enum above */
 247                 uint32 card_arch;           /* see card_arch enum above */
 248                 uint8 chip_rev;                         /* chip revision number */
 249                 bool laptop;                /* mobile chipset or not ('internal' flatpanel!) */
 250                 bool slaved_tmds1;                      /* external TMDS encoder active on CRTC1 */
 251                 bool slaved_tmds2;                      /* external TMDS encoder active on CRTC2 */
 252                 bool master_tmds1;                      /* on die TMDS encoder active on CRTC1 */
 253                 bool master_tmds2;                      /* on die TMDS encoder active on CRTC2 */
 254                 bool tmds1_active;                      /* found panel on CRTC1 that is active */
 255                 bool tmds2_active;                      /* found panel on CRTC2 that is active */
 256                 display_timing p1_timing;       /* 'modeline' fetched for panel 1 */
 257                 display_timing p2_timing;       /* 'modeline' fetched for panel 2 */
 258                 float panel1_aspect;            /* panel's aspect ratio */
 259                 float panel2_aspect;            /* panel's aspect ratio */
 260                 bool crtc2_prim;                        /* using CRTC2 as primary CRTC */
 261                 uint32 tvout_chip_type;     /* see tvchip_type enum above */
 262                 uint8 monitors;                         /* output devices connection matrix */
 263                 status_t pins_status;           /* B_OK if read correctly, B_ERROR if faked */
 264
 265                 /* PINS */
 266                 float f_ref;                            /* PLL reference-oscillator frequency (Mhz) */
 267                 bool ext_pll;                           /* the extended PLL contains more dividers */
 268                 uint32 max_system_vco;          /* graphics engine PLL VCO limits (Mhz) */
 269                 uint32 min_system_vco;
 270                 uint32 max_pixel_vco;           /* dac1 PLL VCO limits (Mhz) */
 271                 uint32 min_pixel_vco;
 272                 uint32 max_video_vco;           /* dac2 PLL VCO limits (Mhz) */
 273                 uint32 min_video_vco;
 274                 uint32 std_engine_clock;        /* graphics engine clock speed needed (Mhz) */
 275                 uint32 std_memory_clock;        /* card memory clock speed needed (Mhz) */
 276                 uint32 max_dac1_clock;          /* dac1 limits (Mhz) */
 277                 uint32 max_dac1_clock_8;        /* dac1 limits correlated to RAMspeed limits (Mhz) */
 278                 uint32 max_dac1_clock_16;
 279                 uint32 max_dac1_clock_24;
 280                 uint32 max_dac1_clock_32;
 281                 uint32 max_dac1_clock_32dh;
 282                 uint32 max_dac2_clock;          /* dac2 limits (Mhz) */
 283                 uint32 max_dac2_clock_8;        /* dac2, maven limits correlated to RAMspeed limits (Mhz) */
 284                 uint32 max_dac2_clock_16;
 285                 uint32 max_dac2_clock_24;
 286                 uint32 max_dac2_clock_32;
 287                 uint32 max_dac2_clock_32dh;
 288                 bool secondary_head;            /* presence of functions */
 289                 bool tvout;
 290                 bool primary_dvi;
 291                 bool secondary_dvi;
 292                 uint32 memory_size;                     /* memory (in bytes) */
 293         } ps;
 294
 295         /* mirror of the ROM (copied in driver, because may not be mapped permanently) */
 296         uint8 rom_mirror[65536];
 297
 298         /* some configuration settings from ~/config/settings/kernel/drivers/skel.settings if exists */
 299         settings settings;
 300
 301         struct
 302         {
 303                 overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */
 304                 int_buf_info myBufInfo[MAXBUFFERS];     /* extra info on scaler input buffers */
 305                 overlay_token myToken;                          /* scaler is free/in use */
 306                 benaphore lock;                                         /* for creating buffers and aquiring overlay unit routines */
 307                 bool crtc;                                                      /* location of overlay unit */
 308                 /* variables needed for virtualscreens (move_overlay()): */
 309                 bool active;                                            /* true is overlay currently in use */
 310                 overlay_window ow;                                      /* current position of overlay output window */
 311                 overlay_buffer ob;                                      /* current inputbuffer in use */
 312                 overlay_view my_ov;                                     /* current corrected view in inputbuffer */
 313                 uint32 h_ifactor;                                       /* current 'unclipped' horizontal inverse scaling factor */
 314                 uint32 v_ifactor;                                       /* current 'unclipped' vertical inverse scaling factor */
 315         } overlay;
 316
 317 } shared_info;
 318
 319 /* Read or write a value in PCI configuration space */
 320 typedef struct {
 321         uint32  magic;          /* magic number to make sure the caller groks us */
 322         uint32  offset;         /* Offset to read/write */
 323         uint32  size;           /* Number of bytes to transfer */
 324         uint32  value;          /* The value read or written */
 325 } eng_get_set_pci;
 326
 327 /* Set some boolean condition (like enabling or disabling interrupts) */
 328 typedef struct {
 329         uint32  magic;          /* magic number to make sure the caller groks us */
 330         bool    do_it;          /* state to set */
 331 } eng_set_bool_state;
 332
 333 /* Retrieve the area_id of the kernel/accelerant shared info */
 334 typedef struct {
 335         uint32  magic;          /* magic number to make sure the caller groks us */
 336         area_id shared_info_area;       /* area_id containing the shared information */
 337 } eng_get_private_data;
 338
 339 /* Retrieve the device name.  Usefull for when we have a file handle, but want
 340 to know the device name (like when we are cloning the accelerant) */
 341 typedef struct {
 342         uint32  magic;          /* magic number to make sure the caller groks us */
 343         char    *name;          /* The name of the device, less the /dev root */
 344 } eng_device_name;
 345
 346 /* Retrieve an AGP device interface if there. Usefull to find the AGP speed scheme
 347 used (pre 3.x or 3.x) */
 348 typedef struct {
 349         uint32          magic;  /* magic number to make sure the caller groks us */
 350         bool            agp_bus;/* indicates if we have access to the AGP busmanager */
 351         uint8           index;  /* device index in list of devices found */
 352         bool            exist;  /* we got AGP device info */
 353         agp_info        agpi;   /* AGP interface info of a device */
 354 } eng_nth_agp_info;
 355
 356 /* Execute an AGP command */
 357 typedef struct {
 358         uint32          magic;  /* magic number to make sure the caller groks us */
 359         bool            agp_bus;/* indicates if we have access to the AGP busmanager */
 360         uint32          cmd;    /* actual command to execute */
 361 } eng_cmd_agp;
 362
 363 /* Read or write a value in ISA I/O space */
 364 typedef struct {
 365         uint32  magic;          /* magic number to make sure the caller groks us */
 366         uint16  adress;         /* Offset to read/write */
 367         uint8   size;           /* Number of bytes to transfer */
 368         uint16  data;           /* The value read or written */
 369 } eng_in_out_isa;
 370
 371 enum {
 372
 373         _WAIT_FOR_VBLANK = (1 << 0)
 374 };
 375
 376 #if defined(__cplusplus)
 377 }
 378 #endif
 379
 380
 381 #endif