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[NETFILTER]: sip conntrack: make header shortcuts optional
[hh.org.git] / drivers / ata / ata_piix.c
blob720174d628fa762d4ee3e2367645229d14771b06
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "2.00ac6"
97
98 enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
102 PIIX_SCC = 0x0A, /* sub-class code register */
103
104 PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */
105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108
109 /* combined mode. if set, PATA is channel 0.
110 * if clear, PATA is channel 1.
111 */
112 PIIX_PORT_ENABLED = (1 << 0),
113 PIIX_PORT_PRESENT = (1 << 4),
114
115 PIIX_80C_PRI = (1 << 5) | (1 << 4),
116 PIIX_80C_SEC = (1 << 7) | (1 << 6),
117
118 /* controller IDs */
119 piix_pata_33 = 0, /* PIIX3 or 4 at 33Mhz */
120 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
121 ich_pata_66 = 2, /* ICH up to 66 Mhz */
122 ich_pata_100 = 3, /* ICH up to UDMA 100 */
123 ich_pata_133 = 4, /* ICH up to UDMA 133 */
124 ich5_sata = 5,
125 esb_sata = 6,
126 ich6_sata = 7,
127 ich6_sata_ahci = 8,
128 ich6m_sata_ahci = 9,
129 ich8_sata_ahci = 10,
130
131 /* constants for mapping table */
132 P0 = 0, /* port 0 */
133 P1 = 1, /* port 1 */
134 P2 = 2, /* port 2 */
135 P3 = 3, /* port 3 */
136 IDE = -1, /* IDE */
137 NA = -2, /* not avaliable */
138 RV = -3, /* reserved */
139
140 PIIX_AHCI_DEVICE = 6,
141 };
142
143 struct piix_map_db {
144 const u32 mask;
145 const u16 port_enable;
146 const int present_shift;
147 const int map[][4];
148 };
149
150 struct piix_host_priv {
151 const int *map;
152 const struct piix_map_db *map_db;
153 };
154
155 static int piix_init_one (struct pci_dev *pdev,
156 const struct pci_device_id *ent);
157 static void piix_host_stop(struct ata_host *host);
158 static void piix_pata_error_handler(struct ata_port *ap);
159 static void ich_pata_error_handler(struct ata_port *ap);
160 static void piix_sata_error_handler(struct ata_port *ap);
161 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
162 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
163 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
164
165 static unsigned int in_module_init = 1;
166
167 static const struct pci_device_id piix_pci_tbl[] = {
168 #ifdef ATA_ENABLE_PATA
169 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
170 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
171 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
172 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
173 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
174 /* Intel PIIX4 */
175 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
176 /* Intel PIIX4 */
177 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
178 /* Intel PIIX */
179 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
180 /* Intel ICH (i810, i815, i840) UDMA 66*/
181 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
182 /* Intel ICH0 : UDMA 33*/
183 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
184 /* Intel ICH2M */
185 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
186 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
187 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
188 /* Intel ICH3M */
189 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
190 /* Intel ICH3 (E7500/1) UDMA 100 */
191 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
193 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
194 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
195 /* Intel ICH5 */
196 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
197 /* C-ICH (i810E2) */
198 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
200 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* ICH6 (and 6) (i915) UDMA 100 */
202 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* ICH7/7-R (i945, i975) UDMA 100*/
204 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
205 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
206 #endif
207
208 /* NOTE: The following PCI ids must be kept in sync with the
209 * list in drivers/pci/quirks.c.
210 */
211
212 /* 82801EB (ICH5) */
213 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
214 /* 82801EB (ICH5) */
215 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
216 /* 6300ESB (ICH5 variant with broken PCS present bits) */
217 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
218 /* 6300ESB pretending RAID */
219 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
220 /* 82801FB/FW (ICH6/ICH6W) */
221 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
222 /* 82801FR/FRW (ICH6R/ICH6RW) */
223 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
224 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
225 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
226 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
227 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
228 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
229 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
230 /* Enterprise Southbridge 2 (where's the datasheet?) */
231 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
232 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
233 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
234 /* SATA Controller 2 IDE (ICH8, ditto) */
235 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
236 /* Mobile SATA Controller IDE (ICH8M, ditto) */
237 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
238
239 { } /* terminate list */
240 };
241
242 static struct pci_driver piix_pci_driver = {
243 .name = DRV_NAME,
244 .id_table = piix_pci_tbl,
245 .probe = piix_init_one,
246 .remove = ata_pci_remove_one,
247 .suspend = ata_pci_device_suspend,
248 .resume = ata_pci_device_resume,
249 };
250
251 static struct scsi_host_template piix_sht = {
252 .module = THIS_MODULE,
253 .name = DRV_NAME,
254 .ioctl = ata_scsi_ioctl,
255 .queuecommand = ata_scsi_queuecmd,
256 .can_queue = ATA_DEF_QUEUE,
257 .this_id = ATA_SHT_THIS_ID,
258 .sg_tablesize = LIBATA_MAX_PRD,
259 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
260 .emulated = ATA_SHT_EMULATED,
261 .use_clustering = ATA_SHT_USE_CLUSTERING,
262 .proc_name = DRV_NAME,
263 .dma_boundary = ATA_DMA_BOUNDARY,
264 .slave_configure = ata_scsi_slave_config,
265 .slave_destroy = ata_scsi_slave_destroy,
266 .bios_param = ata_std_bios_param,
267 .resume = ata_scsi_device_resume,
268 .suspend = ata_scsi_device_suspend,
269 };
270
271 static const struct ata_port_operations piix_pata_ops = {
272 .port_disable = ata_port_disable,
273 .set_piomode = piix_set_piomode,
274 .set_dmamode = piix_set_dmamode,
275 .mode_filter = ata_pci_default_filter,
276
277 .tf_load = ata_tf_load,
278 .tf_read = ata_tf_read,
279 .check_status = ata_check_status,
280 .exec_command = ata_exec_command,
281 .dev_select = ata_std_dev_select,
282
283 .bmdma_setup = ata_bmdma_setup,
284 .bmdma_start = ata_bmdma_start,
285 .bmdma_stop = ata_bmdma_stop,
286 .bmdma_status = ata_bmdma_status,
287 .qc_prep = ata_qc_prep,
288 .qc_issue = ata_qc_issue_prot,
289 .data_xfer = ata_pio_data_xfer,
290
291 .freeze = ata_bmdma_freeze,
292 .thaw = ata_bmdma_thaw,
293 .error_handler = piix_pata_error_handler,
294 .post_internal_cmd = ata_bmdma_post_internal_cmd,
295
296 .irq_handler = ata_interrupt,
297 .irq_clear = ata_bmdma_irq_clear,
298
299 .port_start = ata_port_start,
300 .port_stop = ata_port_stop,
301 .host_stop = piix_host_stop,
302 };
303
304 static const struct ata_port_operations ich_pata_ops = {
305 .port_disable = ata_port_disable,
306 .set_piomode = piix_set_piomode,
307 .set_dmamode = ich_set_dmamode,
308 .mode_filter = ata_pci_default_filter,
309
310 .tf_load = ata_tf_load,
311 .tf_read = ata_tf_read,
312 .check_status = ata_check_status,
313 .exec_command = ata_exec_command,
314 .dev_select = ata_std_dev_select,
315
316 .bmdma_setup = ata_bmdma_setup,
317 .bmdma_start = ata_bmdma_start,
318 .bmdma_stop = ata_bmdma_stop,
319 .bmdma_status = ata_bmdma_status,
320 .qc_prep = ata_qc_prep,
321 .qc_issue = ata_qc_issue_prot,
322 .data_xfer = ata_pio_data_xfer,
323
324 .freeze = ata_bmdma_freeze,
325 .thaw = ata_bmdma_thaw,
326 .error_handler = ich_pata_error_handler,
327 .post_internal_cmd = ata_bmdma_post_internal_cmd,
328
329 .irq_handler = ata_interrupt,
330 .irq_clear = ata_bmdma_irq_clear,
331
332 .port_start = ata_port_start,
333 .port_stop = ata_port_stop,
334 .host_stop = ata_host_stop,
335 };
336
337 static const struct ata_port_operations piix_sata_ops = {
338 .port_disable = ata_port_disable,
339
340 .tf_load = ata_tf_load,
341 .tf_read = ata_tf_read,
342 .check_status = ata_check_status,
343 .exec_command = ata_exec_command,
344 .dev_select = ata_std_dev_select,
345
346 .bmdma_setup = ata_bmdma_setup,
347 .bmdma_start = ata_bmdma_start,
348 .bmdma_stop = ata_bmdma_stop,
349 .bmdma_status = ata_bmdma_status,
350 .qc_prep = ata_qc_prep,
351 .qc_issue = ata_qc_issue_prot,
352 .data_xfer = ata_pio_data_xfer,
353
354 .freeze = ata_bmdma_freeze,
355 .thaw = ata_bmdma_thaw,
356 .error_handler = piix_sata_error_handler,
357 .post_internal_cmd = ata_bmdma_post_internal_cmd,
358
359 .irq_handler = ata_interrupt,
360 .irq_clear = ata_bmdma_irq_clear,
361
362 .port_start = ata_port_start,
363 .port_stop = ata_port_stop,
364 .host_stop = piix_host_stop,
365 };
366
367 static const struct piix_map_db ich5_map_db = {
368 .mask = 0x7,
369 .port_enable = 0x3,
370 .present_shift = 4,
371 .map = {
372 /* PM PS SM SS MAP */
373 { P0, NA, P1, NA }, /* 000b */
374 { P1, NA, P0, NA }, /* 001b */
375 { RV, RV, RV, RV },
376 { RV, RV, RV, RV },
377 { P0, P1, IDE, IDE }, /* 100b */
378 { P1, P0, IDE, IDE }, /* 101b */
379 { IDE, IDE, P0, P1 }, /* 110b */
380 { IDE, IDE, P1, P0 }, /* 111b */
381 },
382 };
383
384 static const struct piix_map_db ich6_map_db = {
385 .mask = 0x3,
386 .port_enable = 0xf,
387 .present_shift = 4,
388 .map = {
389 /* PM PS SM SS MAP */
390 { P0, P2, P1, P3 }, /* 00b */
391 { IDE, IDE, P1, P3 }, /* 01b */
392 { P0, P2, IDE, IDE }, /* 10b */
393 { RV, RV, RV, RV },
394 },
395 };
396
397 static const struct piix_map_db ich6m_map_db = {
398 .mask = 0x3,
399 .port_enable = 0x5,
400 .present_shift = 4,
401
402 /* Map 01b isn't specified in the doc but some notebooks use
403 * it anyway. MAP 01b have been spotted on both ICH6M and
404 * ICH7M.
405 */
406 .map = {
407 /* PM PS SM SS MAP */
408 { P0, P2, RV, RV }, /* 00b */
409 { IDE, IDE, P1, P3 }, /* 01b */
410 { P0, P2, IDE, IDE }, /* 10b */
411 { RV, RV, RV, RV },
412 },
413 };
414
415 static const struct piix_map_db ich8_map_db = {
416 .mask = 0x3,
417 .port_enable = 0x3,
418 .present_shift = 8,
419 .map = {
420 /* PM PS SM SS MAP */
421 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
422 { RV, RV, RV, RV },
423 { IDE, IDE, NA, NA }, /* 10b (IDE mode) */
424 { RV, RV, RV, RV },
425 },
426 };
427
428 static const struct piix_map_db *piix_map_db_table[] = {
429 [ich5_sata] = &ich5_map_db,
430 [esb_sata] = &ich5_map_db,
431 [ich6_sata] = &ich6_map_db,
432 [ich6_sata_ahci] = &ich6_map_db,
433 [ich6m_sata_ahci] = &ich6m_map_db,
434 [ich8_sata_ahci] = &ich8_map_db,
435 };
436
437 static struct ata_port_info piix_port_info[] = {
438 /* piix_pata_33: 0: PIIX3 or 4 at 33MHz */
439 {
440 .sht = &piix_sht,
441 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
442 .pio_mask = 0x1f, /* pio0-4 */
443 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
444 .udma_mask = ATA_UDMA_MASK_40C,
445 .port_ops = &piix_pata_ops,
446 },
447
448 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
449 {
450 .sht = &piix_sht,
451 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
452 .pio_mask = 0x1f, /* pio 0-4 */
453 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
454 .udma_mask = ATA_UDMA2, /* UDMA33 */
455 .port_ops = &ich_pata_ops,
456 },
457 /* ich_pata_66: 2 ICH controllers up to 66MHz */
458 {
459 .sht = &piix_sht,
460 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
461 .pio_mask = 0x1f, /* pio 0-4 */
462 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
463 .udma_mask = ATA_UDMA4,
464 .port_ops = &ich_pata_ops,
465 },
466
467 /* ich_pata_100: 3 */
468 {
469 .sht = &piix_sht,
470 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
471 .pio_mask = 0x1f, /* pio0-4 */
472 .mwdma_mask = 0x06, /* mwdma1-2 */
473 .udma_mask = ATA_UDMA5, /* udma0-5 */
474 .port_ops = &ich_pata_ops,
475 },
476
477 /* ich_pata_133: 4 ICH with full UDMA6 */
478 {
479 .sht = &piix_sht,
480 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
481 .pio_mask = 0x1f, /* pio 0-4 */
482 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
483 .udma_mask = ATA_UDMA6, /* UDMA133 */
484 .port_ops = &ich_pata_ops,
485 },
486
487 /* ich5_sata: 5 */
488 {
489 .sht = &piix_sht,
490 .flags = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR |
491 PIIX_FLAG_IGNORE_PCS,
492 .pio_mask = 0x1f, /* pio0-4 */
493 .mwdma_mask = 0x07, /* mwdma0-2 */
494 .udma_mask = 0x7f, /* udma0-6 */
495 .port_ops = &piix_sata_ops,
496 },
497
498 /* i6300esb_sata: 6 */
499 {
500 .sht = &piix_sht,
501 .flags = ATA_FLAG_SATA |
502 PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS,
503 .pio_mask = 0x1f, /* pio0-4 */
504 .mwdma_mask = 0x07, /* mwdma0-2 */
505 .udma_mask = 0x7f, /* udma0-6 */
506 .port_ops = &piix_sata_ops,
507 },
508
509 /* ich6_sata: 7 */
510 {
511 .sht = &piix_sht,
512 .flags = ATA_FLAG_SATA |
513 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR,
514 .pio_mask = 0x1f, /* pio0-4 */
515 .mwdma_mask = 0x07, /* mwdma0-2 */
516 .udma_mask = 0x7f, /* udma0-6 */
517 .port_ops = &piix_sata_ops,
518 },
519
520 /* ich6_sata_ahci: 8 */
521 {
522 .sht = &piix_sht,
523 .flags = ATA_FLAG_SATA |
524 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
525 PIIX_FLAG_AHCI,
526 .pio_mask = 0x1f, /* pio0-4 */
527 .mwdma_mask = 0x07, /* mwdma0-2 */
528 .udma_mask = 0x7f, /* udma0-6 */
529 .port_ops = &piix_sata_ops,
530 },
531
532 /* ich6m_sata_ahci: 9 */
533 {
534 .sht = &piix_sht,
535 .flags = ATA_FLAG_SATA |
536 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
537 PIIX_FLAG_AHCI,
538 .pio_mask = 0x1f, /* pio0-4 */
539 .mwdma_mask = 0x07, /* mwdma0-2 */
540 .udma_mask = 0x7f, /* udma0-6 */
541 .port_ops = &piix_sata_ops,
542 },
543
544 /* ich8_sata_ahci: 10 */
545 {
546 .sht = &piix_sht,
547 .flags = ATA_FLAG_SATA |
548 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
549 PIIX_FLAG_AHCI,
550 .pio_mask = 0x1f, /* pio0-4 */
551 .mwdma_mask = 0x07, /* mwdma0-2 */
552 .udma_mask = 0x7f, /* udma0-6 */
553 .port_ops = &piix_sata_ops,
554 },
555
556 };
557
558 static struct pci_bits piix_enable_bits[] = {
559 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
560 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
561 };
562
563 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
564 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
565 MODULE_LICENSE("GPL");
566 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
567 MODULE_VERSION(DRV_VERSION);
568
569 static int force_pcs = 0;
570 module_param(force_pcs, int, 0444);
571 MODULE_PARM_DESC(force_pcs, "force honoring or ignoring PCS to work around "
572 "device mis-detection (0=default, 1=ignore PCS, 2=honor PCS)");
573
574 /**
575 * piix_pata_cbl_detect - Probe host controller cable detect info
576 * @ap: Port for which cable detect info is desired
577 *
578 * Read 80c cable indicator from ATA PCI device's PCI config
579 * register. This register is normally set by firmware (BIOS).
580 *
581 * LOCKING:
582 * None (inherited from caller).
583 */
584
585 static void ich_pata_cbl_detect(struct ata_port *ap)
586 {
587 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
588 u8 tmp, mask;
589
590 /* no 80c support in host controller? */
591 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
592 goto cbl40;
593
594 /* check BIOS cable detect results */
595 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
596 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
597 if ((tmp & mask) == 0)
598 goto cbl40;
599
600 ap->cbl = ATA_CBL_PATA80;
601 return;
602
603 cbl40:
604 ap->cbl = ATA_CBL_PATA40;
605 }
606
607 /**
608 * piix_pata_prereset - prereset for PATA host controller
609 * @ap: Target port
610 *
611 *
612 * LOCKING:
613 * None (inherited from caller).
614 */
615 static int piix_pata_prereset(struct ata_port *ap)
616 {
617 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
618
619 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
620 return -ENOENT;
621
622 ap->cbl = ATA_CBL_PATA40;
623 return ata_std_prereset(ap);
624 }
625
626 static void piix_pata_error_handler(struct ata_port *ap)
627 {
628 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
629 ata_std_postreset);
630 }
631
632
633 /**
634 * ich_pata_prereset - prereset for PATA host controller
635 * @ap: Target port
636 *
637 *
638 * LOCKING:
639 * None (inherited from caller).
640 */
641 static int ich_pata_prereset(struct ata_port *ap)
642 {
643 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
644
645 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) {
646 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
647 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
648 return 0;
649 }
650
651 ich_pata_cbl_detect(ap);
652
653 return ata_std_prereset(ap);
654 }
655
656 static void ich_pata_error_handler(struct ata_port *ap)
657 {
658 ata_bmdma_drive_eh(ap, ich_pata_prereset, ata_std_softreset, NULL,
659 ata_std_postreset);
660 }
661
662 /**
663 * piix_sata_present_mask - determine present mask for SATA host controller
664 * @ap: Target port
665 *
666 * Reads SATA PCI device's PCI config register Port Configuration
667 * and Status (PCS) to determine port and device availability.
668 *
669 * LOCKING:
670 * None (inherited from caller).
671 *
672 * RETURNS:
673 * determined present_mask
674 */
675 static unsigned int piix_sata_present_mask(struct ata_port *ap)
676 {
677 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
678 struct piix_host_priv *hpriv = ap->host->private_data;
679 const unsigned int *map = hpriv->map;
680 int base = 2 * ap->port_no;
681 unsigned int present_mask = 0;
682 int port, i;
683 u16 pcs;
684
685 pci_read_config_word(pdev, ICH5_PCS, &pcs);
686 DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base);
687
688 for (i = 0; i < 2; i++) {
689 port = map[base + i];
690 if (port < 0)
691 continue;
692 if ((ap->flags & PIIX_FLAG_IGNORE_PCS) ||
693 (pcs & 1 << (hpriv->map_db->present_shift + port)))
694 present_mask |= 1 << i;
695 }
696
697 DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n",
698 ap->id, pcs, present_mask);
699
700 return present_mask;
701 }
702
703 /**
704 * piix_sata_softreset - reset SATA host port via ATA SRST
705 * @ap: port to reset
706 * @classes: resulting classes of attached devices
707 *
708 * Reset SATA host port via ATA SRST. On controllers with
709 * reliable PCS present bits, the bits are used to determine
710 * device presence.
711 *
712 * LOCKING:
713 * Kernel thread context (may sleep)
714 *
715 * RETURNS:
716 * 0 on success, -errno otherwise.
717 */
718 static int piix_sata_softreset(struct ata_port *ap, unsigned int *classes)
719 {
720 unsigned int present_mask;
721 int i, rc;
722
723 present_mask = piix_sata_present_mask(ap);
724
725 rc = ata_std_softreset(ap, classes);
726 if (rc)
727 return rc;
728
729 for (i = 0; i < ATA_MAX_DEVICES; i++) {
730 if (!(present_mask & (1 << i)))
731 classes[i] = ATA_DEV_NONE;
732 }
733
734 return 0;
735 }
736
737 static void piix_sata_error_handler(struct ata_port *ap)
738 {
739 ata_bmdma_drive_eh(ap, ata_std_prereset, piix_sata_softreset, NULL,
740 ata_std_postreset);
741 }
742
743 /**
744 * piix_set_piomode - Initialize host controller PATA PIO timings
745 * @ap: Port whose timings we are configuring
746 * @adev: um
747 *
748 * Set PIO mode for device, in host controller PCI config space.
749 *
750 * LOCKING:
751 * None (inherited from caller).
752 */
753
754 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
755 {
756 unsigned int pio = adev->pio_mode - XFER_PIO_0;
757 struct pci_dev *dev = to_pci_dev(ap->host->dev);
758 unsigned int is_slave = (adev->devno != 0);
759 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
760 unsigned int slave_port = 0x44;
761 u16 master_data;
762 u8 slave_data;
763 u8 udma_enable;
764 int control = 0;
765
766 /*
767 * See Intel Document 298600-004 for the timing programing rules
768 * for ICH controllers.
769 */
770
771 static const /* ISP RTC */
772 u8 timings[][2] = { { 0, 0 },
773 { 0, 0 },
774 { 1, 0 },
775 { 2, 1 },
776 { 2, 3 }, };
777
778 if (pio >= 2)
779 control |= 1; /* TIME1 enable */
780 if (ata_pio_need_iordy(adev))
781 control |= 2; /* IE enable */
782
783 /* Intel specifies that the PPE functionality is for disk only */
784 if (adev->class == ATA_DEV_ATA)
785 control |= 4; /* PPE enable */
786
787 pci_read_config_word(dev, master_port, &master_data);
788 if (is_slave) {
789 /* Enable SITRE (seperate slave timing register) */
790 master_data |= 0x4000;
791 /* enable PPE1, IE1 and TIME1 as needed */
792 master_data |= (control << 4);
793 pci_read_config_byte(dev, slave_port, &slave_data);
794 slave_data &= (ap->port_no ? 0x0f : 0xf0);
795 /* Load the timing nibble for this slave */
796 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
797 } else {
798 /* Master keeps the bits in a different format */
799 master_data &= 0xccf8;
800 /* Enable PPE, IE and TIME as appropriate */
801 master_data |= control;
802 master_data |=
803 (timings[pio][0] << 12) |
804 (timings[pio][1] << 8);
805 }
806 pci_write_config_word(dev, master_port, master_data);
807 if (is_slave)
808 pci_write_config_byte(dev, slave_port, slave_data);
809
810 /* Ensure the UDMA bit is off - it will be turned back on if
811 UDMA is selected */
812
813 if (ap->udma_mask) {
814 pci_read_config_byte(dev, 0x48, &udma_enable);
815 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
816 pci_write_config_byte(dev, 0x48, udma_enable);
817 }
818 }
819
820 /**
821 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
822 * @ap: Port whose timings we are configuring
823 * @adev: Drive in question
824 * @udma: udma mode, 0 - 6
825 * @isich: set if the chip is an ICH device
826 *
827 * Set UDMA mode for device, in host controller PCI config space.
828 *
829 * LOCKING:
830 * None (inherited from caller).
831 */
832
833 static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
834 {
835 struct pci_dev *dev = to_pci_dev(ap->host->dev);
836 u8 master_port = ap->port_no ? 0x42 : 0x40;
837 u16 master_data;
838 u8 speed = adev->dma_mode;
839 int devid = adev->devno + 2 * ap->port_no;
840 u8 udma_enable;
841
842 static const /* ISP RTC */
843 u8 timings[][2] = { { 0, 0 },
844 { 0, 0 },
845 { 1, 0 },
846 { 2, 1 },
847 { 2, 3 }, };
848
849 pci_read_config_word(dev, master_port, &master_data);
850 pci_read_config_byte(dev, 0x48, &udma_enable);
851
852 if (speed >= XFER_UDMA_0) {
853 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
854 u16 udma_timing;
855 u16 ideconf;
856 int u_clock, u_speed;
857
858 /*
859 * UDMA is handled by a combination of clock switching and
860 * selection of dividers
861 *
862 * Handy rule: Odd modes are UDMATIMx 01, even are 02
863 * except UDMA0 which is 00
864 */
865 u_speed = min(2 - (udma & 1), udma);
866 if (udma == 5)
867 u_clock = 0x1000; /* 100Mhz */
868 else if (udma > 2)
869 u_clock = 1; /* 66Mhz */
870 else
871 u_clock = 0; /* 33Mhz */
872
873 udma_enable |= (1 << devid);
874
875 /* Load the CT/RP selection */
876 pci_read_config_word(dev, 0x4A, &udma_timing);
877 udma_timing &= ~(3 << (4 * devid));
878 udma_timing |= u_speed << (4 * devid);
879 pci_write_config_word(dev, 0x4A, udma_timing);
880
881 if (isich) {
882 /* Select a 33/66/100Mhz clock */
883 pci_read_config_word(dev, 0x54, &ideconf);
884 ideconf &= ~(0x1001 << devid);
885 ideconf |= u_clock << devid;
886 /* For ICH or later we should set bit 10 for better
887 performance (WR_PingPong_En) */
888 pci_write_config_word(dev, 0x54, ideconf);
889 }
890 } else {
891 /*
892 * MWDMA is driven by the PIO timings. We must also enable
893 * IORDY unconditionally along with TIME1. PPE has already
894 * been set when the PIO timing was set.
895 */
896 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
897 unsigned int control;
898 u8 slave_data;
899 const unsigned int needed_pio[3] = {
900 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
901 };
902 int pio = needed_pio[mwdma] - XFER_PIO_0;
903
904 control = 3; /* IORDY|TIME1 */
905
906 /* If the drive MWDMA is faster than it can do PIO then
907 we must force PIO into PIO0 */
908
909 if (adev->pio_mode < needed_pio[mwdma])
910 /* Enable DMA timing only */
911 control |= 8; /* PIO cycles in PIO0 */
912
913 if (adev->devno) { /* Slave */
914 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
915 master_data |= control << 4;
916 pci_read_config_byte(dev, 0x44, &slave_data);
917 slave_data &= (0x0F + 0xE1 * ap->port_no);
918 /* Load the matching timing */
919 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
920 pci_write_config_byte(dev, 0x44, slave_data);
921 } else { /* Master */
922 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
923 and master timing bits */
924 master_data |= control;
925 master_data |=
926 (timings[pio][0] << 12) |
927 (timings[pio][1] << 8);
928 }
929 udma_enable &= ~(1 << devid);
930 pci_write_config_word(dev, master_port, master_data);
931 }
932 /* Don't scribble on 0x48 if the controller does not support UDMA */
933 if (ap->udma_mask)
934 pci_write_config_byte(dev, 0x48, udma_enable);
935 }
936
937 /**
938 * piix_set_dmamode - Initialize host controller PATA DMA timings
939 * @ap: Port whose timings we are configuring
940 * @adev: um
941 *
942 * Set MW/UDMA mode for device, in host controller PCI config space.
943 *
944 * LOCKING:
945 * None (inherited from caller).
946 */
947
948 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
949 {
950 do_pata_set_dmamode(ap, adev, 0);
951 }
952
953 /**
954 * ich_set_dmamode - Initialize host controller PATA DMA timings
955 * @ap: Port whose timings we are configuring
956 * @adev: um
957 *
958 * Set MW/UDMA mode for device, in host controller PCI config space.
959 *
960 * LOCKING:
961 * None (inherited from caller).
962 */
963
964 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
965 {
966 do_pata_set_dmamode(ap, adev, 1);
967 }
968
969 #define AHCI_PCI_BAR 5
970 #define AHCI_GLOBAL_CTL 0x04
971 #define AHCI_ENABLE (1 << 31)
972 static int piix_disable_ahci(struct pci_dev *pdev)
973 {
974 void __iomem *mmio;
975 u32 tmp;
976 int rc = 0;
977
978 /* BUG: pci_enable_device has not yet been called. This
979 * works because this device is usually set up by BIOS.
980 */
981
982 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
983 !pci_resource_len(pdev, AHCI_PCI_BAR))
984 return 0;
985
986 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
987 if (!mmio)
988 return -ENOMEM;
989
990 tmp = readl(mmio + AHCI_GLOBAL_CTL);
991 if (tmp & AHCI_ENABLE) {
992 tmp &= ~AHCI_ENABLE;
993 writel(tmp, mmio + AHCI_GLOBAL_CTL);
994
995 tmp = readl(mmio + AHCI_GLOBAL_CTL);
996 if (tmp & AHCI_ENABLE)
997 rc = -EIO;
998 }
999
1000 pci_iounmap(pdev, mmio);
1001 return rc;
1002 }
1003
1004 /**
1005 * piix_check_450nx_errata - Check for problem 450NX setup
1006 * @ata_dev: the PCI device to check
1007 *
1008 * Check for the present of 450NX errata #19 and errata #25. If
1009 * they are found return an error code so we can turn off DMA
1010 */
1011
1012 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1013 {
1014 struct pci_dev *pdev = NULL;
1015 u16 cfg;
1016 u8 rev;
1017 int no_piix_dma = 0;
1018
1019 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
1020 {
1021 /* Look for 450NX PXB. Check for problem configurations
1022 A PCI quirk checks bit 6 already */
1023 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
1024 pci_read_config_word(pdev, 0x41, &cfg);
1025 /* Only on the original revision: IDE DMA can hang */
1026 if (rev == 0x00)
1027 no_piix_dma = 1;
1028 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1029 else if (cfg & (1<<14) && rev < 5)
1030 no_piix_dma = 2;
1031 }
1032 if (no_piix_dma)
1033 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1034 if (no_piix_dma == 2)
1035 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1036 return no_piix_dma;
1037 }
1038
1039 static void __devinit piix_init_pcs(struct pci_dev *pdev,
1040 struct ata_port_info *pinfo,
1041 const struct piix_map_db *map_db)
1042 {
1043 u16 pcs, new_pcs;
1044
1045 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1046
1047 new_pcs = pcs | map_db->port_enable;
1048
1049 if (new_pcs != pcs) {
1050 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1051 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1052 msleep(150);
1053 }
1054
1055 if (force_pcs == 1) {
1056 dev_printk(KERN_INFO, &pdev->dev,
1057 "force ignoring PCS (0x%x)\n", new_pcs);
1058 pinfo[0].flags |= PIIX_FLAG_IGNORE_PCS;
1059 pinfo[1].flags |= PIIX_FLAG_IGNORE_PCS;
1060 } else if (force_pcs == 2) {
1061 dev_printk(KERN_INFO, &pdev->dev,
1062 "force honoring PCS (0x%x)\n", new_pcs);
1063 pinfo[0].flags &= ~PIIX_FLAG_IGNORE_PCS;
1064 pinfo[1].flags &= ~PIIX_FLAG_IGNORE_PCS;
1065 }
1066 }
1067
1068 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
1069 struct ata_port_info *pinfo,
1070 const struct piix_map_db *map_db)
1071 {
1072 struct piix_host_priv *hpriv = pinfo[0].private_data;
1073 const unsigned int *map;
1074 int i, invalid_map = 0;
1075 u8 map_value;
1076
1077 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1078
1079 map = map_db->map[map_value & map_db->mask];
1080
1081 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1082 for (i = 0; i < 4; i++) {
1083 switch (map[i]) {
1084 case RV:
1085 invalid_map = 1;
1086 printk(" XX");
1087 break;
1088
1089 case NA:
1090 printk(" --");
1091 break;
1092
1093 case IDE:
1094 WARN_ON((i & 1) || map[i + 1] != IDE);
1095 pinfo[i / 2] = piix_port_info[ich_pata_100];
1096 pinfo[i / 2].private_data = hpriv;
1097 i++;
1098 printk(" IDE IDE");
1099 break;
1100
1101 default:
1102 printk(" P%d", map[i]);
1103 if (i & 1)
1104 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1105 break;
1106 }
1107 }
1108 printk(" ]\n");
1109
1110 if (invalid_map)
1111 dev_printk(KERN_ERR, &pdev->dev,
1112 "invalid MAP value %u\n", map_value);
1113
1114 hpriv->map = map;
1115 hpriv->map_db = map_db;
1116 }
1117
1118 /**
1119 * piix_init_one - Register PIIX ATA PCI device with kernel services
1120 * @pdev: PCI device to register
1121 * @ent: Entry in piix_pci_tbl matching with @pdev
1122 *
1123 * Called from kernel PCI layer. We probe for combined mode (sigh),
1124 * and then hand over control to libata, for it to do the rest.
1125 *
1126 * LOCKING:
1127 * Inherited from PCI layer (may sleep).
1128 *
1129 * RETURNS:
1130 * Zero on success, or -ERRNO value.
1131 */
1132
1133 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1134 {
1135 static int printed_version;
1136 struct ata_port_info port_info[2];
1137 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
1138 struct piix_host_priv *hpriv;
1139 unsigned long port_flags;
1140
1141 if (!printed_version++)
1142 dev_printk(KERN_DEBUG, &pdev->dev,
1143 "version " DRV_VERSION "\n");
1144
1145 /* no hotplugging support (FIXME) */
1146 if (!in_module_init)
1147 return -ENODEV;
1148
1149 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
1150 if (!hpriv)
1151 return -ENOMEM;
1152
1153 port_info[0] = piix_port_info[ent->driver_data];
1154 port_info[1] = piix_port_info[ent->driver_data];
1155 port_info[0].private_data = hpriv;
1156 port_info[1].private_data = hpriv;
1157
1158 port_flags = port_info[0].flags;
1159
1160 if (port_flags & PIIX_FLAG_AHCI) {
1161 u8 tmp;
1162 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1163 if (tmp == PIIX_AHCI_DEVICE) {
1164 int rc = piix_disable_ahci(pdev);
1165 if (rc)
1166 return rc;
1167 }
1168 }
1169
1170 /* Initialize SATA map */
1171 if (port_flags & ATA_FLAG_SATA) {
1172 piix_init_sata_map(pdev, port_info,
1173 piix_map_db_table[ent->driver_data]);
1174 piix_init_pcs(pdev, port_info,
1175 piix_map_db_table[ent->driver_data]);
1176 }
1177
1178 /* On ICH5, some BIOSen disable the interrupt using the
1179 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1180 * On ICH6, this bit has the same effect, but only when
1181 * MSI is disabled (and it is disabled, as we don't use
1182 * message-signalled interrupts currently).
1183 */
1184 if (port_flags & PIIX_FLAG_CHECKINTR)
1185 pci_intx(pdev, 1);
1186
1187 if (piix_check_450nx_errata(pdev)) {
1188 /* This writes into the master table but it does not
1189 really matter for this errata as we will apply it to
1190 all the PIIX devices on the board */
1191 port_info[0].mwdma_mask = 0;
1192 port_info[0].udma_mask = 0;
1193 port_info[1].mwdma_mask = 0;
1194 port_info[1].udma_mask = 0;
1195 }
1196 return ata_pci_init_one(pdev, ppinfo, 2);
1197 }
1198
1199 static void piix_host_stop(struct ata_host *host)
1200 {
1201 struct piix_host_priv *hpriv = host->private_data;
1202
1203 ata_host_stop(host);
1204
1205 kfree(hpriv);
1206 }
1207
1208 static int __init piix_init(void)
1209 {
1210 int rc;
1211
1212 DPRINTK("pci_register_driver\n");
1213 rc = pci_register_driver(&piix_pci_driver);
1214 if (rc)
1215 return rc;
1216
1217 in_module_init = 0;
1218
1219 DPRINTK("done\n");
1220 return 0;
1221 }
1222
1223 static void __exit piix_exit(void)
1224 {
1225 pci_unregister_driver(&piix_pci_driver);
1226 }
1227
1228 module_init(piix_init);
1229 module_exit(piix_exit);
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