STM32H757xx HAL User Manual: stm32h7xx_ll_tim.h Source File

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stm32h7xx_ll_tim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_tim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TIM LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef __STM32H7xx_LL_TIM_H
00022 #define __STM32H7xx_LL_TIM_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
00036
00037 /** @defgroup TIM_LL TIM
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
00044   * @{
00045   */
00046 static const uint8_t OFFSET_TAB_CCMRx[] =
00047 {
00048   0x00U,   /* 0: TIMx_CH1  */
00049   0x00U,   /* 1: TIMx_CH1N */
00050   0x00U,   /* 2: TIMx_CH2  */
00051   0x00U,   /* 3: TIMx_CH2N */
00052   0x04U,   /* 4: TIMx_CH3  */
00053   0x04U,   /* 5: TIMx_CH3N */
00054   0x04U,   /* 6: TIMx_CH4  */
00055   0x3CU,   /* 7: TIMx_CH5  */
00056   0x3CU    /* 8: TIMx_CH6  */
00057 };
00058
00059 static const uint8_t SHIFT_TAB_OCxx[] =
00060 {
00061   0U,            /* 0: OC1M, OC1FE, OC1PE */
00062   0U,            /* 1: - NA */
00063   8U,            /* 2: OC2M, OC2FE, OC2PE */
00064   0U,            /* 3: - NA */
00065   0U,            /* 4: OC3M, OC3FE, OC3PE */
00066   0U,            /* 5: - NA */
00067   8U,            /* 6: OC4M, OC4FE, OC4PE */
00068   0U,            /* 7: OC5M, OC5FE, OC5PE */
00069   8U             /* 8: OC6M, OC6FE, OC6PE */
00070 };
00071
00072 static const uint8_t SHIFT_TAB_ICxx[] =
00073 {
00074   0U,            /* 0: CC1S, IC1PSC, IC1F */
00075   0U,            /* 1: - NA */
00076   8U,            /* 2: CC2S, IC2PSC, IC2F */
00077   0U,            /* 3: - NA */
00078   0U,            /* 4: CC3S, IC3PSC, IC3F */
00079   0U,            /* 5: - NA */
00080   8U,            /* 6: CC4S, IC4PSC, IC4F */
00081   0U,            /* 7: - NA */
00082   0U             /* 8: - NA */
00083 };
00084
00085 static const uint8_t SHIFT_TAB_CCxP[] =
00086 {
00087   0U,            /* 0: CC1P */
00088   2U,            /* 1: CC1NP */
00089   4U,            /* 2: CC2P */
00090   6U,            /* 3: CC2NP */
00091   8U,            /* 4: CC3P */
00092   10U,           /* 5: CC3NP */
00093   12U,           /* 6: CC4P */
00094   16U,           /* 7: CC5P */
00095   20U            /* 8: CC6P */
00096 };
00097
00098 static const uint8_t SHIFT_TAB_OISx[] =
00099 {
00100   0U,            /* 0: OIS1 */
00101   1U,            /* 1: OIS1N */
00102   2U,            /* 2: OIS2 */
00103   3U,            /* 3: OIS2N */
00104   4U,            /* 4: OIS3 */
00105   5U,            /* 5: OIS3N */
00106   6U,            /* 6: OIS4 */
00107   8U,            /* 7: OIS5 */
00108   10U            /* 8: OIS6 */
00109 };
00110 /**
00111   * @}
00112   */
00113
00114 /* Private constants ---------------------------------------------------------*/
00115 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
00116   * @{
00117   */
00118
00119 #if   defined(TIM_BREAK_INPUT_SUPPORT)
00120 /* Defines used for the bit position in the register and perform offsets */
00121 #define TIM_POSITION_BRK_SOURCE            (POSITION_VAL(Source) & 0x1FUL)
00122
00123 /* Generic bit definitions for TIMx_AF1 register */
00124 #define TIMx_AF1_BKINE     TIM1_AF1_BKINE     /*!< BRK BKIN input enable */
00125 #define TIMx_AF1_BKCOMP1E  TIM1_AF1_BKCMP1E   /*!< BRK COMP1 enable */
00126 #define TIMx_AF1_BKCOMP2E  TIM1_AF1_BKCMP2E   /*!< BRK COMP2 enable */
00127 #define TIMx_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E /*!< BRK DFSDM1_BREAK[0] enable */
00128 #define TIMx_AF1_BKINP     TIM1_AF1_BKINP     /*!< BRK BKIN input polarity */
00129 #define TIMx_AF1_BKCOMP1P  TIM1_AF1_BKCMP1P   /*!< BRK COMP1 input polarity */
00130 #define TIMx_AF1_BKCOMP2P  TIM1_AF1_BKCMP2P   /*!< BRK COMP2 input polarity */
00131 #define TIMx_AF1_ETRSEL    TIM1_AF1_ETRSEL    /*!< TIMx ETR source selection */
00132
00133 /* Generic bit definitions for TIMx_AF2 register */
00134 #define TIMx_AF2_BK2INE    TIM1_AF2_BK2INE      /*!< BRK2 BKIN2 input enable */
00135 #define TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E    /*!< BRK2 COMP1 enable */
00136 #define TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E    /*!< BRK2 COMP2 enable */
00137 #define TIMx_AF2_BK2DF1BK1E TIM1_AF2_BK2DF1BK1E /*!< BRK2 DFSDM1_BREAK[1] enable */
00138 #define TIMx_AF2_BK2INP    TIM1_AF2_BK2INP      /*!< BRK2 BKIN2 input polarity */
00139 #define TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P    /*!< BRK2 COMP1 input polarity */
00140 #define TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P    /*!< BRK2 COMP2 input polarity */
00141 #endif /* TIM_BREAK_INPUT_SUPPORT */
00142
00143
00144 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
00145 #define DT_DELAY_1 ((uint8_t)0x7F)
00146 #define DT_DELAY_2 ((uint8_t)0x3F)
00147 #define DT_DELAY_3 ((uint8_t)0x1F)
00148 #define DT_DELAY_4 ((uint8_t)0x1F)
00149
00150 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
00151 #define DT_RANGE_1 ((uint8_t)0x00)
00152 #define DT_RANGE_2 ((uint8_t)0x80)
00153 #define DT_RANGE_3 ((uint8_t)0xC0)
00154 #define DT_RANGE_4 ((uint8_t)0xE0)
00155
00156
00157 /**
00158   * @}
00159   */
00160
00161 /* Private macros ------------------------------------------------------------*/
00162 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
00163   * @{
00164   */
00165 /** @brief  Convert channel id into channel index.
00166   * @param  __CHANNEL__ This parameter can be one of the following values:
00167   *         @arg @ref LL_TIM_CHANNEL_CH1
00168   *         @arg @ref LL_TIM_CHANNEL_CH1N
00169   *         @arg @ref LL_TIM_CHANNEL_CH2
00170   *         @arg @ref LL_TIM_CHANNEL_CH2N
00171   *         @arg @ref LL_TIM_CHANNEL_CH3
00172   *         @arg @ref LL_TIM_CHANNEL_CH3N
00173   *         @arg @ref LL_TIM_CHANNEL_CH4
00174   *         @arg @ref LL_TIM_CHANNEL_CH5
00175   *         @arg @ref LL_TIM_CHANNEL_CH6
00176   * @retval none
00177   */
00178 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
00179   (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
00180    ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
00181    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
00182    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
00183    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
00184    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
00185    ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
00186    ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
00187
00188 /** @brief  Calculate the deadtime sampling period(in ps).
00189   * @param  __TIMCLK__ timer input clock frequency (in Hz).
00190   * @param  __CKD__ This parameter can be one of the following values:
00191   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
00192   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
00193   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
00194   * @retval none
00195   */
00196 #define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
00197   (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
00198    ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
00199    ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
00200 /**
00201   * @}
00202   */
00203
00204
00205 /* Exported types ------------------------------------------------------------*/
00206 #if defined(USE_FULL_LL_DRIVER)
00207 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
00208   * @{
00209   */
00210
00211 /**
00212   * @brief  TIM Time Base configuration structure definition.
00213   */
00214 typedef struct
00215 {
00216   uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00217                                    This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00218
00219                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
00220
00221   uint32_t CounterMode;       /*!< Specifies the counter mode.
00222                                    This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
00223
00224                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
00225
00226   uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
00227                                    Auto-Reload Register at the next update event.
00228                                    This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00229                                    Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
00230
00231                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
00232
00233   uint32_t ClockDivision;     /*!< Specifies the clock division.
00234                                    This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
00235
00236                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
00237
00238   uint8_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00239                                    reaches zero, an update event is generated and counting restarts
00240                                    from the RCR value (N).
00241                                    This means in PWM mode that (N+1) corresponds to:
00242                                       - the number of PWM periods in edge-aligned mode
00243                                       - the number of half PWM period in center-aligned mode
00244                                    This parameter must be a number between 0x00 and 0xFF.
00245
00246                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
00247 } LL_TIM_InitTypeDef;
00248
00249 /**
00250   * @brief  TIM Output Compare configuration structure definition.
00251   */
00252 typedef struct
00253 {
00254   uint32_t OCMode;        /*!< Specifies the output mode.
00255                                This parameter can be a value of @ref TIM_LL_EC_OCMODE.
00256
00257                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
00258
00259   uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
00260                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
00261
00262                                This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
00263
00264   uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
00265                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
00266
00267                                This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
00268
00269   uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
00270                                This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00271
00272                                This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
00273
00274   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00275                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
00276
00277                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
00278
00279   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00280                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
00281
00282                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
00283
00284
00285   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00286                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
00287
00288                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
00289
00290   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00291                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
00292
00293                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
00294 } LL_TIM_OC_InitTypeDef;
00295
00296 /**
00297   * @brief  TIM Input Capture configuration structure definition.
00298   */
00299
00300 typedef struct
00301 {
00302
00303   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00304                                This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00305
00306                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00307
00308   uint32_t ICActiveInput; /*!< Specifies the input.
00309                                This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00310
00311                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00312
00313   uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
00314                                This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00315
00316                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00317
00318   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00319                                This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00320
00321                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00322 } LL_TIM_IC_InitTypeDef;
00323
00324
00325 /**
00326   * @brief  TIM Encoder interface configuration structure definition.
00327   */
00328 typedef struct
00329 {
00330   uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
00331                                  This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
00332
00333                                  This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
00334
00335   uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
00336                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00337
00338                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00339
00340   uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
00341                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00342
00343                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00344
00345   uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
00346                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00347
00348                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00349
00350   uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
00351                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00352
00353                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00354
00355   uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
00356                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00357
00358                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00359
00360   uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
00361                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00362
00363                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00364
00365   uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
00366                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00367
00368                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00369
00370   uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
00371                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00372
00373                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00374
00375 } LL_TIM_ENCODER_InitTypeDef;
00376
00377 /**
00378   * @brief  TIM Hall sensor interface configuration structure definition.
00379   */
00380 typedef struct
00381 {
00382
00383   uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
00384                                     This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00385
00386                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00387
00388   uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
00389                                     Prescaler must be set to get a maximum counter period longer than the
00390                                     time interval between 2 consecutive changes on the Hall inputs.
00391                                     This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00392
00393                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00394
00395   uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
00396                                     This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00397
00398                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00399
00400   uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
00401                                     A positive pulse (TRGO event) is generated with a programmable delay every time
00402                                     a change occurs on the Hall inputs.
00403                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
00404
00405                                     This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
00406 } LL_TIM_HALLSENSOR_InitTypeDef;
00407
00408 /**
00409   * @brief  BDTR (Break and Dead Time) structure definition
00410   */
00411 typedef struct
00412 {
00413   uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
00414                                       This parameter can be a value of @ref TIM_LL_EC_OSSR
00415
00416                                       This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
00417
00418                                       @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
00419
00420   uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
00421                                       This parameter can be a value of @ref TIM_LL_EC_OSSI
00422
00423                                       This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
00424
00425                                       @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
00426
00427   uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
00428                                       This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
00429
00430                                       @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
00431                                             has been written, their content is frozen until the next reset.*/
00432
00433   uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
00434                                       switching-on of the outputs.
00435                                       This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00436
00437                                       This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
00438
00439                                       @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
00440
00441   uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
00442                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
00443
00444                                       This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
00445
00446                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00447
00448   uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
00449                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
00450
00451                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
00452
00453                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00454
00455   uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
00456                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
00457
00458                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
00459
00460                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00461
00462   uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
00463                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
00464
00465                                       This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
00466
00467                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00468
00469   uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
00470                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
00471
00472                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
00473
00474                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00475
00476   uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
00477                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
00478
00479                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
00480
00481                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00482
00483   uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
00484                                       This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
00485
00486                                       This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
00487
00488                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00489 } LL_TIM_BDTR_InitTypeDef;
00490
00491 /**
00492   * @}
00493   */
00494 #endif /* USE_FULL_LL_DRIVER */
00495
00496 /* Exported constants --------------------------------------------------------*/
00497 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
00498   * @{
00499   */
00500
00501 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
00502   * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
00503   * @{
00504   */
00505 #define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
00506 #define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
00507 #define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
00508 #define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
00509 #define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
00510 #define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */
00511 #define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */
00512 #define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
00513 #define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
00514 #define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
00515 #define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */
00516 #define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
00517 #define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
00518 #define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
00519 #define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
00520 #define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt flag  */
00521 /**
00522   * @}
00523   */
00524
00525 #if defined(USE_FULL_LL_DRIVER)
00526 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
00527   * @{
00528   */
00529 #define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
00530 #define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
00531 /**
00532   * @}
00533   */
00534
00535 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
00536   * @{
00537   */
00538 #define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
00539 #define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
00540 /**
00541   * @}
00542   */
00543
00544 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
00545   * @{
00546   */
00547 #define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
00548 #define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
00549 /**
00550   * @}
00551   */
00552 #endif /* USE_FULL_LL_DRIVER */
00553
00554 /** @defgroup TIM_LL_EC_IT IT Defines
00555   * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
00556   * @{
00557   */
00558 #define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
00559 #define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
00560 #define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
00561 #define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
00562 #define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
00563 #define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
00564 #define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
00565 #define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
00566 /**
00567   * @}
00568   */
00569
00570 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
00571   * @{
00572   */
00573 #define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
00574 #define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
00575 /**
00576   * @}
00577   */
00578
00579 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
00580   * @{
00581   */
00582 #define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter is not stopped at update event */
00583 #define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter stops counting at the next update event */
00584 /**
00585   * @}
00586   */
00587
00588 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
00589   * @{
00590   */
00591 #define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
00592 #define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
00593 #define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
00594 #define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
00595 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
00596 /**
00597   * @}
00598   */
00599
00600 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
00601   * @{
00602   */
00603 #define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
00604 #define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
00605 #define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
00606 /**
00607   * @}
00608   */
00609
00610 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
00611   * @{
00612   */
00613 #define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
00614 #define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
00615 /**
00616   * @}
00617   */
00618
00619 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
00620   * @{
00621   */
00622 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
00623 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
00624 /**
00625   * @}
00626   */
00627
00628 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
00629   * @{
00630   */
00631 #define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
00632 #define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
00633 /**
00634   * @}
00635   */
00636
00637 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
00638   * @{
00639   */
00640 #define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
00641 #define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
00642 #define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
00643 #define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
00644 /**
00645   * @}
00646   */
00647
00648 /** @defgroup TIM_LL_EC_CHANNEL Channel
00649   * @{
00650   */
00651 #define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
00652 #define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
00653 #define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
00654 #define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
00655 #define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
00656 #define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
00657 #define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
00658 #define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
00659 #define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
00660 /**
00661   * @}
00662   */
00663
00664 #if defined(USE_FULL_LL_DRIVER)
00665 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
00666   * @{
00667   */
00668 #define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
00669 #define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
00670 /**
00671   * @}
00672   */
00673 #endif /* USE_FULL_LL_DRIVER */
00674
00675 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
00676   * @{
00677   */
00678 #define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
00679 #define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
00680 #define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
00681 #define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
00682 #define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
00683 #define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
00684 #define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
00685 #define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
00686 #define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/
00687 #define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/
00688 #define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/
00689 #define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
00690 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
00691 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
00692 /**
00693   * @}
00694   */
00695
00696 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
00697   * @{
00698   */
00699 #define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
00700 #define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
00701 /**
00702   * @}
00703   */
00704
00705 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
00706   * @{
00707   */
00708 #define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
00709 #define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
00710 /**
00711   * @}
00712   */
00713
00714 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
00715   * @{
00716   */
00717 #define LL_TIM_GROUPCH5_NONE                   0x00000000U           /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
00718 #define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
00719 #define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
00720 #define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
00721 /**
00722   * @}
00723   */
00724
00725 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
00726   * @{
00727   */
00728 #define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
00729 #define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
00730 #define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
00731 /**
00732   * @}
00733   */
00734
00735 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
00736   * @{
00737   */
00738 #define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
00739 #define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
00740 #define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
00741 #define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
00742 /**
00743   * @}
00744   */
00745
00746 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
00747   * @{
00748   */
00749 #define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
00750 #define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
00751 #define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
00752 #define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
00753 #define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
00754 #define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
00755 #define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
00756 #define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
00757 #define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
00758 #define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
00759 #define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
00760 #define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
00761 #define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
00762 #define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
00763 #define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
00764 #define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
00765 /**
00766   * @}
00767   */
00768
00769 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
00770   * @{
00771   */
00772 #define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
00773 #define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
00774 #define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
00775 /**
00776   * @}
00777   */
00778
00779 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
00780   * @{
00781   */
00782 #define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
00783 #define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
00784 #define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
00785 /**
00786   * @}
00787   */
00788
00789 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
00790   * @{
00791   */
00792 #define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
00793 #define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
00794 #define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
00795 /**
00796   * @}
00797   */
00798
00799 /** @defgroup TIM_LL_EC_TRGO Trigger Output
00800   * @{
00801   */
00802 #define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
00803 #define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
00804 #define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
00805 #define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
00806 #define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
00807 #define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
00808 #define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
00809 #define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
00810 /**
00811   * @}
00812   */
00813
00814 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
00815   * @{
00816   */
00817 #define LL_TIM_TRGO2_RESET                     0x00000000U                                                         /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
00818 #define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
00819 #define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */
00820 #define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */
00821 #define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */
00822 #define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */
00823 #define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */
00824 #define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */
00825 #define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */
00826 #define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */
00827 #define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */
00828 #define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */
00829 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
00830 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
00831 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
00832 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
00833 /**
00834   * @}
00835   */
00836
00837 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
00838   * @{
00839   */
00840 #define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
00841 #define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
00842 #define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
00843 #define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
00844 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */
00845 /**
00846   * @}
00847   */
00848
00849 /** @defgroup TIM_LL_EC_TS Trigger Selection
00850   * @{
00851   */
00852 #define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
00853 #define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
00854 #define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
00855 #define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
00856 #define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
00857 #define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
00858 #define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
00859 #define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
00860 #define LL_TIM_TS_ITR4                         (TIM_SMCR_TS_3)                                                 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
00861 #define LL_TIM_TS_ITR5                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 5 (ITR5) is used as trigger input */
00862 #define LL_TIM_TS_ITR6                         (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 6 (ITR6) is used as trigger input */
00863 #define LL_TIM_TS_ITR7                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 7 (ITR7) is used as trigger input */
00864 #define LL_TIM_TS_ITR8                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 8 (ITR8) is used as trigger input */
00865 /**
00866   * @}
00867   */
00868
00869 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
00870   * @{
00871   */
00872 #define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
00873 #define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
00874 /**
00875   * @}
00876   */
00877
00878 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
00879   * @{
00880   */
00881 #define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
00882 #define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
00883 #define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
00884 #define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
00885 /**
00886   * @}
00887   */
00888
00889 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
00890   * @{
00891   */
00892 #define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
00893 #define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
00894 #define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
00895 #define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
00896 #define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
00897 #define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
00898 #define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
00899 #define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
00900 #define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
00901 #define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
00902 #define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
00903 #define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
00904 #define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
00905 #define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
00906 #define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
00907 #define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
00908 /**
00909   * @}
00910   */
00911
00912
00913 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
00914   * @{
00915   */
00916 #define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
00917 #define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
00918 /**
00919   * @}
00920   */
00921
00922 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
00923   * @{
00924   */
00925 #define LL_TIM_BREAK_FILTER_FDIV1              0x00000000U   /*!< No filter, BRK acts asynchronously */
00926 #define LL_TIM_BREAK_FILTER_FDIV1_N2           0x00010000U   /*!< fSAMPLING=fCK_INT, N=2 */
00927 #define LL_TIM_BREAK_FILTER_FDIV1_N4           0x00020000U   /*!< fSAMPLING=fCK_INT, N=4 */
00928 #define LL_TIM_BREAK_FILTER_FDIV1_N8           0x00030000U   /*!< fSAMPLING=fCK_INT, N=8 */
00929 #define LL_TIM_BREAK_FILTER_FDIV2_N6           0x00040000U   /*!< fSAMPLING=fDTS/2, N=6 */
00930 #define LL_TIM_BREAK_FILTER_FDIV2_N8           0x00050000U   /*!< fSAMPLING=fDTS/2, N=8 */
00931 #define LL_TIM_BREAK_FILTER_FDIV4_N6           0x00060000U   /*!< fSAMPLING=fDTS/4, N=6 */
00932 #define LL_TIM_BREAK_FILTER_FDIV4_N8           0x00070000U   /*!< fSAMPLING=fDTS/4, N=8 */
00933 #define LL_TIM_BREAK_FILTER_FDIV8_N6           0x00080000U   /*!< fSAMPLING=fDTS/8, N=6 */
00934 #define LL_TIM_BREAK_FILTER_FDIV8_N8           0x00090000U   /*!< fSAMPLING=fDTS/8, N=8 */
00935 #define LL_TIM_BREAK_FILTER_FDIV16_N5          0x000A0000U   /*!< fSAMPLING=fDTS/16, N=5 */
00936 #define LL_TIM_BREAK_FILTER_FDIV16_N6          0x000B0000U   /*!< fSAMPLING=fDTS/16, N=6 */
00937 #define LL_TIM_BREAK_FILTER_FDIV16_N8          0x000C0000U   /*!< fSAMPLING=fDTS/16, N=8 */
00938 #define LL_TIM_BREAK_FILTER_FDIV32_N5          0x000D0000U   /*!< fSAMPLING=fDTS/32, N=5 */
00939 #define LL_TIM_BREAK_FILTER_FDIV32_N6          0x000E0000U   /*!< fSAMPLING=fDTS/32, N=6 */
00940 #define LL_TIM_BREAK_FILTER_FDIV32_N8          0x000F0000U   /*!< fSAMPLING=fDTS/32, N=8 */
00941 /**
00942   * @}
00943   */
00944
00945 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
00946   * @{
00947   */
00948 #define LL_TIM_BREAK2_POLARITY_LOW             0x00000000U             /*!< Break input BRK2 is active low */
00949 #define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           /*!< Break input BRK2 is active high */
00950 /**
00951   * @}
00952   */
00953
00954 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
00955   * @{
00956   */
00957 #define LL_TIM_BREAK2_FILTER_FDIV1             0x00000000U   /*!< No filter, BRK acts asynchronously */
00958 #define LL_TIM_BREAK2_FILTER_FDIV1_N2          0x00100000U   /*!< fSAMPLING=fCK_INT, N=2 */
00959 #define LL_TIM_BREAK2_FILTER_FDIV1_N4          0x00200000U   /*!< fSAMPLING=fCK_INT, N=4 */
00960 #define LL_TIM_BREAK2_FILTER_FDIV1_N8          0x00300000U   /*!< fSAMPLING=fCK_INT, N=8 */
00961 #define LL_TIM_BREAK2_FILTER_FDIV2_N6          0x00400000U   /*!< fSAMPLING=fDTS/2, N=6 */
00962 #define LL_TIM_BREAK2_FILTER_FDIV2_N8          0x00500000U   /*!< fSAMPLING=fDTS/2, N=8 */
00963 #define LL_TIM_BREAK2_FILTER_FDIV4_N6          0x00600000U   /*!< fSAMPLING=fDTS/4, N=6 */
00964 #define LL_TIM_BREAK2_FILTER_FDIV4_N8          0x00700000U   /*!< fSAMPLING=fDTS/4, N=8 */
00965 #define LL_TIM_BREAK2_FILTER_FDIV8_N6          0x00800000U   /*!< fSAMPLING=fDTS/8, N=6 */
00966 #define LL_TIM_BREAK2_FILTER_FDIV8_N8          0x00900000U   /*!< fSAMPLING=fDTS/8, N=8 */
00967 #define LL_TIM_BREAK2_FILTER_FDIV16_N5         0x00A00000U   /*!< fSAMPLING=fDTS/16, N=5 */
00968 #define LL_TIM_BREAK2_FILTER_FDIV16_N6         0x00B00000U   /*!< fSAMPLING=fDTS/16, N=6 */
00969 #define LL_TIM_BREAK2_FILTER_FDIV16_N8         0x00C00000U   /*!< fSAMPLING=fDTS/16, N=8 */
00970 #define LL_TIM_BREAK2_FILTER_FDIV32_N5         0x00D00000U   /*!< fSAMPLING=fDTS/32, N=5 */
00971 #define LL_TIM_BREAK2_FILTER_FDIV32_N6         0x00E00000U   /*!< fSAMPLING=fDTS/32, N=6 */
00972 #define LL_TIM_BREAK2_FILTER_FDIV32_N8         0x00F00000U   /*!< fSAMPLING=fDTS/32, N=8 */
00973 /**
00974   * @}
00975   */
00976
00977 /** @defgroup TIM_LL_EC_OSSI OSSI
00978   * @{
00979   */
00980 #define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
00981 #define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
00982 /**
00983   * @}
00984   */
00985
00986 /** @defgroup TIM_LL_EC_OSSR OSSR
00987   * @{
00988   */
00989 #define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
00990 #define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
00991 /**
00992   * @}
00993   */
00994
00995 #if   defined(TIM_BREAK_INPUT_SUPPORT)
00996 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
00997   * @{
00998   */
00999 #define LL_TIM_BREAK_INPUT_BKIN                0x00000000U  /*!< TIMx_BKIN input */
01000 #define LL_TIM_BREAK_INPUT_BKIN2               0x00000004U  /*!< TIMx_BKIN2 input */
01001 /**
01002   * @}
01003   */
01004
01005 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
01006   * @{
01007   */
01008 #define LL_TIM_BKIN_SOURCE_BKIN                TIM1_AF1_BKINE      /*!< BKIN input from AF controller */
01009 #define LL_TIM_BKIN_SOURCE_BKCOMP1             TIM1_AF1_BKCMP1E    /*!< internal signal: COMP1 output */
01010 #define LL_TIM_BKIN_SOURCE_BKCOMP2             TIM1_AF1_BKCMP2E    /*!< internal signal: COMP2 output */
01011 #define LL_TIM_BKIN_SOURCE_DF1BK               TIM1_AF1_BKDF1BK0E  /*!< internal signal: DFSDM1 break output */
01012 /**
01013   * @}
01014   */
01015
01016 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
01017   * @{
01018   */
01019 #define LL_TIM_BKIN_POLARITY_LOW               TIM1_AF1_BKINP           /*!< BRK BKIN input is active low */
01020 #define LL_TIM_BKIN_POLARITY_HIGH              0x00000000U              /*!< BRK BKIN input is active high */
01021 /**
01022   * @}
01023   */
01024 #endif /* TIM_BREAK_INPUT_SUPPORT */
01025
01026 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
01027   * @{
01028   */
01029 #define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
01030 #define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
01031 #define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
01032 #define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
01033 #define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
01034 #define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
01035 #define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
01036 #define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
01037 #define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
01038 #define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
01039 #define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
01040 #define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
01041 #define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
01042 #define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
01043 #define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
01044 #define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
01045 #define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
01046 #define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
01047 #define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
01048 #define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
01049 #define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
01050 #if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE)
01051 #define LL_TIM_DMABURST_BASEADDR_AF1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)                                  /*!< TIMx_AF1 register is the DMA base address for DMA burst */
01052 #define LL_TIM_DMABURST_BASEADDR_AF2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                  /*!< TIMx_AF2 register is the DMA base address for DMA burst */
01053 #endif /* TIM_AF1_BKINE && TIM_AF2_BKINE */
01054 #define LL_TIM_DMABURST_BASEADDR_TISEL         (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                  /*!< TIMx_TISEL register is the DMA base address for DMA burst */
01055 /**
01056   * @}
01057   */
01058
01059 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
01060   * @{
01061   */
01062 #define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
01063 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
01064 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
01065 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
01066 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
01067 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
01068 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
01069 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
01070 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
01071 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
01072 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
01073 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
01074 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
01075 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
01076 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
01077 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
01078 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
01079 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
01080 /**
01081   * @}
01082   */
01083
01084
01085 #if defined(TIM_BREAK_INPUT_SUPPORT)
01086 /** Legacy definitions for compatibility purpose
01087 @cond 0
01088   */
01089 #define LL_TIM_BKIN_SOURCE_DFBK  LL_TIM_BKIN_SOURCE_DF1BK
01090 /**
01091 @endcond
01092   */
01093 #endif /* TIM_BREAK_INPUT_SUPPORT */
01094 /**
01095   * @}
01096   */
01097
01098 /* Exported macro ------------------------------------------------------------*/
01099 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
01100   * @{
01101   */
01102
01103 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
01104   * @{
01105   */
01106 /**
01107   * @brief  Write a value in TIM register.
01108   * @param  __INSTANCE__ TIM Instance
01109   * @param  __REG__ Register to be written
01110   * @param  __VALUE__ Value to be written in the register
01111   * @retval None
01112   */
01113 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
01114
01115 /**
01116   * @brief  Read a value in TIM register.
01117   * @param  __INSTANCE__ TIM Instance
01118   * @param  __REG__ Register to be read
01119   * @retval Register value
01120   */
01121 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
01122 /**
01123   * @}
01124   */
01125
01126 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
01127   * @{
01128   */
01129
01130 /**
01131   * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
01132   * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
01133   * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
01134   *        to TIMx_CNT register bit 31)
01135   * @param  __CNT__ Counter value
01136   * @retval UIF status bit
01137   */
01138 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
01139   (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
01140
01141 /**
01142   * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
01143   * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
01144   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01145   * @param  __CKD__ This parameter can be one of the following values:
01146   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01147   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01148   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01149   * @param  __DT__ deadtime duration (in ns)
01150   * @retval DTG[0:7]
01151   */
01152 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
01153   ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :                                               \
01154     (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
01155     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
01156     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
01157     0U)
01158
01159 /**
01160   * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
01161   * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
01162   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01163   * @param  __CNTCLK__ counter clock frequency (in Hz)
01164   * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
01165   */
01166 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
01167   (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
01168
01169 /**
01170   * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
01171   * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
01172   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01173   * @param  __PSC__ prescaler
01174   * @param  __FREQ__ output signal frequency (in Hz)
01175   * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
01176   */
01177 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
01178   ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
01179
01180 /**
01181   * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
01182   * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
01183   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01184   * @param  __PSC__ prescaler
01185   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01186   * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
01187   */
01188 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
01189   ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
01190               / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
01191
01192 /**
01193   * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
01194   * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
01195   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01196   * @param  __PSC__ prescaler
01197   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01198   * @param  __PULSE__ pulse duration (in us)
01199   * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
01200   */
01201 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
01202   ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
01203               + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
01204
01205 /**
01206   * @brief  HELPER macro retrieving the ratio of the input capture prescaler
01207   * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
01208   * @param  __ICPSC__ This parameter can be one of the following values:
01209   *         @arg @ref LL_TIM_ICPSC_DIV1
01210   *         @arg @ref LL_TIM_ICPSC_DIV2
01211   *         @arg @ref LL_TIM_ICPSC_DIV4
01212   *         @arg @ref LL_TIM_ICPSC_DIV8
01213   * @retval Input capture prescaler ratio (1, 2, 4 or 8)
01214   */
01215 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
01216   ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
01217
01218
01219 /**
01220   * @}
01221   */
01222
01223
01224 /**
01225   * @}
01226   */
01227
01228 /* Exported functions --------------------------------------------------------*/
01229 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
01230   * @{
01231   */
01232
01233 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
01234   * @{
01235   */
01236 /**
01237   * @brief  Enable timer counter.
01238   * @rmtoll CR1          CEN           LL_TIM_EnableCounter
01239   * @param  TIMx Timer instance
01240   * @retval None
01241   */
01242 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
01243 {
01244   SET_BIT(TIMx->CR1, TIM_CR1_CEN);
01245 }
01246
01247 /**
01248   * @brief  Disable timer counter.
01249   * @rmtoll CR1          CEN           LL_TIM_DisableCounter
01250   * @param  TIMx Timer instance
01251   * @retval None
01252   */
01253 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
01254 {
01255   CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
01256 }
01257
01258 /**
01259   * @brief  Indicates whether the timer counter is enabled.
01260   * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
01261   * @param  TIMx Timer instance
01262   * @retval State of bit (1 or 0).
01263   */
01264 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
01265 {
01266   return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
01267 }
01268
01269 /**
01270   * @brief  Enable update event generation.
01271   * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
01272   * @param  TIMx Timer instance
01273   * @retval None
01274   */
01275 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
01276 {
01277   CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
01278 }
01279
01280 /**
01281   * @brief  Disable update event generation.
01282   * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
01283   * @param  TIMx Timer instance
01284   * @retval None
01285   */
01286 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
01287 {
01288   SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
01289 }
01290
01291 /**
01292   * @brief  Indicates whether update event generation is enabled.
01293   * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
01294   * @param  TIMx Timer instance
01295   * @retval Inverted state of bit (0 or 1).
01296   */
01297 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
01298 {
01299   return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
01300 }
01301
01302 /**
01303   * @brief  Set update event source
01304   * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
01305   *       generate an update interrupt or DMA request if enabled:
01306   *        - Counter overflow/underflow
01307   *        - Setting the UG bit
01308   *        - Update generation through the slave mode controller
01309   * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
01310   *       overflow/underflow generates an update interrupt or DMA request if enabled.
01311   * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
01312   * @param  TIMx Timer instance
01313   * @param  UpdateSource This parameter can be one of the following values:
01314   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
01315   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
01316   * @retval None
01317   */
01318 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
01319 {
01320   MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
01321 }
01322
01323 /**
01324   * @brief  Get actual event update source
01325   * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
01326   * @param  TIMx Timer instance
01327   * @retval Returned value can be one of the following values:
01328   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
01329   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
01330   */
01331 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
01332 {
01333   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
01334 }
01335
01336 /**
01337   * @brief  Set one pulse mode (one shot v.s. repetitive).
01338   * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
01339   * @param  TIMx Timer instance
01340   * @param  OnePulseMode This parameter can be one of the following values:
01341   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
01342   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
01343   * @retval None
01344   */
01345 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
01346 {
01347   MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
01348 }
01349
01350 /**
01351   * @brief  Get actual one pulse mode.
01352   * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
01353   * @param  TIMx Timer instance
01354   * @retval Returned value can be one of the following values:
01355   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
01356   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
01357   */
01358 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
01359 {
01360   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
01361 }
01362
01363 /**
01364   * @brief  Set the timer counter counting mode.
01365   * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
01366   *       check whether or not the counter mode selection feature is supported
01367   *       by a timer instance.
01368   * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
01369   *       requires a timer reset to avoid unexpected direction
01370   *       due to DIR bit readonly in center aligned mode.
01371   * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
01372   *         CR1          CMS           LL_TIM_SetCounterMode
01373   * @param  TIMx Timer instance
01374   * @param  CounterMode This parameter can be one of the following values:
01375   *         @arg @ref LL_TIM_COUNTERMODE_UP
01376   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
01377   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
01378   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
01379   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
01380   * @retval None
01381   */
01382 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
01383 {
01384   MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
01385 }
01386
01387 /**
01388   * @brief  Get actual counter mode.
01389   * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
01390   *       check whether or not the counter mode selection feature is supported
01391   *       by a timer instance.
01392   * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
01393   *         CR1          CMS           LL_TIM_GetCounterMode
01394   * @param  TIMx Timer instance
01395   * @retval Returned value can be one of the following values:
01396   *         @arg @ref LL_TIM_COUNTERMODE_UP
01397   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
01398   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
01399   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
01400   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
01401   */
01402 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
01403 {
01404   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
01405 }
01406
01407 /**
01408   * @brief  Enable auto-reload (ARR) preload.
01409   * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
01410   * @param  TIMx Timer instance
01411   * @retval None
01412   */
01413 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
01414 {
01415   SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
01416 }
01417
01418 /**
01419   * @brief  Disable auto-reload (ARR) preload.
01420   * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
01421   * @param  TIMx Timer instance
01422   * @retval None
01423   */
01424 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
01425 {
01426   CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
01427 }
01428
01429 /**
01430   * @brief  Indicates whether auto-reload (ARR) preload is enabled.
01431   * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
01432   * @param  TIMx Timer instance
01433   * @retval State of bit (1 or 0).
01434   */
01435 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
01436 {
01437   return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
01438 }
01439
01440 /**
01441   * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
01442   * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
01443   *       whether or not the clock division feature is supported by the timer
01444   *       instance.
01445   * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
01446   * @param  TIMx Timer instance
01447   * @param  ClockDivision This parameter can be one of the following values:
01448   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01449   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01450   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01451   * @retval None
01452   */
01453 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
01454 {
01455   MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
01456 }
01457
01458 /**
01459   * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
01460   * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
01461   *       whether or not the clock division feature is supported by the timer
01462   *       instance.
01463   * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
01464   * @param  TIMx Timer instance
01465   * @retval Returned value can be one of the following values:
01466   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01467   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01468   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01469   */
01470 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
01471 {
01472   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
01473 }
01474
01475 /**
01476   * @brief  Set the counter value.
01477   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01478   *       whether or not a timer instance supports a 32 bits counter.
01479   * @rmtoll CNT          CNT           LL_TIM_SetCounter
01480   * @param  TIMx Timer instance
01481   * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
01482   * @retval None
01483   */
01484 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
01485 {
01486   WRITE_REG(TIMx->CNT, Counter);
01487 }
01488
01489 /**
01490   * @brief  Get the counter value.
01491   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01492   *       whether or not a timer instance supports a 32 bits counter.
01493   * @rmtoll CNT          CNT           LL_TIM_GetCounter
01494   * @param  TIMx Timer instance
01495   * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
01496   */
01497 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
01498 {
01499   return (uint32_t)(READ_REG(TIMx->CNT));
01500 }
01501
01502 /**
01503   * @brief  Get the current direction of the counter
01504   * @rmtoll CR1          DIR           LL_TIM_GetDirection
01505   * @param  TIMx Timer instance
01506   * @retval Returned value can be one of the following values:
01507   *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
01508   *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
01509   */
01510 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
01511 {
01512   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
01513 }
01514
01515 /**
01516   * @brief  Set the prescaler value.
01517   * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
01518   * @note The prescaler can be changed on the fly as this control register is buffered. The new
01519   *       prescaler ratio is taken into account at the next update event.
01520   * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
01521   * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
01522   * @param  TIMx Timer instance
01523   * @param  Prescaler between Min_Data=0 and Max_Data=65535
01524   * @retval None
01525   */
01526 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
01527 {
01528   WRITE_REG(TIMx->PSC, Prescaler);
01529 }
01530
01531 /**
01532   * @brief  Get the prescaler value.
01533   * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
01534   * @param  TIMx Timer instance
01535   * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
01536   */
01537 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
01538 {
01539   return (uint32_t)(READ_REG(TIMx->PSC));
01540 }
01541
01542 /**
01543   * @brief  Set the auto-reload value.
01544   * @note The counter is blocked while the auto-reload value is null.
01545   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01546   *       whether or not a timer instance supports a 32 bits counter.
01547   * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
01548   * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
01549   * @param  TIMx Timer instance
01550   * @param  AutoReload between Min_Data=0 and Max_Data=65535
01551   * @retval None
01552   */
01553 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
01554 {
01555   WRITE_REG(TIMx->ARR, AutoReload);
01556 }
01557
01558 /**
01559   * @brief  Get the auto-reload value.
01560   * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
01561   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01562   *       whether or not a timer instance supports a 32 bits counter.
01563   * @param  TIMx Timer instance
01564   * @retval Auto-reload value
01565   */
01566 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
01567 {
01568   return (uint32_t)(READ_REG(TIMx->ARR));
01569 }
01570
01571 /**
01572   * @brief  Set the repetition counter value.
01573   * @note For advanced timer instances RepetitionCounter can be up to 65535.
01574   * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
01575   *       whether or not a timer instance supports a repetition counter.
01576   * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
01577   * @param  TIMx Timer instance
01578   * @param  RepetitionCounter between Min_Data=0 and Max_Data=255
01579   * @retval None
01580   */
01581 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
01582 {
01583   WRITE_REG(TIMx->RCR, RepetitionCounter);
01584 }
01585
01586 /**
01587   * @brief  Get the repetition counter value.
01588   * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
01589   *       whether or not a timer instance supports a repetition counter.
01590   * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
01591   * @param  TIMx Timer instance
01592   * @retval Repetition counter value
01593   */
01594 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
01595 {
01596   return (uint32_t)(READ_REG(TIMx->RCR));
01597 }
01598
01599 /**
01600   * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
01601   * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
01602   * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
01603   * @param  TIMx Timer instance
01604   * @retval None
01605   */
01606 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
01607 {
01608   SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
01609 }
01610
01611 /**
01612   * @brief  Disable update interrupt flag (UIF) remapping.
01613   * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
01614   * @param  TIMx Timer instance
01615   * @retval None
01616   */
01617 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
01618 {
01619   CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
01620 }
01621
01622 /**
01623   * @}
01624   */
01625
01626 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
01627   * @{
01628   */
01629 /**
01630   * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
01631   * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
01632   *       they are updated only when a commutation event (COM) occurs.
01633   * @note Only on channels that have a complementary output.
01634   * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01635   *       whether or not a timer instance is able to generate a commutation event.
01636   * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
01637   * @param  TIMx Timer instance
01638   * @retval None
01639   */
01640 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
01641 {
01642   SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
01643 }
01644
01645 /**
01646   * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
01647   * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01648   *       whether or not a timer instance is able to generate a commutation event.
01649   * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
01650   * @param  TIMx Timer instance
01651   * @retval None
01652   */
01653 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
01654 {
01655   CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
01656 }
01657
01658 /**
01659   * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
01660   * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01661   *       whether or not a timer instance is able to generate a commutation event.
01662   * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
01663   * @param  TIMx Timer instance
01664   * @param  CCUpdateSource This parameter can be one of the following values:
01665   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
01666   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
01667   * @retval None
01668   */
01669 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
01670 {
01671   MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
01672 }
01673
01674 /**
01675   * @brief  Set the trigger of the capture/compare DMA request.
01676   * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
01677   * @param  TIMx Timer instance
01678   * @param  DMAReqTrigger This parameter can be one of the following values:
01679   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
01680   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
01681   * @retval None
01682   */
01683 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
01684 {
01685   MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
01686 }
01687
01688 /**
01689   * @brief  Get actual trigger of the capture/compare DMA request.
01690   * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
01691   * @param  TIMx Timer instance
01692   * @retval Returned value can be one of the following values:
01693   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
01694   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
01695   */
01696 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
01697 {
01698   return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
01699 }
01700
01701 /**
01702   * @brief  Set the lock level to freeze the
01703   *         configuration of several capture/compare parameters.
01704   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
01705   *       the lock mechanism is supported by a timer instance.
01706   * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
01707   * @param  TIMx Timer instance
01708   * @param  LockLevel This parameter can be one of the following values:
01709   *         @arg @ref LL_TIM_LOCKLEVEL_OFF
01710   *         @arg @ref LL_TIM_LOCKLEVEL_1
01711   *         @arg @ref LL_TIM_LOCKLEVEL_2
01712   *         @arg @ref LL_TIM_LOCKLEVEL_3
01713   * @retval None
01714   */
01715 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
01716 {
01717   MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
01718 }
01719
01720 /**
01721   * @brief  Enable capture/compare channels.
01722   * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
01723   *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
01724   *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
01725   *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
01726   *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
01727   *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
01728   *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
01729   *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
01730   *         CCER         CC6E          LL_TIM_CC_EnableChannel
01731   * @param  TIMx Timer instance
01732   * @param  Channels This parameter can be a combination of the following values:
01733   *         @arg @ref LL_TIM_CHANNEL_CH1
01734   *         @arg @ref LL_TIM_CHANNEL_CH1N
01735   *         @arg @ref LL_TIM_CHANNEL_CH2
01736   *         @arg @ref LL_TIM_CHANNEL_CH2N
01737   *         @arg @ref LL_TIM_CHANNEL_CH3
01738   *         @arg @ref LL_TIM_CHANNEL_CH3N
01739   *         @arg @ref LL_TIM_CHANNEL_CH4
01740   *         @arg @ref LL_TIM_CHANNEL_CH5
01741   *         @arg @ref LL_TIM_CHANNEL_CH6
01742   * @retval None
01743   */
01744 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
01745 {
01746   SET_BIT(TIMx->CCER, Channels);
01747 }
01748
01749 /**
01750   * @brief  Disable capture/compare channels.
01751   * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
01752   *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
01753   *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
01754   *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
01755   *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
01756   *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
01757   *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
01758   *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
01759   *         CCER         CC6E          LL_TIM_CC_DisableChannel
01760   * @param  TIMx Timer instance
01761   * @param  Channels This parameter can be a combination of the following values:
01762   *         @arg @ref LL_TIM_CHANNEL_CH1
01763   *         @arg @ref LL_TIM_CHANNEL_CH1N
01764   *         @arg @ref LL_TIM_CHANNEL_CH2
01765   *         @arg @ref LL_TIM_CHANNEL_CH2N
01766   *         @arg @ref LL_TIM_CHANNEL_CH3
01767   *         @arg @ref LL_TIM_CHANNEL_CH3N
01768   *         @arg @ref LL_TIM_CHANNEL_CH4
01769   *         @arg @ref LL_TIM_CHANNEL_CH5
01770   *         @arg @ref LL_TIM_CHANNEL_CH6
01771   * @retval None
01772   */
01773 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
01774 {
01775   CLEAR_BIT(TIMx->CCER, Channels);
01776 }
01777
01778 /**
01779   * @brief  Indicate whether channel(s) is(are) enabled.
01780   * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
01781   *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
01782   *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
01783   *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
01784   *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
01785   *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
01786   *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
01787   *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
01788   *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
01789   * @param  TIMx Timer instance
01790   * @param  Channels This parameter can be a combination of the following values:
01791   *         @arg @ref LL_TIM_CHANNEL_CH1
01792   *         @arg @ref LL_TIM_CHANNEL_CH1N
01793   *         @arg @ref LL_TIM_CHANNEL_CH2
01794   *         @arg @ref LL_TIM_CHANNEL_CH2N
01795   *         @arg @ref LL_TIM_CHANNEL_CH3
01796   *         @arg @ref LL_TIM_CHANNEL_CH3N
01797   *         @arg @ref LL_TIM_CHANNEL_CH4
01798   *         @arg @ref LL_TIM_CHANNEL_CH5
01799   *         @arg @ref LL_TIM_CHANNEL_CH6
01800   * @retval State of bit (1 or 0).
01801   */
01802 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
01803 {
01804   return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
01805 }
01806
01807 /**
01808   * @}
01809   */
01810
01811 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
01812   * @{
01813   */
01814 /**
01815   * @brief  Configure an output channel.
01816   * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
01817   *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
01818   *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
01819   *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
01820   *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
01821   *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
01822   *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
01823   *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
01824   *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
01825   *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
01826   *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
01827   *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
01828   *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
01829   *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
01830   *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
01831   *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
01832   *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
01833   *         CR2          OIS6          LL_TIM_OC_ConfigOutput
01834   * @param  TIMx Timer instance
01835   * @param  Channel This parameter can be one of the following values:
01836   *         @arg @ref LL_TIM_CHANNEL_CH1
01837   *         @arg @ref LL_TIM_CHANNEL_CH2
01838   *         @arg @ref LL_TIM_CHANNEL_CH3
01839   *         @arg @ref LL_TIM_CHANNEL_CH4
01840   *         @arg @ref LL_TIM_CHANNEL_CH5
01841   *         @arg @ref LL_TIM_CHANNEL_CH6
01842   * @param  Configuration This parameter must be a combination of all the following values:
01843   *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
01844   *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
01845   * @retval None
01846   */
01847 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
01848 {
01849   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01850   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
01851   CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
01852   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
01853              (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
01854   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
01855              (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
01856 }
01857
01858 /**
01859   * @brief  Define the behavior of the output reference signal OCxREF from which
01860   *         OCx and OCxN (when relevant) are derived.
01861   * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
01862   *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
01863   *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
01864   *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
01865   *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
01866   *         CCMR3        OC6M          LL_TIM_OC_SetMode
01867   * @param  TIMx Timer instance
01868   * @param  Channel This parameter can be one of the following values:
01869   *         @arg @ref LL_TIM_CHANNEL_CH1
01870   *         @arg @ref LL_TIM_CHANNEL_CH2
01871   *         @arg @ref LL_TIM_CHANNEL_CH3
01872   *         @arg @ref LL_TIM_CHANNEL_CH4
01873   *         @arg @ref LL_TIM_CHANNEL_CH5
01874   *         @arg @ref LL_TIM_CHANNEL_CH6
01875   * @param  Mode This parameter can be one of the following values:
01876   *         @arg @ref LL_TIM_OCMODE_FROZEN
01877   *         @arg @ref LL_TIM_OCMODE_ACTIVE
01878   *         @arg @ref LL_TIM_OCMODE_INACTIVE
01879   *         @arg @ref LL_TIM_OCMODE_TOGGLE
01880   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
01881   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
01882   *         @arg @ref LL_TIM_OCMODE_PWM1
01883   *         @arg @ref LL_TIM_OCMODE_PWM2
01884   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
01885   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
01886   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
01887   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
01888   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
01889   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
01890   * @retval None
01891   */
01892 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
01893 {
01894   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01895   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
01896   MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]),  Mode << SHIFT_TAB_OCxx[iChannel]);
01897 }
01898
01899 /**
01900   * @brief  Get the output compare mode of an output channel.
01901   * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
01902   *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
01903   *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
01904   *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
01905   *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
01906   *         CCMR3        OC6M          LL_TIM_OC_GetMode
01907   * @param  TIMx Timer instance
01908   * @param  Channel This parameter can be one of the following values:
01909   *         @arg @ref LL_TIM_CHANNEL_CH1
01910   *         @arg @ref LL_TIM_CHANNEL_CH2
01911   *         @arg @ref LL_TIM_CHANNEL_CH3
01912   *         @arg @ref LL_TIM_CHANNEL_CH4
01913   *         @arg @ref LL_TIM_CHANNEL_CH5
01914   *         @arg @ref LL_TIM_CHANNEL_CH6
01915   * @retval Returned value can be one of the following values:
01916   *         @arg @ref LL_TIM_OCMODE_FROZEN
01917   *         @arg @ref LL_TIM_OCMODE_ACTIVE
01918   *         @arg @ref LL_TIM_OCMODE_INACTIVE
01919   *         @arg @ref LL_TIM_OCMODE_TOGGLE
01920   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
01921   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
01922   *         @arg @ref LL_TIM_OCMODE_PWM1
01923   *         @arg @ref LL_TIM_OCMODE_PWM2
01924   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
01925   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
01926   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
01927   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
01928   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
01929   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
01930   */
01931 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
01932 {
01933   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01934   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
01935   return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
01936 }
01937
01938 /**
01939   * @brief  Set the polarity of an output channel.
01940   * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
01941   *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
01942   *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
01943   *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
01944   *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
01945   *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
01946   *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
01947   *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
01948   *         CCER         CC6P          LL_TIM_OC_SetPolarity
01949   * @param  TIMx Timer instance
01950   * @param  Channel This parameter can be one of the following values:
01951   *         @arg @ref LL_TIM_CHANNEL_CH1
01952   *         @arg @ref LL_TIM_CHANNEL_CH1N
01953   *         @arg @ref LL_TIM_CHANNEL_CH2
01954   *         @arg @ref LL_TIM_CHANNEL_CH2N
01955   *         @arg @ref LL_TIM_CHANNEL_CH3
01956   *         @arg @ref LL_TIM_CHANNEL_CH3N
01957   *         @arg @ref LL_TIM_CHANNEL_CH4
01958   *         @arg @ref LL_TIM_CHANNEL_CH5
01959   *         @arg @ref LL_TIM_CHANNEL_CH6
01960   * @param  Polarity This parameter can be one of the following values:
01961   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
01962   *         @arg @ref LL_TIM_OCPOLARITY_LOW
01963   * @retval None
01964   */
01965 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
01966 {
01967   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01968   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
01969 }
01970
01971 /**
01972   * @brief  Get the polarity of an output channel.
01973   * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
01974   *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
01975   *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
01976   *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
01977   *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
01978   *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
01979   *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
01980   *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
01981   *         CCER         CC6P          LL_TIM_OC_GetPolarity
01982   * @param  TIMx Timer instance
01983   * @param  Channel This parameter can be one of the following values:
01984   *         @arg @ref LL_TIM_CHANNEL_CH1
01985   *         @arg @ref LL_TIM_CHANNEL_CH1N
01986   *         @arg @ref LL_TIM_CHANNEL_CH2
01987   *         @arg @ref LL_TIM_CHANNEL_CH2N
01988   *         @arg @ref LL_TIM_CHANNEL_CH3
01989   *         @arg @ref LL_TIM_CHANNEL_CH3N
01990   *         @arg @ref LL_TIM_CHANNEL_CH4
01991   *         @arg @ref LL_TIM_CHANNEL_CH5
01992   *         @arg @ref LL_TIM_CHANNEL_CH6
01993   * @retval Returned value can be one of the following values:
01994   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
01995   *         @arg @ref LL_TIM_OCPOLARITY_LOW
01996   */
01997 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
01998 {
01999   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02000   return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
02001 }
02002
02003 /**
02004   * @brief  Set the IDLE state of an output channel
02005   * @note This function is significant only for the timer instances
02006   *       supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
02007   *       can be used to check whether or not a timer instance provides
02008   *       a break input.
02009   * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
02010   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
02011   *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
02012   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
02013   *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
02014   *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
02015   *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
02016   *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
02017   *         CR2         OIS6          LL_TIM_OC_SetIdleState
02018   * @param  TIMx Timer instance
02019   * @param  Channel This parameter can be one of the following values:
02020   *         @arg @ref LL_TIM_CHANNEL_CH1
02021   *         @arg @ref LL_TIM_CHANNEL_CH1N
02022   *         @arg @ref LL_TIM_CHANNEL_CH2
02023   *         @arg @ref LL_TIM_CHANNEL_CH2N
02024   *         @arg @ref LL_TIM_CHANNEL_CH3
02025   *         @arg @ref LL_TIM_CHANNEL_CH3N
02026   *         @arg @ref LL_TIM_CHANNEL_CH4
02027   *         @arg @ref LL_TIM_CHANNEL_CH5
02028   *         @arg @ref LL_TIM_CHANNEL_CH6
02029   * @param  IdleState This parameter can be one of the following values:
02030   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
02031   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
02032   * @retval None
02033   */
02034 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
02035 {
02036   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02037   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
02038 }
02039
02040 /**
02041   * @brief  Get the IDLE state of an output channel
02042   * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
02043   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
02044   *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
02045   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
02046   *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
02047   *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
02048   *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
02049   *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
02050   *         CR2         OIS6          LL_TIM_OC_GetIdleState
02051   * @param  TIMx Timer instance
02052   * @param  Channel This parameter can be one of the following values:
02053   *         @arg @ref LL_TIM_CHANNEL_CH1
02054   *         @arg @ref LL_TIM_CHANNEL_CH1N
02055   *         @arg @ref LL_TIM_CHANNEL_CH2
02056   *         @arg @ref LL_TIM_CHANNEL_CH2N
02057   *         @arg @ref LL_TIM_CHANNEL_CH3
02058   *         @arg @ref LL_TIM_CHANNEL_CH3N
02059   *         @arg @ref LL_TIM_CHANNEL_CH4
02060   *         @arg @ref LL_TIM_CHANNEL_CH5
02061   *         @arg @ref LL_TIM_CHANNEL_CH6
02062   * @retval Returned value can be one of the following values:
02063   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
02064   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
02065   */
02066 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
02067 {
02068   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02069   return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
02070 }
02071
02072 /**
02073   * @brief  Enable fast mode for the output channel.
02074   * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
02075   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
02076   *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
02077   *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
02078   *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
02079   *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
02080   *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
02081   * @param  TIMx Timer instance
02082   * @param  Channel This parameter can be one of the following values:
02083   *         @arg @ref LL_TIM_CHANNEL_CH1
02084   *         @arg @ref LL_TIM_CHANNEL_CH2
02085   *         @arg @ref LL_TIM_CHANNEL_CH3
02086   *         @arg @ref LL_TIM_CHANNEL_CH4
02087   *         @arg @ref LL_TIM_CHANNEL_CH5
02088   *         @arg @ref LL_TIM_CHANNEL_CH6
02089   * @retval None
02090   */
02091 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
02092 {
02093   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02094   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02095   SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
02096
02097 }
02098
02099 /**
02100   * @brief  Disable fast mode for the output channel.
02101   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
02102   *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
02103   *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
02104   *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
02105   *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
02106   *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
02107   * @param  TIMx Timer instance
02108   * @param  Channel This parameter can be one of the following values:
02109   *         @arg @ref LL_TIM_CHANNEL_CH1
02110   *         @arg @ref LL_TIM_CHANNEL_CH2
02111   *         @arg @ref LL_TIM_CHANNEL_CH3
02112   *         @arg @ref LL_TIM_CHANNEL_CH4
02113   *         @arg @ref LL_TIM_CHANNEL_CH5
02114   *         @arg @ref LL_TIM_CHANNEL_CH6
02115   * @retval None
02116   */
02117 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
02118 {
02119   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02120   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02121   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
02122
02123 }
02124
02125 /**
02126   * @brief  Indicates whether fast mode is enabled for the output channel.
02127   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
02128   *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
02129   *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
02130   *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
02131   *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
02132   *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
02133   * @param  TIMx Timer instance
02134   * @param  Channel This parameter can be one of the following values:
02135   *         @arg @ref LL_TIM_CHANNEL_CH1
02136   *         @arg @ref LL_TIM_CHANNEL_CH2
02137   *         @arg @ref LL_TIM_CHANNEL_CH3
02138   *         @arg @ref LL_TIM_CHANNEL_CH4
02139   *         @arg @ref LL_TIM_CHANNEL_CH5
02140   *         @arg @ref LL_TIM_CHANNEL_CH6
02141   * @retval State of bit (1 or 0).
02142   */
02143 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
02144 {
02145   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02146   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02147   register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
02148   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
02149 }
02150
02151 /**
02152   * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
02153   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
02154   *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
02155   *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
02156   *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
02157   *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
02158   *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
02159   * @param  TIMx Timer instance
02160   * @param  Channel This parameter can be one of the following values:
02161   *         @arg @ref LL_TIM_CHANNEL_CH1
02162   *         @arg @ref LL_TIM_CHANNEL_CH2
02163   *         @arg @ref LL_TIM_CHANNEL_CH3
02164   *         @arg @ref LL_TIM_CHANNEL_CH4
02165   *         @arg @ref LL_TIM_CHANNEL_CH5
02166   *         @arg @ref LL_TIM_CHANNEL_CH6
02167   * @retval None
02168   */
02169 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
02170 {
02171   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02172   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02173   SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
02174 }
02175
02176 /**
02177   * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
02178   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
02179   *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
02180   *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
02181   *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
02182   *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
02183   *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
02184   * @param  TIMx Timer instance
02185   * @param  Channel This parameter can be one of the following values:
02186   *         @arg @ref LL_TIM_CHANNEL_CH1
02187   *         @arg @ref LL_TIM_CHANNEL_CH2
02188   *         @arg @ref LL_TIM_CHANNEL_CH3
02189   *         @arg @ref LL_TIM_CHANNEL_CH4
02190   *         @arg @ref LL_TIM_CHANNEL_CH5
02191   *         @arg @ref LL_TIM_CHANNEL_CH6
02192   * @retval None
02193   */
02194 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
02195 {
02196   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02197   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02198   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
02199 }
02200
02201 /**
02202   * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
02203   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
02204   *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
02205   *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
02206   *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
02207   *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
02208   *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
02209   * @param  TIMx Timer instance
02210   * @param  Channel This parameter can be one of the following values:
02211   *         @arg @ref LL_TIM_CHANNEL_CH1
02212   *         @arg @ref LL_TIM_CHANNEL_CH2
02213   *         @arg @ref LL_TIM_CHANNEL_CH3
02214   *         @arg @ref LL_TIM_CHANNEL_CH4
02215   *         @arg @ref LL_TIM_CHANNEL_CH5
02216   *         @arg @ref LL_TIM_CHANNEL_CH6
02217   * @retval State of bit (1 or 0).
02218   */
02219 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
02220 {
02221   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02222   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02223   register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
02224   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
02225 }
02226
02227 /**
02228   * @brief  Enable clearing the output channel on an external event.
02229   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
02230   * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02231   *       or not a timer instance can clear the OCxREF signal on an external event.
02232   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
02233   *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
02234   *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
02235   *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
02236   *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
02237   *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
02238   * @param  TIMx Timer instance
02239   * @param  Channel This parameter can be one of the following values:
02240   *         @arg @ref LL_TIM_CHANNEL_CH1
02241   *         @arg @ref LL_TIM_CHANNEL_CH2
02242   *         @arg @ref LL_TIM_CHANNEL_CH3
02243   *         @arg @ref LL_TIM_CHANNEL_CH4
02244   *         @arg @ref LL_TIM_CHANNEL_CH5
02245   *         @arg @ref LL_TIM_CHANNEL_CH6
02246   * @retval None
02247   */
02248 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
02249 {
02250   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02251   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02252   SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
02253 }
02254
02255 /**
02256   * @brief  Disable clearing the output channel on an external event.
02257   * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02258   *       or not a timer instance can clear the OCxREF signal on an external event.
02259   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
02260   *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
02261   *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
02262   *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
02263   *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
02264   *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
02265   * @param  TIMx Timer instance
02266   * @param  Channel This parameter can be one of the following values:
02267   *         @arg @ref LL_TIM_CHANNEL_CH1
02268   *         @arg @ref LL_TIM_CHANNEL_CH2
02269   *         @arg @ref LL_TIM_CHANNEL_CH3
02270   *         @arg @ref LL_TIM_CHANNEL_CH4
02271   *         @arg @ref LL_TIM_CHANNEL_CH5
02272   *         @arg @ref LL_TIM_CHANNEL_CH6
02273   * @retval None
02274   */
02275 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
02276 {
02277   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02278   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02279   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
02280 }
02281
02282 /**
02283   * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
02284   * @note This function enables clearing the output channel on an external event.
02285   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
02286   * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02287   *       or not a timer instance can clear the OCxREF signal on an external event.
02288   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
02289   *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
02290   *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
02291   *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
02292   *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
02293   *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
02294   * @param  TIMx Timer instance
02295   * @param  Channel This parameter can be one of the following values:
02296   *         @arg @ref LL_TIM_CHANNEL_CH1
02297   *         @arg @ref LL_TIM_CHANNEL_CH2
02298   *         @arg @ref LL_TIM_CHANNEL_CH3
02299   *         @arg @ref LL_TIM_CHANNEL_CH4
02300   *         @arg @ref LL_TIM_CHANNEL_CH5
02301   *         @arg @ref LL_TIM_CHANNEL_CH6
02302   * @retval State of bit (1 or 0).
02303   */
02304 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
02305 {
02306   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02307   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02308   register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
02309   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
02310 }
02311
02312 /**
02313   * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
02314   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02315   *       dead-time insertion feature is supported by a timer instance.
02316   * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
02317   * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
02318   * @param  TIMx Timer instance
02319   * @param  DeadTime between Min_Data=0 and Max_Data=255
02320   * @retval None
02321   */
02322 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
02323 {
02324   MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
02325 }
02326
02327 /**
02328   * @brief  Set compare value for output channel 1 (TIMx_CCR1).
02329   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02330   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02331   *       whether or not a timer instance supports a 32 bits counter.
02332   * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02333   *       output channel 1 is supported by a timer instance.
02334   * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
02335   * @param  TIMx Timer instance
02336   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02337   * @retval None
02338   */
02339 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
02340 {
02341   WRITE_REG(TIMx->CCR1, CompareValue);
02342 }
02343
02344 /**
02345   * @brief  Set compare value for output channel 2 (TIMx_CCR2).
02346   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02347   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02348   *       whether or not a timer instance supports a 32 bits counter.
02349   * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02350   *       output channel 2 is supported by a timer instance.
02351   * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
02352   * @param  TIMx Timer instance
02353   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02354   * @retval None
02355   */
02356 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
02357 {
02358   WRITE_REG(TIMx->CCR2, CompareValue);
02359 }
02360
02361 /**
02362   * @brief  Set compare value for output channel 3 (TIMx_CCR3).
02363   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02364   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02365   *       whether or not a timer instance supports a 32 bits counter.
02366   * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02367   *       output channel is supported by a timer instance.
02368   * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
02369   * @param  TIMx Timer instance
02370   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02371   * @retval None
02372   */
02373 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
02374 {
02375   WRITE_REG(TIMx->CCR3, CompareValue);
02376 }
02377
02378 /**
02379   * @brief  Set compare value for output channel 4 (TIMx_CCR4).
02380   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02381   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02382   *       whether or not a timer instance supports a 32 bits counter.
02383   * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02384   *       output channel 4 is supported by a timer instance.
02385   * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
02386   * @param  TIMx Timer instance
02387   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02388   * @retval None
02389   */
02390 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
02391 {
02392   WRITE_REG(TIMx->CCR4, CompareValue);
02393 }
02394
02395 /**
02396   * @brief  Set compare value for output channel 5 (TIMx_CCR5).
02397   * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
02398   *       output channel 5 is supported by a timer instance.
02399   * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
02400   * @param  TIMx Timer instance
02401   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02402   * @retval None
02403   */
02404 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
02405 {
02406   MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
02407 }
02408
02409 /**
02410   * @brief  Set compare value for output channel 6 (TIMx_CCR6).
02411   * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
02412   *       output channel 6 is supported by a timer instance.
02413   * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
02414   * @param  TIMx Timer instance
02415   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02416   * @retval None
02417   */
02418 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
02419 {
02420   WRITE_REG(TIMx->CCR6, CompareValue);
02421 }
02422
02423 /**
02424   * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
02425   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02426   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02427   *       whether or not a timer instance supports a 32 bits counter.
02428   * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02429   *       output channel 1 is supported by a timer instance.
02430   * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
02431   * @param  TIMx Timer instance
02432   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02433   */
02434 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
02435 {
02436   return (uint32_t)(READ_REG(TIMx->CCR1));
02437 }
02438
02439 /**
02440   * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
02441   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02442   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02443   *       whether or not a timer instance supports a 32 bits counter.
02444   * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02445   *       output channel 2 is supported by a timer instance.
02446   * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
02447   * @param  TIMx Timer instance
02448   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02449   */
02450 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
02451 {
02452   return (uint32_t)(READ_REG(TIMx->CCR2));
02453 }
02454
02455 /**
02456   * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
02457   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02458   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02459   *       whether or not a timer instance supports a 32 bits counter.
02460   * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02461   *       output channel 3 is supported by a timer instance.
02462   * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
02463   * @param  TIMx Timer instance
02464   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02465   */
02466 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
02467 {
02468   return (uint32_t)(READ_REG(TIMx->CCR3));
02469 }
02470
02471 /**
02472   * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
02473   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02474   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02475   *       whether or not a timer instance supports a 32 bits counter.
02476   * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02477   *       output channel 4 is supported by a timer instance.
02478   * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
02479   * @param  TIMx Timer instance
02480   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02481   */
02482 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
02483 {
02484   return (uint32_t)(READ_REG(TIMx->CCR4));
02485 }
02486
02487 /**
02488   * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
02489   * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
02490   *       output channel 5 is supported by a timer instance.
02491   * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
02492   * @param  TIMx Timer instance
02493   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02494   */
02495 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
02496 {
02497   return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
02498 }
02499
02500 /**
02501   * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
02502   * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
02503   *       output channel 6 is supported by a timer instance.
02504   * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
02505   * @param  TIMx Timer instance
02506   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02507   */
02508 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
02509 {
02510   return (uint32_t)(READ_REG(TIMx->CCR6));
02511 }
02512
02513 /**
02514   * @brief  Select on which reference signal the OC5REF is combined to.
02515   * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
02516   *       whether or not a timer instance supports the combined 3-phase PWM mode.
02517   * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
02518   *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
02519   *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
02520   * @param  TIMx Timer instance
02521   * @param  GroupCH5 This parameter can be a combination of the following values:
02522   *         @arg @ref LL_TIM_GROUPCH5_NONE
02523   *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
02524   *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
02525   *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
02526   * @retval None
02527   */
02528 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
02529 {
02530   MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
02531 }
02532
02533 /**
02534   * @}
02535   */
02536
02537 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
02538   * @{
02539   */
02540 /**
02541   * @brief  Configure input channel.
02542   * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
02543   *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
02544   *         CCMR1        IC1F          LL_TIM_IC_Config\n
02545   *         CCMR1        CC2S          LL_TIM_IC_Config\n
02546   *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
02547   *         CCMR1        IC2F          LL_TIM_IC_Config\n
02548   *         CCMR2        CC3S          LL_TIM_IC_Config\n
02549   *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
02550   *         CCMR2        IC3F          LL_TIM_IC_Config\n
02551   *         CCMR2        CC4S          LL_TIM_IC_Config\n
02552   *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
02553   *         CCMR2        IC4F          LL_TIM_IC_Config\n
02554   *         CCER         CC1P          LL_TIM_IC_Config\n
02555   *         CCER         CC1NP         LL_TIM_IC_Config\n
02556   *         CCER         CC2P          LL_TIM_IC_Config\n
02557   *         CCER         CC2NP         LL_TIM_IC_Config\n
02558   *         CCER         CC3P          LL_TIM_IC_Config\n
02559   *         CCER         CC3NP         LL_TIM_IC_Config\n
02560   *         CCER         CC4P          LL_TIM_IC_Config\n
02561   *         CCER         CC4NP         LL_TIM_IC_Config
02562   * @param  TIMx Timer instance
02563   * @param  Channel This parameter can be one of the following values:
02564   *         @arg @ref LL_TIM_CHANNEL_CH1
02565   *         @arg @ref LL_TIM_CHANNEL_CH2
02566   *         @arg @ref LL_TIM_CHANNEL_CH3
02567   *         @arg @ref LL_TIM_CHANNEL_CH4
02568   * @param  Configuration This parameter must be a combination of all the following values:
02569   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
02570   *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
02571   *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
02572   *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
02573   * @retval None
02574   */
02575 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
02576 {
02577   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02578   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02579   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
02580              ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))  << SHIFT_TAB_ICxx[iChannel]);
02581   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
02582              (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
02583 }
02584
02585 /**
02586   * @brief  Set the active input.
02587   * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
02588   *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
02589   *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
02590   *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
02591   * @param  TIMx Timer instance
02592   * @param  Channel This parameter can be one of the following values:
02593   *         @arg @ref LL_TIM_CHANNEL_CH1
02594   *         @arg @ref LL_TIM_CHANNEL_CH2
02595   *         @arg @ref LL_TIM_CHANNEL_CH3
02596   *         @arg @ref LL_TIM_CHANNEL_CH4
02597   * @param  ICActiveInput This parameter can be one of the following values:
02598   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
02599   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
02600   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
02601   * @retval None
02602   */
02603 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
02604 {
02605   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02606   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02607   MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02608 }
02609
02610 /**
02611   * @brief  Get the current active input.
02612   * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
02613   *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
02614   *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
02615   *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
02616   * @param  TIMx Timer instance
02617   * @param  Channel This parameter can be one of the following values:
02618   *         @arg @ref LL_TIM_CHANNEL_CH1
02619   *         @arg @ref LL_TIM_CHANNEL_CH2
02620   *         @arg @ref LL_TIM_CHANNEL_CH3
02621   *         @arg @ref LL_TIM_CHANNEL_CH4
02622   * @retval Returned value can be one of the following values:
02623   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
02624   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
02625   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
02626   */
02627 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
02628 {
02629   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02630   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02631   return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
02632 }
02633
02634 /**
02635   * @brief  Set the prescaler of input channel.
02636   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
02637   *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
02638   *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
02639   *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
02640   * @param  TIMx Timer instance
02641   * @param  Channel This parameter can be one of the following values:
02642   *         @arg @ref LL_TIM_CHANNEL_CH1
02643   *         @arg @ref LL_TIM_CHANNEL_CH2
02644   *         @arg @ref LL_TIM_CHANNEL_CH3
02645   *         @arg @ref LL_TIM_CHANNEL_CH4
02646   * @param  ICPrescaler This parameter can be one of the following values:
02647   *         @arg @ref LL_TIM_ICPSC_DIV1
02648   *         @arg @ref LL_TIM_ICPSC_DIV2
02649   *         @arg @ref LL_TIM_ICPSC_DIV4
02650   *         @arg @ref LL_TIM_ICPSC_DIV8
02651   * @retval None
02652   */
02653 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
02654 {
02655   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02656   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02657   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02658 }
02659
02660 /**
02661   * @brief  Get the current prescaler value acting on an  input channel.
02662   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
02663   *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
02664   *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
02665   *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
02666   * @param  TIMx Timer instance
02667   * @param  Channel This parameter can be one of the following values:
02668   *         @arg @ref LL_TIM_CHANNEL_CH1
02669   *         @arg @ref LL_TIM_CHANNEL_CH2
02670   *         @arg @ref LL_TIM_CHANNEL_CH3
02671   *         @arg @ref LL_TIM_CHANNEL_CH4
02672   * @retval Returned value can be one of the following values:
02673   *         @arg @ref LL_TIM_ICPSC_DIV1
02674   *         @arg @ref LL_TIM_ICPSC_DIV2
02675   *         @arg @ref LL_TIM_ICPSC_DIV4
02676   *         @arg @ref LL_TIM_ICPSC_DIV8
02677   */
02678 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
02679 {
02680   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02681   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02682   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
02683 }
02684
02685 /**
02686   * @brief  Set the input filter duration.
02687   * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
02688   *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
02689   *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
02690   *         CCMR2        IC4F          LL_TIM_IC_SetFilter
02691   * @param  TIMx Timer instance
02692   * @param  Channel This parameter can be one of the following values:
02693   *         @arg @ref LL_TIM_CHANNEL_CH1
02694   *         @arg @ref LL_TIM_CHANNEL_CH2
02695   *         @arg @ref LL_TIM_CHANNEL_CH3
02696   *         @arg @ref LL_TIM_CHANNEL_CH4
02697   * @param  ICFilter This parameter can be one of the following values:
02698   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
02699   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
02700   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
02701   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
02702   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
02703   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
02704   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
02705   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
02706   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
02707   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
02708   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
02709   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
02710   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
02711   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
02712   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
02713   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
02714   * @retval None
02715   */
02716 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
02717 {
02718   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02719   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02720   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02721 }
02722
02723 /**
02724   * @brief  Get the input filter duration.
02725   * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
02726   *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
02727   *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
02728   *         CCMR2        IC4F          LL_TIM_IC_GetFilter
02729   * @param  TIMx Timer instance
02730   * @param  Channel This parameter can be one of the following values:
02731   *         @arg @ref LL_TIM_CHANNEL_CH1
02732   *         @arg @ref LL_TIM_CHANNEL_CH2
02733   *         @arg @ref LL_TIM_CHANNEL_CH3
02734   *         @arg @ref LL_TIM_CHANNEL_CH4
02735   * @retval Returned value can be one of the following values:
02736   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
02737   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
02738   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
02739   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
02740   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
02741   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
02742   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
02743   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
02744   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
02745   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
02746   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
02747   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
02748   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
02749   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
02750   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
02751   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
02752   */
02753 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
02754 {
02755   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02756   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02757   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
02758 }
02759
02760 /**
02761   * @brief  Set the input channel polarity.
02762   * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
02763   *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
02764   *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
02765   *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
02766   *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
02767   *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
02768   *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
02769   *         CCER         CC4NP         LL_TIM_IC_SetPolarity
02770   * @param  TIMx Timer instance
02771   * @param  Channel This parameter can be one of the following values:
02772   *         @arg @ref LL_TIM_CHANNEL_CH1
02773   *         @arg @ref LL_TIM_CHANNEL_CH2
02774   *         @arg @ref LL_TIM_CHANNEL_CH3
02775   *         @arg @ref LL_TIM_CHANNEL_CH4
02776   * @param  ICPolarity This parameter can be one of the following values:
02777   *         @arg @ref LL_TIM_IC_POLARITY_RISING
02778   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
02779   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
02780   * @retval None
02781   */
02782 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
02783 {
02784   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02785   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
02786              ICPolarity << SHIFT_TAB_CCxP[iChannel]);
02787 }
02788
02789 /**
02790   * @brief  Get the current input channel polarity.
02791   * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
02792   *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
02793   *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
02794   *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
02795   *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
02796   *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
02797   *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
02798   *         CCER         CC4NP         LL_TIM_IC_GetPolarity
02799   * @param  TIMx Timer instance
02800   * @param  Channel This parameter can be one of the following values:
02801   *         @arg @ref LL_TIM_CHANNEL_CH1
02802   *         @arg @ref LL_TIM_CHANNEL_CH2
02803   *         @arg @ref LL_TIM_CHANNEL_CH3
02804   *         @arg @ref LL_TIM_CHANNEL_CH4
02805   * @retval Returned value can be one of the following values:
02806   *         @arg @ref LL_TIM_IC_POLARITY_RISING
02807   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
02808   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
02809   */
02810 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
02811 {
02812   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02813   return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
02814           SHIFT_TAB_CCxP[iChannel]);
02815 }
02816
02817 /**
02818   * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
02819   * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
02820   *       a timer instance provides an XOR input.
02821   * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
02822   * @param  TIMx Timer instance
02823   * @retval None
02824   */
02825 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
02826 {
02827   SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
02828 }
02829
02830 /**
02831   * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
02832   * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
02833   *       a timer instance provides an XOR input.
02834   * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
02835   * @param  TIMx Timer instance
02836   * @retval None
02837   */
02838 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
02839 {
02840   CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
02841 }
02842
02843 /**
02844   * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
02845   * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
02846   * a timer instance provides an XOR input.
02847   * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
02848   * @param  TIMx Timer instance
02849   * @retval State of bit (1 or 0).
02850   */
02851 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
02852 {
02853   return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
02854 }
02855
02856 /**
02857   * @brief  Get captured value for input channel 1.
02858   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
02859   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02860   *       whether or not a timer instance supports a 32 bits counter.
02861   * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02862   *       input channel 1 is supported by a timer instance.
02863   * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
02864   * @param  TIMx Timer instance
02865   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
02866   */
02867 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
02868 {
02869   return (uint32_t)(READ_REG(TIMx->CCR1));
02870 }
02871
02872 /**
02873   * @brief  Get captured value for input channel 2.
02874   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
02875   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02876   *       whether or not a timer instance supports a 32 bits counter.
02877   * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02878   *       input channel 2 is supported by a timer instance.
02879   * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
02880   * @param  TIMx Timer instance
02881   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
02882   */
02883 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
02884 {
02885   return (uint32_t)(READ_REG(TIMx->CCR2));
02886 }
02887
02888 /**
02889   * @brief  Get captured value for input channel 3.
02890   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
02891   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02892   *       whether or not a timer instance supports a 32 bits counter.
02893   * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02894   *       input channel 3 is supported by a timer instance.
02895   * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
02896   * @param  TIMx Timer instance
02897   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
02898   */
02899 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
02900 {
02901   return (uint32_t)(READ_REG(TIMx->CCR3));
02902 }
02903
02904 /**
02905   * @brief  Get captured value for input channel 4.
02906   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
02907   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02908   *       whether or not a timer instance supports a 32 bits counter.
02909   * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02910   *       input channel 4 is supported by a timer instance.
02911   * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
02912   * @param  TIMx Timer instance
02913   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
02914   */
02915 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
02916 {
02917   return (uint32_t)(READ_REG(TIMx->CCR4));
02918 }
02919
02920 /**
02921   * @}
02922   */
02923
02924 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
02925   * @{
02926   */
02927 /**
02928   * @brief  Enable external clock mode 2.
02929   * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
02930   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
02931   *       whether or not a timer instance supports external clock mode2.
02932   * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
02933   * @param  TIMx Timer instance
02934   * @retval None
02935   */
02936 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
02937 {
02938   SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
02939 }
02940
02941 /**
02942   * @brief  Disable external clock mode 2.
02943   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
02944   *       whether or not a timer instance supports external clock mode2.
02945   * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
02946   * @param  TIMx Timer instance
02947   * @retval None
02948   */
02949 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
02950 {
02951   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
02952 }
02953
02954 /**
02955   * @brief  Indicate whether external clock mode 2 is enabled.
02956   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
02957   *       whether or not a timer instance supports external clock mode2.
02958   * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
02959   * @param  TIMx Timer instance
02960   * @retval State of bit (1 or 0).
02961   */
02962 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
02963 {
02964   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
02965 }
02966
02967 /**
02968   * @brief  Set the clock source of the counter clock.
02969   * @note when selected clock source is external clock mode 1, the timer input
02970   *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
02971   *       function. This timer input must be configured by calling
02972   *       the @ref LL_TIM_IC_Config() function.
02973   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
02974   *       whether or not a timer instance supports external clock mode1.
02975   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
02976   *       whether or not a timer instance supports external clock mode2.
02977   * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
02978   *         SMCR         ECE           LL_TIM_SetClockSource
02979   * @param  TIMx Timer instance
02980   * @param  ClockSource This parameter can be one of the following values:
02981   *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
02982   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
02983   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
02984   * @retval None
02985   */
02986 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
02987 {
02988   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
02989 }
02990
02991 /**
02992   * @brief  Set the encoder interface mode.
02993   * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
02994   *       whether or not a timer instance supports the encoder mode.
02995   * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
02996   * @param  TIMx Timer instance
02997   * @param  EncoderMode This parameter can be one of the following values:
02998   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
02999   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
03000   *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
03001   * @retval None
03002   */
03003 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
03004 {
03005   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
03006 }
03007
03008 /**
03009   * @}
03010   */
03011
03012 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
03013   * @{
03014   */
03015 /**
03016   * @brief  Set the trigger output (TRGO) used for timer synchronization .
03017   * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
03018   *       whether or not a timer instance can operate as a master timer.
03019   * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
03020   * @param  TIMx Timer instance
03021   * @param  TimerSynchronization This parameter can be one of the following values:
03022   *         @arg @ref LL_TIM_TRGO_RESET
03023   *         @arg @ref LL_TIM_TRGO_ENABLE
03024   *         @arg @ref LL_TIM_TRGO_UPDATE
03025   *         @arg @ref LL_TIM_TRGO_CC1IF
03026   *         @arg @ref LL_TIM_TRGO_OC1REF
03027   *         @arg @ref LL_TIM_TRGO_OC2REF
03028   *         @arg @ref LL_TIM_TRGO_OC3REF
03029   *         @arg @ref LL_TIM_TRGO_OC4REF
03030   * @retval None
03031   */
03032 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
03033 {
03034   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
03035 }
03036
03037 /**
03038   * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
03039   * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
03040   *       whether or not a timer instance can be used for ADC synchronization.
03041   * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
03042   * @param  TIMx Timer Instance
03043   * @param  ADCSynchronization This parameter can be one of the following values:
03044   *         @arg @ref LL_TIM_TRGO2_RESET
03045   *         @arg @ref LL_TIM_TRGO2_ENABLE
03046   *         @arg @ref LL_TIM_TRGO2_UPDATE
03047   *         @arg @ref LL_TIM_TRGO2_CC1F
03048   *         @arg @ref LL_TIM_TRGO2_OC1
03049   *         @arg @ref LL_TIM_TRGO2_OC2
03050   *         @arg @ref LL_TIM_TRGO2_OC3
03051   *         @arg @ref LL_TIM_TRGO2_OC4
03052   *         @arg @ref LL_TIM_TRGO2_OC5
03053   *         @arg @ref LL_TIM_TRGO2_OC6
03054   *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
03055   *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
03056   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
03057   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
03058   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
03059   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
03060   * @retval None
03061   */
03062 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
03063 {
03064   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
03065 }
03066
03067 /**
03068   * @brief  Set the synchronization mode of a slave timer.
03069   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03070   *       a timer instance can operate as a slave timer.
03071   * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
03072   * @param  TIMx Timer instance
03073   * @param  SlaveMode This parameter can be one of the following values:
03074   *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
03075   *         @arg @ref LL_TIM_SLAVEMODE_RESET
03076   *         @arg @ref LL_TIM_SLAVEMODE_GATED
03077   *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
03078   *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
03079   * @retval None
03080   */
03081 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
03082 {
03083   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
03084 }
03085
03086 /**
03087   * @brief  Set the selects the trigger input to be used to synchronize the counter.
03088   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03089   *       a timer instance can operate as a slave timer.
03090   * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
03091   * @param  TIMx Timer instance
03092   * @param  TriggerInput This parameter can be one of the following values:
03093   *         @arg @ref LL_TIM_TS_ITR0
03094   *         @arg @ref LL_TIM_TS_ITR1
03095   *         @arg @ref LL_TIM_TS_ITR2
03096   *         @arg @ref LL_TIM_TS_ITR3
03097   *         @arg @ref LL_TIM_TS_TI1F_ED
03098   *         @arg @ref LL_TIM_TS_TI1FP1
03099   *         @arg @ref LL_TIM_TS_TI2FP2
03100   *         @arg @ref LL_TIM_TS_ETRF
03101   *         @arg @ref LL_TIM_TS_ITR4
03102   *         @arg @ref LL_TIM_TS_ITR5
03103   *         @arg @ref LL_TIM_TS_ITR6
03104   *         @arg @ref LL_TIM_TS_ITR7
03105   *         @arg @ref LL_TIM_TS_ITR8
03106   * @retval None
03107   */
03108 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
03109 {
03110   MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
03111 }
03112
03113 /**
03114   * @brief  Enable the Master/Slave mode.
03115   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03116   *       a timer instance can operate as a slave timer.
03117   * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
03118   * @param  TIMx Timer instance
03119   * @retval None
03120   */
03121 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
03122 {
03123   SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
03124 }
03125
03126 /**
03127   * @brief  Disable the Master/Slave mode.
03128   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03129   *       a timer instance can operate as a slave timer.
03130   * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
03131   * @param  TIMx Timer instance
03132   * @retval None
03133   */
03134 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
03135 {
03136   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
03137 }
03138
03139 /**
03140   * @brief Indicates whether the Master/Slave mode is enabled.
03141   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03142   * a timer instance can operate as a slave timer.
03143   * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
03144   * @param  TIMx Timer instance
03145   * @retval State of bit (1 or 0).
03146   */
03147 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
03148 {
03149   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
03150 }
03151
03152 /**
03153   * @brief  Configure the external trigger (ETR) input.
03154   * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
03155   *       a timer instance provides an external trigger input.
03156   * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
03157   *         SMCR         ETPS          LL_TIM_ConfigETR\n
03158   *         SMCR         ETF           LL_TIM_ConfigETR
03159   * @param  TIMx Timer instance
03160   * @param  ETRPolarity This parameter can be one of the following values:
03161   *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
03162   *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
03163   * @param  ETRPrescaler This parameter can be one of the following values:
03164   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
03165   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
03166   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
03167   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
03168   * @param  ETRFilter This parameter can be one of the following values:
03169   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
03170   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
03171   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
03172   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
03173   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
03174   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
03175   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
03176   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
03177   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
03178   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
03179   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
03180   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
03181   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
03182   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
03183   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
03184   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
03185   * @retval None
03186   */
03187 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
03188                                       uint32_t ETRFilter)
03189 {
03190   MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
03191 }
03192
03193 /**
03194   * @}
03195   */
03196
03197 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
03198   * @{
03199   */
03200 /**
03201   * @brief  Enable the break function.
03202   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03203   *       a timer instance provides a break input.
03204   * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
03205   * @param  TIMx Timer instance
03206   * @retval None
03207   */
03208 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
03209 {
03210   SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
03211 }
03212
03213 /**
03214   * @brief  Disable the break function.
03215   * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
03216   * @param  TIMx Timer instance
03217   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03218   *       a timer instance provides a break input.
03219   * @retval None
03220   */
03221 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
03222 {
03223   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
03224 }
03225
03226 /**
03227   * @brief  Configure the break input.
03228   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03229   *       a timer instance provides a break input.
03230   * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
03231   *         BDTR         BKF           LL_TIM_ConfigBRK
03232   * @param  TIMx Timer instance
03233   * @param  BreakPolarity This parameter can be one of the following values:
03234   *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
03235   *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
03236   * @param  BreakFilter This parameter can be one of the following values:
03237   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
03238   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
03239   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
03240   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
03241   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
03242   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
03243   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
03244   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
03245   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
03246   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
03247   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
03248   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
03249   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
03250   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
03251   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
03252   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
03253   * @retval None
03254   */
03255 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
03256                                       uint32_t BreakFilter)
03257 {
03258   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
03259 }
03260
03261 /**
03262   * @brief  Enable the break 2 function.
03263   * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03264   *       a timer instance provides a second break input.
03265   * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
03266   * @param  TIMx Timer instance
03267   * @retval None
03268   */
03269 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
03270 {
03271   SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
03272 }
03273
03274 /**
03275   * @brief  Disable the break  2 function.
03276   * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03277   *       a timer instance provides a second break input.
03278   * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
03279   * @param  TIMx Timer instance
03280   * @retval None
03281   */
03282 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
03283 {
03284   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
03285 }
03286
03287 /**
03288   * @brief  Configure the break 2 input.
03289   * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03290   *       a timer instance provides a second break input.
03291   * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
03292   *         BDTR         BK2F          LL_TIM_ConfigBRK2
03293   * @param  TIMx Timer instance
03294   * @param  Break2Polarity This parameter can be one of the following values:
03295   *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
03296   *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
03297   * @param  Break2Filter This parameter can be one of the following values:
03298   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
03299   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
03300   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
03301   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
03302   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
03303   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
03304   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
03305   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
03306   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
03307   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
03308   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
03309   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
03310   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
03311   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
03312   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
03313   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
03314   * @retval None
03315   */
03316 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
03317 {
03318   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
03319 }
03320
03321 /**
03322   * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
03323   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03324   *       a timer instance provides a break input.
03325   * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
03326   *         BDTR         OSSR          LL_TIM_SetOffStates
03327   * @param  TIMx Timer instance
03328   * @param  OffStateIdle This parameter can be one of the following values:
03329   *         @arg @ref LL_TIM_OSSI_DISABLE
03330   *         @arg @ref LL_TIM_OSSI_ENABLE
03331   * @param  OffStateRun This parameter can be one of the following values:
03332   *         @arg @ref LL_TIM_OSSR_DISABLE
03333   *         @arg @ref LL_TIM_OSSR_ENABLE
03334   * @retval None
03335   */
03336 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
03337 {
03338   MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
03339 }
03340
03341 /**
03342   * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
03343   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03344   *       a timer instance provides a break input.
03345   * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
03346   * @param  TIMx Timer instance
03347   * @retval None
03348   */
03349 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
03350 {
03351   SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
03352 }
03353
03354 /**
03355   * @brief  Disable automatic output (MOE can be set only by software).
03356   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03357   *       a timer instance provides a break input.
03358   * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
03359   * @param  TIMx Timer instance
03360   * @retval None
03361   */
03362 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
03363 {
03364   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
03365 }
03366
03367 /**
03368   * @brief  Indicate whether automatic output is enabled.
03369   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03370   *       a timer instance provides a break input.
03371   * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
03372   * @param  TIMx Timer instance
03373   * @retval State of bit (1 or 0).
03374   */
03375 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
03376 {
03377   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
03378 }
03379
03380 /**
03381   * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
03382   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
03383   *       software and is reset in case of break or break2 event
03384   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03385   *       a timer instance provides a break input.
03386   * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
03387   * @param  TIMx Timer instance
03388   * @retval None
03389   */
03390 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
03391 {
03392   SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
03393 }
03394
03395 /**
03396   * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
03397   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
03398   *       software and is reset in case of break or break2 event.
03399   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03400   *       a timer instance provides a break input.
03401   * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
03402   * @param  TIMx Timer instance
03403   * @retval None
03404   */
03405 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
03406 {
03407   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
03408 }
03409
03410 /**
03411   * @brief  Indicates whether outputs are enabled.
03412   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03413   *       a timer instance provides a break input.
03414   * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
03415   * @param  TIMx Timer instance
03416   * @retval State of bit (1 or 0).
03417   */
03418 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
03419 {
03420   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
03421 }
03422
03423 #if defined(TIM_BREAK_INPUT_SUPPORT)
03424 /**
03425   * @brief  Enable the signals connected to the designated timer break input.
03426   * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03427   *       or not a timer instance allows for break input selection.
03428   * @rmtoll AF1          BKINE         LL_TIM_EnableBreakInputSource\n
03429   *         AF1          BKCMP1E       LL_TIM_EnableBreakInputSource\n
03430   *         AF1          BKCMP2E       LL_TIM_EnableBreakInputSource\n
03431   *         AF1          BKDF1BK0E     LL_TIM_EnableBreakInputSource\n
03432   *         AF2          BK2INE        LL_TIM_EnableBreakInputSource\n
03433   *         AF2          BK2CMP1E      LL_TIM_EnableBreakInputSource\n
03434   *         AF2          BK2CMP2E      LL_TIM_EnableBreakInputSource\n
03435   *         AF2          BK2DF1BK1E    LL_TIM_EnableBreakInputSource
03436   * @param  TIMx Timer instance
03437   * @param  BreakInput This parameter can be one of the following values:
03438   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
03439   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
03440   * @param  Source This parameter can be one of the following values:
03441   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
03442   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
03443   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
03444   *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
03445   * @retval None
03446   */
03447 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
03448 {
03449   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
03450   SET_BIT(*pReg, Source);
03451 }
03452
03453 /**
03454   * @brief  Disable the signals connected to the designated timer break input.
03455   * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03456   *       or not a timer instance allows for break input selection.
03457   * @rmtoll AF1          BKINE         LL_TIM_DisableBreakInputSource\n
03458   *         AF1          BKCMP1E       LL_TIM_DisableBreakInputSource\n
03459   *         AF1          BKCMP2E       LL_TIM_DisableBreakInputSource\n
03460   *         AF1          BKDF1BK0E     LL_TIM_DisableBreakInputSource\n
03461   *         AF2          BK2INE        LL_TIM_DisableBreakInputSource\n
03462   *         AF2          BK2CMP1E      LL_TIM_DisableBreakInputSource\n
03463   *         AF2          BK2CMP2E      LL_TIM_DisableBreakInputSource\n
03464   *         AF2          BK2DF1BK1E    LL_TIM_DisableBreakInputSource
03465   * @param  TIMx Timer instance
03466   * @param  BreakInput This parameter can be one of the following values:
03467   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
03468   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
03469   * @param  Source This parameter can be one of the following values:
03470   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
03471   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
03472   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
03473   *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
03474   * @retval None
03475   */
03476 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
03477 {
03478   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
03479   CLEAR_BIT(*pReg, Source);
03480 }
03481
03482 /**
03483   * @brief  Set the polarity of the break signal for the timer break input.
03484   * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03485   *       or not a timer instance allows for break input selection.
03486   * @rmtoll AF1          BKINP         LL_TIM_SetBreakInputSourcePolarity\n
03487   *         AF1          BKCMP1P       LL_TIM_SetBreakInputSourcePolarity\n
03488   *         AF1          BKCMP2P       LL_TIM_SetBreakInputSourcePolarity\n
03489   *         AF2          BK2INP        LL_TIM_SetBreakInputSourcePolarity\n
03490   *         AF2          BK2CMP1P      LL_TIM_SetBreakInputSourcePolarity\n
03491   *         AF2          BK2CMP2P      LL_TIM_SetBreakInputSourcePolarity
03492   * @param  TIMx Timer instance
03493   * @param  BreakInput This parameter can be one of the following values:
03494   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
03495   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
03496   * @param  Source This parameter can be one of the following values:
03497   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
03498   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
03499   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
03500   * @param  Polarity This parameter can be one of the following values:
03501   *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
03502   *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
03503   * @retval None
03504   */
03505 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
03506                                                         uint32_t Polarity)
03507 {
03508   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
03509   MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
03510 }
03511 #endif /* TIM_BREAK_INPUT_SUPPORT */
03512 /**
03513   * @}
03514   */
03515
03516 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
03517   * @{
03518   */
03519 /**
03520   * @brief  Configures the timer DMA burst feature.
03521   * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
03522   *       not a timer instance supports the DMA burst mode.
03523   * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
03524   *         DCR          DBA           LL_TIM_ConfigDMABurst
03525   * @param  TIMx Timer instance
03526   * @param  DMABurstBaseAddress This parameter can be one of the following values:
03527   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
03528   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
03529   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
03530   *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
03531   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
03532   *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
03533   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
03534   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
03535   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
03536   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
03537   *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
03538   *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
03539   *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
03540   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
03541   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
03542   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
03543   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
03544   *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
03545   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
03546   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
03547   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
03548   *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
03549   *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
03550   *         @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
03551   *
03552   * @param  DMABurstLength This parameter can be one of the following values:
03553   *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
03554   *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
03555   *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
03556   *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
03557   *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
03558   *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
03559   *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
03560   *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
03561   *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
03562   *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
03563   *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
03564   *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
03565   *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
03566   *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
03567   *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
03568   *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
03569   *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
03570   *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
03571   * @retval None
03572   */
03573 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
03574 {
03575   MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
03576 }
03577
03578 /**
03579   * @}
03580   */
03581
03582 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
03583   * @{
03584   */
03585 /**
03586   * @brief  Remap TIM inputs (input channel, internal/external triggers).
03587   * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
03588   *       a some timer inputs can be remapped.
03589   * @retval None
03590   */
03591 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
03592 {
03593   MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
03594 }
03595
03596 /**
03597   * @}
03598   */
03599
03600 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
03601   * @{
03602   */
03603 /**
03604   * @brief  Clear the update interrupt flag (UIF).
03605   * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
03606   * @param  TIMx Timer instance
03607   * @retval None
03608   */
03609 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
03610 {
03611   WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
03612 }
03613
03614 /**
03615   * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
03616   * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
03617   * @param  TIMx Timer instance
03618   * @retval State of bit (1 or 0).
03619   */
03620 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
03621 {
03622   return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
03623 }
03624
03625 /**
03626   * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
03627   * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
03628   * @param  TIMx Timer instance
03629   * @retval None
03630   */
03631 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
03632 {
03633   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
03634 }
03635
03636 /**
03637   * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
03638   * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
03639   * @param  TIMx Timer instance
03640   * @retval State of bit (1 or 0).
03641   */
03642 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
03643 {
03644   return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
03645 }
03646
03647 /**
03648   * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
03649   * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
03650   * @param  TIMx Timer instance
03651   * @retval None
03652   */
03653 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
03654 {
03655   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
03656 }
03657
03658 /**
03659   * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
03660   * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
03661   * @param  TIMx Timer instance
03662   * @retval State of bit (1 or 0).
03663   */
03664 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
03665 {
03666   return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
03667 }
03668
03669 /**
03670   * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
03671   * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
03672   * @param  TIMx Timer instance
03673   * @retval None
03674   */
03675 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
03676 {
03677   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
03678 }
03679
03680 /**
03681   * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
03682   * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
03683   * @param  TIMx Timer instance
03684   * @retval State of bit (1 or 0).
03685   */
03686 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
03687 {
03688   return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
03689 }
03690
03691 /**
03692   * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
03693   * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
03694   * @param  TIMx Timer instance
03695   * @retval None
03696   */
03697 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
03698 {
03699   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
03700 }
03701
03702 /**
03703   * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
03704   * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
03705   * @param  TIMx Timer instance
03706   * @retval State of bit (1 or 0).
03707   */
03708 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
03709 {
03710   return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
03711 }
03712
03713 /**
03714   * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
03715   * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
03716   * @param  TIMx Timer instance
03717   * @retval None
03718   */
03719 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
03720 {
03721   WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
03722 }
03723
03724 /**
03725   * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
03726   * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
03727   * @param  TIMx Timer instance
03728   * @retval State of bit (1 or 0).
03729   */
03730 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
03731 {
03732   return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
03733 }
03734
03735 /**
03736   * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
03737   * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
03738   * @param  TIMx Timer instance
03739   * @retval None
03740   */
03741 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
03742 {
03743   WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
03744 }
03745
03746 /**
03747   * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
03748   * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
03749   * @param  TIMx Timer instance
03750   * @retval State of bit (1 or 0).
03751   */
03752 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
03753 {
03754   return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
03755 }
03756
03757 /**
03758   * @brief  Clear the commutation interrupt flag (COMIF).
03759   * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
03760   * @param  TIMx Timer instance
03761   * @retval None
03762   */
03763 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
03764 {
03765   WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
03766 }
03767
03768 /**
03769   * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
03770   * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
03771   * @param  TIMx Timer instance
03772   * @retval State of bit (1 or 0).
03773   */
03774 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
03775 {
03776   return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
03777 }
03778
03779 /**
03780   * @brief  Clear the trigger interrupt flag (TIF).
03781   * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
03782   * @param  TIMx Timer instance
03783   * @retval None
03784   */
03785 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
03786 {
03787   WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
03788 }
03789
03790 /**
03791   * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
03792   * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
03793   * @param  TIMx Timer instance
03794   * @retval State of bit (1 or 0).
03795   */
03796 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
03797 {
03798   return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
03799 }
03800
03801 /**
03802   * @brief  Clear the break interrupt flag (BIF).
03803   * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
03804   * @param  TIMx Timer instance
03805   * @retval None
03806   */
03807 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
03808 {
03809   WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
03810 }
03811
03812 /**
03813   * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
03814   * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
03815   * @param  TIMx Timer instance
03816   * @retval State of bit (1 or 0).
03817   */
03818 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
03819 {
03820   return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
03821 }
03822
03823 /**
03824   * @brief  Clear the break 2 interrupt flag (B2IF).
03825   * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
03826   * @param  TIMx Timer instance
03827   * @retval None
03828   */
03829 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
03830 {
03831   WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
03832 }
03833
03834 /**
03835   * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
03836   * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
03837   * @param  TIMx Timer instance
03838   * @retval State of bit (1 or 0).
03839   */
03840 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
03841 {
03842   return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
03843 }
03844
03845 /**
03846   * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
03847   * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
03848   * @param  TIMx Timer instance
03849   * @retval None
03850   */
03851 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
03852 {
03853   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
03854 }
03855
03856 /**
03857   * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
03858   * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
03859   * @param  TIMx Timer instance
03860   * @retval State of bit (1 or 0).
03861   */
03862 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
03863 {
03864   return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
03865 }
03866
03867 /**
03868   * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
03869   * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
03870   * @param  TIMx Timer instance
03871   * @retval None
03872   */
03873 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
03874 {
03875   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
03876 }
03877
03878 /**
03879   * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
03880   * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
03881   * @param  TIMx Timer instance
03882   * @retval State of bit (1 or 0).
03883   */
03884 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
03885 {
03886   return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
03887 }
03888
03889 /**
03890   * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
03891   * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
03892   * @param  TIMx Timer instance
03893   * @retval None
03894   */
03895 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
03896 {
03897   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
03898 }
03899
03900 /**
03901   * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
03902   * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
03903   * @param  TIMx Timer instance
03904   * @retval State of bit (1 or 0).
03905   */
03906 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
03907 {
03908   return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
03909 }
03910
03911 /**
03912   * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
03913   * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
03914   * @param  TIMx Timer instance
03915   * @retval None
03916   */
03917 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
03918 {
03919   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
03920 }
03921
03922 /**
03923   * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
03924   * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
03925   * @param  TIMx Timer instance
03926   * @retval State of bit (1 or 0).
03927   */
03928 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
03929 {
03930   return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
03931 }
03932
03933 /**
03934   * @brief  Clear the system break interrupt flag (SBIF).
03935   * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
03936   * @param  TIMx Timer instance
03937   * @retval None
03938   */
03939 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
03940 {
03941   WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
03942 }
03943
03944 /**
03945   * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
03946   * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
03947   * @param  TIMx Timer instance
03948   * @retval State of bit (1 or 0).
03949   */
03950 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
03951 {
03952   return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
03953 }
03954
03955 /**
03956   * @}
03957   */
03958
03959 /** @defgroup TIM_LL_EF_IT_Management IT-Management
03960   * @{
03961   */
03962 /**
03963   * @brief  Enable update interrupt (UIE).
03964   * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
03965   * @param  TIMx Timer instance
03966   * @retval None
03967   */
03968 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
03969 {
03970   SET_BIT(TIMx->DIER, TIM_DIER_UIE);
03971 }
03972
03973 /**
03974   * @brief  Disable update interrupt (UIE).
03975   * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
03976   * @param  TIMx Timer instance
03977   * @retval None
03978   */
03979 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
03980 {
03981   CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
03982 }
03983
03984 /**
03985   * @brief  Indicates whether the update interrupt (UIE) is enabled.
03986   * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
03987   * @param  TIMx Timer instance
03988   * @retval State of bit (1 or 0).
03989   */
03990 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
03991 {
03992   return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
03993 }
03994
03995 /**
03996   * @brief  Enable capture/compare 1 interrupt (CC1IE).
03997   * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
03998   * @param  TIMx Timer instance
03999   * @retval None
04000   */
04001 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
04002 {
04003   SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
04004 }
04005
04006 /**
04007   * @brief  Disable capture/compare 1  interrupt (CC1IE).
04008   * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
04009   * @param  TIMx Timer instance
04010   * @retval None
04011   */
04012 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
04013 {
04014   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
04015 }
04016
04017 /**
04018   * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
04019   * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
04020   * @param  TIMx Timer instance
04021   * @retval State of bit (1 or 0).
04022   */
04023 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
04024 {
04025   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
04026 }
04027
04028 /**
04029   * @brief  Enable capture/compare 2 interrupt (CC2IE).
04030   * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
04031   * @param  TIMx Timer instance
04032   * @retval None
04033   */
04034 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
04035 {
04036   SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
04037 }
04038
04039 /**
04040   * @brief  Disable capture/compare 2  interrupt (CC2IE).
04041   * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
04042   * @param  TIMx Timer instance
04043   * @retval None
04044   */
04045 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
04046 {
04047   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
04048 }
04049
04050 /**
04051   * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
04052   * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
04053   * @param  TIMx Timer instance
04054   * @retval State of bit (1 or 0).
04055   */
04056 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
04057 {
04058   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
04059 }
04060
04061 /**
04062   * @brief  Enable capture/compare 3 interrupt (CC3IE).
04063   * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
04064   * @param  TIMx Timer instance
04065   * @retval None
04066   */
04067 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
04068 {
04069   SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
04070 }
04071
04072 /**
04073   * @brief  Disable capture/compare 3  interrupt (CC3IE).
04074   * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
04075   * @param  TIMx Timer instance
04076   * @retval None
04077   */
04078 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
04079 {
04080   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
04081 }
04082
04083 /**
04084   * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
04085   * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
04086   * @param  TIMx Timer instance
04087   * @retval State of bit (1 or 0).
04088   */
04089 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
04090 {
04091   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
04092 }
04093
04094 /**
04095   * @brief  Enable capture/compare 4 interrupt (CC4IE).
04096   * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
04097   * @param  TIMx Timer instance
04098   * @retval None
04099   */
04100 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
04101 {
04102   SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
04103 }
04104
04105 /**
04106   * @brief  Disable capture/compare 4  interrupt (CC4IE).
04107   * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
04108   * @param  TIMx Timer instance
04109   * @retval None
04110   */
04111 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
04112 {
04113   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
04114 }
04115
04116 /**
04117   * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
04118   * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
04119   * @param  TIMx Timer instance
04120   * @retval State of bit (1 or 0).
04121   */
04122 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
04123 {
04124   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
04125 }
04126
04127 /**
04128   * @brief  Enable commutation interrupt (COMIE).
04129   * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
04130   * @param  TIMx Timer instance
04131   * @retval None
04132   */
04133 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
04134 {
04135   SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
04136 }
04137
04138 /**
04139   * @brief  Disable commutation interrupt (COMIE).
04140   * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
04141   * @param  TIMx Timer instance
04142   * @retval None
04143   */
04144 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
04145 {
04146   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
04147 }
04148
04149 /**
04150   * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
04151   * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
04152   * @param  TIMx Timer instance
04153   * @retval State of bit (1 or 0).
04154   */
04155 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
04156 {
04157   return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
04158 }
04159
04160 /**
04161   * @brief  Enable trigger interrupt (TIE).
04162   * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
04163   * @param  TIMx Timer instance
04164   * @retval None
04165   */
04166 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
04167 {
04168   SET_BIT(TIMx->DIER, TIM_DIER_TIE);
04169 }
04170
04171 /**
04172   * @brief  Disable trigger interrupt (TIE).
04173   * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
04174   * @param  TIMx Timer instance
04175   * @retval None
04176   */
04177 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
04178 {
04179   CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
04180 }
04181
04182 /**
04183   * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
04184   * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
04185   * @param  TIMx Timer instance
04186   * @retval State of bit (1 or 0).
04187   */
04188 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
04189 {
04190   return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
04191 }
04192
04193 /**
04194   * @brief  Enable break interrupt (BIE).
04195   * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
04196   * @param  TIMx Timer instance
04197   * @retval None
04198   */
04199 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
04200 {
04201   SET_BIT(TIMx->DIER, TIM_DIER_BIE);
04202 }
04203
04204 /**
04205   * @brief  Disable break interrupt (BIE).
04206   * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
04207   * @param  TIMx Timer instance
04208   * @retval None
04209   */
04210 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
04211 {
04212   CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
04213 }
04214
04215 /**
04216   * @brief  Indicates whether the break interrupt (BIE) is enabled.
04217   * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
04218   * @param  TIMx Timer instance
04219   * @retval State of bit (1 or 0).
04220   */
04221 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
04222 {
04223   return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
04224 }
04225
04226 /**
04227   * @}
04228   */
04229
04230 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
04231   * @{
04232   */
04233 /**
04234   * @brief  Enable update DMA request (UDE).
04235   * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
04236   * @param  TIMx Timer instance
04237   * @retval None
04238   */
04239 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
04240 {
04241   SET_BIT(TIMx->DIER, TIM_DIER_UDE);
04242 }
04243
04244 /**
04245   * @brief  Disable update DMA request (UDE).
04246   * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
04247   * @param  TIMx Timer instance
04248   * @retval None
04249   */
04250 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
04251 {
04252   CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
04253 }
04254
04255 /**
04256   * @brief  Indicates whether the update DMA request  (UDE) is enabled.
04257   * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
04258   * @param  TIMx Timer instance
04259   * @retval State of bit (1 or 0).
04260   */
04261 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
04262 {
04263   return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
04264 }
04265
04266 /**
04267   * @brief  Enable capture/compare 1 DMA request (CC1DE).
04268   * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
04269   * @param  TIMx Timer instance
04270   * @retval None
04271   */
04272 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
04273 {
04274   SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
04275 }
04276
04277 /**
04278   * @brief  Disable capture/compare 1  DMA request (CC1DE).
04279   * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
04280   * @param  TIMx Timer instance
04281   * @retval None
04282   */
04283 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
04284 {
04285   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
04286 }
04287
04288 /**
04289   * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
04290   * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
04291   * @param  TIMx Timer instance
04292   * @retval State of bit (1 or 0).
04293   */
04294 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
04295 {
04296   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
04297 }
04298
04299 /**
04300   * @brief  Enable capture/compare 2 DMA request (CC2DE).
04301   * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
04302   * @param  TIMx Timer instance
04303   * @retval None
04304   */
04305 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
04306 {
04307   SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
04308 }
04309
04310 /**
04311   * @brief  Disable capture/compare 2  DMA request (CC2DE).
04312   * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
04313   * @param  TIMx Timer instance
04314   * @retval None
04315   */
04316 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
04317 {
04318   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
04319 }
04320
04321 /**
04322   * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
04323   * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
04324   * @param  TIMx Timer instance
04325   * @retval State of bit (1 or 0).
04326   */
04327 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
04328 {
04329   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
04330 }
04331
04332 /**
04333   * @brief  Enable capture/compare 3 DMA request (CC3DE).
04334   * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
04335   * @param  TIMx Timer instance
04336   * @retval None
04337   */
04338 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
04339 {
04340   SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
04341 }
04342
04343 /**
04344   * @brief  Disable capture/compare 3  DMA request (CC3DE).
04345   * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
04346   * @param  TIMx Timer instance
04347   * @retval None
04348   */
04349 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
04350 {
04351   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
04352 }
04353
04354 /**
04355   * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
04356   * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
04357   * @param  TIMx Timer instance
04358   * @retval State of bit (1 or 0).
04359   */
04360 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
04361 {
04362   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
04363 }
04364
04365 /**
04366   * @brief  Enable capture/compare 4 DMA request (CC4DE).
04367   * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
04368   * @param  TIMx Timer instance
04369   * @retval None
04370   */
04371 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
04372 {
04373   SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
04374 }
04375
04376 /**
04377   * @brief  Disable capture/compare 4  DMA request (CC4DE).
04378   * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
04379   * @param  TIMx Timer instance
04380   * @retval None
04381   */
04382 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
04383 {
04384   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
04385 }
04386
04387 /**
04388   * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
04389   * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
04390   * @param  TIMx Timer instance
04391   * @retval State of bit (1 or 0).
04392   */
04393 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
04394 {
04395   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
04396 }
04397
04398 /**
04399   * @brief  Enable commutation DMA request (COMDE).
04400   * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
04401   * @param  TIMx Timer instance
04402   * @retval None
04403   */
04404 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
04405 {
04406   SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
04407 }
04408
04409 /**
04410   * @brief  Disable commutation DMA request (COMDE).
04411   * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
04412   * @param  TIMx Timer instance
04413   * @retval None
04414   */
04415 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
04416 {
04417   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
04418 }
04419
04420 /**
04421   * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
04422   * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
04423   * @param  TIMx Timer instance
04424   * @retval State of bit (1 or 0).
04425   */
04426 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
04427 {
04428   return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
04429 }
04430
04431 /**
04432   * @brief  Enable trigger interrupt (TDE).
04433   * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
04434   * @param  TIMx Timer instance
04435   * @retval None
04436   */
04437 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
04438 {
04439   SET_BIT(TIMx->DIER, TIM_DIER_TDE);
04440 }
04441
04442 /**
04443   * @brief  Disable trigger interrupt (TDE).
04444   * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
04445   * @param  TIMx Timer instance
04446   * @retval None
04447   */
04448 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
04449 {
04450   CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
04451 }
04452
04453 /**
04454   * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
04455   * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
04456   * @param  TIMx Timer instance
04457   * @retval State of bit (1 or 0).
04458   */
04459 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
04460 {
04461   return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
04462 }
04463
04464 /**
04465   * @}
04466   */
04467
04468 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
04469   * @{
04470   */
04471 /**
04472   * @brief  Generate an update event.
04473   * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
04474   * @param  TIMx Timer instance
04475   * @retval None
04476   */
04477 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
04478 {
04479   SET_BIT(TIMx->EGR, TIM_EGR_UG);
04480 }
04481
04482 /**
04483   * @brief  Generate Capture/Compare 1 event.
04484   * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
04485   * @param  TIMx Timer instance
04486   * @retval None
04487   */
04488 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
04489 {
04490   SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
04491 }
04492
04493 /**
04494   * @brief  Generate Capture/Compare 2 event.
04495   * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
04496   * @param  TIMx Timer instance
04497   * @retval None
04498   */
04499 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
04500 {
04501   SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
04502 }
04503
04504 /**
04505   * @brief  Generate Capture/Compare 3 event.
04506   * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
04507   * @param  TIMx Timer instance
04508   * @retval None
04509   */
04510 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
04511 {
04512   SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
04513 }
04514
04515 /**
04516   * @brief  Generate Capture/Compare 4 event.
04517   * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
04518   * @param  TIMx Timer instance
04519   * @retval None
04520   */
04521 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
04522 {
04523   SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
04524 }
04525
04526 /**
04527   * @brief  Generate commutation event.
04528   * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
04529   * @param  TIMx Timer instance
04530   * @retval None
04531   */
04532 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
04533 {
04534   SET_BIT(TIMx->EGR, TIM_EGR_COMG);
04535 }
04536
04537 /**
04538   * @brief  Generate trigger event.
04539   * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
04540   * @param  TIMx Timer instance
04541   * @retval None
04542   */
04543 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
04544 {
04545   SET_BIT(TIMx->EGR, TIM_EGR_TG);
04546 }
04547
04548 /**
04549   * @brief  Generate break event.
04550   * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
04551   * @param  TIMx Timer instance
04552   * @retval None
04553   */
04554 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
04555 {
04556   SET_BIT(TIMx->EGR, TIM_EGR_BG);
04557 }
04558
04559 /**
04560   * @brief  Generate break 2 event.
04561   * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
04562   * @param  TIMx Timer instance
04563   * @retval None
04564   */
04565 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
04566 {
04567   SET_BIT(TIMx->EGR, TIM_EGR_B2G);
04568 }
04569
04570 /**
04571   * @}
04572   */
04573
04574 #if defined(USE_FULL_LL_DRIVER)
04575 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
04576   * @{
04577   */
04578
04579 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
04580 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
04581 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
04582 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
04583 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
04584 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
04585 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
04586 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
04587 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
04588 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
04589 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
04590 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
04591 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
04592 /**
04593   * @}
04594   */
04595 #endif /* USE_FULL_LL_DRIVER */
04596
04597 /**
04598   * @}
04599   */
04600
04601 /**
04602   * @}
04603   */
04604
04605 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 */
04606
04607 /**
04608   * @}
04609   */
04610
04611 #ifdef __cplusplus
04612 }
04613 #endif
04614
04615 #endif /* __STM32H7xx_LL_TIM_H */
04616 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Mar 29 2019 11:38:19 for STM32H757xx HAL User Manual by doxygen 1.7.6.1


STM32H757xx HAL User Manual: stm32h7xx_ll_usart.c Source File

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stm32h7xx_ll_usart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_usart.c
00004   * @author  MCD Application Team
00005   * @brief   USART LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32h7xx_ll_usart.h"
00023 #include "stm32h7xx_ll_rcc.h"
00024 #include "stm32h7xx_ll_bus.h"
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8)
00036
00037 /** @addtogroup USART_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @addtogroup USART_LL_Private_Constants
00045   * @{
00046   */
00047
00048 /**
00049   * @}
00050   */
00051
00052 /* Private macros ------------------------------------------------------------*/
00053 /** @addtogroup USART_LL_Private_Macros
00054   * @{
00055   */
00056
00057 #define IS_LL_USART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_USART_PRESCALER_DIV1) \
00058                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
00059                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
00060                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
00061                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
00062                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
00063                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
00064                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
00065                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
00066                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
00067                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
00068                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV256))
00069
00070 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
00071  *              divided by the smallest oversampling used on the USART (i.e. 8)    */
00072 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
00073
00074 /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
00075 #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
00076
00077 /* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
00078 #define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
00079
00080 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
00081                                        || ((__VALUE__) == LL_USART_DIRECTION_RX) \
00082                                        || ((__VALUE__) == LL_USART_DIRECTION_TX) \
00083                                        || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
00084
00085 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
00086                                     || ((__VALUE__) == LL_USART_PARITY_EVEN) \
00087                                     || ((__VALUE__) == LL_USART_PARITY_ODD))
00088
00089 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
00090                                        || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
00091                                        || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
00092
00093 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
00094                                           || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
00095
00096 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
00097                                               || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
00098
00099 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
00100                                         || ((__VALUE__) == LL_USART_PHASE_2EDGE))
00101
00102 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
00103                                            || ((__VALUE__) == LL_USART_POLARITY_HIGH))
00104
00105 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
00106                                          || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
00107
00108 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
00109                                       || ((__VALUE__) == LL_USART_STOPBITS_1) \
00110                                       || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
00111                                       || ((__VALUE__) == LL_USART_STOPBITS_2))
00112
00113 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
00114                                        || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
00115                                        || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
00116                                        || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
00117
00118 /**
00119   * @}
00120   */
00121
00122 /* Private function prototypes -----------------------------------------------*/
00123
00124 /* Exported functions --------------------------------------------------------*/
00125 /** @addtogroup USART_LL_Exported_Functions
00126   * @{
00127   */
00128
00129 /** @addtogroup USART_LL_EF_Init
00130   * @{
00131   */
00132
00133 /**
00134   * @brief  De-initialize USART registers (Registers restored to their default values).
00135   * @param  USARTx USART Instance
00136   * @retval An ErrorStatus enumeration value:
00137   *          - SUCCESS: USART registers are de-initialized
00138   *          - ERROR: USART registers are not de-initialized
00139   */
00140 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
00141 {
00142   ErrorStatus status = SUCCESS;
00143
00144   /* Check the parameters */
00145   assert_param(IS_UART_INSTANCE(USARTx));
00146
00147   if (USARTx == USART1)
00148   {
00149     /* Force reset of USART clock */
00150     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
00151
00152     /* Release reset of USART clock */
00153     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
00154   }
00155   else if (USARTx == USART2)
00156   {
00157     /* Force reset of USART clock */
00158     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
00159
00160     /* Release reset of USART clock */
00161     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
00162   }
00163   else if (USARTx == USART3)
00164   {
00165     /* Force reset of USART clock */
00166     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
00167
00168     /* Release reset of USART clock */
00169     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
00170   }
00171   else if (USARTx == UART4)
00172   {
00173     /* Force reset of UART clock */
00174     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
00175
00176     /* Release reset of UART clock */
00177     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
00178   }
00179   else if (USARTx == UART5)
00180   {
00181     /* Force reset of UART clock */
00182     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
00183
00184     /* Release reset of UART clock */
00185     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
00186   }
00187   else if (USARTx == USART6)
00188   {
00189     /* Force reset of USART clock */
00190     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
00191
00192     /* Release reset of USART clock */
00193     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
00194   }
00195   else if (USARTx == UART7)
00196   {
00197     /* Force reset of UART clock */
00198     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);
00199
00200     /* Release reset of UART clock */
00201     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);
00202   }
00203   else if (USARTx == UART8)
00204   {
00205     /* Force reset of UART clock */
00206     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);
00207
00208     /* Release reset of UART clock */
00209     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);
00210   }
00211   else
00212   {
00213     status = ERROR;
00214   }
00215
00216   return (status);
00217 }
00218
00219 /**
00220   * @brief  Initialize USART registers according to the specified
00221   *         parameters in USART_InitStruct.
00222   * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
00223   *         USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00224   * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
00225   * @param  USARTx USART Instance
00226   * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure
00227   *         that contains the configuration information for the specified USART peripheral.
00228   * @retval An ErrorStatus enumeration value:
00229   *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
00230   *          - ERROR: Problem occurred during USART Registers initialization
00231   */
00232 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
00233 {
00234   ErrorStatus status = ERROR;
00235   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
00236
00237   /* Check the parameters */
00238   assert_param(IS_UART_INSTANCE(USARTx));
00239   assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue));
00240   assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
00241   assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
00242   assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
00243   assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
00244   assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
00245   assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
00246   assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
00247
00248   /* USART needs to be in disabled state, in order to be able to configure some bits in
00249      CRx registers */
00250   if (LL_USART_IsEnabled(USARTx) == 0U)
00251   {
00252     /*---------------------------- USART CR1 Configuration ---------------------
00253      * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
00254      * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
00255      * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
00256      * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
00257      * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
00258      */
00259     MODIFY_REG(USARTx->CR1,
00260                (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
00261                 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
00262                (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
00263                 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
00264
00265     /*---------------------------- USART CR2 Configuration ---------------------
00266      * Configure USARTx CR2 (Stop bits) with parameters:
00267      * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
00268      * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
00269      */
00270     LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
00271
00272     /*---------------------------- USART CR3 Configuration ---------------------
00273      * Configure USARTx CR3 (Hardware Flow Control) with parameters:
00274      * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
00275      */
00276     LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
00277
00278     /*---------------------------- USART BRR Configuration ---------------------
00279      * Retrieve Clock frequency used for USART Peripheral
00280      */
00281     if (USARTx == USART1)
00282     {
00283       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
00284     }
00285     else if (USARTx == USART2)
00286     {
00287       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
00288     }
00289     else if (USARTx == USART3)
00290     {
00291       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
00292     }
00293     else if (USARTx == UART4)
00294     {
00295       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
00296     }
00297     else if (USARTx == UART5)
00298     {
00299       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
00300     }
00301     else if (USARTx == USART6)
00302     {
00303       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
00304     }
00305     else if (USARTx == UART7)
00306     {
00307       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
00308     }
00309     else if (USARTx == UART8)
00310     {
00311       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
00312     }
00313     else
00314     {
00315       /* Nothing to do, as error code is already assigned to ERROR value */
00316     }
00317
00318     /* Configure the USART Baud Rate :
00319        - prescaler value is required
00320        - valid baud rate value (different from 0) is required
00321        - Peripheral clock as returned by RCC service, should be valid (different from 0).
00322     */
00323     if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
00324         && (USART_InitStruct->BaudRate != 0U))
00325     {
00326       status = SUCCESS;
00327       LL_USART_SetBaudRate(USARTx,
00328                            periphclk,
00329                            USART_InitStruct->PrescalerValue,
00330                            USART_InitStruct->OverSampling,
00331                            USART_InitStruct->BaudRate);
00332
00333       /* Check BRR is greater than or equal to 16d */
00334       assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
00335
00336       /* Check BRR is lower than or equal to 0xFFFF */
00337       assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
00338     }
00339
00340     /*---------------------------- USART PRESC Configuration -----------------------
00341      * Configure USARTx PRESC (Prescaler) with parameters:
00342      * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value.
00343      */
00344     LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue);
00345   }
00346   /* Endif (=> USART not in Disabled state => return ERROR) */
00347
00348   return (status);
00349 }
00350
00351 /**
00352   * @brief Set each @ref LL_USART_InitTypeDef field to default value.
00353   * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
00354   *                         whose fields will be set to default values.
00355   * @retval None
00356   */
00357
00358 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
00359 {
00360   /* Set USART_InitStruct fields to default values */
00361   USART_InitStruct->PrescalerValue      = LL_USART_PRESCALER_DIV1;
00362   USART_InitStruct->BaudRate            = 9600U;
00363   USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
00364   USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
00365   USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
00366   USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
00367   USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
00368   USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
00369 }
00370
00371 /**
00372   * @brief  Initialize USART Clock related settings according to the
00373   *         specified parameters in the USART_ClockInitStruct.
00374   * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
00375   *         USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00376   * @param  USARTx USART Instance
00377   * @param  USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
00378   *         that contains the Clock configuration information for the specified USART peripheral.
00379   * @retval An ErrorStatus enumeration value:
00380   *          - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
00381   *          - ERROR: Problem occurred during USART Registers initialization
00382   */
00383 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
00384 {
00385   ErrorStatus status = SUCCESS;
00386
00387   /* Check USART Instance and Clock signal output parameters */
00388   assert_param(IS_UART_INSTANCE(USARTx));
00389   assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
00390
00391   /* USART needs to be in disabled state, in order to be able to configure some bits in
00392      CRx registers */
00393   if (LL_USART_IsEnabled(USARTx) == 0U)
00394   {
00395     /*---------------------------- USART CR2 Configuration -----------------------*/
00396     /* If Clock signal has to be output */
00397     if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
00398     {
00399       /* Deactivate Clock signal delivery :
00400        * - Disable Clock Output:        USART_CR2_CLKEN cleared
00401        */
00402       LL_USART_DisableSCLKOutput(USARTx);
00403     }
00404     else
00405     {
00406       /* Ensure USART instance is USART capable */
00407       assert_param(IS_USART_INSTANCE(USARTx));
00408
00409       /* Check clock related parameters */
00410       assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
00411       assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
00412       assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
00413
00414       /*---------------------------- USART CR2 Configuration -----------------------
00415        * Configure USARTx CR2 (Clock signal related bits) with parameters:
00416        * - Enable Clock Output:         USART_CR2_CLKEN set
00417        * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
00418        * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
00419        * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
00420        */
00421       MODIFY_REG(USARTx->CR2,
00422                  USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
00423                  USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
00424                  USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
00425     }
00426   }
00427   /* Else (USART not in Disabled state => return ERROR */
00428   else
00429   {
00430     status = ERROR;
00431   }
00432
00433   return (status);
00434 }
00435
00436 /**
00437   * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
00438   * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
00439   *                              whose fields will be set to default values.
00440   * @retval None
00441   */
00442 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
00443 {
00444   /* Set LL_USART_ClockInitStruct fields with default values */
00445   USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
00446   USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00447   USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00448   USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00449 }
00450
00451 /**
00452   * @}
00453   */
00454
00455 /**
00456   * @}
00457   */
00458
00459 /**
00460   * @}
00461   */
00462
00463 #endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 */
00464
00465 /**
00466   * @}
00467   */
00468
00469 #endif /* USE_FULL_LL_DRIVER */
00470
00471 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00472


STM32H757xx HAL User Manual: stm32h7xx_ll_usart.h Source File

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stm32h7xx_ll_usart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_usart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of USART LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_USART_H
00022 #define STM32H7xx_LL_USART_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8)
00036
00037 /** @defgroup USART_LL USART
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /** @defgroup USART_LL_Private_Variables USART Private Variables
00044   * @{
00045   */
00046 /* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
00047 static const uint16_t USART_PRESCALER_TAB[] =
00048 {
00049   (uint16_t)1,
00050   (uint16_t)2,
00051   (uint16_t)4,
00052   (uint16_t)6,
00053   (uint16_t)8,
00054   (uint16_t)10,
00055   (uint16_t)12,
00056   (uint16_t)16,
00057   (uint16_t)32,
00058   (uint16_t)64,
00059   (uint16_t)128,
00060   (uint16_t)256
00061 };
00062 /**
00063   * @}
00064   */
00065
00066 /* Private constants ---------------------------------------------------------*/
00067 /** @defgroup USART_LL_Private_Constants USART Private Constants
00068   * @{
00069   */
00070 /**
00071   * @}
00072   */
00073
00074 /* Private macros ------------------------------------------------------------*/
00075 #if defined(USE_FULL_LL_DRIVER)
00076 /** @defgroup USART_LL_Private_Macros USART Private Macros
00077   * @{
00078   */
00079 /**
00080   * @}
00081   */
00082 #endif /*USE_FULL_LL_DRIVER*/
00083
00084 /* Exported types ------------------------------------------------------------*/
00085 #if defined(USE_FULL_LL_DRIVER)
00086 /** @defgroup USART_LL_ES_INIT USART Exported Init structures
00087   * @{
00088   */
00089
00090 /**
00091   * @brief LL USART Init Structure definition
00092   */
00093 typedef struct
00094 {
00095   uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
00096                                            This parameter can be a value of @ref USART_LL_EC_PRESCALER.
00097
00098                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/
00099
00100   uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
00101
00102                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
00103
00104   uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
00105                                            This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
00106
00107                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
00108
00109   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00110                                            This parameter can be a value of @ref USART_LL_EC_STOPBITS.
00111
00112                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
00113
00114   uint32_t Parity;                    /*!< Specifies the parity mode.
00115                                            This parameter can be a value of @ref USART_LL_EC_PARITY.
00116
00117                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
00118
00119   uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
00120                                            This parameter can be a value of @ref USART_LL_EC_DIRECTION.
00121
00122                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
00123
00124   uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
00125                                            This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
00126
00127                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
00128
00129   uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
00130                                            This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
00131
00132                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
00133
00134 } LL_USART_InitTypeDef;
00135
00136 /**
00137   * @brief LL USART Clock Init Structure definition
00138   */
00139 typedef struct
00140 {
00141   uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
00142                                            This parameter can be a value of @ref USART_LL_EC_CLOCK.
00143
00144                                            USART HW configuration can be modified afterwards using unitary functions
00145                                            @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
00146                                            For more details, refer to description of this function. */
00147
00148   uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
00149                                            This parameter can be a value of @ref USART_LL_EC_POLARITY.
00150
00151                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
00152                                            For more details, refer to description of this function. */
00153
00154   uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
00155                                            This parameter can be a value of @ref USART_LL_EC_PHASE.
00156
00157                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
00158                                            For more details, refer to description of this function. */
00159
00160   uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
00161                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00162                                            This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
00163
00164                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
00165                                            For more details, refer to description of this function. */
00166
00167 } LL_USART_ClockInitTypeDef;
00168
00169 /**
00170   * @}
00171   */
00172 #endif /* USE_FULL_LL_DRIVER */
00173
00174 /* Exported constants --------------------------------------------------------*/
00175 /** @defgroup USART_LL_Exported_Constants USART Exported Constants
00176   * @{
00177   */
00178
00179 /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
00180   * @brief    Flags defines which can be used with LL_USART_WriteReg function
00181   * @{
00182   */
00183 #define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error flag */
00184 #define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error flag */
00185 #define LL_USART_ICR_NECF                       USART_ICR_NECF                /*!< Noise error detected flag */
00186 #define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error flag */
00187 #define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected flag */
00188 #define LL_USART_ICR_TXFECF                     USART_ICR_TXFECF              /*!< TX FIFO Empty Clear flag */
00189 #define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete flag */
00190 #define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time flag */
00191 #define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection flag */
00192 #define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS flag */
00193 #define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout flag */
00194 #define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block flag */
00195 #define LL_USART_ICR_UDRCF                      USART_ICR_UDRCF               /*!< SPI Slave Underrun Clear flag */
00196 #define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match flag */
00197 #define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
00203   * @brief    Flags defines which can be used with LL_USART_ReadReg function
00204   * @{
00205   */
00206 #define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
00207 #define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
00208 #define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
00209 #define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
00210 #define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
00211 #define LL_USART_ISR_RXNE_RXFNE                 USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */
00212 #define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
00213 #define LL_USART_ISR_TXE_TXFNF                  USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/
00214 #define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
00215 #define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
00216 #define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
00217 #define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
00218 #define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
00219 #define LL_USART_ISR_UDR                        USART_ISR_UDR                 /*!< SPI Slave underrun error flag */
00220 #define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
00221 #define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
00222 #define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
00223 #define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
00224 #define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
00225 #define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
00226 #define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
00227 #define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
00228 #define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
00229 #define LL_USART_ISR_TXFE                       USART_ISR_TXFE                /*!< TX FIFO empty flag */
00230 #define LL_USART_ISR_RXFF                       USART_ISR_RXFF                /*!< RX FIFO full flag */
00231 #define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
00232 #define LL_USART_ISR_RXFT                       USART_ISR_RXFT                /*!< RX FIFO threshold flag */
00233 #define LL_USART_ISR_TXFT                       USART_ISR_TXFT                /*!< TX FIFO threshold flag */
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup USART_LL_EC_IT IT Defines
00239   * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
00240   * @{
00241   */
00242 #define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
00243 #define LL_USART_CR1_RXNEIE_RXFNEIE             USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */
00244 #define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
00245 #define LL_USART_CR1_TXEIE_TXFNFIE              USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */
00246 #define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
00247 #define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
00248 #define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
00249 #define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
00250 #define LL_USART_CR1_TXFEIE                     USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */
00251 #define LL_USART_CR1_RXFFIE                     USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */
00252 #define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
00253 #define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
00254 #define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
00255 #define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
00256 #define LL_USART_CR3_TXFTIE                     USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */
00257 #define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
00258 #define LL_USART_CR3_RXFTIE                     USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
00264   * @{
00265   */
00266 #define LL_USART_FIFOTHRESHOLD_1_8              0x00000000U /*!< FIFO reaches 1/8 of its depth */
00267 #define LL_USART_FIFOTHRESHOLD_1_4              0x00000001U /*!< FIFO reaches 1/4 of its depth */
00268 #define LL_USART_FIFOTHRESHOLD_1_2              0x00000002U /*!< FIFO reaches 1/2 of its depth */
00269 #define LL_USART_FIFOTHRESHOLD_3_4              0x00000003U /*!< FIFO reaches 3/4 of its depth */
00270 #define LL_USART_FIFOTHRESHOLD_7_8              0x00000004U /*!< FIFO reaches 7/8 of its depth */
00271 #define LL_USART_FIFOTHRESHOLD_8_8              0x00000005U /*!< FIFO becomes empty for TX and full for RX */
00272 /**
00273   * @}
00274   */
00275
00276 /** @defgroup USART_LL_EC_DIRECTION Communication Direction
00277   * @{
00278   */
00279 #define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
00280 #define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
00281 #define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
00282 #define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup USART_LL_EC_PARITY Parity Control
00288   * @{
00289   */
00290 #define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
00291 #define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
00292 #define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup USART_LL_EC_WAKEUP Wakeup
00298   * @{
00299   */
00300 #define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
00301 #define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup USART_LL_EC_DATAWIDTH Datawidth
00307   * @{
00308   */
00309 #define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
00310 #define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
00311 #define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
00317   * @{
00318   */
00319 #define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
00320 #define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
00321 /**
00322   * @}
00323   */
00324
00325 #if defined(USE_FULL_LL_DRIVER)
00326 /** @defgroup USART_LL_EC_CLOCK Clock Signal
00327   * @{
00328   */
00329
00330 #define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
00331 #define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
00332 /**
00333   * @}
00334   */
00335 #endif /*USE_FULL_LL_DRIVER*/
00336
00337 /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
00338   * @{
00339   */
00340 #define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
00341 #define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup USART_LL_EC_PHASE Clock Phase
00347   * @{
00348   */
00349 #define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
00350 #define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup USART_LL_EC_POLARITY Clock Polarity
00356   * @{
00357   */
00358 #define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
00359 #define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
00365   * @{
00366   */
00367 #define LL_USART_PRESCALER_DIV1                 0x00000000U                                                                   /*!< Input clock not devided   */
00368 #define LL_USART_PRESCALER_DIV2                 (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock devided by 2  */
00369 #define LL_USART_PRESCALER_DIV4                 (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock devided by 4  */
00370 #define LL_USART_PRESCALER_DIV6                 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 6  */
00371 #define LL_USART_PRESCALER_DIV8                 (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock devided by 8  */
00372 #define LL_USART_PRESCALER_DIV10                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 10 */
00373 #define LL_USART_PRESCALER_DIV12                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 12 */
00374 #define LL_USART_PRESCALER_DIV16                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */
00375 #define LL_USART_PRESCALER_DIV32                (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock devided by 32 */
00376 #define LL_USART_PRESCALER_DIV64                (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 64 */
00377 #define LL_USART_PRESCALER_DIV128               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 128 */
00378 #define LL_USART_PRESCALER_DIV256               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup USART_LL_EC_STOPBITS Stop Bits
00384   * @{
00385   */
00386 #define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
00387 #define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
00388 #define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
00389 #define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
00395   * @{
00396   */
00397 #define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
00398 #define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
00404   * @{
00405   */
00406 #define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
00407 #define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
00408 /**
00409   * @}
00410   */
00411
00412 /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
00413   * @{
00414   */
00415 #define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
00416 #define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
00417 /**
00418   * @}
00419   */
00420
00421 /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
00422   * @{
00423   */
00424 #define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
00425 #define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
00426 /**
00427   * @}
00428   */
00429
00430 /** @defgroup USART_LL_EC_BITORDER Bit Order
00431   * @{
00432   */
00433 #define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
00434 #define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
00435 /**
00436   * @}
00437   */
00438
00439 /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
00440   * @{
00441   */
00442 #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
00443 #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
00444 #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
00445 #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
00446 /**
00447   * @}
00448   */
00449
00450 /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
00451   * @{
00452   */
00453 #define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
00454 #define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
00455 /**
00456   * @}
00457   */
00458
00459 /** @defgroup USART_LL_EC_HWCONTROL Hardware Control
00460   * @{
00461   */
00462 #define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
00463 #define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
00464 #define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
00465 #define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
00466 /**
00467   * @}
00468   */
00469
00470 /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
00471   * @{
00472   */
00473 #define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
00474 #define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
00475 #define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
00476 /**
00477   * @}
00478   */
00479
00480 /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
00481   * @{
00482   */
00483 #define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
00484 #define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
00485 /**
00486   * @}
00487   */
00488
00489 /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
00490   * @{
00491   */
00492 #define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
00493 #define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
00494 /**
00495   * @}
00496   */
00497
00498 /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
00499   * @{
00500   */
00501 #define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
00502 #define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
00503 /**
00504   * @}
00505   */
00506
00507 /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
00508   * @{
00509   */
00510 #define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
00511 #define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
00512 /**
00513   * @}
00514   */
00515
00516 /**
00517   * @}
00518   */
00519
00520 /* Exported macro ------------------------------------------------------------*/
00521 /** @defgroup USART_LL_Exported_Macros USART Exported Macros
00522   * @{
00523   */
00524
00525 /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
00526   * @{
00527   */
00528
00529 /**
00530   * @brief  Write a value in USART register
00531   * @param  __INSTANCE__ USART Instance
00532   * @param  __REG__ Register to be written
00533   * @param  __VALUE__ Value to be written in the register
00534   * @retval None
00535   */
00536 #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00537
00538 /**
00539   * @brief  Read a value in USART register
00540   * @param  __INSTANCE__ USART Instance
00541   * @param  __REG__ Register to be read
00542   * @retval Register value
00543   */
00544 #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00545 /**
00546   * @}
00547   */
00548
00549 /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
00550   * @{
00551   */
00552
00553 /**
00554   * @brief  Compute USARTDIV value according to Peripheral Clock and
00555   *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
00556   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
00557   * @param  __PRESCALER__ This parameter can be one of the following values:
00558   *         @arg @ref LL_USART_PRESCALER_DIV1
00559   *         @arg @ref LL_USART_PRESCALER_DIV2
00560   *         @arg @ref LL_USART_PRESCALER_DIV4
00561   *         @arg @ref LL_USART_PRESCALER_DIV6
00562   *         @arg @ref LL_USART_PRESCALER_DIV8
00563   *         @arg @ref LL_USART_PRESCALER_DIV10
00564   *         @arg @ref LL_USART_PRESCALER_DIV12
00565   *         @arg @ref LL_USART_PRESCALER_DIV16
00566   *         @arg @ref LL_USART_PRESCALER_DIV32
00567   *         @arg @ref LL_USART_PRESCALER_DIV64
00568   *         @arg @ref LL_USART_PRESCALER_DIV128
00569   *         @arg @ref LL_USART_PRESCALER_DIV256
00570   * @param  __BAUDRATE__ Baud rate value to achieve
00571   * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
00572   */
00573 #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
00574
00575 /**
00576   * @brief  Compute USARTDIV value according to Peripheral Clock and
00577   *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
00578   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
00579   * @param  __PRESCALER__ This parameter can be one of the following values:
00580   *         @arg @ref LL_USART_PRESCALER_DIV1
00581   *         @arg @ref LL_USART_PRESCALER_DIV2
00582   *         @arg @ref LL_USART_PRESCALER_DIV4
00583   *         @arg @ref LL_USART_PRESCALER_DIV6
00584   *         @arg @ref LL_USART_PRESCALER_DIV8
00585   *         @arg @ref LL_USART_PRESCALER_DIV10
00586   *         @arg @ref LL_USART_PRESCALER_DIV12
00587   *         @arg @ref LL_USART_PRESCALER_DIV16
00588   *         @arg @ref LL_USART_PRESCALER_DIV32
00589   *         @arg @ref LL_USART_PRESCALER_DIV64
00590   *         @arg @ref LL_USART_PRESCALER_DIV128
00591   *         @arg @ref LL_USART_PRESCALER_DIV256
00592   * @param  __BAUDRATE__ Baud rate value to achieve
00593   * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
00594   */
00595 #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
00596
00597 /**
00598   * @}
00599   */
00600
00601 /**
00602   * @}
00603   */
00604
00605 /* Exported functions --------------------------------------------------------*/
00606
00607 /** @defgroup USART_LL_Exported_Functions USART Exported Functions
00608   * @{
00609   */
00610
00611 /** @defgroup USART_LL_EF_Configuration Configuration functions
00612   * @{
00613   */
00614
00615 /**
00616   * @brief  USART Enable
00617   * @rmtoll CR1          UE            LL_USART_Enable
00618   * @param  USARTx USART Instance
00619   * @retval None
00620   */
00621 __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
00622 {
00623   SET_BIT(USARTx->CR1, USART_CR1_UE);
00624 }
00625
00626 /**
00627   * @brief  USART Disable (all USART prescalers and outputs are disabled)
00628   * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
00629   *         and current operations are discarded. The configuration of the USART is kept, but all the status
00630   *         flags, in the USARTx_ISR are set to their default values.
00631   * @rmtoll CR1          UE            LL_USART_Disable
00632   * @param  USARTx USART Instance
00633   * @retval None
00634   */
00635 __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
00636 {
00637   CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
00638 }
00639
00640 /**
00641   * @brief  Indicate if USART is enabled
00642   * @rmtoll CR1          UE            LL_USART_IsEnabled
00643   * @param  USARTx USART Instance
00644   * @retval State of bit (1 or 0).
00645   */
00646 __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
00647 {
00648   return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
00649 }
00650
00651 /**
00652   * @brief  FIFO Mode Enable
00653   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00654   *         FIFO mode feature is supported by the USARTx instance.
00655   * @rmtoll CR1          FIFOEN        LL_USART_EnableFIFO
00656   * @param  USARTx USART Instance
00657   * @retval None
00658   */
00659 __STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
00660 {
00661   SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
00662 }
00663
00664 /**
00665   * @brief  FIFO Mode Disable
00666   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00667   *         FIFO mode feature is supported by the USARTx instance.
00668   * @rmtoll CR1          FIFOEN        LL_USART_DisableFIFO
00669   * @param  USARTx USART Instance
00670   * @retval None
00671   */
00672 __STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
00673 {
00674   CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
00675 }
00676
00677 /**
00678   * @brief  Indicate if FIFO Mode is enabled
00679   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00680   *         FIFO mode feature is supported by the USARTx instance.
00681   * @rmtoll CR1          FIFOEN        LL_USART_IsEnabledFIFO
00682   * @param  USARTx USART Instance
00683   * @retval State of bit (1 or 0).
00684   */
00685 __STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
00686 {
00687   return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
00688 }
00689
00690 /**
00691   * @brief  Configure TX FIFO Threshold
00692   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00693   *         FIFO mode feature is supported by the USARTx instance.
00694   * @rmtoll CR3          TXFTCFG       LL_USART_SetTXFIFOThreshold
00695   * @param  USARTx USART Instance
00696   * @param  Threshold This parameter can be one of the following values:
00697   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00698   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00699   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00700   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00701   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00702   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00703   * @retval None
00704   */
00705 __STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
00706 {
00707   MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
00708 }
00709
00710 /**
00711   * @brief  Return TX FIFO Threshold Configuration
00712   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00713   *         FIFO mode feature is supported by the USARTx instance.
00714   * @rmtoll CR3          TXFTCFG       LL_USART_GetTXFIFOThreshold
00715   * @param  USARTx USART Instance
00716   * @retval Returned value can be one of the following values:
00717   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00718   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00719   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00720   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00721   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00722   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00723   */
00724 __STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
00725 {
00726   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
00727 }
00728
00729 /**
00730   * @brief  Configure RX FIFO Threshold
00731   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00732   *         FIFO mode feature is supported by the USARTx instance.
00733   * @rmtoll CR3          RXFTCFG       LL_USART_SetRXFIFOThreshold
00734   * @param  USARTx USART Instance
00735   * @param  Threshold This parameter can be one of the following values:
00736   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00737   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00738   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00739   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00740   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00741   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00742   * @retval None
00743   */
00744 __STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
00745 {
00746   MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
00747 }
00748
00749 /**
00750   * @brief  Return RX FIFO Threshold Configuration
00751   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00752   *         FIFO mode feature is supported by the USARTx instance.
00753   * @rmtoll CR3          RXFTCFG       LL_USART_GetRXFIFOThreshold
00754   * @param  USARTx USART Instance
00755   * @retval Returned value can be one of the following values:
00756   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00757   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00758   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00759   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00760   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00761   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00762   */
00763 __STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
00764 {
00765   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
00766 }
00767
00768 /**
00769   * @brief  Configure TX and RX FIFOs Threshold
00770   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00771   *         FIFO mode feature is supported by the USARTx instance.
00772   * @rmtoll CR3          TXFTCFG       LL_USART_ConfigFIFOsThreshold\n
00773   *         CR3          RXFTCFG       LL_USART_ConfigFIFOsThreshold
00774   * @param  USARTx USART Instance
00775   * @param  TXThreshold This parameter can be one of the following values:
00776   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00777   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00778   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00779   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00780   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00781   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00782   * @param  RXThreshold This parameter can be one of the following values:
00783   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00784   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00785   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00786   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00787   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00788   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00789   * @retval None
00790   */
00791 __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
00792 {
00793   MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));
00794 }
00795
00796 /**
00797   * @brief  USART enabled in STOP Mode.
00798   * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
00799   *         USART clock selection is HSI or LSE in RCC.
00800   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00801   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00802   * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
00803   * @param  USARTx USART Instance
00804   * @retval None
00805   */
00806 __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
00807 {
00808   SET_BIT(USARTx->CR1, USART_CR1_UESM);
00809 }
00810
00811 /**
00812   * @brief  USART disabled in STOP Mode.
00813   * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
00814   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00815   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00816   * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
00817   * @param  USARTx USART Instance
00818   * @retval None
00819   */
00820 __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
00821 {
00822   CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
00823 }
00824
00825 /**
00826   * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
00827   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00828   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00829   * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
00830   * @param  USARTx USART Instance
00831   * @retval State of bit (1 or 0).
00832   */
00833 __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
00834 {
00835   return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
00836 }
00837
00838 /**
00839   * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
00840   * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
00841   * @param  USARTx USART Instance
00842   * @retval None
00843   */
00844 __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
00845 {
00846   SET_BIT(USARTx->CR1, USART_CR1_RE);
00847 }
00848
00849 /**
00850   * @brief  Receiver Disable
00851   * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
00852   * @param  USARTx USART Instance
00853   * @retval None
00854   */
00855 __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
00856 {
00857   CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
00858 }
00859
00860 /**
00861   * @brief  Transmitter Enable
00862   * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
00863   * @param  USARTx USART Instance
00864   * @retval None
00865   */
00866 __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
00867 {
00868   SET_BIT(USARTx->CR1, USART_CR1_TE);
00869 }
00870
00871 /**
00872   * @brief  Transmitter Disable
00873   * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
00874   * @param  USARTx USART Instance
00875   * @retval None
00876   */
00877 __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
00878 {
00879   CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
00880 }
00881
00882 /**
00883   * @brief  Configure simultaneously enabled/disabled states
00884   *         of Transmitter and Receiver
00885   * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
00886   *         CR1          TE            LL_USART_SetTransferDirection
00887   * @param  USARTx USART Instance
00888   * @param  TransferDirection This parameter can be one of the following values:
00889   *         @arg @ref LL_USART_DIRECTION_NONE
00890   *         @arg @ref LL_USART_DIRECTION_RX
00891   *         @arg @ref LL_USART_DIRECTION_TX
00892   *         @arg @ref LL_USART_DIRECTION_TX_RX
00893   * @retval None
00894   */
00895 __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
00896 {
00897   MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
00898 }
00899
00900 /**
00901   * @brief  Return enabled/disabled states of Transmitter and Receiver
00902   * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
00903   *         CR1          TE            LL_USART_GetTransferDirection
00904   * @param  USARTx USART Instance
00905   * @retval Returned value can be one of the following values:
00906   *         @arg @ref LL_USART_DIRECTION_NONE
00907   *         @arg @ref LL_USART_DIRECTION_RX
00908   *         @arg @ref LL_USART_DIRECTION_TX
00909   *         @arg @ref LL_USART_DIRECTION_TX_RX
00910   */
00911 __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
00912 {
00913   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
00914 }
00915
00916 /**
00917   * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
00918   * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
00919   *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
00920   *         (9th or 8th bit depending on data width) and parity is checked on the received data.
00921   * @rmtoll CR1          PS            LL_USART_SetParity\n
00922   *         CR1          PCE           LL_USART_SetParity
00923   * @param  USARTx USART Instance
00924   * @param  Parity This parameter can be one of the following values:
00925   *         @arg @ref LL_USART_PARITY_NONE
00926   *         @arg @ref LL_USART_PARITY_EVEN
00927   *         @arg @ref LL_USART_PARITY_ODD
00928   * @retval None
00929   */
00930 __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
00931 {
00932   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
00933 }
00934
00935 /**
00936   * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
00937   * @rmtoll CR1          PS            LL_USART_GetParity\n
00938   *         CR1          PCE           LL_USART_GetParity
00939   * @param  USARTx USART Instance
00940   * @retval Returned value can be one of the following values:
00941   *         @arg @ref LL_USART_PARITY_NONE
00942   *         @arg @ref LL_USART_PARITY_EVEN
00943   *         @arg @ref LL_USART_PARITY_ODD
00944   */
00945 __STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
00946 {
00947   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
00948 }
00949
00950 /**
00951   * @brief  Set Receiver Wake Up method from Mute mode.
00952   * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
00953   * @param  USARTx USART Instance
00954   * @param  Method This parameter can be one of the following values:
00955   *         @arg @ref LL_USART_WAKEUP_IDLELINE
00956   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
00957   * @retval None
00958   */
00959 __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
00960 {
00961   MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
00962 }
00963
00964 /**
00965   * @brief  Return Receiver Wake Up method from Mute mode
00966   * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
00967   * @param  USARTx USART Instance
00968   * @retval Returned value can be one of the following values:
00969   *         @arg @ref LL_USART_WAKEUP_IDLELINE
00970   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
00971   */
00972 __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
00973 {
00974   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
00975 }
00976
00977 /**
00978   * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
00979   * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
00980   *         CR1          M1            LL_USART_SetDataWidth
00981   * @param  USARTx USART Instance
00982   * @param  DataWidth This parameter can be one of the following values:
00983   *         @arg @ref LL_USART_DATAWIDTH_7B
00984   *         @arg @ref LL_USART_DATAWIDTH_8B
00985   *         @arg @ref LL_USART_DATAWIDTH_9B
00986   * @retval None
00987   */
00988 __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
00989 {
00990   MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
00991 }
00992
00993 /**
00994   * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
00995   * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
00996   *         CR1          M1            LL_USART_GetDataWidth
00997   * @param  USARTx USART Instance
00998   * @retval Returned value can be one of the following values:
00999   *         @arg @ref LL_USART_DATAWIDTH_7B
01000   *         @arg @ref LL_USART_DATAWIDTH_8B
01001   *         @arg @ref LL_USART_DATAWIDTH_9B
01002   */
01003 __STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
01004 {
01005   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
01006 }
01007
01008 /**
01009   * @brief  Allow switch between Mute Mode and Active mode
01010   * @rmtoll CR1          MME           LL_USART_EnableMuteMode
01011   * @param  USARTx USART Instance
01012   * @retval None
01013   */
01014 __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
01015 {
01016   SET_BIT(USARTx->CR1, USART_CR1_MME);
01017 }
01018
01019 /**
01020   * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
01021   * @rmtoll CR1          MME           LL_USART_DisableMuteMode
01022   * @param  USARTx USART Instance
01023   * @retval None
01024   */
01025 __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
01026 {
01027   CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
01028 }
01029
01030 /**
01031   * @brief  Indicate if switch between Mute Mode and Active mode is allowed
01032   * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
01033   * @param  USARTx USART Instance
01034   * @retval State of bit (1 or 0).
01035   */
01036 __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
01037 {
01038   return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
01039 }
01040
01041 /**
01042   * @brief  Set Oversampling to 8-bit or 16-bit mode
01043   * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
01044   * @param  USARTx USART Instance
01045   * @param  OverSampling This parameter can be one of the following values:
01046   *         @arg @ref LL_USART_OVERSAMPLING_16
01047   *         @arg @ref LL_USART_OVERSAMPLING_8
01048   * @retval None
01049   */
01050 __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
01051 {
01052   MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
01053 }
01054
01055 /**
01056   * @brief  Return Oversampling mode
01057   * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
01058   * @param  USARTx USART Instance
01059   * @retval Returned value can be one of the following values:
01060   *         @arg @ref LL_USART_OVERSAMPLING_16
01061   *         @arg @ref LL_USART_OVERSAMPLING_8
01062   */
01063 __STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
01064 {
01065   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
01066 }
01067
01068 /**
01069   * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
01070   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01071   *         Synchronous mode is supported by the USARTx instance.
01072   * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
01073   * @param  USARTx USART Instance
01074   * @param  LastBitClockPulse This parameter can be one of the following values:
01075   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
01076   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
01077   * @retval None
01078   */
01079 __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
01080 {
01081   MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
01082 }
01083
01084 /**
01085   * @brief  Retrieve Clock pulse of the last data bit output configuration
01086   *         (Last bit Clock pulse output to the SCLK pin or not)
01087   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01088   *         Synchronous mode is supported by the USARTx instance.
01089   * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
01090   * @param  USARTx USART Instance
01091   * @retval Returned value can be one of the following values:
01092   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
01093   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
01094   */
01095 __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
01096 {
01097   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
01098 }
01099
01100 /**
01101   * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
01102   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01103   *         Synchronous mode is supported by the USARTx instance.
01104   * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
01105   * @param  USARTx USART Instance
01106   * @param  ClockPhase This parameter can be one of the following values:
01107   *         @arg @ref LL_USART_PHASE_1EDGE
01108   *         @arg @ref LL_USART_PHASE_2EDGE
01109   * @retval None
01110   */
01111 __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
01112 {
01113   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
01114 }
01115
01116 /**
01117   * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
01118   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01119   *         Synchronous mode is supported by the USARTx instance.
01120   * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
01121   * @param  USARTx USART Instance
01122   * @retval Returned value can be one of the following values:
01123   *         @arg @ref LL_USART_PHASE_1EDGE
01124   *         @arg @ref LL_USART_PHASE_2EDGE
01125   */
01126 __STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
01127 {
01128   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
01129 }
01130
01131 /**
01132   * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
01133   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01134   *         Synchronous mode is supported by the USARTx instance.
01135   * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
01136   * @param  USARTx USART Instance
01137   * @param  ClockPolarity This parameter can be one of the following values:
01138   *         @arg @ref LL_USART_POLARITY_LOW
01139   *         @arg @ref LL_USART_POLARITY_HIGH
01140   * @retval None
01141   */
01142 __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
01143 {
01144   MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
01145 }
01146
01147 /**
01148   * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
01149   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01150   *         Synchronous mode is supported by the USARTx instance.
01151   * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
01152   * @param  USARTx USART Instance
01153   * @retval Returned value can be one of the following values:
01154   *         @arg @ref LL_USART_POLARITY_LOW
01155   *         @arg @ref LL_USART_POLARITY_HIGH
01156   */
01157 __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
01158 {
01159   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
01160 }
01161
01162 /**
01163   * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
01164   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01165   *         Synchronous mode is supported by the USARTx instance.
01166   * @note   Call of this function is equivalent to following function call sequence :
01167   *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
01168   *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
01169   *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
01170   * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
01171   *         CR2          CPOL          LL_USART_ConfigClock\n
01172   *         CR2          LBCL          LL_USART_ConfigClock
01173   * @param  USARTx USART Instance
01174   * @param  Phase This parameter can be one of the following values:
01175   *         @arg @ref LL_USART_PHASE_1EDGE
01176   *         @arg @ref LL_USART_PHASE_2EDGE
01177   * @param  Polarity This parameter can be one of the following values:
01178   *         @arg @ref LL_USART_POLARITY_LOW
01179   *         @arg @ref LL_USART_POLARITY_HIGH
01180   * @param  LBCPOutput This parameter can be one of the following values:
01181   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
01182   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
01183   * @retval None
01184   */
01185 __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
01186 {
01187   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
01188 }
01189
01190 /**
01191   * @brief  Configure Clock source prescaler for baudrate generator and oversampling
01192   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
01193   *         FIFO mode feature is supported by the USARTx instance.
01194   * @rmtoll PRESC        PRESCALER     LL_USART_SetPrescaler
01195   * @param  USARTx USART Instance
01196   * @param  PrescalerValue This parameter can be one of the following values:
01197   *         @arg @ref LL_USART_PRESCALER_DIV1
01198   *         @arg @ref LL_USART_PRESCALER_DIV2
01199   *         @arg @ref LL_USART_PRESCALER_DIV4
01200   *         @arg @ref LL_USART_PRESCALER_DIV6
01201   *         @arg @ref LL_USART_PRESCALER_DIV8
01202   *         @arg @ref LL_USART_PRESCALER_DIV10
01203   *         @arg @ref LL_USART_PRESCALER_DIV12
01204   *         @arg @ref LL_USART_PRESCALER_DIV16
01205   *         @arg @ref LL_USART_PRESCALER_DIV32
01206   *         @arg @ref LL_USART_PRESCALER_DIV64
01207   *         @arg @ref LL_USART_PRESCALER_DIV128
01208   *         @arg @ref LL_USART_PRESCALER_DIV256
01209   * @retval None
01210   */
01211 __STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
01212 {
01213   MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
01214 }
01215
01216 /**
01217   * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
01218   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
01219   *         FIFO mode feature is supported by the USARTx instance.
01220   * @rmtoll PRESC        PRESCALER     LL_USART_GetPrescaler
01221   * @param  USARTx USART Instance
01222   * @retval Returned value can be one of the following values:
01223   *         @arg @ref LL_USART_PRESCALER_DIV1
01224   *         @arg @ref LL_USART_PRESCALER_DIV2
01225   *         @arg @ref LL_USART_PRESCALER_DIV4
01226   *         @arg @ref LL_USART_PRESCALER_DIV6
01227   *         @arg @ref LL_USART_PRESCALER_DIV8
01228   *         @arg @ref LL_USART_PRESCALER_DIV10
01229   *         @arg @ref LL_USART_PRESCALER_DIV12
01230   *         @arg @ref LL_USART_PRESCALER_DIV16
01231   *         @arg @ref LL_USART_PRESCALER_DIV32
01232   *         @arg @ref LL_USART_PRESCALER_DIV64
01233   *         @arg @ref LL_USART_PRESCALER_DIV128
01234   *         @arg @ref LL_USART_PRESCALER_DIV256
01235   */
01236 __STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)
01237 {
01238   return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
01239 }
01240
01241 /**
01242   * @brief  Enable Clock output on SCLK pin
01243   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01244   *         Synchronous mode is supported by the USARTx instance.
01245   * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
01246   * @param  USARTx USART Instance
01247   * @retval None
01248   */
01249 __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
01250 {
01251   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
01252 }
01253
01254 /**
01255   * @brief  Disable Clock output on SCLK pin
01256   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01257   *         Synchronous mode is supported by the USARTx instance.
01258   * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
01259   * @param  USARTx USART Instance
01260   * @retval None
01261   */
01262 __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
01263 {
01264   CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
01265 }
01266
01267 /**
01268   * @brief  Indicate if Clock output on SCLK pin is enabled
01269   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01270   *         Synchronous mode is supported by the USARTx instance.
01271   * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
01272   * @param  USARTx USART Instance
01273   * @retval State of bit (1 or 0).
01274   */
01275 __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
01276 {
01277   return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
01278 }
01279
01280 /**
01281   * @brief  Set the length of the stop bits
01282   * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
01283   * @param  USARTx USART Instance
01284   * @param  StopBits This parameter can be one of the following values:
01285   *         @arg @ref LL_USART_STOPBITS_0_5
01286   *         @arg @ref LL_USART_STOPBITS_1
01287   *         @arg @ref LL_USART_STOPBITS_1_5
01288   *         @arg @ref LL_USART_STOPBITS_2
01289   * @retval None
01290   */
01291 __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
01292 {
01293   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
01294 }
01295
01296 /**
01297   * @brief  Retrieve the length of the stop bits
01298   * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
01299   * @param  USARTx USART Instance
01300   * @retval Returned value can be one of the following values:
01301   *         @arg @ref LL_USART_STOPBITS_0_5
01302   *         @arg @ref LL_USART_STOPBITS_1
01303   *         @arg @ref LL_USART_STOPBITS_1_5
01304   *         @arg @ref LL_USART_STOPBITS_2
01305   */
01306 __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
01307 {
01308   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
01309 }
01310
01311 /**
01312   * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
01313   * @note   Call of this function is equivalent to following function call sequence :
01314   *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
01315   *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
01316   *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
01317   * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
01318   *         CR1          PCE           LL_USART_ConfigCharacter\n
01319   *         CR1          M0            LL_USART_ConfigCharacter\n
01320   *         CR1          M1            LL_USART_ConfigCharacter\n
01321   *         CR2          STOP          LL_USART_ConfigCharacter
01322   * @param  USARTx USART Instance
01323   * @param  DataWidth This parameter can be one of the following values:
01324   *         @arg @ref LL_USART_DATAWIDTH_7B
01325   *         @arg @ref LL_USART_DATAWIDTH_8B
01326   *         @arg @ref LL_USART_DATAWIDTH_9B
01327   * @param  Parity This parameter can be one of the following values:
01328   *         @arg @ref LL_USART_PARITY_NONE
01329   *         @arg @ref LL_USART_PARITY_EVEN
01330   *         @arg @ref LL_USART_PARITY_ODD
01331   * @param  StopBits This parameter can be one of the following values:
01332   *         @arg @ref LL_USART_STOPBITS_0_5
01333   *         @arg @ref LL_USART_STOPBITS_1
01334   *         @arg @ref LL_USART_STOPBITS_1_5
01335   *         @arg @ref LL_USART_STOPBITS_2
01336   * @retval None
01337   */
01338 __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
01339                                               uint32_t StopBits)
01340 {
01341   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
01342   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
01343 }
01344
01345 /**
01346   * @brief  Configure TX/RX pins swapping setting.
01347   * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
01348   * @param  USARTx USART Instance
01349   * @param  SwapConfig This parameter can be one of the following values:
01350   *         @arg @ref LL_USART_TXRX_STANDARD
01351   *         @arg @ref LL_USART_TXRX_SWAPPED
01352   * @retval None
01353   */
01354 __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
01355 {
01356   MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
01357 }
01358
01359 /**
01360   * @brief  Retrieve TX/RX pins swapping configuration.
01361   * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
01362   * @param  USARTx USART Instance
01363   * @retval Returned value can be one of the following values:
01364   *         @arg @ref LL_USART_TXRX_STANDARD
01365   *         @arg @ref LL_USART_TXRX_SWAPPED
01366   */
01367 __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
01368 {
01369   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
01370 }
01371
01372 /**
01373   * @brief  Configure RX pin active level logic
01374   * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
01375   * @param  USARTx USART Instance
01376   * @param  PinInvMethod This parameter can be one of the following values:
01377   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
01378   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
01379   * @retval None
01380   */
01381 __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
01382 {
01383   MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
01384 }
01385
01386 /**
01387   * @brief  Retrieve RX pin active level logic configuration
01388   * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
01389   * @param  USARTx USART Instance
01390   * @retval Returned value can be one of the following values:
01391   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
01392   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
01393   */
01394 __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
01395 {
01396   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
01397 }
01398
01399 /**
01400   * @brief  Configure TX pin active level logic
01401   * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
01402   * @param  USARTx USART Instance
01403   * @param  PinInvMethod This parameter can be one of the following values:
01404   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
01405   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
01406   * @retval None
01407   */
01408 __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
01409 {
01410   MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
01411 }
01412
01413 /**
01414   * @brief  Retrieve TX pin active level logic configuration
01415   * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
01416   * @param  USARTx USART Instance
01417   * @retval Returned value can be one of the following values:
01418   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
01419   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
01420   */
01421 __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
01422 {
01423   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
01424 }
01425
01426 /**
01427   * @brief  Configure Binary data logic.
01428   * @note   Allow to define how Logical data from the data register are send/received :
01429   *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
01430   * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
01431   * @param  USARTx USART Instance
01432   * @param  DataLogic This parameter can be one of the following values:
01433   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
01434   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
01435   * @retval None
01436   */
01437 __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
01438 {
01439   MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
01440 }
01441
01442 /**
01443   * @brief  Retrieve Binary data configuration
01444   * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
01445   * @param  USARTx USART Instance
01446   * @retval Returned value can be one of the following values:
01447   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
01448   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
01449   */
01450 __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
01451 {
01452   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
01453 }
01454
01455 /**
01456   * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
01457   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01458   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01459   * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
01460   * @param  USARTx USART Instance
01461   * @param  BitOrder This parameter can be one of the following values:
01462   *         @arg @ref LL_USART_BITORDER_LSBFIRST
01463   *         @arg @ref LL_USART_BITORDER_MSBFIRST
01464   * @retval None
01465   */
01466 __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
01467 {
01468   MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
01469 }
01470
01471 /**
01472   * @brief  Return transfer bit order (either Less or Most Significant Bit First)
01473   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01474   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01475   * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
01476   * @param  USARTx USART Instance
01477   * @retval Returned value can be one of the following values:
01478   *         @arg @ref LL_USART_BITORDER_LSBFIRST
01479   *         @arg @ref LL_USART_BITORDER_MSBFIRST
01480   */
01481 __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
01482 {
01483   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
01484 }
01485
01486 /**
01487   * @brief  Enable Auto Baud-Rate Detection
01488   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01489   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01490   * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
01491   * @param  USARTx USART Instance
01492   * @retval None
01493   */
01494 __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
01495 {
01496   SET_BIT(USARTx->CR2, USART_CR2_ABREN);
01497 }
01498
01499 /**
01500   * @brief  Disable Auto Baud-Rate Detection
01501   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01502   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01503   * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
01504   * @param  USARTx USART Instance
01505   * @retval None
01506   */
01507 __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
01508 {
01509   CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
01510 }
01511
01512 /**
01513   * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
01514   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01515   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01516   * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
01517   * @param  USARTx USART Instance
01518   * @retval State of bit (1 or 0).
01519   */
01520 __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
01521 {
01522   return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
01523 }
01524
01525 /**
01526   * @brief  Set Auto Baud-Rate mode bits
01527   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01528   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01529   * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
01530   * @param  USARTx USART Instance
01531   * @param  AutoBaudRateMode This parameter can be one of the following values:
01532   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
01533   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
01534   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
01535   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
01536   * @retval None
01537   */
01538 __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
01539 {
01540   MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
01541 }
01542
01543 /**
01544   * @brief  Return Auto Baud-Rate mode
01545   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01546   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01547   * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
01548   * @param  USARTx USART Instance
01549   * @retval Returned value can be one of the following values:
01550   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
01551   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
01552   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
01553   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
01554   */
01555 __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
01556 {
01557   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
01558 }
01559
01560 /**
01561   * @brief  Enable Receiver Timeout
01562   * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
01563   * @param  USARTx USART Instance
01564   * @retval None
01565   */
01566 __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
01567 {
01568   SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
01569 }
01570
01571 /**
01572   * @brief  Disable Receiver Timeout
01573   * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
01574   * @param  USARTx USART Instance
01575   * @retval None
01576   */
01577 __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
01578 {
01579   CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
01580 }
01581
01582 /**
01583   * @brief  Indicate if Receiver Timeout feature is enabled
01584   * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
01585   * @param  USARTx USART Instance
01586   * @retval State of bit (1 or 0).
01587   */
01588 __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
01589 {
01590   return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
01591 }
01592
01593 /**
01594   * @brief  Set Address of the USART node.
01595   * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
01596   *         for wake up with address mark detection.
01597   * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
01598   *         (b7-b4 should be set to 0)
01599   *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
01600   *         (This is used in multiprocessor communication during Mute mode or Stop mode,
01601   *         for wake up with 7-bit address mark detection.
01602   *         The MSB of the character sent by the transmitter should be equal to 1.
01603   *         It may also be used for character detection during normal reception,
01604   *         Mute mode inactive (for example, end of block detection in ModBus protocol).
01605   *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
01606   *         value and CMF flag is set on match)
01607   * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
01608   *         CR2          ADDM7         LL_USART_ConfigNodeAddress
01609   * @param  USARTx USART Instance
01610   * @param  AddressLen This parameter can be one of the following values:
01611   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
01612   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
01613   * @param  NodeAddress 4 or 7 bit Address of the USART node.
01614   * @retval None
01615   */
01616 __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
01617 {
01618   MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
01619              (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
01620 }
01621
01622 /**
01623   * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
01624   * @note   If 4-bit Address Detection is selected in ADDM7,
01625   *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
01626   *         If 7-bit Address Detection is selected in ADDM7,
01627   *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
01628   * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
01629   * @param  USARTx USART Instance
01630   * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
01631   */
01632 __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
01633 {
01634   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
01635 }
01636
01637 /**
01638   * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
01639   * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
01640   * @param  USARTx USART Instance
01641   * @retval Returned value can be one of the following values:
01642   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
01643   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
01644   */
01645 __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
01646 {
01647   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
01648 }
01649
01650 /**
01651   * @brief  Enable RTS HW Flow Control
01652   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01653   *         Hardware Flow control feature is supported by the USARTx instance.
01654   * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
01655   * @param  USARTx USART Instance
01656   * @retval None
01657   */
01658 __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
01659 {
01660   SET_BIT(USARTx->CR3, USART_CR3_RTSE);
01661 }
01662
01663 /**
01664   * @brief  Disable RTS HW Flow Control
01665   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01666   *         Hardware Flow control feature is supported by the USARTx instance.
01667   * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
01668   * @param  USARTx USART Instance
01669   * @retval None
01670   */
01671 __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
01672 {
01673   CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
01674 }
01675
01676 /**
01677   * @brief  Enable CTS HW Flow Control
01678   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01679   *         Hardware Flow control feature is supported by the USARTx instance.
01680   * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
01681   * @param  USARTx USART Instance
01682   * @retval None
01683   */
01684 __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
01685 {
01686   SET_BIT(USARTx->CR3, USART_CR3_CTSE);
01687 }
01688
01689 /**
01690   * @brief  Disable CTS HW Flow Control
01691   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01692   *         Hardware Flow control feature is supported by the USARTx instance.
01693   * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
01694   * @param  USARTx USART Instance
01695   * @retval None
01696   */
01697 __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
01698 {
01699   CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
01700 }
01701
01702 /**
01703   * @brief  Configure HW Flow Control mode (both CTS and RTS)
01704   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01705   *         Hardware Flow control feature is supported by the USARTx instance.
01706   * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
01707   *         CR3          CTSE          LL_USART_SetHWFlowCtrl
01708   * @param  USARTx USART Instance
01709   * @param  HardwareFlowControl This parameter can be one of the following values:
01710   *         @arg @ref LL_USART_HWCONTROL_NONE
01711   *         @arg @ref LL_USART_HWCONTROL_RTS
01712   *         @arg @ref LL_USART_HWCONTROL_CTS
01713   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
01714   * @retval None
01715   */
01716 __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
01717 {
01718   MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
01719 }
01720
01721 /**
01722   * @brief  Return HW Flow Control configuration (both CTS and RTS)
01723   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01724   *         Hardware Flow control feature is supported by the USARTx instance.
01725   * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
01726   *         CR3          CTSE          LL_USART_GetHWFlowCtrl
01727   * @param  USARTx USART Instance
01728   * @retval Returned value can be one of the following values:
01729   *         @arg @ref LL_USART_HWCONTROL_NONE
01730   *         @arg @ref LL_USART_HWCONTROL_RTS
01731   *         @arg @ref LL_USART_HWCONTROL_CTS
01732   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
01733   */
01734 __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
01735 {
01736   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
01737 }
01738
01739 /**
01740   * @brief  Enable One bit sampling method
01741   * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
01742   * @param  USARTx USART Instance
01743   * @retval None
01744   */
01745 __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
01746 {
01747   SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
01748 }
01749
01750 /**
01751   * @brief  Disable One bit sampling method
01752   * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
01753   * @param  USARTx USART Instance
01754   * @retval None
01755   */
01756 __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
01757 {
01758   CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
01759 }
01760
01761 /**
01762   * @brief  Indicate if One bit sampling method is enabled
01763   * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
01764   * @param  USARTx USART Instance
01765   * @retval State of bit (1 or 0).
01766   */
01767 __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
01768 {
01769   return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
01770 }
01771
01772 /**
01773   * @brief  Enable Overrun detection
01774   * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
01775   * @param  USARTx USART Instance
01776   * @retval None
01777   */
01778 __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
01779 {
01780   CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
01781 }
01782
01783 /**
01784   * @brief  Disable Overrun detection
01785   * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
01786   * @param  USARTx USART Instance
01787   * @retval None
01788   */
01789 __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
01790 {
01791   SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
01792 }
01793
01794 /**
01795   * @brief  Indicate if Overrun detection is enabled
01796   * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
01797   * @param  USARTx USART Instance
01798   * @retval State of bit (1 or 0).
01799   */
01800 __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
01801 {
01802   return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
01803 }
01804
01805 /**
01806   * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01807   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
01808   *         Wake-up from Stop mode feature is supported by the USARTx instance.
01809   * @rmtoll CR3          WUS           LL_USART_SetWKUPType
01810   * @param  USARTx USART Instance
01811   * @param  Type This parameter can be one of the following values:
01812   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
01813   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
01814   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
01815   * @retval None
01816   */
01817 __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
01818 {
01819   MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
01820 }
01821
01822 /**
01823   * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01824   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
01825   *         Wake-up from Stop mode feature is supported by the USARTx instance.
01826   * @rmtoll CR3          WUS           LL_USART_GetWKUPType
01827   * @param  USARTx USART Instance
01828   * @retval Returned value can be one of the following values:
01829   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
01830   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
01831   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
01832   */
01833 __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
01834 {
01835   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
01836 }
01837
01838 /**
01839   * @brief  Configure USART BRR register for achieving expected Baud Rate value.
01840   * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
01841   *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
01842   * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
01843   *         (Baud rate value != 0)
01844   * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
01845   * @rmtoll BRR          BRR           LL_USART_SetBaudRate
01846   * @param  USARTx USART Instance
01847   * @param  PeriphClk Peripheral Clock
01848   * @param  PrescalerValue This parameter can be one of the following values:
01849   *         @arg @ref LL_USART_PRESCALER_DIV1
01850   *         @arg @ref LL_USART_PRESCALER_DIV2
01851   *         @arg @ref LL_USART_PRESCALER_DIV4
01852   *         @arg @ref LL_USART_PRESCALER_DIV6
01853   *         @arg @ref LL_USART_PRESCALER_DIV8
01854   *         @arg @ref LL_USART_PRESCALER_DIV10
01855   *         @arg @ref LL_USART_PRESCALER_DIV12
01856   *         @arg @ref LL_USART_PRESCALER_DIV16
01857   *         @arg @ref LL_USART_PRESCALER_DIV32
01858   *         @arg @ref LL_USART_PRESCALER_DIV64
01859   *         @arg @ref LL_USART_PRESCALER_DIV128
01860   *         @arg @ref LL_USART_PRESCALER_DIV256
01861   * @param  OverSampling This parameter can be one of the following values:
01862   *         @arg @ref LL_USART_OVERSAMPLING_16
01863   *         @arg @ref LL_USART_OVERSAMPLING_8
01864   * @param  BaudRate Baud Rate
01865   * @retval None
01866   */
01867 __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling,
01868                                           uint32_t BaudRate)
01869 {
01870   register uint32_t usartdiv;
01871   register uint32_t brrtemp;
01872
01873   if (OverSampling == LL_USART_OVERSAMPLING_8)
01874   {
01875     usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint16_t)PrescalerValue, BaudRate));
01876     brrtemp = usartdiv & 0xFFF0U;
01877     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
01878     USARTx->BRR = brrtemp;
01879   }
01880   else
01881   {
01882     USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint16_t)PrescalerValue, BaudRate));
01883   }
01884 }
01885
01886 /**
01887   * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
01888   *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
01889   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
01890   * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
01891   * @rmtoll BRR          BRR           LL_USART_GetBaudRate
01892   * @param  USARTx USART Instance
01893   * @param  PeriphClk Peripheral Clock
01894   * @param  PrescalerValue This parameter can be one of the following values:
01895   *         @arg @ref LL_USART_PRESCALER_DIV1
01896   *         @arg @ref LL_USART_PRESCALER_DIV2
01897   *         @arg @ref LL_USART_PRESCALER_DIV4
01898   *         @arg @ref LL_USART_PRESCALER_DIV6
01899   *         @arg @ref LL_USART_PRESCALER_DIV8
01900   *         @arg @ref LL_USART_PRESCALER_DIV10
01901   *         @arg @ref LL_USART_PRESCALER_DIV12
01902   *         @arg @ref LL_USART_PRESCALER_DIV16
01903   *         @arg @ref LL_USART_PRESCALER_DIV32
01904   *         @arg @ref LL_USART_PRESCALER_DIV64
01905   *         @arg @ref LL_USART_PRESCALER_DIV128
01906   *         @arg @ref LL_USART_PRESCALER_DIV256
01907   * @param  OverSampling This parameter can be one of the following values:
01908   *         @arg @ref LL_USART_OVERSAMPLING_16
01909   *         @arg @ref LL_USART_OVERSAMPLING_8
01910   * @retval Baud Rate
01911   */
01912 __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling)
01913 {
01914   register uint32_t usartdiv;
01915   register uint32_t brrresult = 0x0U;
01916   register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
01917
01918   usartdiv = USARTx->BRR;
01919
01920   if (usartdiv == 0U)
01921   {
01922     /* Do not perform a division by 0 */
01923   }
01924   else if (OverSampling == LL_USART_OVERSAMPLING_8)
01925   {
01926     usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
01927     if (usartdiv != 0U)
01928     {
01929       brrresult = (periphclkpresc * 2U) / usartdiv;
01930     }
01931   }
01932   else
01933   {
01934     if ((usartdiv & 0xFFFFU) != 0U)
01935     {
01936       brrresult = periphclkpresc / usartdiv;
01937     }
01938   }
01939   return (brrresult);
01940 }
01941
01942 /**
01943   * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
01944   * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
01945   * @param  USARTx USART Instance
01946   * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
01947   * @retval None
01948   */
01949 __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
01950 {
01951   MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
01952 }
01953
01954 /**
01955   * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
01956   * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
01957   * @param  USARTx USART Instance
01958   * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
01959   */
01960 __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
01961 {
01962   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
01963 }
01964
01965 /**
01966   * @brief  Set Block Length value in reception
01967   * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
01968   * @param  USARTx USART Instance
01969   * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
01970   * @retval None
01971   */
01972 __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
01973 {
01974   MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
01975 }
01976
01977 /**
01978   * @brief  Get Block Length value in reception
01979   * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
01980   * @param  USARTx USART Instance
01981   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
01982   */
01983 __STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
01984 {
01985   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
01986 }
01987
01988 /**
01989   * @}
01990   */
01991
01992 /** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
01993   * @{
01994   */
01995
01996 /**
01997   * @brief  Enable IrDA mode
01998   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01999   *         IrDA feature is supported by the USARTx instance.
02000   * @rmtoll CR3          IREN          LL_USART_EnableIrda
02001   * @param  USARTx USART Instance
02002   * @retval None
02003   */
02004 __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
02005 {
02006   SET_BIT(USARTx->CR3, USART_CR3_IREN);
02007 }
02008
02009 /**
02010   * @brief  Disable IrDA mode
02011   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02012   *         IrDA feature is supported by the USARTx instance.
02013   * @rmtoll CR3          IREN          LL_USART_DisableIrda
02014   * @param  USARTx USART Instance
02015   * @retval None
02016   */
02017 __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
02018 {
02019   CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
02020 }
02021
02022 /**
02023   * @brief  Indicate if IrDA mode is enabled
02024   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02025   *         IrDA feature is supported by the USARTx instance.
02026   * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
02027   * @param  USARTx USART Instance
02028   * @retval State of bit (1 or 0).
02029   */
02030 __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
02031 {
02032   return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
02033 }
02034
02035 /**
02036   * @brief  Configure IrDA Power Mode (Normal or Low Power)
02037   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02038   *         IrDA feature is supported by the USARTx instance.
02039   * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
02040   * @param  USARTx USART Instance
02041   * @param  PowerMode This parameter can be one of the following values:
02042   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
02043   *         @arg @ref LL_USART_IRDA_POWER_LOW
02044   * @retval None
02045   */
02046 __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
02047 {
02048   MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
02049 }
02050
02051 /**
02052   * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
02053   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02054   *         IrDA feature is supported by the USARTx instance.
02055   * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
02056   * @param  USARTx USART Instance
02057   * @retval Returned value can be one of the following values:
02058   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
02059   *         @arg @ref LL_USART_PHASE_2EDGE
02060   */
02061 __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
02062 {
02063   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
02064 }
02065
02066 /**
02067   * @brief  Set Irda prescaler value, used for dividing the USART clock source
02068   *         to achieve the Irda Low Power frequency (8 bits value)
02069   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02070   *         IrDA feature is supported by the USARTx instance.
02071   * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
02072   * @param  USARTx USART Instance
02073   * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
02074   * @retval None
02075   */
02076 __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
02077 {
02078   MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
02079 }
02080
02081 /**
02082   * @brief  Return Irda prescaler value, used for dividing the USART clock source
02083   *         to achieve the Irda Low Power frequency (8 bits value)
02084   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02085   *         IrDA feature is supported by the USARTx instance.
02086   * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
02087   * @param  USARTx USART Instance
02088   * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
02089   */
02090 __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
02091 {
02092   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
02093 }
02094
02095 /**
02096   * @}
02097   */
02098
02099 /** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
02100   * @{
02101   */
02102
02103 /**
02104   * @brief  Enable Smartcard NACK transmission
02105   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02106   *         Smartcard feature is supported by the USARTx instance.
02107   * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
02108   * @param  USARTx USART Instance
02109   * @retval None
02110   */
02111 __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
02112 {
02113   SET_BIT(USARTx->CR3, USART_CR3_NACK);
02114 }
02115
02116 /**
02117   * @brief  Disable Smartcard NACK transmission
02118   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02119   *         Smartcard feature is supported by the USARTx instance.
02120   * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
02121   * @param  USARTx USART Instance
02122   * @retval None
02123   */
02124 __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
02125 {
02126   CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
02127 }
02128
02129 /**
02130   * @brief  Indicate if Smartcard NACK transmission is enabled
02131   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02132   *         Smartcard feature is supported by the USARTx instance.
02133   * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
02134   * @param  USARTx USART Instance
02135   * @retval State of bit (1 or 0).
02136   */
02137 __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
02138 {
02139   return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
02140 }
02141
02142 /**
02143   * @brief  Enable Smartcard mode
02144   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02145   *         Smartcard feature is supported by the USARTx instance.
02146   * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
02147   * @param  USARTx USART Instance
02148   * @retval None
02149   */
02150 __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
02151 {
02152   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
02153 }
02154
02155 /**
02156   * @brief  Disable Smartcard mode
02157   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02158   *         Smartcard feature is supported by the USARTx instance.
02159   * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
02160   * @param  USARTx USART Instance
02161   * @retval None
02162   */
02163 __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
02164 {
02165   CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
02166 }
02167
02168 /**
02169   * @brief  Indicate if Smartcard mode is enabled
02170   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02171   *         Smartcard feature is supported by the USARTx instance.
02172   * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
02173   * @param  USARTx USART Instance
02174   * @retval State of bit (1 or 0).
02175   */
02176 __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
02177 {
02178   return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
02179 }
02180
02181 /**
02182   * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
02183   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02184   *         Smartcard feature is supported by the USARTx instance.
02185   * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
02186   *         In transmission mode, it specifies the number of automatic retransmission retries, before
02187   *         generating a transmission error (FE bit set).
02188   *         In reception mode, it specifies the number or erroneous reception trials, before generating a
02189   *         reception error (RXNE and PE bits set)
02190   * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
02191   * @param  USARTx USART Instance
02192   * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
02193   * @retval None
02194   */
02195 __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
02196 {
02197   MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
02198 }
02199
02200 /**
02201   * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
02202   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02203   *         Smartcard feature is supported by the USARTx instance.
02204   * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
02205   * @param  USARTx USART Instance
02206   * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
02207   */
02208 __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
02209 {
02210   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
02211 }
02212
02213 /**
02214   * @brief  Set Smartcard prescaler value, used for dividing the USART clock
02215   *         source to provide the SMARTCARD Clock (5 bits value)
02216   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02217   *         Smartcard feature is supported by the USARTx instance.
02218   * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
02219   * @param  USARTx USART Instance
02220   * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
02221   * @retval None
02222   */
02223 __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
02224 {
02225   MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
02226 }
02227
02228 /**
02229   * @brief  Return Smartcard prescaler value, used for dividing the USART clock
02230   *         source to provide the SMARTCARD Clock (5 bits value)
02231   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02232   *         Smartcard feature is supported by the USARTx instance.
02233   * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
02234   * @param  USARTx USART Instance
02235   * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
02236   */
02237 __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
02238 {
02239   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
02240 }
02241
02242 /**
02243   * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
02244   *         (GT[7:0] bits : Guard time value)
02245   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02246   *         Smartcard feature is supported by the USARTx instance.
02247   * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
02248   * @param  USARTx USART Instance
02249   * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
02250   * @retval None
02251   */
02252 __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
02253 {
02254   MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
02255 }
02256
02257 /**
02258   * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
02259   *         (GT[7:0] bits : Guard time value)
02260   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02261   *         Smartcard feature is supported by the USARTx instance.
02262   * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
02263   * @param  USARTx USART Instance
02264   * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
02265   */
02266 __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
02267 {
02268   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
02269 }
02270
02271 /**
02272   * @}
02273   */
02274
02275 /** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
02276   * @{
02277   */
02278
02279 /**
02280   * @brief  Enable Single Wire Half-Duplex mode
02281   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02282   *         Half-Duplex mode is supported by the USARTx instance.
02283   * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
02284   * @param  USARTx USART Instance
02285   * @retval None
02286   */
02287 __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
02288 {
02289   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
02290 }
02291
02292 /**
02293   * @brief  Disable Single Wire Half-Duplex mode
02294   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02295   *         Half-Duplex mode is supported by the USARTx instance.
02296   * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
02297   * @param  USARTx USART Instance
02298   * @retval None
02299   */
02300 __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
02301 {
02302   CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
02303 }
02304
02305 /**
02306   * @brief  Indicate if Single Wire Half-Duplex mode is enabled
02307   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02308   *         Half-Duplex mode is supported by the USARTx instance.
02309   * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
02310   * @param  USARTx USART Instance
02311   * @retval State of bit (1 or 0).
02312   */
02313 __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
02314 {
02315   return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
02316 }
02317
02318 /**
02319   * @}
02320   */
02321
02322 /** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
02323   * @{
02324   */
02325 /**
02326   * @brief  Enable SPI Synchronous Slave mode
02327   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02328   *         SPI Slave mode feature is supported by the USARTx instance.
02329   * @rmtoll CR2          SLVEN         LL_USART_EnableSPISlave
02330   * @param  USARTx USART Instance
02331   * @retval None
02332   */
02333 __STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
02334 {
02335   SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
02336 }
02337
02338 /**
02339   * @brief  Disable SPI Synchronous Slave mode
02340   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02341   *         SPI Slave mode feature is supported by the USARTx instance.
02342   * @rmtoll CR2          SLVEN         LL_USART_DisableSPISlave
02343   * @param  USARTx USART Instance
02344   * @retval None
02345   */
02346 __STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
02347 {
02348   CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
02349 }
02350
02351 /**
02352   * @brief  Indicate if  SPI Synchronous Slave mode is enabled
02353   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02354   *         SPI Slave mode feature is supported by the USARTx instance.
02355   * @rmtoll CR2          SLVEN         LL_USART_IsEnabledSPISlave
02356   * @param  USARTx USART Instance
02357   * @retval State of bit (1 or 0).
02358   */
02359 __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)
02360 {
02361   return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
02362 }
02363
02364 /**
02365   * @brief  Enable SPI Slave Selection using NSS input pin
02366   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02367   *         SPI Slave mode feature is supported by the USARTx instance.
02368   * @note   SPI Slave Selection depends on NSS input pin
02369   *         (The slave is selected when NSS is low and deselected when NSS is high).
02370   * @rmtoll CR2          DIS_NSS       LL_USART_EnableSPISlaveSelect
02371   * @param  USARTx USART Instance
02372   * @retval None
02373   */
02374 __STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
02375 {
02376   CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
02377 }
02378
02379 /**
02380   * @brief  Disable SPI Slave Selection using NSS input pin
02381   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02382   *         SPI Slave mode feature is supported by the USARTx instance.
02383   * @note   SPI Slave will be always selected and NSS input pin will be ignored.
02384   * @rmtoll CR2          DIS_NSS       LL_USART_DisableSPISlaveSelect
02385   * @param  USARTx USART Instance
02386   * @retval None
02387   */
02388 __STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
02389 {
02390   SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
02391 }
02392
02393 /**
02394   * @brief  Indicate if  SPI Slave Selection depends on NSS input pin
02395   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02396   *         SPI Slave mode feature is supported by the USARTx instance.
02397   * @rmtoll CR2          DIS_NSS       LL_USART_IsEnabledSPISlaveSelect
02398   * @param  USARTx USART Instance
02399   * @retval State of bit (1 or 0).
02400   */
02401 __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)
02402 {
02403   return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
02404 }
02405
02406 /**
02407   * @}
02408   */
02409
02410 /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
02411   * @{
02412   */
02413
02414 /**
02415   * @brief  Set LIN Break Detection Length
02416   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02417   *         LIN feature is supported by the USARTx instance.
02418   * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
02419   * @param  USARTx USART Instance
02420   * @param  LINBDLength This parameter can be one of the following values:
02421   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
02422   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
02423   * @retval None
02424   */
02425 __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
02426 {
02427   MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
02428 }
02429
02430 /**
02431   * @brief  Return LIN Break Detection Length
02432   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02433   *         LIN feature is supported by the USARTx instance.
02434   * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
02435   * @param  USARTx USART Instance
02436   * @retval Returned value can be one of the following values:
02437   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
02438   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
02439   */
02440 __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
02441 {
02442   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
02443 }
02444
02445 /**
02446   * @brief  Enable LIN mode
02447   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02448   *         LIN feature is supported by the USARTx instance.
02449   * @rmtoll CR2          LINEN         LL_USART_EnableLIN
02450   * @param  USARTx USART Instance
02451   * @retval None
02452   */
02453 __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
02454 {
02455   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
02456 }
02457
02458 /**
02459   * @brief  Disable LIN mode
02460   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02461   *         LIN feature is supported by the USARTx instance.
02462   * @rmtoll CR2          LINEN         LL_USART_DisableLIN
02463   * @param  USARTx USART Instance
02464   * @retval None
02465   */
02466 __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
02467 {
02468   CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
02469 }
02470
02471 /**
02472   * @brief  Indicate if LIN mode is enabled
02473   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02474   *         LIN feature is supported by the USARTx instance.
02475   * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
02476   * @param  USARTx USART Instance
02477   * @retval State of bit (1 or 0).
02478   */
02479 __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
02480 {
02481   return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
02482 }
02483
02484 /**
02485   * @}
02486   */
02487
02488 /** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
02489   * @{
02490   */
02491
02492 /**
02493   * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
02494   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02495   *         Driver Enable feature is supported by the USARTx instance.
02496   * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
02497   * @param  USARTx USART Instance
02498   * @param  Time Value between Min_Data=0 and Max_Data=31
02499   * @retval None
02500   */
02501 __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
02502 {
02503   MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
02504 }
02505
02506 /**
02507   * @brief  Return DEDT (Driver Enable De-Assertion Time)
02508   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02509   *         Driver Enable feature is supported by the USARTx instance.
02510   * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
02511   * @param  USARTx USART Instance
02512   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
02513   */
02514 __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
02515 {
02516   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
02517 }
02518
02519 /**
02520   * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
02521   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02522   *         Driver Enable feature is supported by the USARTx instance.
02523   * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
02524   * @param  USARTx USART Instance
02525   * @param  Time Value between Min_Data=0 and Max_Data=31
02526   * @retval None
02527   */
02528 __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
02529 {
02530   MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
02531 }
02532
02533 /**
02534   * @brief  Return DEAT (Driver Enable Assertion Time)
02535   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02536   *         Driver Enable feature is supported by the USARTx instance.
02537   * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
02538   * @param  USARTx USART Instance
02539   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
02540   */
02541 __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
02542 {
02543   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
02544 }
02545
02546 /**
02547   * @brief  Enable Driver Enable (DE) Mode
02548   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02549   *         Driver Enable feature is supported by the USARTx instance.
02550   * @rmtoll CR3          DEM           LL_USART_EnableDEMode
02551   * @param  USARTx USART Instance
02552   * @retval None
02553   */
02554 __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
02555 {
02556   SET_BIT(USARTx->CR3, USART_CR3_DEM);
02557 }
02558
02559 /**
02560   * @brief  Disable Driver Enable (DE) Mode
02561   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02562   *         Driver Enable feature is supported by the USARTx instance.
02563   * @rmtoll CR3          DEM           LL_USART_DisableDEMode
02564   * @param  USARTx USART Instance
02565   * @retval None
02566   */
02567 __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
02568 {
02569   CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
02570 }
02571
02572 /**
02573   * @brief  Indicate if Driver Enable (DE) Mode is enabled
02574   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02575   *         Driver Enable feature is supported by the USARTx instance.
02576   * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
02577   * @param  USARTx USART Instance
02578   * @retval State of bit (1 or 0).
02579   */
02580 __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
02581 {
02582   return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
02583 }
02584
02585 /**
02586   * @brief  Select Driver Enable Polarity
02587   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02588   *         Driver Enable feature is supported by the USARTx instance.
02589   * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
02590   * @param  USARTx USART Instance
02591   * @param  Polarity This parameter can be one of the following values:
02592   *         @arg @ref LL_USART_DE_POLARITY_HIGH
02593   *         @arg @ref LL_USART_DE_POLARITY_LOW
02594   * @retval None
02595   */
02596 __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
02597 {
02598   MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
02599 }
02600
02601 /**
02602   * @brief  Return Driver Enable Polarity
02603   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02604   *         Driver Enable feature is supported by the USARTx instance.
02605   * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
02606   * @param  USARTx USART Instance
02607   * @retval Returned value can be one of the following values:
02608   *         @arg @ref LL_USART_DE_POLARITY_HIGH
02609   *         @arg @ref LL_USART_DE_POLARITY_LOW
02610   */
02611 __STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
02612 {
02613   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
02614 }
02615
02616 /**
02617   * @}
02618   */
02619
02620 /** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
02621   * @{
02622   */
02623
02624 /**
02625   * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
02626   * @note   In UART mode, the following bits must be kept cleared:
02627   *           - LINEN bit in the USART_CR2 register,
02628   *           - CLKEN bit in the USART_CR2 register,
02629   *           - SCEN bit in the USART_CR3 register,
02630   *           - IREN bit in the USART_CR3 register,
02631   *           - HDSEL bit in the USART_CR3 register.
02632   * @note   Call of this function is equivalent to following function call sequence :
02633   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02634   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02635   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02636   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02637   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02638   * @note   Other remaining configurations items related to Asynchronous Mode
02639   *         (as Baud Rate, Word length, Parity, ...) should be set using
02640   *         dedicated functions
02641   * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
02642   *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
02643   *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
02644   *         CR3          IREN          LL_USART_ConfigAsyncMode\n
02645   *         CR3          HDSEL         LL_USART_ConfigAsyncMode
02646   * @param  USARTx USART Instance
02647   * @retval None
02648   */
02649 __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
02650 {
02651   /* In Asynchronous mode, the following bits must be kept cleared:
02652   - LINEN, CLKEN bits in the USART_CR2 register,
02653   - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
02654   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02655   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
02656 }
02657
02658 /**
02659   * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
02660   * @note   In Synchronous mode, the following bits must be kept cleared:
02661   *           - LINEN bit in the USART_CR2 register,
02662   *           - SCEN bit in the USART_CR3 register,
02663   *           - IREN bit in the USART_CR3 register,
02664   *           - HDSEL bit in the USART_CR3 register.
02665   *         This function also sets the USART in Synchronous mode.
02666   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
02667   *         Synchronous mode is supported by the USARTx instance.
02668   * @note   Call of this function is equivalent to following function call sequence :
02669   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02670   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02671   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02672   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02673   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
02674   * @note   Other remaining configurations items related to Synchronous Mode
02675   *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
02676   *         dedicated functions
02677   * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
02678   *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
02679   *         CR3          SCEN          LL_USART_ConfigSyncMode\n
02680   *         CR3          IREN          LL_USART_ConfigSyncMode\n
02681   *         CR3          HDSEL         LL_USART_ConfigSyncMode
02682   * @param  USARTx USART Instance
02683   * @retval None
02684   */
02685 __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
02686 {
02687   /* In Synchronous mode, the following bits must be kept cleared:
02688   - LINEN bit in the USART_CR2 register,
02689   - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
02690   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
02691   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
02692   /* set the UART/USART in Synchronous mode */
02693   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
02694 }
02695
02696 /**
02697   * @brief  Perform basic configuration of USART for enabling use in LIN Mode
02698   * @note   In LIN mode, the following bits must be kept cleared:
02699   *           - STOP and CLKEN bits in the USART_CR2 register,
02700   *           - SCEN bit in the USART_CR3 register,
02701   *           - IREN bit in the USART_CR3 register,
02702   *           - HDSEL bit in the USART_CR3 register.
02703   *         This function also set the UART/USART in LIN mode.
02704   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02705   *         LIN feature is supported by the USARTx instance.
02706   * @note   Call of this function is equivalent to following function call sequence :
02707   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02708   *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02709   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02710   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02711   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02712   *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
02713   * @note   Other remaining configurations items related to LIN Mode
02714   *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
02715   *         dedicated functions
02716   * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
02717   *         CR2          STOP          LL_USART_ConfigLINMode\n
02718   *         CR2          LINEN         LL_USART_ConfigLINMode\n
02719   *         CR3          IREN          LL_USART_ConfigLINMode\n
02720   *         CR3          SCEN          LL_USART_ConfigLINMode\n
02721   *         CR3          HDSEL         LL_USART_ConfigLINMode
02722   * @param  USARTx USART Instance
02723   * @retval None
02724   */
02725 __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
02726 {
02727   /* In LIN mode, the following bits must be kept cleared:
02728   - STOP and CLKEN bits in the USART_CR2 register,
02729   - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
02730   CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
02731   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
02732   /* Set the UART/USART in LIN mode */
02733   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
02734 }
02735
02736 /**
02737   * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
02738   * @note   In Half Duplex mode, the following bits must be kept cleared:
02739   *           - LINEN bit in the USART_CR2 register,
02740   *           - CLKEN bit in the USART_CR2 register,
02741   *           - SCEN bit in the USART_CR3 register,
02742   *           - IREN bit in the USART_CR3 register,
02743   *         This function also sets the UART/USART in Half Duplex mode.
02744   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02745   *         Half-Duplex mode is supported by the USARTx instance.
02746   * @note   Call of this function is equivalent to following function call sequence :
02747   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02748   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02749   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02750   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02751   *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
02752   * @note   Other remaining configurations items related to Half Duplex Mode
02753   *         (as Baud Rate, Word length, Parity, ...) should be set using
02754   *         dedicated functions
02755   * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
02756   *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
02757   *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
02758   *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
02759   *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
02760   * @param  USARTx USART Instance
02761   * @retval None
02762   */
02763 __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
02764 {
02765   /* In Half Duplex mode, the following bits must be kept cleared:
02766   - LINEN and CLKEN bits in the USART_CR2 register,
02767   - SCEN and IREN bits in the USART_CR3 register.*/
02768   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02769   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
02770   /* set the UART/USART in Half Duplex mode */
02771   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
02772 }
02773
02774 /**
02775   * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
02776   * @note   In Smartcard mode, the following bits must be kept cleared:
02777   *           - LINEN bit in the USART_CR2 register,
02778   *           - IREN bit in the USART_CR3 register,
02779   *           - HDSEL bit in the USART_CR3 register.
02780   *         This function also configures Stop bits to 1.5 bits and
02781   *         sets the USART in Smartcard mode (SCEN bit).
02782   *         Clock Output is also enabled (CLKEN).
02783   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02784   *         Smartcard feature is supported by the USARTx instance.
02785   * @note   Call of this function is equivalent to following function call sequence :
02786   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02787   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02788   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02789   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02790   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
02791   *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
02792   * @note   Other remaining configurations items related to Smartcard Mode
02793   *         (as Baud Rate, Word length, Parity, ...) should be set using
02794   *         dedicated functions
02795   * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
02796   *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
02797   *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
02798   *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
02799   *         CR3          SCEN          LL_USART_ConfigSmartcardMode
02800   * @param  USARTx USART Instance
02801   * @retval None
02802   */
02803 __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
02804 {
02805   /* In Smartcard mode, the following bits must be kept cleared:
02806   - LINEN bit in the USART_CR2 register,
02807   - IREN and HDSEL bits in the USART_CR3 register.*/
02808   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
02809   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
02810   /* Configure Stop bits to 1.5 bits */
02811   /* Synchronous mode is activated by default */
02812   SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
02813   /* set the UART/USART in Smartcard mode */
02814   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
02815 }
02816
02817 /**
02818   * @brief  Perform basic configuration of USART for enabling use in Irda Mode
02819   * @note   In IRDA mode, the following bits must be kept cleared:
02820   *           - LINEN bit in the USART_CR2 register,
02821   *           - STOP and CLKEN bits in the USART_CR2 register,
02822   *           - SCEN bit in the USART_CR3 register,
02823   *           - HDSEL bit in the USART_CR3 register.
02824   *         This function also sets the UART/USART in IRDA mode (IREN bit).
02825   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02826   *         IrDA feature is supported by the USARTx instance.
02827   * @note   Call of this function is equivalent to following function call sequence :
02828   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02829   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02830   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02831   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02832   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02833   *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
02834   * @note   Other remaining configurations items related to Irda Mode
02835   *         (as Baud Rate, Word length, Power mode, ...) should be set using
02836   *         dedicated functions
02837   * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
02838   *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
02839   *         CR2          STOP          LL_USART_ConfigIrdaMode\n
02840   *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
02841   *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
02842   *         CR3          IREN          LL_USART_ConfigIrdaMode
02843   * @param  USARTx USART Instance
02844   * @retval None
02845   */
02846 __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
02847 {
02848   /* In IRDA mode, the following bits must be kept cleared:
02849   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
02850   - SCEN and HDSEL bits in the USART_CR3 register.*/
02851   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
02852   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
02853   /* set the UART/USART in IRDA mode */
02854   SET_BIT(USARTx->CR3, USART_CR3_IREN);
02855 }
02856
02857 /**
02858   * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
02859   *         (several USARTs connected in a network, one of the USARTs can be the master,
02860   *         its TX output connected to the RX inputs of the other slaves USARTs).
02861   * @note   In MultiProcessor mode, the following bits must be kept cleared:
02862   *           - LINEN bit in the USART_CR2 register,
02863   *           - CLKEN bit in the USART_CR2 register,
02864   *           - SCEN bit in the USART_CR3 register,
02865   *           - IREN bit in the USART_CR3 register,
02866   *           - HDSEL bit in the USART_CR3 register.
02867   * @note   Call of this function is equivalent to following function call sequence :
02868   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02869   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02870   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02871   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02872   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02873   * @note   Other remaining configurations items related to Multi processor Mode
02874   *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
02875   *         dedicated functions
02876   * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
02877   *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
02878   *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
02879   *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
02880   *         CR3          IREN          LL_USART_ConfigMultiProcessMode
02881   * @param  USARTx USART Instance
02882   * @retval None
02883   */
02884 __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
02885 {
02886   /* In Multi Processor mode, the following bits must be kept cleared:
02887   - LINEN and CLKEN bits in the USART_CR2 register,
02888   - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
02889   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02890   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
02891 }
02892
02893 /**
02894   * @}
02895   */
02896
02897 /** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
02898   * @{
02899   */
02900
02901 /**
02902   * @brief  Check if the USART Parity Error Flag is set or not
02903   * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
02904   * @param  USARTx USART Instance
02905   * @retval State of bit (1 or 0).
02906   */
02907 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
02908 {
02909   return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
02910 }
02911
02912 /**
02913   * @brief  Check if the USART Framing Error Flag is set or not
02914   * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
02915   * @param  USARTx USART Instance
02916   * @retval State of bit (1 or 0).
02917   */
02918 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
02919 {
02920   return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
02921 }
02922
02923 /**
02924   * @brief  Check if the USART Noise error detected Flag is set or not
02925   * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
02926   * @param  USARTx USART Instance
02927   * @retval State of bit (1 or 0).
02928   */
02929 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
02930 {
02931   return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
02932 }
02933
02934 /**
02935   * @brief  Check if the USART OverRun Error Flag is set or not
02936   * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
02937   * @param  USARTx USART Instance
02938   * @retval State of bit (1 or 0).
02939   */
02940 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
02941 {
02942   return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
02943 }
02944
02945 /**
02946   * @brief  Check if the USART IDLE line detected Flag is set or not
02947   * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
02948   * @param  USARTx USART Instance
02949   * @retval State of bit (1 or 0).
02950   */
02951 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
02952 {
02953   return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
02954 }
02955
02956 /* Legacy define */
02957 #define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE
02958
02959 /**
02960   * @brief  Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
02961   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
02962   *         FIFO mode feature is supported by the USARTx instance.
02963   * @rmtoll ISR          RXNE_RXFNE    LL_USART_IsActiveFlag_RXNE_RXFNE
02964   * @param  USARTx USART Instance
02965   * @retval State of bit (1 or 0).
02966   */
02967 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
02968 {
02969   return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
02970 }
02971
02972 /**
02973   * @brief  Check if the USART Transmission Complete Flag is set or not
02974   * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
02975   * @param  USARTx USART Instance
02976   * @retval State of bit (1 or 0).
02977   */
02978 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
02979 {
02980   return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
02981 }
02982
02983 /* Legacy define */
02984 #define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF
02985
02986 /**
02987   * @brief  Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
02988   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
02989   *         FIFO mode feature is supported by the USARTx instance.
02990   * @rmtoll ISR          TXE_TXFNF     LL_USART_IsActiveFlag_TXE_TXFNF
02991   * @param  USARTx USART Instance
02992   * @retval State of bit (1 or 0).
02993   */
02994 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
02995 {
02996   return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
02997 }
02998
02999 /**
03000   * @brief  Check if the USART LIN Break Detection Flag is set or not
03001   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03002   *         LIN feature is supported by the USARTx instance.
03003   * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
03004   * @param  USARTx USART Instance
03005   * @retval State of bit (1 or 0).
03006   */
03007 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
03008 {
03009   return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
03010 }
03011
03012 /**
03013   * @brief  Check if the USART CTS interrupt Flag is set or not
03014   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03015   *         Hardware Flow control feature is supported by the USARTx instance.
03016   * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
03017   * @param  USARTx USART Instance
03018   * @retval State of bit (1 or 0).
03019   */
03020 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
03021 {
03022   return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
03023 }
03024
03025 /**
03026   * @brief  Check if the USART CTS Flag is set or not
03027   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03028   *         Hardware Flow control feature is supported by the USARTx instance.
03029   * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
03030   * @param  USARTx USART Instance
03031   * @retval State of bit (1 or 0).
03032   */
03033 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
03034 {
03035   return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
03036 }
03037
03038 /**
03039   * @brief  Check if the USART Receiver Time Out Flag is set or not
03040   * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
03041   * @param  USARTx USART Instance
03042   * @retval State of bit (1 or 0).
03043   */
03044 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
03045 {
03046   return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
03047 }
03048
03049 /**
03050   * @brief  Check if the USART End Of Block Flag is set or not
03051   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03052   *         Smartcard feature is supported by the USARTx instance.
03053   * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
03054   * @param  USARTx USART Instance
03055   * @retval State of bit (1 or 0).
03056   */
03057 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
03058 {
03059   return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
03060 }
03061
03062 /**
03063   * @brief  Check if the SPI Slave Underrun error flag is set or not
03064   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
03065   *         SPI Slave mode feature is supported by the USARTx instance.
03066   * @rmtoll ISR          UDR           LL_USART_IsActiveFlag_UDR
03067   * @param  USARTx USART Instance
03068   * @retval State of bit (1 or 0).
03069   */
03070 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
03071 {
03072   return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
03073 }
03074
03075 /**
03076   * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
03077   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
03078   *         Auto Baud Rate detection feature is supported by the USARTx instance.
03079   * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
03080   * @param  USARTx USART Instance
03081   * @retval State of bit (1 or 0).
03082   */
03083 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
03084 {
03085   return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
03086 }
03087
03088 /**
03089   * @brief  Check if the USART Auto-Baud Rate Flag is set or not
03090   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
03091   *         Auto Baud Rate detection feature is supported by the USARTx instance.
03092   * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
03093   * @param  USARTx USART Instance
03094   * @retval State of bit (1 or 0).
03095   */
03096 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
03097 {
03098   return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
03099 }
03100
03101 /**
03102   * @brief  Check if the USART Busy Flag is set or not
03103   * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
03104   * @param  USARTx USART Instance
03105   * @retval State of bit (1 or 0).
03106   */
03107 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
03108 {
03109   return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
03110 }
03111
03112 /**
03113   * @brief  Check if the USART Character Match Flag is set or not
03114   * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
03115   * @param  USARTx USART Instance
03116   * @retval State of bit (1 or 0).
03117   */
03118 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
03119 {
03120   return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
03121 }
03122
03123 /**
03124   * @brief  Check if the USART Send Break Flag is set or not
03125   * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
03126   * @param  USARTx USART Instance
03127   * @retval State of bit (1 or 0).
03128   */
03129 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
03130 {
03131   return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
03132 }
03133
03134 /**
03135   * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
03136   * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
03137   * @param  USARTx USART Instance
03138   * @retval State of bit (1 or 0).
03139   */
03140 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
03141 {
03142   return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
03143 }
03144
03145 /**
03146   * @brief  Check if the USART Wake Up from stop mode Flag is set or not
03147   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03148   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03149   * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
03150   * @param  USARTx USART Instance
03151   * @retval State of bit (1 or 0).
03152   */
03153 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
03154 {
03155   return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
03156 }
03157
03158 /**
03159   * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
03160   * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
03161   * @param  USARTx USART Instance
03162   * @retval State of bit (1 or 0).
03163   */
03164 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
03165 {
03166   return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
03167 }
03168
03169 /**
03170   * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
03171   * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
03172   * @param  USARTx USART Instance
03173   * @retval State of bit (1 or 0).
03174   */
03175 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
03176 {
03177   return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
03178 }
03179
03180 /**
03181   * @brief  Check if the USART TX FIFO Empty Flag is set or not
03182   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03183   *         FIFO mode feature is supported by the USARTx instance.
03184   * @rmtoll ISR          TXFE          LL_USART_IsActiveFlag_TXFE
03185   * @param  USARTx USART Instance
03186   * @retval State of bit (1 or 0).
03187   */
03188 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
03189 {
03190   return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
03191 }
03192
03193 /**
03194   * @brief  Check if the USART RX FIFO Full Flag is set or not
03195   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03196   *         FIFO mode feature is supported by the USARTx instance.
03197   * @rmtoll ISR          RXFF          LL_USART_IsActiveFlag_RXFF
03198   * @param  USARTx USART Instance
03199   * @retval State of bit (1 or 0).
03200   */
03201 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
03202 {
03203   return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
03204 }
03205
03206 /**
03207   * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
03208   * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
03209   * @param  USARTx USART Instance
03210   * @retval State of bit (1 or 0).
03211   */
03212 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
03213 {
03214   return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
03215 }
03216
03217 /**
03218   * @brief  Check if the USART TX FIFO Threshold Flag is set or not
03219   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03220   *         FIFO mode feature is supported by the USARTx instance.
03221   * @rmtoll ISR          TXFT          LL_USART_IsActiveFlag_TXFT
03222   * @param  USARTx USART Instance
03223   * @retval State of bit (1 or 0).
03224   */
03225 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
03226 {
03227   return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
03228 }
03229
03230 /**
03231   * @brief  Check if the USART RX FIFO Threshold Flag is set or not
03232   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03233   *         FIFO mode feature is supported by the USARTx instance.
03234   * @rmtoll ISR          RXFT          LL_USART_IsActiveFlag_RXFT
03235   * @param  USARTx USART Instance
03236   * @retval State of bit (1 or 0).
03237   */
03238 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)
03239 {
03240   return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
03241 }
03242
03243 /**
03244   * @brief  Clear Parity Error Flag
03245   * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
03246   * @param  USARTx USART Instance
03247   * @retval None
03248   */
03249 __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
03250 {
03251   WRITE_REG(USARTx->ICR, USART_ICR_PECF);
03252 }
03253
03254 /**
03255   * @brief  Clear Framing Error Flag
03256   * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
03257   * @param  USARTx USART Instance
03258   * @retval None
03259   */
03260 __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
03261 {
03262   WRITE_REG(USARTx->ICR, USART_ICR_FECF);
03263 }
03264
03265 /**
03266   * @brief  Clear Noise Error detected Flag
03267   * @rmtoll ICR          NECF           LL_USART_ClearFlag_NE
03268   * @param  USARTx USART Instance
03269   * @retval None
03270   */
03271 __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
03272 {
03273   WRITE_REG(USARTx->ICR, USART_ICR_NECF);
03274 }
03275
03276 /**
03277   * @brief  Clear OverRun Error Flag
03278   * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
03279   * @param  USARTx USART Instance
03280   * @retval None
03281   */
03282 __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
03283 {
03284   WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
03285 }
03286
03287 /**
03288   * @brief  Clear IDLE line detected Flag
03289   * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
03290   * @param  USARTx USART Instance
03291   * @retval None
03292   */
03293 __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
03294 {
03295   WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
03296 }
03297
03298 /**
03299   * @brief  Clear TX FIFO Empty Flag
03300   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03301   *         FIFO mode feature is supported by the USARTx instance.
03302   * @rmtoll ICR          TXFECF        LL_USART_ClearFlag_TXFE
03303   * @param  USARTx USART Instance
03304   * @retval None
03305   */
03306 __STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
03307 {
03308   WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
03309 }
03310
03311 /**
03312   * @brief  Clear Transmission Complete Flag
03313   * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
03314   * @param  USARTx USART Instance
03315   * @retval None
03316   */
03317 __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
03318 {
03319   WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
03320 }
03321
03322 /**
03323   * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
03324   * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
03325   * @param  USARTx USART Instance
03326   * @retval None
03327   */
03328 __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
03329 {
03330   WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
03331 }
03332
03333 /**
03334   * @brief  Clear LIN Break Detection Flag
03335   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03336   *         LIN feature is supported by the USARTx instance.
03337   * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
03338   * @param  USARTx USART Instance
03339   * @retval None
03340   */
03341 __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
03342 {
03343   WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
03344 }
03345
03346 /**
03347   * @brief  Clear CTS Interrupt Flag
03348   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03349   *         Hardware Flow control feature is supported by the USARTx instance.
03350   * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
03351   * @param  USARTx USART Instance
03352   * @retval None
03353   */
03354 __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
03355 {
03356   WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
03357 }
03358
03359 /**
03360   * @brief  Clear Receiver Time Out Flag
03361   * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
03362   * @param  USARTx USART Instance
03363   * @retval None
03364   */
03365 __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
03366 {
03367   WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
03368 }
03369
03370 /**
03371   * @brief  Clear End Of Block Flag
03372   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03373   *         Smartcard feature is supported by the USARTx instance.
03374   * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
03375   * @param  USARTx USART Instance
03376   * @retval None
03377   */
03378 __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
03379 {
03380   WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
03381 }
03382
03383 /**
03384   * @brief  Clear SPI Slave Underrun Flag
03385   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
03386   *         SPI Slave mode feature is supported by the USARTx instance.
03387   * @rmtoll ICR          UDRCF         LL_USART_ClearFlag_UDR
03388   * @param  USARTx USART Instance
03389   * @retval None
03390   */
03391 __STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
03392 {
03393   WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
03394 }
03395
03396 /**
03397   * @brief  Clear Character Match Flag
03398   * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
03399   * @param  USARTx USART Instance
03400   * @retval None
03401   */
03402 __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
03403 {
03404   WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
03405 }
03406
03407 /**
03408   * @brief  Clear Wake Up from stop mode Flag
03409   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03410   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03411   * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
03412   * @param  USARTx USART Instance
03413   * @retval None
03414   */
03415 __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
03416 {
03417   WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
03418 }
03419
03420 /**
03421   * @}
03422   */
03423
03424 /** @defgroup USART_LL_EF_IT_Management IT_Management
03425   * @{
03426   */
03427
03428 /**
03429   * @brief  Enable IDLE Interrupt
03430   * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
03431   * @param  USARTx USART Instance
03432   * @retval None
03433   */
03434 __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
03435 {
03436   SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
03437 }
03438
03439 /* Legacy define */
03440 #define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE
03441
03442 /**
03443   * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
03444   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03445   *         FIFO mode feature is supported by the USARTx instance.
03446   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_EnableIT_RXNE_RXFNE
03447   * @param  USARTx USART Instance
03448   * @retval None
03449   */
03450 __STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
03451 {
03452   SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
03453 }
03454
03455 /**
03456   * @brief  Enable Transmission Complete Interrupt
03457   * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
03458   * @param  USARTx USART Instance
03459   * @retval None
03460   */
03461 __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
03462 {
03463   SET_BIT(USARTx->CR1, USART_CR1_TCIE);
03464 }
03465
03466 /* Legacy define */
03467 #define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF
03468
03469 /**
03470   * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
03471   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03472   *         FIFO mode feature is supported by the USARTx instance.
03473   * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_EnableIT_TXE_TXFNF
03474   * @param  USARTx USART Instance
03475   * @retval None
03476   */
03477 __STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
03478 {
03479   SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
03480 }
03481
03482 /**
03483   * @brief  Enable Parity Error Interrupt
03484   * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
03485   * @param  USARTx USART Instance
03486   * @retval None
03487   */
03488 __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
03489 {
03490   SET_BIT(USARTx->CR1, USART_CR1_PEIE);
03491 }
03492
03493 /**
03494   * @brief  Enable Character Match Interrupt
03495   * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
03496   * @param  USARTx USART Instance
03497   * @retval None
03498   */
03499 __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
03500 {
03501   SET_BIT(USARTx->CR1, USART_CR1_CMIE);
03502 }
03503
03504 /**
03505   * @brief  Enable Receiver Timeout Interrupt
03506   * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
03507   * @param  USARTx USART Instance
03508   * @retval None
03509   */
03510 __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
03511 {
03512   SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
03513 }
03514
03515 /**
03516   * @brief  Enable End Of Block Interrupt
03517   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03518   *         Smartcard feature is supported by the USARTx instance.
03519   * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
03520   * @param  USARTx USART Instance
03521   * @retval None
03522   */
03523 __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
03524 {
03525   SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
03526 }
03527
03528 /**
03529   * @brief  Enable TX FIFO Empty Interrupt
03530   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03531   *         FIFO mode feature is supported by the USARTx instance.
03532   * @rmtoll CR1          TXFEIE        LL_USART_EnableIT_TXFE
03533   * @param  USARTx USART Instance
03534   * @retval None
03535   */
03536 __STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
03537 {
03538   SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
03539 }
03540
03541 /**
03542   * @brief  Enable RX FIFO Full Interrupt
03543   * @rmtoll CR1          RXFFIE        LL_USART_EnableIT_RXFF
03544   * @param  USARTx USART Instance
03545   * @retval None
03546   */
03547 __STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
03548 {
03549   SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
03550 }
03551
03552 /**
03553   * @brief  Enable LIN Break Detection Interrupt
03554   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03555   *         LIN feature is supported by the USARTx instance.
03556   * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
03557   * @param  USARTx USART Instance
03558   * @retval None
03559   */
03560 __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
03561 {
03562   SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
03563 }
03564
03565 /**
03566   * @brief  Enable Error Interrupt
03567   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
03568   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
03569   *           0: Interrupt is inhibited
03570   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
03571   * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
03572   * @param  USARTx USART Instance
03573   * @retval None
03574   */
03575 __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
03576 {
03577   SET_BIT(USARTx->CR3, USART_CR3_EIE);
03578 }
03579
03580 /**
03581   * @brief  Enable CTS Interrupt
03582   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03583   *         Hardware Flow control feature is supported by the USARTx instance.
03584   * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
03585   * @param  USARTx USART Instance
03586   * @retval None
03587   */
03588 __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
03589 {
03590   SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
03591 }
03592
03593 /**
03594   * @brief  Enable Wake Up from Stop Mode Interrupt
03595   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03596   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03597   * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
03598   * @param  USARTx USART Instance
03599   * @retval None
03600   */
03601 __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
03602 {
03603   SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
03604 }
03605
03606 /**
03607   * @brief  Enable TX FIFO Threshold Interrupt
03608   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03609   *         FIFO mode feature is supported by the USARTx instance.
03610   * @rmtoll CR3          TXFTIE        LL_USART_EnableIT_TXFT
03611   * @param  USARTx USART Instance
03612   * @retval None
03613   */
03614 __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
03615 {
03616   SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
03617 }
03618
03619 /**
03620   * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
03621   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03622   *         Smartcard feature is supported by the USARTx instance.
03623   * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
03624   * @param  USARTx USART Instance
03625   * @retval None
03626   */
03627 __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
03628 {
03629   SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
03630 }
03631
03632 /**
03633   * @brief  Enable RX FIFO Threshold Interrupt
03634   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03635   *         FIFO mode feature is supported by the USARTx instance.
03636   * @rmtoll CR3          RXFTIE        LL_USART_EnableIT_RXFT
03637   * @param  USARTx USART Instance
03638   * @retval None
03639   */
03640 __STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
03641 {
03642   SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
03643 }
03644
03645 /**
03646   * @brief  Disable IDLE Interrupt
03647   * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
03648   * @param  USARTx USART Instance
03649   * @retval None
03650   */
03651 __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
03652 {
03653   CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
03654 }
03655
03656 /* Legacy define */
03657 #define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE
03658
03659 /**
03660   * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
03661   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03662   *         FIFO mode feature is supported by the USARTx instance.
03663   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_DisableIT_RXNE_RXFNE
03664   * @param  USARTx USART Instance
03665   * @retval None
03666   */
03667 __STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
03668 {
03669   CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
03670 }
03671
03672 /**
03673   * @brief  Disable Transmission Complete Interrupt
03674   * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
03675   * @param  USARTx USART Instance
03676   * @retval None
03677   */
03678 __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
03679 {
03680   CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
03681 }
03682
03683 /* Legacy define */
03684 #define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF
03685
03686 /**
03687   * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
03688   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03689   *         FIFO mode feature is supported by the USARTx instance.
03690   * @rmtoll CR1        TXEIE_TXFNFIE  LL_USART_DisableIT_TXE_TXFNF
03691   * @param  USARTx USART Instance
03692   * @retval None
03693   */
03694 __STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
03695 {
03696   CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
03697 }
03698
03699 /**
03700   * @brief  Disable Parity Error Interrupt
03701   * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
03702   * @param  USARTx USART Instance
03703   * @retval None
03704   */
03705 __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
03706 {
03707   CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
03708 }
03709
03710 /**
03711   * @brief  Disable Character Match Interrupt
03712   * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
03713   * @param  USARTx USART Instance
03714   * @retval None
03715   */
03716 __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
03717 {
03718   CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
03719 }
03720
03721 /**
03722   * @brief  Disable Receiver Timeout Interrupt
03723   * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
03724   * @param  USARTx USART Instance
03725   * @retval None
03726   */
03727 __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
03728 {
03729   CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
03730 }
03731
03732 /**
03733   * @brief  Disable End Of Block Interrupt
03734   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03735   *         Smartcard feature is supported by the USARTx instance.
03736   * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
03737   * @param  USARTx USART Instance
03738   * @retval None
03739   */
03740 __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
03741 {
03742   CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
03743 }
03744
03745 /**
03746   * @brief  Disable TX FIFO Empty Interrupt
03747   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03748   *         FIFO mode feature is supported by the USARTx instance.
03749   * @rmtoll CR1          TXFEIE        LL_USART_DisableIT_TXFE
03750   * @param  USARTx USART Instance
03751   * @retval None
03752   */
03753 __STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
03754 {
03755   CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
03756 }
03757
03758 /**
03759   * @brief  Disable RX FIFO Full Interrupt
03760   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03761   *         FIFO mode feature is supported by the USARTx instance.
03762   * @rmtoll CR1          RXFFIE        LL_USART_DisableIT_RXFF
03763   * @param  USARTx USART Instance
03764   * @retval None
03765   */
03766 __STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
03767 {
03768   CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
03769 }
03770
03771 /**
03772   * @brief  Disable LIN Break Detection Interrupt
03773   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03774   *         LIN feature is supported by the USARTx instance.
03775   * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
03776   * @param  USARTx USART Instance
03777   * @retval None
03778   */
03779 __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
03780 {
03781   CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
03782 }
03783
03784 /**
03785   * @brief  Disable Error Interrupt
03786   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
03787   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
03788   *           0: Interrupt is inhibited
03789   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
03790   * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
03791   * @param  USARTx USART Instance
03792   * @retval None
03793   */
03794 __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
03795 {
03796   CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
03797 }
03798
03799 /**
03800   * @brief  Disable CTS Interrupt
03801   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03802   *         Hardware Flow control feature is supported by the USARTx instance.
03803   * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
03804   * @param  USARTx USART Instance
03805   * @retval None
03806   */
03807 __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
03808 {
03809   CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
03810 }
03811
03812 /**
03813   * @brief  Disable Wake Up from Stop Mode Interrupt
03814   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03815   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03816   * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
03817   * @param  USARTx USART Instance
03818   * @retval None
03819   */
03820 __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
03821 {
03822   CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
03823 }
03824
03825 /**
03826   * @brief  Disable TX FIFO Threshold Interrupt
03827   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03828   *         FIFO mode feature is supported by the USARTx instance.
03829   * @rmtoll CR3          TXFTIE        LL_USART_DisableIT_TXFT
03830   * @param  USARTx USART Instance
03831   * @retval None
03832   */
03833 __STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
03834 {
03835   CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
03836 }
03837
03838 /**
03839   * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
03840   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03841   *         Smartcard feature is supported by the USARTx instance.
03842   * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
03843   * @param  USARTx USART Instance
03844   * @retval None
03845   */
03846 __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
03847 {
03848   CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
03849 }
03850
03851 /**
03852   * @brief  Disable RX FIFO Threshold Interrupt
03853   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03854   *         FIFO mode feature is supported by the USARTx instance.
03855   * @rmtoll CR3          RXFTIE        LL_USART_DisableIT_RXFT
03856   * @param  USARTx USART Instance
03857   * @retval None
03858   */
03859 __STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
03860 {
03861   CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
03862 }
03863
03864 /**
03865   * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
03866   * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
03867   * @param  USARTx USART Instance
03868   * @retval State of bit (1 or 0).
03869   */
03870 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
03871 {
03872   return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
03873 }
03874
03875 /* Legacy define */
03876 #define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE
03877
03878 /**
03879   * @brief  Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
03880   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03881   *         FIFO mode feature is supported by the USARTx instance.
03882   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_IsEnabledIT_RXNE_RXFNE
03883   * @param  USARTx USART Instance
03884   * @retval State of bit (1 or 0).
03885   */
03886 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
03887 {
03888   return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
03889 }
03890
03891 /**
03892   * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
03893   * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
03894   * @param  USARTx USART Instance
03895   * @retval State of bit (1 or 0).
03896   */
03897 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
03898 {
03899   return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
03900 }
03901
03902 /* Legacy define */
03903 #define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF
03904
03905 /**
03906   * @brief  Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
03907   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03908   *         FIFO mode feature is supported by the USARTx instance.
03909   * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_IsEnabledIT_TXE_TXFNF
03910   * @param  USARTx USART Instance
03911   * @retval State of bit (1 or 0).
03912   */
03913 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
03914 {
03915   return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
03916 }
03917
03918 /**
03919   * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
03920   * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
03921   * @param  USARTx USART Instance
03922   * @retval State of bit (1 or 0).
03923   */
03924 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
03925 {
03926   return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
03927 }
03928
03929 /**
03930   * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
03931   * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
03932   * @param  USARTx USART Instance
03933   * @retval State of bit (1 or 0).
03934   */
03935 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
03936 {
03937   return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
03938 }
03939
03940 /**
03941   * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
03942   * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
03943   * @param  USARTx USART Instance
03944   * @retval State of bit (1 or 0).
03945   */
03946 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
03947 {
03948   return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
03949 }
03950
03951 /**
03952   * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
03953   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03954   *         Smartcard feature is supported by the USARTx instance.
03955   * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
03956   * @param  USARTx USART Instance
03957   * @retval State of bit (1 or 0).
03958   */
03959 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
03960 {
03961   return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
03962 }
03963
03964 /**
03965   * @brief  Check if the USART TX FIFO Empty Interrupt is enabled or disabled
03966   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03967   *         FIFO mode feature is supported by the USARTx instance.
03968   * @rmtoll CR1          TXFEIE        LL_USART_IsEnabledIT_TXFE
03969   * @param  USARTx USART Instance
03970   * @retval State of bit (1 or 0).
03971   */
03972 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
03973 {
03974   return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
03975 }
03976
03977 /**
03978   * @brief  Check if the USART RX FIFO Full Interrupt is enabled or disabled
03979   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03980   *         FIFO mode feature is supported by the USARTx instance.
03981   * @rmtoll CR1          RXFFIE        LL_USART_IsEnabledIT_RXFF
03982   * @param  USARTx USART Instance
03983   * @retval State of bit (1 or 0).
03984   */
03985 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
03986 {
03987   return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
03988 }
03989
03990 /**
03991   * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
03992   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03993   *         LIN feature is supported by the USARTx instance.
03994   * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
03995   * @param  USARTx USART Instance
03996   * @retval State of bit (1 or 0).
03997   */
03998 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
03999 {
04000   return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
04001 }
04002
04003 /**
04004   * @brief  Check if the USART Error Interrupt is enabled or disabled.
04005   * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
04006   * @param  USARTx USART Instance
04007   * @retval State of bit (1 or 0).
04008   */
04009 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
04010 {
04011   return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
04012 }
04013
04014 /**
04015   * @brief  Check if the USART CTS Interrupt is enabled or disabled.
04016   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
04017   *         Hardware Flow control feature is supported by the USARTx instance.
04018   * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
04019   * @param  USARTx USART Instance
04020   * @retval State of bit (1 or 0).
04021   */
04022 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
04023 {
04024   return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
04025 }
04026
04027 /**
04028   * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
04029   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
04030   *         Wake-up from Stop mode feature is supported by the USARTx instance.
04031   * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
04032   * @param  USARTx USART Instance
04033   * @retval State of bit (1 or 0).
04034   */
04035 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
04036 {
04037   return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
04038 }
04039
04040 /**
04041   * @brief  Check if USART TX FIFO Threshold Interrupt is enabled or disabled
04042   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04043   *         FIFO mode feature is supported by the USARTx instance.
04044   * @rmtoll CR3          TXFTIE        LL_USART_IsEnabledIT_TXFT
04045   * @param  USARTx USART Instance
04046   * @retval State of bit (1 or 0).
04047   */
04048 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
04049 {
04050   return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
04051 }
04052
04053 /**
04054   * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
04055   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
04056   *         Smartcard feature is supported by the USARTx instance.
04057   * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
04058   * @param  USARTx USART Instance
04059   * @retval State of bit (1 or 0).
04060   */
04061 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
04062 {
04063   return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
04064 }
04065
04066 /**
04067   * @brief  Check if USART RX FIFO Threshold Interrupt is enabled or disabled
04068   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04069   *         FIFO mode feature is supported by the USARTx instance.
04070   * @rmtoll CR3          RXFTIE        LL_USART_IsEnabledIT_RXFT
04071   * @param  USARTx USART Instance
04072   * @retval State of bit (1 or 0).
04073   */
04074 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
04075 {
04076   return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
04077 }
04078
04079 /**
04080   * @}
04081   */
04082
04083 /** @defgroup USART_LL_EF_DMA_Management DMA_Management
04084   * @{
04085   */
04086
04087 /**
04088   * @brief  Enable DMA Mode for reception
04089   * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
04090   * @param  USARTx USART Instance
04091   * @retval None
04092   */
04093 __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
04094 {
04095   SET_BIT(USARTx->CR3, USART_CR3_DMAR);
04096 }
04097
04098 /**
04099   * @brief  Disable DMA Mode for reception
04100   * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
04101   * @param  USARTx USART Instance
04102   * @retval None
04103   */
04104 __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
04105 {
04106   CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
04107 }
04108
04109 /**
04110   * @brief  Check if DMA Mode is enabled for reception
04111   * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
04112   * @param  USARTx USART Instance
04113   * @retval State of bit (1 or 0).
04114   */
04115 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
04116 {
04117   return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
04118 }
04119
04120 /**
04121   * @brief  Enable DMA Mode for transmission
04122   * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
04123   * @param  USARTx USART Instance
04124   * @retval None
04125   */
04126 __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
04127 {
04128   SET_BIT(USARTx->CR3, USART_CR3_DMAT);
04129 }
04130
04131 /**
04132   * @brief  Disable DMA Mode for transmission
04133   * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
04134   * @param  USARTx USART Instance
04135   * @retval None
04136   */
04137 __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
04138 {
04139   CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
04140 }
04141
04142 /**
04143   * @brief  Check if DMA Mode is enabled for transmission
04144   * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
04145   * @param  USARTx USART Instance
04146   * @retval State of bit (1 or 0).
04147   */
04148 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
04149 {
04150   return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
04151 }
04152
04153 /**
04154   * @brief  Enable DMA Disabling on Reception Error
04155   * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
04156   * @param  USARTx USART Instance
04157   * @retval None
04158   */
04159 __STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
04160 {
04161   SET_BIT(USARTx->CR3, USART_CR3_DDRE);
04162 }
04163
04164 /**
04165   * @brief  Disable DMA Disabling on Reception Error
04166   * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
04167   * @param  USARTx USART Instance
04168   * @retval None
04169   */
04170 __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
04171 {
04172   CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
04173 }
04174
04175 /**
04176   * @brief  Indicate if DMA Disabling on Reception Error is disabled
04177   * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
04178   * @param  USARTx USART Instance
04179   * @retval State of bit (1 or 0).
04180   */
04181 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
04182 {
04183   return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
04184 }
04185
04186 /**
04187   * @brief  Get the data register address used for DMA transfer
04188   * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
04189   * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
04190   * @param  USARTx USART Instance
04191   * @param  Direction This parameter can be one of the following values:
04192   *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
04193   *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
04194   * @retval Address of data register
04195   */
04196 __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
04197 {
04198   register uint32_t data_reg_addr;
04199
04200   if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
04201   {
04202     /* return address of TDR register */
04203     data_reg_addr = (uint32_t) & (USARTx->TDR);
04204   }
04205   else
04206   {
04207     /* return address of RDR register */
04208     data_reg_addr = (uint32_t) & (USARTx->RDR);
04209   }
04210
04211   return data_reg_addr;
04212 }
04213
04214 /**
04215   * @}
04216   */
04217
04218 /** @defgroup USART_LL_EF_Data_Management Data_Management
04219   * @{
04220   */
04221
04222 /**
04223   * @brief  Read Receiver Data register (Receive Data value, 8 bits)
04224   * @rmtoll RDR          RDR           LL_USART_ReceiveData8
04225   * @param  USARTx USART Instance
04226   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
04227   */
04228 __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
04229 {
04230   return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
04231 }
04232
04233 /**
04234   * @brief  Read Receiver Data register (Receive Data value, 9 bits)
04235   * @rmtoll RDR          RDR           LL_USART_ReceiveData9
04236   * @param  USARTx USART Instance
04237   * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
04238   */
04239 __STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
04240 {
04241   return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
04242 }
04243
04244 /**
04245   * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
04246   * @rmtoll TDR          TDR           LL_USART_TransmitData8
04247   * @param  USARTx USART Instance
04248   * @param  Value between Min_Data=0x00 and Max_Data=0xFF
04249   * @retval None
04250   */
04251 __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
04252 {
04253   USARTx->TDR = Value;
04254 }
04255
04256 /**
04257   * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
04258   * @rmtoll TDR          TDR           LL_USART_TransmitData9
04259   * @param  USARTx USART Instance
04260   * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
04261   * @retval None
04262   */
04263 __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
04264 {
04265   USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
04266 }
04267
04268 /**
04269   * @}
04270   */
04271
04272 /** @defgroup USART_LL_EF_Execution Execution
04273   * @{
04274   */
04275
04276 /**
04277   * @brief  Request an Automatic Baud Rate measurement on next received data frame
04278   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
04279   *         Auto Baud Rate detection feature is supported by the USARTx instance.
04280   * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
04281   * @param  USARTx USART Instance
04282   * @retval None
04283   */
04284 __STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
04285 {
04286   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
04287 }
04288
04289 /**
04290   * @brief  Request Break sending
04291   * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
04292   * @param  USARTx USART Instance
04293   * @retval None
04294   */
04295 __STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
04296 {
04297   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
04298 }
04299
04300 /**
04301   * @brief  Put USART in mute mode and set the RWU flag
04302   * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
04303   * @param  USARTx USART Instance
04304   * @retval None
04305   */
04306 __STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
04307 {
04308   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
04309 }
04310
04311 /**
04312   * @brief  Request a Receive Data and FIFO flush
04313   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04314   *         FIFO mode feature is supported by the USARTx instance.
04315   * @note   Allows to discard the received data without reading them, and avoid an overrun
04316   *         condition.
04317   * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
04318   * @param  USARTx USART Instance
04319   * @retval None
04320   */
04321 __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
04322 {
04323   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
04324 }
04325
04326 /**
04327   * @brief  Request a Transmit data and FIFO flush
04328   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04329   *         FIFO mode feature is supported by the USARTx instance.
04330   * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
04331   * @param  USARTx USART Instance
04332   * @retval None
04333   */
04334 __STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
04335 {
04336   SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
04337 }
04338
04339 /**
04340   * @}
04341   */
04342
04343 #if defined(USE_FULL_LL_DRIVER)
04344 /** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
04345   * @{
04346   */
04347 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
04348 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
04349 void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
04350 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
04351 void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
04352 /**
04353   * @}
04354   */
04355 #endif /* USE_FULL_LL_DRIVER */
04356
04357 /**
04358   * @}
04359   */
04360
04361 /**
04362   * @}
04363   */
04364
04365 #endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 */
04366
04367 /**
04368   * @}
04369   */
04370
04371 #ifdef __cplusplus
04372 }
04373 #endif
04374
04375 #endif /* STM32H7xx_LL_USART_H */
04376
04377 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM32H757xx HAL User Manual: stm32h7xx_ll_utils.c Source File

  • Drivers
  • STM32H7xx_HAL_Driver
  • Src
stm32h7xx_ll_utils.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_utils.c
00004   * @author  MCD Application Team
00005   * @brief   UTILS LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 /* Includes ------------------------------------------------------------------*/
00020 #include "stm32h7xx_ll_utils.h"
00021 #include "stm32h7xx_ll_rcc.h"
00022 #include "stm32h7xx_ll_pwr.h"
00023
00024 #ifdef  USE_FULL_ASSERT
00025   #include "stm32_assert.h"
00026 #else
00027   #define assert_param(expr) ((void)0U)
00028 #endif /* USE_FULL_ASSERT */
00029
00030 /** @addtogroup STM32H7xx_LL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup UTILS_LL
00035   * @{
00036   */
00037
00038 /* Private types -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private constants ---------------------------------------------------------*/
00041 /** @addtogroup UTILS_LL_Private_Constants
00042   * @{
00043   */
00044 #define UTILS_MAX_FREQUENCY_SCALE1  400000000U      /*!< Maximum frequency for system clock at power scale1, in Hz */
00045 #define UTILS_MAX_FREQUENCY_SCALE2  300000000U      /*!< Maximum frequency for system clock at power scale2, in Hz */
00046 #define UTILS_MAX_FREQUENCY_SCALE3  200000000U      /*!< Maximum frequency for system clock at power scale3, in Hz */
00047
00048 /* Defines used for PLL range */
00049 #define UTILS_PLLVCO_INPUT_MIN1       1000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
00050 #define UTILS_PLLVCO_INPUT_MAX1       2000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
00051 #define UTILS_PLLVCO_INPUT_MIN2       2000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
00052 #define UTILS_PLLVCO_INPUT_MAX2       4000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
00053 #define UTILS_PLLVCO_INPUT_MIN3       4000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
00054 #define UTILS_PLLVCO_INPUT_MAX3       8000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
00055 #define UTILS_PLLVCO_INPUT_MIN4       8000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
00056 #define UTILS_PLLVCO_INPUT_MAX4      16000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
00057
00058 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN    150000000U      /*!< Frequency min for the medium range PLLVCO output, in Hz   */
00059 #define UTILS_PLLVCO_WIDE_OUTPUT_MIN      192000000U      /*!< Frequency min for the wide range PLLVCO output, in Hz   */
00060 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX    420000000U      /*!< Frequency max for the wide range PLLVCO output, in Hz  */
00061 #define UTILS_PLLVCO_WIDE_OUTPUT_MAX      836000000U      /*!< Frequency max for the wide range PLLVCO output, in Hz  */
00062
00063 /* Defines used for HSE range */
00064 #define UTILS_HSE_FREQUENCY_MIN      4000000U        /*!< Frequency min for HSE frequency, in Hz   */
00065 #define UTILS_HSE_FREQUENCY_MAX     48000000U        /*!< Frequency max for HSE frequency, in Hz   */
00066
00067 /* Defines used for FLASH latency according to HCLK Frequency */
00068 #define UTILS_SCALE1_LATENCY0_FREQ   70000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 1  */
00069 #define UTILS_SCALE1_LATENCY1_FREQ  140000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
00070 #define UTILS_SCALE1_LATENCY2_FREQ  210000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
00071
00072 #define UTILS_SCALE2_LATENCY0_FREQ   55000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 2  */
00073 #define UTILS_SCALE2_LATENCY1_FREQ  110000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
00074 #define UTILS_SCALE2_LATENCY2_FREQ  165000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
00075 #define UTILS_SCALE2_LATENCY3_FREQ  220000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
00076
00077 #define UTILS_SCALE3_LATENCY0_FREQ   45000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 3  */
00078 #define UTILS_SCALE3_LATENCY1_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */
00079 #define UTILS_SCALE3_LATENCY2_FREQ  135000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */
00080 #define UTILS_SCALE3_LATENCY3_FREQ  180000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */
00081 #define UTILS_SCALE3_LATENCY4_FREQ  225000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 3  */
00082 /**
00083   * @}
00084   */
00085
00086 /* Private macros ------------------------------------------------------------*/
00087 /** @addtogroup UTILS_LL_Private_Macros
00088   * @{
00089   */
00090 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
00091                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
00092                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
00093                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
00094                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
00095                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
00096                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
00097                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
00098                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
00099
00100 #define IS_LL_UTILS_AHB_DIV(__VALUE__)    (((__VALUE__) == LL_RCC_AHB_DIV_1)   \
00101                                         || ((__VALUE__) == LL_RCC_AHB_DIV_2)   \
00102                                         || ((__VALUE__) == LL_RCC_AHB_DIV_4)   \
00103                                         || ((__VALUE__) == LL_RCC_AHB_DIV_8)   \
00104                                         || ((__VALUE__) == LL_RCC_AHB_DIV_16)  \
00105                                         || ((__VALUE__) == LL_RCC_AHB_DIV_64)  \
00106                                         || ((__VALUE__) == LL_RCC_AHB_DIV_128) \
00107                                         || ((__VALUE__) == LL_RCC_AHB_DIV_256) \
00108                                         || ((__VALUE__) == LL_RCC_AHB_DIV_512))
00109
00110 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
00111                                       || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
00112                                       || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
00113                                       || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
00114                                       || ((__VALUE__) == LL_RCC_APB1_DIV_16))
00115
00116 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
00117                                       || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
00118                                       || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
00119                                       || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
00120                                       || ((__VALUE__) == LL_RCC_APB2_DIV_16))
00121
00122 #define IS_LL_UTILS_APB3_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB3_DIV_1) \
00123                                       || ((__VALUE__) == LL_RCC_APB3_DIV_2) \
00124                                       || ((__VALUE__) == LL_RCC_APB3_DIV_4) \
00125                                       || ((__VALUE__) == LL_RCC_APB3_DIV_8) \
00126                                       || ((__VALUE__) == LL_RCC_APB3_DIV_16))
00127
00128 #define IS_LL_UTILS_APB4_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB4_DIV_1) \
00129                                       || ((__VALUE__) == LL_RCC_APB4_DIV_2) \
00130                                       || ((__VALUE__) == LL_RCC_APB4_DIV_4) \
00131                                       || ((__VALUE__) == LL_RCC_APB4_DIV_8) \
00132                                       || ((__VALUE__) == LL_RCC_APB4_DIV_16))
00133
00134 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U))
00135
00136 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((4U <= (__VALUE__)) && ((__VALUE__) <= 512U))
00137
00138 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U))
00139
00140 #define IS_LL_UTILS_FRACN_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
00141
00142 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__, __RANGE__)  ( \
00143 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_1_2) && (UTILS_PLLVCO_INPUT_MIN1 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX1)) || \
00144 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_2_4) && (UTILS_PLLVCO_INPUT_MIN2 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX2)) || \
00145 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_4_8) && (UTILS_PLLVCO_INPUT_MIN3 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX3)) || \
00146 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_8_16) && (UTILS_PLLVCO_INPUT_MIN4 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX4)))
00147
00148 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__, __RANGE__) ( \
00149 (((__RANGE__) == LL_RCC_PLLVCORANGE_MEDIUM) && (UTILS_PLLVCO_MEDIUM_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_MEDIUM_OUTPUT_MAX)) || \
00150 (((__RANGE__) == LL_RCC_PLLVCORANGE_WIDE) && (UTILS_PLLVCO_WIDE_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_WIDE_OUTPUT_MAX)))
00151
00152 #define IS_LL_UTILS_CHECK_VCO_RANGES(__RANGEIN__, __RANGEOUT__) ( \
00153 (((__RANGEIN__) == LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_MEDIUM)) || \
00154 (((__RANGEIN__) != LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_WIDE)))
00155
00156 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
00157                                               (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
00158                                               ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
00159
00160 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
00161                                         || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
00162
00163 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
00164 /**
00165   * @}
00166   */
00167 /* Private function prototypes -----------------------------------------------*/
00168 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
00169   * @{
00170   */
00171 static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
00172 static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t *latency);
00173 static ErrorStatus UTILS_SetFlashLatency(uint32_t latency);
00174 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00175 static ErrorStatus UTILS_IsPLLsReady(void);
00176 /**
00177   * @}
00178   */
00179
00180 /* Exported functions --------------------------------------------------------*/
00181 /** @addtogroup UTILS_LL_Exported_Functions
00182   * @{
00183   */
00184
00185 /** @addtogroup UTILS_LL_EF_DELAY
00186   * @{
00187   */
00188 #if defined (DUAL_CORE)
00189 /**
00190   * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
00191   * @note   When a RTOS is used, it is recommended to avoid changing the Systick
00192   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00193   * @param  CPU_Frequency Core frequency in Hz
00194   * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
00195   *         @ref LL_RCC_GetSystemClocksFreq
00196   *         LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency
00197   *         and __LL_RCC_CALC_HCLK_FREQ is used to caluclate the CM4 clock frequency.
00198   * @retval None
00199   */
00200 #else
00201 /**
00202   * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
00203   * @note   When a RTOS is used, it is recommended to avoid changing the Systick
00204   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00205   * @param  CPU_Frequency Core frequency in Hz
00206   * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
00207   *         @ref LL_RCC_GetSystemClocksFreq
00208   * @retval None
00209   */
00210 #endif /* DUAL_CORE */
00211 void LL_Init1msTick(uint32_t CPU_Frequency)
00212 {
00213   /* Use frequency provided in argument */
00214   LL_InitTick(CPU_Frequency, 1000U);
00215 }
00216
00217
00218 /**
00219   * @brief  This function provides accurate delay (in milliseconds) based
00220   *         on SysTick counter flag
00221   * @note   When a RTOS is used, it is recommended to avoid using blocking delay
00222   *         and use rather osDelay service.
00223   * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
00224   *         will configure Systick to 1ms
00225   * @param  Delay specifies the delay time length, in milliseconds.
00226   * @retval None
00227   */
00228 void LL_mDelay(uint32_t Delay)
00229 {
00230   uint32_t count = Delay;
00231   __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
00232   /* Add this code to indicate that local variable is not used */
00233   ((void)tmp);
00234
00235   /* Add a period to guaranty minimum wait */
00236   if(count < LL_MAX_DELAY)
00237   {
00238     count++;
00239   }
00240
00241   while (count != 0U)
00242   {
00243     if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
00244     {
00245       count--;
00246     }
00247   }
00248 }
00249
00250 /**
00251   * @}
00252   */
00253
00254 /** @addtogroup UTILS_EF_SYSTEM
00255   *  @brief    System Configuration functions
00256   *
00257   @verbatim
00258  ===============================================================================
00259            ##### System Configuration functions #####
00260  ===============================================================================
00261     [..]
00262          System, AHB and APB buses clocks configuration
00263
00264          (+) The maximum frequency of the SYSCLK is 400 MHz and HCLK is 200 MHz.
00265          (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 100 MHz.
00266   @endverbatim
00267   @internal
00268              Depending on the device voltage range, the maximum frequency should be
00269              adapted accordingly:
00270              (++) +----------------------------------------------------------------------------+
00271              (++) |  Wait states   |                           HCLK clock frequency (MHz)      |
00272              (++) |                |-----------------------------------------------------------|
00273              (++) |  (Latency)     |   voltage range 1 |   voltage range 2 |   voltage range 3 |
00274              (++) |                |    1.15V - 1.26V  |    1.05V - 1.15V  |    0.95V - 1.05V  |
00275              (++) |----------------|-------------------|-------------------|-------------------|
00276              (++) |0WS(1CPU cycle) |   0 < HCLK <= 70  |   0 < HCLK <= 55  |   0 < HCLK <= 45  |
00277              (++) |----------------|-------------------|-------------------|-------------------|
00278              (++) |1WS(2CPU cycle) |  70 < HCLK <= 140 |  55 < HCLK <= 110 |  45 < HCLK <= 90  |
00279              (++) |----------------|-------------------|-------------------|-------------------|
00280              (++) |2WS(3CPU cycle) | 140 < HCLK <= 210 | 110 < HCLK <= 165 |  90 < HCLK <= 135 |
00281              (++) |----------------|-------------------|-------------------|-------------------|
00282              (++) |3WS(4CPU cycle) |        --         | 165 < HCLK <= 220 | 135 < HCLK <= 180 |
00283              (++) |----------------|-------------------|-------------------|-------------------|
00284              (++) |4WS(5CPU cycle) |        --         |        --         | 180 < HCLK <= 225 |
00285              (++) +----------------------------------------------------------------------------+
00286
00287   @endinternal
00288   * @{
00289   */
00290 #if defined (DUAL_CORE)
00291 /**
00292   * @brief  This function sets directly SystemCoreClock CMSIS variable.
00293   * @note   Variable can be calculated also through SystemCoreClockUpdate function.
00294   * @param  CPU_Frequency Core frequency in Hz
00295   * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
00296   *         @ref LL_RCC_GetSystemClocksFreq
00297   *         LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency
00298   *         and __LL_RCC_CALC_HCLK_FREQ is used to caluclate the CM4 clock frequency.
00299   * @retval None
00300   */
00301 #else
00302 /**
00303   * @brief  This function sets directly SystemCoreClock CMSIS variable.
00304   * @note   Variable can be calculated also through SystemCoreClockUpdate function.
00305   * @param  CPU_Frequency Core frequency in Hz
00306   * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
00307   *         @ref LL_RCC_GetSystemClocksFreq
00308   * @retval None
00309   */
00310 #endif /* DUAL_CORE */
00311 void LL_SetSystemCoreClock(uint32_t CPU_Frequency)
00312 {
00313   /* HCLK clock frequency */
00314   SystemCoreClock = CPU_Frequency;
00315 }
00316
00317 /**
00318   * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL
00319   * @note   The application need to ensure that PLL is disabled.
00320   * @note   Function is based on the following formula:
00321   *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
00322   *         - PLLM: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
00323   *         - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz (PLLVCO_output = PLLVCO_input * PLLN)
00324   *         - PLLP: ensure that max frequency at 400000000 Hz is reach (PLLVCO_output / PLLP)
00325   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00326   *                             the configuration information for the PLL.
00327   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00328   *                             the configuration information for the BUS prescalers.
00329   * @retval An ErrorStatus enumeration value:
00330   *          - SUCCESS: Max frequency configuration done
00331   *          - ERROR: Max frequency configuration not done
00332   */
00333 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00334                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00335 {
00336   ErrorStatus status;
00337 #ifdef  USE_FULL_ASSERT
00338   uint32_t vcoinput_freq, vcooutput_freq;
00339 #endif
00340   uint32_t pllfreq, hsi_clk;
00341
00342   /* Check the parameters */
00343   assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
00344   assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
00345   assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
00346   assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
00347
00348   hsi_clk = (HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos));
00349
00350   /* Check VCO Input frequency */
00351 #ifdef  USE_FULL_ASSERT
00352   vcoinput_freq = hsi_clk / UTILS_PLLInitStruct->PLLM;
00353 #endif
00354   assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
00355
00356   /* Check VCO Output frequency */
00357 #ifdef  USE_FULL_ASSERT
00358   vcooutput_freq = LL_RCC_CalcPLLClockFreq(hsi_clk, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1UL);
00359 #endif
00360   assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
00361
00362   /* Check VCO Input ranges */
00363   assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
00364
00365   /* Check if one of the PLL is enabled */
00366   if(UTILS_IsPLLsReady() == SUCCESS)
00367   {
00368     /* Calculate the new PLL output frequency */
00369     pllfreq = UTILS_GetPLLOutputFrequency(hsi_clk, UTILS_PLLInitStruct);
00370
00371     /* Enable HSI if not enabled */
00372     if(LL_RCC_HSI_IsReady() != 1U)
00373     {
00374       LL_RCC_HSI_Enable();
00375       while (LL_RCC_HSI_IsReady() != 1U)
00376       {
00377         /* Wait for HSI ready */
00378       }
00379     }
00380
00381     /* Configure PLL */
00382     LL_RCC_PLL1P_Enable();
00383     LL_RCC_PLL1FRACN_Enable();
00384     LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSI);
00385     LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
00386     LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
00387     LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM);
00388     LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN);
00389     LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP);
00390     LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
00391
00392     /* Enable PLL and switch system clock to PLL */
00393     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
00394   }
00395   else
00396   {
00397     /* Current PLL configuration cannot be modified */
00398     status = ERROR;
00399   }
00400
00401   return status;
00402 }
00403
00404 /**
00405   * @brief  This function configures system clock with HSE as clock source of the PLL
00406   * @note   The application need to ensure that PLL is disabled.
00407   * @note   Function is based on the following formula:
00408   *         - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
00409   *         - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
00410   *         - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz (PLLVCO_output = PLLVCO_input * PLLN)
00411   *         - PLLP: ensure that max frequency at 400000000 Hz is reached (PLLVCO_output / PLLP)
00412   * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
00413   * @param  HSEBypass This parameter can be one of the following values:
00414   *         @arg @ref LL_UTILS_HSEBYPASS_ON
00415   *         @arg @ref LL_UTILS_HSEBYPASS_OFF
00416   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00417   *                             the configuration information for the PLL.
00418   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00419   *                             the configuration information for the BUS prescalers.
00420   * @retval An ErrorStatus enumeration value:
00421   *          - SUCCESS: Max frequency configuration done
00422   *          - ERROR: Max frequency configuration not done
00423   */
00424 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
00425                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00426 {
00427   ErrorStatus status;
00428 #ifdef  USE_FULL_ASSERT
00429   uint32_t vcoinput_freq, vcooutput_freq;
00430 #endif
00431   uint32_t pllfreq;
00432
00433   /* Check the parameters */
00434   assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
00435   assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
00436   assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
00437   assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
00438   assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
00439   assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
00440
00441   /* Check VCO Input frequency */
00442 #ifdef  USE_FULL_ASSERT
00443   vcoinput_freq = HSEFrequency / UTILS_PLLInitStruct->PLLM;
00444 #endif
00445   assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
00446
00447   /* Check VCO output frequency */
00448 #ifdef  USE_FULL_ASSERT
00449   vcooutput_freq = LL_RCC_CalcPLLClockFreq(HSEFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1U);
00450 #endif
00451   assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
00452
00453   /* Check VCO Input/output ranges compatibility */
00454   assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
00455
00456   /* Check if one of the PLL is enabled */
00457   if(UTILS_IsPLLsReady() == SUCCESS)
00458   {
00459     /* Calculate the new PLL output frequency */
00460     pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
00461
00462     /* Enable HSE if not enabled */
00463     if(LL_RCC_HSE_IsReady() != 1U)
00464     {
00465       /* Check if need to enable HSE bypass feature or not */
00466       if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
00467       {
00468         LL_RCC_HSE_EnableBypass();
00469       }
00470       else
00471       {
00472         LL_RCC_HSE_DisableBypass();
00473       }
00474
00475       /* Enable HSE */
00476       LL_RCC_HSE_Enable();
00477       while (LL_RCC_HSE_IsReady() != 1U)
00478       {
00479         /* Wait for HSE ready */
00480       }
00481     }
00482
00483     /* Configure PLL */
00484     LL_RCC_PLL1P_Enable();
00485     LL_RCC_PLL1FRACN_Enable();
00486     LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
00487     LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
00488     LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
00489     LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM);
00490     LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN);
00491     LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP);
00492     LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
00493
00494     /* Enable PLL and switch system clock to PLL */
00495     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
00496   }
00497   else
00498   {
00499     /* Current PLL configuration cannot be modified */
00500     status = ERROR;
00501   }
00502
00503   return status;
00504 }
00505
00506 /**
00507   * @}
00508   */
00509
00510 /**
00511   * @}
00512   */
00513
00514 /** @addtogroup UTILS_LL_Private_Functions
00515   * @{
00516   */
00517
00518 /**
00519   * @brief  Calculate and check the Flash wait states number according to the
00520             new HCLK frequency and current voltage range.
00521   * @param  HCLK_Frequency  HCLK frequency
00522   * @param  latency This parameter can be one of the following values:
00523   *         @arg @ref LL_FLASH_LATENCY_0
00524   *         @arg @ref LL_FLASH_LATENCY_1
00525   *         @arg @ref LL_FLASH_LATENCY_2
00526   *         @arg @ref LL_FLASH_LATENCY_3
00527   *         @arg @ref LL_FLASH_LATENCY_4
00528   *         @arg @ref LL_FLASH_LATENCY_5
00529   *         @arg @ref LL_FLASH_LATENCY_6
00530   *         @arg @ref LL_FLASH_LATENCY_7
00531   * @retval An ErrorStatus enumeration value:
00532   *          - SUCCESS: Latency has been modified
00533   *          - ERROR: Latency cannot be modified
00534   */
00535 static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t *latency)
00536 {
00537   ErrorStatus status = SUCCESS;
00538
00539   /* Frequency cannot be equal to 0 */
00540   if(HCLK_Frequency == 0U)
00541   {
00542     status = ERROR;
00543   }
00544   else
00545   {
00546     if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
00547     {
00548       if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
00549       {
00550         /* 140 < HCLK <= 210 => 2WS (3 CPU cycles) */
00551         *latency = LL_FLASH_LATENCY_2;
00552       }
00553       else if((HCLK_Frequency > UTILS_SCALE1_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ))
00554       {
00555         /* 70 < HCLK <= 140 => 1WS (2 CPU cycles) */
00556         *latency = LL_FLASH_LATENCY_1;
00557       }
00558       else if(HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ)
00559       {
00560         /* HCLK <= 70 => 0WS (1 CPU cycles) */
00561         *latency = LL_FLASH_LATENCY_0;
00562       }
00563       else
00564       {
00565         status = ERROR;
00566       }
00567     }
00568     else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
00569     {
00570       if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ))
00571       {
00572         /* 165 < HCLK <= 220 => 3WS (4 CPU cycles) */
00573         *latency = LL_FLASH_LATENCY_3;
00574       }
00575       else if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ))
00576       {
00577         /* 110 < HCLK <= 165 => 2WS (3 CPU cycles) */
00578         *latency = LL_FLASH_LATENCY_2;
00579       }
00580       else if((HCLK_Frequency > UTILS_SCALE2_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ))
00581       {
00582         /* 55 < HCLK <= 110 => 1WS (2 CPU cycles) */
00583         *latency = LL_FLASH_LATENCY_1;
00584       }
00585       else if(HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ)
00586       {
00587         /* HCLK <= 55 => 0WS (1 CPU cycles) */
00588         *latency = LL_FLASH_LATENCY_0;
00589       }
00590       else
00591       {
00592         status = ERROR;
00593       }
00594     }
00595     else /* Scale 3 */
00596     {
00597       if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY4_FREQ))
00598       {
00599         /* 180 < HCLK <= 225 => 4WS (5 CPU cycles) */
00600         *latency = LL_FLASH_LATENCY_4;
00601       }
00602       else if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ))
00603       {
00604         /* 135 < HCLK <= 180 => 3WS (4 CPU cycles) */
00605         *latency = LL_FLASH_LATENCY_3;
00606       }
00607       else if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ))
00608       {
00609         /* 90 < HCLK <= 135 => 2WS (3 CPU cycles) */
00610         *latency = LL_FLASH_LATENCY_2;
00611       }
00612       else if((HCLK_Frequency > UTILS_SCALE3_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY1_FREQ))
00613       {
00614         /* 45 < HCLK <= 90 => 1WS (2 CPU cycles) */
00615         *latency = LL_FLASH_LATENCY_1;
00616       }
00617       else if(HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ)
00618       {
00619         /* HCLK <= 45 => 0WS (1 CPU cycles) */
00620         *latency = LL_FLASH_LATENCY_0;
00621       }
00622       else
00623       {
00624         status = ERROR;
00625       }
00626     }
00627   }
00628
00629   return status;
00630 }
00631
00632 /**
00633   * @brief  Update number of Flash wait states
00634   * @param  latency  Flash Latency
00635   * @retval An ErrorStatus enumeration value:
00636   *          - SUCCESS: Latency has been modified
00637   *          - ERROR: Latency cannot be modified
00638   */
00639 static ErrorStatus UTILS_SetFlashLatency(uint32_t latency)
00640 {
00641   ErrorStatus status = SUCCESS;
00642
00643   LL_FLASH_SetLatency(latency);
00644
00645   /* Check that the new number of wait states is taken into account to access the Flash
00646      memory by reading the FLASH_ACR register */
00647   if(LL_FLASH_GetLatency() != latency)
00648   {
00649     status = ERROR;
00650   }
00651
00652   return status;
00653 }
00654
00655 /**
00656   * @brief  Function to check that PLL can be modified
00657   * @param  PLL_InputFrequency  PLL input frequency (in Hz)
00658   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00659   *                             the configuration information for the PLL.
00660   * @retval PLL output frequency (in Hz)
00661   */
00662 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
00663 {
00664   uint32_t pllfreq;
00665
00666   /* Check the parameters */
00667   assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
00668   assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
00669   assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
00670   assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
00671
00672   pllfreq = LL_RCC_CalcPLLClockFreq(PLL_InputFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, UTILS_PLLInitStruct->PLLP);
00673
00674   return pllfreq;
00675 }
00676
00677 /**
00678   * @brief  Check that all PLLs are ready therefore configuration can be done
00679   * @retval An ErrorStatus enumeration value:
00680   *          - SUCCESS: All PLLs are ready so configuration can be done
00681   *          - ERROR: One PLL at least is busy
00682   */
00683 static ErrorStatus UTILS_IsPLLsReady(void)
00684 {
00685   ErrorStatus status = SUCCESS;
00686
00687   /* Check if one of the PLL1 is busy */
00688   if(LL_RCC_PLL1_IsReady() != 0U)
00689   {
00690     /* PLL1 configuration cannot be done */
00691     status = ERROR;
00692   }
00693
00694   /* Check if one of the PLL2 is busy */
00695   if(LL_RCC_PLL2_IsReady() != 0U)
00696   {
00697     /* PLL2 configuration cannot be done */
00698     status = ERROR;
00699   }
00700
00701   /* Check if one of the PLL3 is busy */
00702   if(LL_RCC_PLL3_IsReady() != 0U)
00703   {
00704     /* PLL3 configuration cannot be done */
00705     status = ERROR;
00706   }
00707
00708   return status;
00709 }
00710
00711 /**
00712   * @brief  Function to enable PLL and switch system clock to PLL
00713   * @param  SYSCLK_Frequency SYSCLK frequency
00714   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00715   *                             the configuration information for the BUS prescalers.
00716   * @retval An ErrorStatus enumeration value:
00717   *          - SUCCESS: No problem to switch system to PLL
00718   *          - ERROR: Problem to switch system to PLL
00719   */
00720 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00721 {
00722   ErrorStatus status;
00723   uint32_t new_hclk_frequency, new_latency;
00724
00725   assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->SYSCLKDivider));
00726   assert_param(IS_LL_UTILS_AHB_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
00727   assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
00728   assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
00729   assert_param(IS_LL_UTILS_APB3_DIV(UTILS_ClkInitStruct->APB3CLKDivider));
00730   assert_param(IS_LL_UTILS_APB4_DIV(UTILS_ClkInitStruct->APB4CLKDivider));
00731
00732   /* Calculate the new HCLK frequency */
00733   new_hclk_frequency = LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
00734
00735   /* Calculate the new FLASH latency according to the new HCLK frequency */
00736   status = UTILS_CalculateFlashLatency(new_hclk_frequency, &new_latency);
00737
00738   if(status == SUCCESS)
00739   {
00740     /* Increasing the number of wait states because of higher CPU frequency */
00741     if(LL_FLASH_GetLatency() < new_latency)
00742     {
00743       status = UTILS_SetFlashLatency(new_latency);
00744     }
00745
00746     /* Update system clock configuration */
00747     if(status == SUCCESS)
00748     {
00749       /* Enable PLL */
00750       LL_RCC_PLL1_Enable();
00751       while (LL_RCC_PLL1_IsReady() != 1U)
00752       {
00753         /* Wait for PLL ready */
00754       }
00755
00756       /* Set All APBxPrescaler to the Highest Divider */
00757       LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16);
00758       LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16);
00759       LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16);
00760       LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16);
00761
00762       /* Set SYS prescaler*/
00763       LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider);
00764
00765       /* Set AHB prescaler*/
00766       LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
00767
00768       /* Sysclk activation on the main PLL */
00769       LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
00770       while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
00771       {
00772         /* Wait for system clock switch to PLL */
00773       }
00774
00775       /* Set APBn prescaler*/
00776       LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
00777       LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
00778       LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider);
00779       LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider);
00780
00781       /* Update SystemCoreClock variable */
00782       LL_SetSystemCoreClock(SYSCLK_Frequency);
00783     }
00784
00785     /* Decreasing the number of wait states because of lower CPU frequency */
00786     if(LL_FLASH_GetLatency() > new_latency)
00787     {
00788       status = UTILS_SetFlashLatency(new_latency);
00789     }
00790   }
00791
00792   return status;
00793 }
00794
00795 /**
00796   * @}
00797   */
00798
00799 /**
00800   * @}
00801   */
00802
00803 /**
00804   * @}
00805   */
00806
00807 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM32H757xx HAL User Manual: stm32h7xx_ll_utils.h Source File

  • Drivers
  • STM32H7xx_HAL_Driver
  • Inc
stm32h7xx_ll_utils.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_utils.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UTILS LL module.
00006   @verbatim
00007   ==============================================================================
00008                      ##### How to use this driver #####
00009   ==============================================================================
00010     [..]
00011     The LL UTILS driver contains a set of generic APIs that can be
00012     used by user:
00013       (+) Device electronic signature
00014       (+) Timing functions
00015       (+) PLL configuration functions
00016
00017   @endverbatim
00018   ******************************************************************************
00019   * @attention
00020   *
00021   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00022   * All rights reserved.</center></h2>
00023   *
00024   * This software component is licensed by ST under BSD 3-Clause license,
00025   * the "License"; You may not use this file except in compliance with the
00026   * License. You may obtain a copy of the License at:
00027   *                        opensource.org/licenses/BSD-3-Clause
00028   *
00029   ******************************************************************************
00030   */
00031
00032 /* Define to prevent recursive inclusion -------------------------------------*/
00033 #ifndef STM32H7xx_LL_UTILS_H
00034 #define STM32H7xx_LL_UTILS_H
00035
00036 #ifdef __cplusplus
00037 extern "C" {
00038 #endif
00039
00040 /* Includes ------------------------------------------------------------------*/
00041 #include "stm32h7xx.h"
00042 #include "stm32h7xx_ll_system.h"
00043 #include "stm32h7xx_ll_bus.h"
00044
00045 /** @addtogroup STM32H7xx_LL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup UTILS_LL UTILS
00050   * @{
00051   */
00052
00053 /* Private types -------------------------------------------------------------*/
00054 /* Private variables ---------------------------------------------------------*/
00055
00056 /* Private constants ---------------------------------------------------------*/
00057 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
00058   * @{
00059   */
00060
00061 /* Max delay can be used in LL_mDelay */
00062 #define LL_MAX_DELAY                  0xFFFFFFFFU
00063
00064 /**
00065  * @brief Unique device ID register base address
00066  */
00067 #define UID_BASE_ADDRESS              UID_BASE
00068
00069 /**
00070  * @brief Flash size data register base address
00071  */
00072 #define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
00073
00074 /**
00075  * @brief Package data register base address
00076  */
00077 #define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
00078
00079 /**
00080   * @}
00081   */
00082
00083 /* Private macros ------------------------------------------------------------*/
00084 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
00085   * @{
00086   */
00087 /**
00088   * @}
00089   */
00090 /* Exported types ------------------------------------------------------------*/
00091 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
00092   * @{
00093   */
00094 /**
00095   * @brief  UTILS PLL structure definition
00096   */
00097 typedef struct
00098 {
00099   uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
00100                         This parameter must be a number between Min_Data = 0 and Max_Data = 63
00101
00102                         This feature can be modified afterwards using unitary function
00103                         @ref LL_RCC_PLL1_SetM(). */
00104
00105   uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
00106                         This parameter must be a number between Min_Data = 4 and Max_Data = 512
00107
00108                         This feature can be modified afterwards using unitary function
00109                         @ref LL_RCC_PLL1_SetN(). */
00110
00111   uint32_t PLLP;   /*!< Division for the main system clock.
00112                         This parameter must be a number between Min_Data = 2 and Max_Data = 128
00113                           odd division factors are not allowed
00114
00115                         This feature can be modified afterwards using unitary function
00116                         @ref LL_RCC_PLL1_SetP(). */
00117
00118   uint32_t FRACN;  /*!< Fractional part of the multiplication factor for PLL VCO.
00119                         This parameter can be a value between 0 and 8191
00120
00121                         This feature can be modified afterwards using unitary function
00122                         @ref LL_RCC_PLL1_SetFRACN(). */
00123
00124   uint32_t VCO_Input;  /*!< Fractional part of the multiplication factor for PLL VCO.
00125                         This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE
00126
00127                         This feature can be modified afterwards using unitary function
00128                         @ref LL_RCC_PLL1_SetVCOInputRange(). */
00129
00130   uint32_t VCO_Output;  /*!< Fractional part of the multiplication factor for PLL VCO.
00131                         This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE
00132
00133                       This feature can be modified afterwards using unitary function
00134                       @ref LL_RCC_PLL1_SetVCOOutputRange(). */
00135
00136 } LL_UTILS_PLLInitTypeDef;
00137
00138 /**
00139   * @brief  UTILS System, AHB and APB buses clock configuration structure definition
00140   */
00141 typedef struct
00142 {
00143   uint32_t SYSCLKDivider;         /*!< The System clock (SYSCLK) divider. This clock is derived from the PLL output.
00144                                      This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
00145
00146                                      This feature can be modified afterwards using unitary function
00147                                      @ref LL_RCC_SetSysPrescaler(). */
00148
00149   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
00150                                        This parameter can be a value of @ref RCC_LL_EC_AHB_DIV
00151
00152                                        This feature can be modified afterwards using unitary function
00153                                        @ref LL_RCC_SetAHBPrescaler(). */
00154
00155   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00156                                        This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
00157
00158                                        This feature can be modified afterwards using unitary function
00159                                        @ref LL_RCC_SetAPB1Prescaler(). */
00160
00161   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
00162                                        This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
00163
00164                                        This feature can be modified afterwards using unitary function
00165                                        @ref LL_RCC_SetAPB2Prescaler(). */
00166
00167   uint32_t APB3CLKDivider;        /*!< The APB2 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK).
00168                                        This parameter can be a value of @ref RCC_LL_EC_APB3_DIV
00169
00170                                        This feature can be modified afterwards using unitary function
00171                                        @ref LL_RCC_SetAPB3Prescaler(). */
00172
00173   uint32_t APB4CLKDivider;        /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK).
00174                                        This parameter can be a value of @ref RCC_LL_EC_APB4_DIV
00175
00176                                        This feature can be modified afterwards using unitary function
00177                                        @ref LL_RCC_SetAPB4Prescaler(). */
00178
00179 } LL_UTILS_ClkInitTypeDef;
00180
00181 /**
00182   * @}
00183   */
00184
00185 /* Exported constants --------------------------------------------------------*/
00186 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
00187   * @{
00188   */
00189
00190 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
00191   * @{
00192   */
00193 #define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
00194 #define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
00200   * @{
00201   */
00202 #define LL_UTILS_PACKAGETYPE_LQFP100            LL_SYSCFG_LQFP100_PACKAGE          /*!< LQFP100 package type             */
00203 #define LL_UTILS_PACKAGETYPE_TQFP144            LL_SYSCFG_TQFP144_PACKAGE          /*!< TQFP144 package type             */
00204 #define LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176   LL_SYSCFG_TQFP176_UFBGA176_PACKAGE /*!< TQFP176 or UFBGA176 package type */
00205 #define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240   LL_SYSCFG_LQFP208_TFBGA240_PACKAGE /*!< LQFP208 or TFBGA240 package type */
00206 /**
00207   * @}
00208   */
00209
00210 /**
00211   * @}
00212   */
00213
00214 /* Exported macro ------------------------------------------------------------*/
00215
00216 /* Exported functions --------------------------------------------------------*/
00217 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
00218   * @{
00219   */
00220
00221 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
00222   * @{
00223   */
00224
00225 /**
00226   * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
00227   * @retval UID[31:0]
00228   */
00229 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
00230 {
00231   return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
00232 }
00233
00234 /**
00235   * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
00236   * @retval UID[63:32]
00237   */
00238 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
00239 {
00240   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
00241 }
00242
00243 /**
00244   * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
00245   * @retval UID[95:64]
00246   */
00247 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
00248 {
00249   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
00250 }
00251
00252 /**
00253   * @brief  Get Flash memory size
00254   * @note   This bitfield indicates the size of the device Flash memory expressed in
00255   *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
00256   * @retval FLASH_SIZE[15:0]: Flash memory size
00257   */
00258 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
00259 {
00260   return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
00261 }
00262
00263 /**
00264   * @brief  Get Package type
00265   * @retval Returned value can be one of the following values:
00266   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
00267   *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP144
00268   *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176
00269   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240
00270   */
00271 __STATIC_INLINE uint32_t LL_GetPackageType(void)
00272 {
00273
00274   LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG);
00275
00276   return LL_SYSCFG_GetPackage();
00277 }
00278
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup UTILS_LL_EF_DELAY DELAY
00284   * @{
00285   */
00286
00287 /**
00288   * @brief  This function configures the Cortex-M SysTick source of the time base.
00289   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
00290   * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
00291   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00292   * @param  Ticks Number of ticks
00293   * @retval None
00294   */
00295 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
00296 {
00297   /* Configure the SysTick to have interrupt in 1ms time base */
00298   SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
00299   SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
00300   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
00301                    SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
00302 }
00303
00304 void        LL_Init1msTick(uint32_t CPU_Frequency);
00305 void        LL_mDelay(uint32_t Delay);
00306
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup UTILS_EF_SYSTEM SYSTEM
00312   * @{
00313   */
00314
00315 void        LL_SetSystemCoreClock(uint32_t CPU_Frequency);
00316 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00317                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00318 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,
00319                                          uint32_t HSEBypass,
00320                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00321                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00322
00323 /**
00324   * @}
00325   */
00326
00327 /**
00328   * @}
00329   */
00330
00331 /**
00332   * @}
00333   */
00334
00335 /**
00336   * @}
00337   */
00338
00339 #ifdef __cplusplus
00340 }
00341 #endif
00342
00343 #endif /* STM32H7xx_LL_UTILS_H */
00344
00345 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


STM32H757xx HAL User Manual: stm32h7xx_ll_wwdg.h Source File

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stm32h7xx_ll_wwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32h7xx_ll_wwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of WWDG LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32H7xx_LL_WWDG_H
00022 #define STM32H7xx_LL_WWDG_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32h7xx.h"
00030
00031 /** @addtogroup STM32H7xx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (WWDG1) || defined (WWDG2)
00036
00037 /** @defgroup WWDG_LL WWDG
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 /* Exported types ------------------------------------------------------------*/
00046 /* Exported constants --------------------------------------------------------*/
00047 /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
00048   * @{
00049   */
00050
00051 /** @defgroup WWDG_LL_EC_IT IT Defines
00052   * @brief    IT defines which can be used with LL_WWDG_ReadReg and  LL_WWDG_WriteReg functions
00053   * @{
00054   */
00055 #define LL_WWDG_CFR_EWI                     WWDG_CFR_EWI
00056 /**
00057   * @}
00058   */
00059
00060 /** @defgroup WWDG_LL_EC_PRESCALER  PRESCALER
00061 * @{
00062 */
00063 #define LL_WWDG_PRESCALER_1                 0x00000000u                                               /*!< WWDG counter clock = (PCLK1/4096)/1 */
00064 #define LL_WWDG_PRESCALER_2                 WWDG_CFR_WDGTB_0                                          /*!< WWDG counter clock = (PCLK1/4096)/2 */
00065 #define LL_WWDG_PRESCALER_4                 WWDG_CFR_WDGTB_1                                          /*!< WWDG counter clock = (PCLK1/4096)/4 */
00066 #define LL_WWDG_PRESCALER_8                 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)                     /*!< WWDG counter clock = (PCLK1/4096)/8 */
00067 #define LL_WWDG_PRESCALER_16                WWDG_CFR_WDGTB_2                                          /*!< WWDG counter clock = (PCLK1/4096)/16 */
00068 #define LL_WWDG_PRESCALER_32                (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)                     /*!< WWDG counter clock = (PCLK1/4096)/32 */
00069 #define LL_WWDG_PRESCALER_64                (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)                     /*!< WWDG counter clock = (PCLK1/4096)/64 */
00070 #define LL_WWDG_PRESCALER_128               (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)  /*!< WWDG counter clock = (PCLK1/4096)/128 */
00071 /**
00072   * @}
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /* Exported macro ------------------------------------------------------------*/
00080 /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
00081   * @{
00082   */
00083 /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
00084   * @{
00085   */
00086 /**
00087   * @brief  Write a value in WWDG register
00088   * @param  __INSTANCE__ WWDG Instance
00089   * @param  __REG__ Register to be written
00090   * @param  __VALUE__ Value to be written in the register
00091   * @retval None
00092   */
00093 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00094
00095 /**
00096   * @brief  Read a value in WWDG register
00097   * @param  __INSTANCE__ WWDG Instance
00098   * @param  __REG__ Register to be read
00099   * @retval Register value
00100   */
00101 #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00102 /**
00103   * @}
00104   */
00105
00106 /**
00107   * @}
00108   */
00109
00110 /* Exported functions --------------------------------------------------------*/
00111 /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
00112   * @{
00113   */
00114
00115 /** @defgroup WWDG_LL_EF_Configuration Configuration
00116   * @{
00117   */
00118 /**
00119   * @brief  Enable Window Watchdog. The watchdog is always disabled after a reset.
00120   * @note   It is enabled by setting the WDGA bit in the WWDG_CR register,
00121   *         then it cannot be disabled again except by a reset.
00122   *         This bit is set by software and only cleared by hardware after a reset.
00123   *         When WDGA = 1, the watchdog can generate a reset.
00124   * @rmtoll CR           WDGA          LL_WWDG_Enable
00125   * @param  WWDGx WWDG Instance
00126   * @retval None
00127   */
00128 __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
00129 {
00130   SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
00131 }
00132
00133 /**
00134   * @brief  Checks if Window Watchdog is enabled
00135   * @rmtoll CR           WDGA          LL_WWDG_IsEnabled
00136   * @param  WWDGx WWDG Instance
00137   * @retval State of bit (1 or 0).
00138   */
00139 __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
00140 {
00141   return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
00142 }
00143
00144 /**
00145   * @brief  Set the Watchdog counter value to provided value (7-bits T[6:0])
00146   * @note   When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
00147   *         This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
00148   *         A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
00149   *         Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
00150   * @rmtoll CR           T             LL_WWDG_SetCounter
00151   * @param  WWDGx WWDG Instance
00152   * @param  Counter 0..0x7F (7 bit counter value)
00153   * @retval None
00154   */
00155 __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
00156 {
00157   MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
00158 }
00159
00160 /**
00161   * @brief  Return current Watchdog Counter Value (7 bits counter value)
00162   * @rmtoll CR           T             LL_WWDG_GetCounter
00163   * @param  WWDGx WWDG Instance
00164   * @retval 7 bit Watchdog Counter value
00165   */
00166 __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
00167 {
00168   return (READ_BIT(WWDGx->CR, WWDG_CR_T));
00169 }
00170
00171 /**
00172   * @brief  Set the time base of the prescaler (WDGTB).
00173   * @note   Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
00174   *         is decremented every (4096 x 2expWDGTB) PCLK cycles
00175   * @rmtoll CFR          WDGTB         LL_WWDG_SetPrescaler
00176   * @param  WWDGx WWDG Instance
00177   * @param  Prescaler This parameter can be one of the following values:
00178   *         @arg @ref LL_WWDG_PRESCALER_1
00179   *         @arg @ref LL_WWDG_PRESCALER_2
00180   *         @arg @ref LL_WWDG_PRESCALER_4
00181   *         @arg @ref LL_WWDG_PRESCALER_8
00182   *         @arg @ref LL_WWDG_PRESCALER_16
00183   *         @arg @ref LL_WWDG_PRESCALER_32
00184   *         @arg @ref LL_WWDG_PRESCALER_64
00185   *         @arg @ref LL_WWDG_PRESCALER_128
00186 * @retval None
00187   */
00188 __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
00189 {
00190   MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
00191 }
00192
00193 /**
00194   * @brief  Return current Watchdog Prescaler Value
00195   * @rmtoll CFR          WDGTB         LL_WWDG_GetPrescaler
00196   * @param  WWDGx WWDG Instance
00197   * @retval Returned value can be one of the following values:
00198   *         @arg @ref LL_WWDG_PRESCALER_1
00199   *         @arg @ref LL_WWDG_PRESCALER_2
00200   *         @arg @ref LL_WWDG_PRESCALER_4
00201   *         @arg @ref LL_WWDG_PRESCALER_8
00202   *         @arg @ref LL_WWDG_PRESCALER_16
00203   *         @arg @ref LL_WWDG_PRESCALER_32
00204   *         @arg @ref LL_WWDG_PRESCALER_64
00205   *         @arg @ref LL_WWDG_PRESCALER_128
00206   */
00207 __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
00208 {
00209   return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
00210 }
00211
00212 /**
00213   * @brief  Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
00214   * @note   This window value defines when write in the WWDG_CR register
00215   *         to program Watchdog counter is allowed.
00216   *         Watchdog counter value update must occur only when the counter value
00217   *         is lower than the Watchdog window register value.
00218   *         Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
00219   *         (in the control register) is refreshed before the downcounter has reached
00220   *         the watchdog window register value.
00221   *         Physically is possible to set the Window lower then 0x40 but it is not recommended.
00222   *         To generate an immediate reset, it is possible to set the Counter lower than 0x40.
00223   * @rmtoll CFR          W             LL_WWDG_SetWindow
00224   * @param  WWDGx WWDG Instance
00225   * @param  Window 0x00..0x7F (7 bit Window value)
00226   * @retval None
00227   */
00228 __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
00229 {
00230   MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
00231 }
00232
00233 /**
00234   * @brief  Return current Watchdog Window Value (7 bits value)
00235   * @rmtoll CFR          W             LL_WWDG_GetWindow
00236   * @param  WWDGx WWDG Instance
00237   * @retval 7 bit Watchdog Window value
00238   */
00239 __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
00240 {
00241   return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
00242 }
00243
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
00249   * @{
00250   */
00251 /**
00252   * @brief  Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
00253   * @note   This bit is set by hardware when the counter has reached the value 0x40.
00254   *         It must be cleared by software by writing 0.
00255   *         A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
00256   * @rmtoll SR           EWIF          LL_WWDG_IsActiveFlag_EWKUP
00257   * @param  WWDGx WWDG Instance
00258   * @retval State of bit (1 or 0).
00259   */
00260 __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
00261 {
00262   return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
00263 }
00264
00265 /**
00266   * @brief  Clear WWDG Early Wakeup Interrupt Flag (EWIF)
00267   * @rmtoll SR           EWIF          LL_WWDG_ClearFlag_EWKUP
00268   * @param  WWDGx WWDG Instance
00269   * @retval None
00270   */
00271 __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
00272 {
00273   WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
00274 }
00275
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup WWDG_LL_EF_IT_Management IT_Management
00281   * @{
00282   */
00283 /**
00284   * @brief  Enable the Early Wakeup Interrupt.
00285   * @note   When set, an interrupt occurs whenever the counter reaches value 0x40.
00286   *         This interrupt is only cleared by hardware after a reset
00287   * @rmtoll CFR          EWI           LL_WWDG_EnableIT_EWKUP
00288   * @param  WWDGx WWDG Instance
00289   * @retval None
00290   */
00291 __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
00292 {
00293   SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
00294 }
00295
00296 /**
00297   * @brief  Check if Early Wakeup Interrupt is enabled
00298   * @rmtoll CFR          EWI           LL_WWDG_IsEnabledIT_EWKUP
00299   * @param  WWDGx WWDG Instance
00300   * @retval State of bit (1 or 0).
00301   */
00302 __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
00303 {
00304   return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
00305 }
00306
00307 /**
00308   * @}
00309   */
00310
00311 /**
00312   * @}
00313   */
00314
00315 /**
00316   * @}
00317   */
00318
00319 #endif /* WWDG1 || WWDG2 */
00320
00321 /**
00322   * @}
00323   */
00324
00325 #ifdef __cplusplus
00326 }
00327 #endif
00328
00329 #endif /* __STM32H7xx_LL_WWDG_H */
00330
00331 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


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