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Fix for assertion error when expanding macro.
[iverilog.git] / tgt-vvp / vvp.conf.in
blob2dbe4a66b9dc6fc4e5c2c97ad5c767ee3aea2787
1 functor:cprop
2 functor:nodangle
3 -t:dll
4 flag:DLL=vvp.tgt
Icarus Verilog