From af5c1d462c0dabb39a0815d11469211d576d2918 Mon Sep 17 00:00:00 2001
From: Dirk Steinke <steinke.dirk.ml@gmail.com>
Date: Fri, 1 Aug 2014 14:00:09 +0200
Subject: [PATCH] Added a test for checking addressing modes.

---
 include/jitcs_memref.h          |  2 +-
 makefile                        |  2 +-
 src/x86/src/x86_xx_codegen.lcpp |  6 ++++++
 tests/test_allinstructions.cpp  |  1 +
 tests/test_asm_x86_xx_ext.lcpp  |  3 ++-
 tests/x86/x86_addrmode.ins      | 19 +++++++++++++++++++
 6 files changed, 30 insertions(+), 3 deletions(-)
 create mode 100644 tests/x86/x86_addrmode.ins

diff --git a/include/jitcs_memref.h b/include/jitcs_memref.h
index 2905f4f..e5bb799 100644
--- a/include/jitcs_memref.h
+++ b/include/jitcs_memref.h
@@ -76,7 +76,7 @@ struct MemoryReference : MemData {
   }
 
   MMode getMode() const { return static_cast<MMode>(modeAndScale &  MMODE_Mask); }
-  int getScale() const { return modeAndScale >> MMODE_Mask; }
+  int getScale() const { return modeAndScale >> MMODE_Bits; }
   int getOffset() const { return offset; }
   RefOrNull<const VirtualRegister> getBaseReg() const  { return regs.base; }
   RefOrNull<const VirtualRegister> getIndexReg() const { return regs.index; }
diff --git a/makefile b/makefile
index df35241..92bf5bb 100644
--- a/makefile
+++ b/makefile
@@ -29,7 +29,7 @@ X86_INS = x86_arith.ins x86_mov_set.ins x86_other.ins x86_other_vex.ins \
 		x86_simd_insext.ins x86_simd_mov.ins x86_simd_shuffle.ins\
 		x86_simd_arith_vex.ins x86_simd_blend_vex.ins x86_simd_cvt_vex.ins \
 		x86_simd_insext_vex.ins x86_simd_mov_vex.ins x86_simd_shuffle_vex.ins \
-		x86_cf.ins
+		x86_cf.ins x86_addrmode.ins
 PREFIXES_LIBSRC = dbg32_ rel32_ dbg64_ rel64_
 PREFIXES_TESTSRC = test32_ test64_ testd32_ testd64_
 OBJDIR = _objs
diff --git a/src/x86/src/x86_xx_codegen.lcpp b/src/x86/src/x86_xx_codegen.lcpp
index b31a0e7..6f5bab0 100644
--- a/src/x86/src/x86_xx_codegen.lcpp
+++ b/src/x86/src/x86_xx_codegen.lcpp
@@ -387,6 +387,12 @@ static jitcs::u8* _X86_%(N)CodeRM
       jitcs::RefOrNull<const jitcs::VirtualRegister> base = mp->getBaseReg();
       jitcs::RefOrNull<const jitcs::VirtualRegister> ix = mp->getIndexReg();
       jitcs::RegId baseid = base._ptr->id;
+//printf("coderm: base %d, index %d, scale %d, offset %d\n", 
+//       base.isNull() ? 0 : base.removeNullType()->id,
+//       ix.isNull() ? 0 : ix.removeNullType()->id,
+//       mp->getScale(),
+//       ofs);
+     
       if (!ix.isNull()) {
         jitcs::RegId ixid = ix.removeNullType()->id;
         if (ofs != 0 || (baseid & 7) == (jitcs::x86_%(N)::R_RBP & 7))
diff --git a/tests/test_allinstructions.cpp b/tests/test_allinstructions.cpp
index 37244b2..369aa5c 100644
--- a/tests/test_allinstructions.cpp
+++ b/tests/test_allinstructions.cpp
@@ -44,6 +44,7 @@ static void test(UnitTest& t) {
     x86as_files.push_back("simd_insext_vex");
     x86as_files.push_back("simd_shuffle_vex");
     x86as_files.push_back("cf");
+    x86as_files.push_back("addrmode");
 
     std::unordered_set<u32> allins;
     std::unordered_set<u32> allins_compressed;
diff --git a/tests/test_asm_x86_xx_ext.lcpp b/tests/test_asm_x86_xx_ext.lcpp
index ed4f12a..6bb02a3 100644
--- a/tests/test_asm_x86_xx_ext.lcpp
+++ b/tests/test_asm_x86_xx_ext.lcpp
@@ -145,6 +145,7 @@ bool TestAssemblerX86_%(N)::makeMemRef
       summands.push_back("-" + p2);
     }
   }
+
   if (summands.size() < 1 || summands.size() > 3) return false;
   // sp + o
   // fp1..7 + o
@@ -191,7 +192,7 @@ bool TestAssemblerX86_%(N)::makeMemRef
     }
   }
   if (ix < summands.size()) {
-    if (!makei32(offset, summands[1])) return false;
+    if (!makei32(offset, summands[ix])) return false;
     ++ix;
   }
   if (ix != summands.size()) return false;
diff --git a/tests/x86/x86_addrmode.ins b/tests/x86/x86_addrmode.ins
new file mode 100644
index 0000000..1c79151
--- /dev/null
+++ b/tests/x86/x86_addrmode.ins
@@ -0,0 +1,19 @@
+  mov{_wm} eax, [RAX]
+  mov{_wm} eax, [RAX + 8]
+  mov{_wm} eax, [RAX + 200]
+  
+  mov{_wm} eax, [RAX + RBX]
+  mov{_wm} eax, [RAX + RBX + 8]
+  mov{_wm} eax, [RAX + RBX + 200]
+  mov{_wm} eax, [RAX + RBX * 2]
+  mov{_wm} eax, [RAX + RBX * 2 + 8]
+  mov{_wm} eax, [RAX + RBX * 2+  200]
+  mov{_wm} eax, [RAX + RBX * 4]
+  mov{_wm} eax, [RAX + RBX * 4 + 8]
+  mov{_wm} eax, [RAX + RBX * 4+  200]
+  mov{_wm} eax, [RAX + RBX * 8]
+  mov{_wm} eax, [RAX + RBX * 8 + 8]
+  mov{_wm} eax, [RAX + RBX * 8+  200]
+  mov{_wm} eax, [RAX + 8 * RBX]
+  mov{_wm} eax, [RAX + 8 * RBX + 8]
+  mov{_wm} eax, [RAX + 8 * RBX +  200]
-- 
2.11.4.GIT