firmware/include/asm/assembler.h

   1 /*
   2  *  linux/include/asm-arm/assembler.h
   3  *
   4  *  Copyright (C) 1996-2000 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  This file contains arm architecture specific defines
  11  *  for the different processors.
  12  *
  13  *  Do not include any C declarations in this file - it is included by
  14  *  assembler source.
  15  */
  16 #ifndef __ASSEMBLY__
  17 #error "Only include this from assembly code"
  18 #endif
  19
  20 #include <asm/ptrace.h>
  21
  22 #define pull            lsl
  23 #define push            lsr
  24 #define get_byte_0      lsr #24
  25 #define get_byte_1      lsr #16
  26 #define get_byte_2      lsr #8
  27 #define get_byte_3      lsl #0
  28 #define put_byte_0      lsl #24
  29 #define put_byte_1      lsl #16
  30 #define put_byte_2      lsl #8
  31 #define put_byte_3      lsl #0
  32
  33 #define PLD(code...)
  34
  35 #define MODE_USR        USR_MODE
  36 #define MODE_FIQ        FIQ_MODE
  37 #define MODE_IRQ        IRQ_MODE
  38 #define MODE_SVC        SVC_MODE
  39
  40 #define DEFAULT_FIQ     MODE_FIQ
  41
  42 /*
  43  * LOADREGS - ldm with PC in register list (eg, ldmfd sp!, {pc})
  44  */
  45 #ifdef __STDC__
  46 #define LOADREGS(cond, base, reglist...)\
  47         ldm##cond       base,reglist
  48 #else
  49 #define LOADREGS(cond, base, reglist...)\
  50         ldm/**/cond     base,reglist
  51 #endif
  52
  53 /*
  54  * Build a return instruction for this processor type.
  55  */
  56 #define RETINSTR(instr, regs...)\
  57         instr   regs
  58
  59 /*
  60  * Enable and disable interrupts
  61  */
  62         .macro  disable_irq
  63         msr     cpsr_c, #PSR_I_BIT | SVC_MODE
  64         .endm
  65
  66         .macro  enable_irq
  67         msr     cpsr_c, #SVC_MODE
  68         .endm
  69
  70 /*
  71  * Save the current IRQ state and disable IRQs.  Note that this macro
  72  * assumes FIQs are enabled, and that the processor is in SVC mode.
  73  */
  74         .macro  save_and_disable_irqs, oldcpsr
  75         mrs     \oldcpsr, cpsr
  76         disable_irq
  77         .endm
  78
  79 /*
  80  * Restore interrupt state previously stored in a register.  We don't
  81  * guarantee that this will preserve the flags.
  82  */
  83         .macro  restore_irqs, oldcpsr
  84         msr     cpsr_c, \oldcpsr
  85         .endm
  86
  87 /*
  88  * These two are used to save LR/restore PC over a user-based access.
  89  * The old 26-bit architecture requires that we do.  On 32-bit
  90  * architecture, we can safely ignore this requirement.
  91  */
  92         .macro  save_lr
  93         .endm
  94
  95         .macro  restore_pc
  96         mov     pc, lr
  97         .endm