qemu/target-cris/helper.c

   1 /*
   2  *  CRIS helper routines.
   3  *
   4  *  Copyright (c) 2007 AXIS Communications AB
   5  *  Written by Edgar E. Iglesias.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <stdio.h>
  23 #include <string.h>
  24
  25 #include "config.h"
  26 #include "cpu.h"
  27 #include "mmu.h"
  28 #include "exec-all.h"
  29 #include "host-utils.h"
  30
  31 #if defined(CONFIG_USER_ONLY)
  32
  33 void do_interrupt (CPUState *env)
  34 {
  35         env->exception_index = -1;
  36         env->pregs[PR_ERP] = env->pc;
  37 }
  38
  39 int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
  40                              int mmu_idx, int is_softmmu)
  41 {
  42         env->exception_index = 0xaa;
  43         env->debug1 = address;
  44         cpu_dump_state(env, stderr, fprintf, 0);
  45         env->pregs[PR_ERP] = env->pc;
  46         return 1;
  47 }
  48
  49 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
  50 {
  51         return addr;
  52 }
  53
  54 #else /* !CONFIG_USER_ONLY */
  55
  56 int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
  57                                int mmu_idx, int is_softmmu)
  58 {
  59         struct cris_mmu_result_t res;
  60         int prot, miss;
  61         target_ulong phy;
  62
  63         address &= TARGET_PAGE_MASK;
  64         prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
  65         miss = cris_mmu_translate(&res, env, address, rw, mmu_idx);
  66         if (miss)
  67         {
  68                 /* handle the miss.  */
  69                 phy = 0;
  70                 env->exception_index = EXCP_MMU_MISS;
  71         }
  72         else
  73         {
  74                 phy = res.phy;
  75         }
  76         return tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu);
  77 }
  78
  79
  80 static void cris_shift_ccs(CPUState *env)
  81 {
  82         uint32_t ccs;
  83         /* Apply the ccs shift.  */
  84         ccs = env->pregs[PR_CCS];
  85         ccs = (ccs & 0xc0000000) | ((ccs << 12) >> 2);
  86         env->pregs[PR_CCS] = ccs;
  87 }
  88
  89 void do_interrupt(CPUState *env)
  90 {
  91         uint32_t ebp, isr;
  92         int irqnum;
  93
  94         fflush(NULL);
  95
  96 #if 0
  97         printf ("exception index=%d interrupt_req=%d\n",
  98                 env->exception_index,
  99                 env->interrupt_request);
 100 #endif
 101
 102         switch (env->exception_index)
 103         {
 104                 case EXCP_BREAK:
 105                         irqnum = env->trapnr;
 106                         ebp = env->pregs[PR_EBP];
 107                         isr = ldl_code(ebp + irqnum * 4);
 108                         env->pregs[PR_ERP] = env->pc + 2;
 109                         env->pc = isr;
 110
 111                         cris_shift_ccs(env);
 112
 113                         break;
 114                 case EXCP_MMU_MISS:
 115                         irqnum = 4;
 116                         ebp = env->pregs[PR_EBP];
 117                         isr = ldl_code(ebp + irqnum * 4);
 118                         env->pregs[PR_ERP] = env->pc;
 119                         env->pc = isr;
 120                         cris_shift_ccs(env);
 121                         break;
 122
 123                 default:
 124                 {
 125                         /* Maybe the irq was acked by sw before we got a
 126                            change to take it.  */
 127                         if (env->interrupt_request & CPU_INTERRUPT_HARD) {
 128                                 if (!env->pending_interrupts)
 129                                         return;
 130                                 if (!(env->pregs[PR_CCS] & I_FLAG)) {
 131                                         return;
 132                                 }
 133
 134                                 irqnum = 31 - clz32(env->pending_interrupts);
 135                                 irqnum += 0x30;
 136                                 ebp = env->pregs[PR_EBP];
 137                                 isr = ldl_code(ebp + irqnum * 4);
 138                                 env->pregs[PR_ERP] = env->pc;
 139                                 env->pc = isr;
 140
 141                                 cris_shift_ccs(env);
 142 #if 0
 143                                 printf ("%s ebp=%x %x isr=%x %d"
 144                                         " ir=%x pending=%x\n",
 145                                         __func__,
 146                                         ebp, ebp + irqnum * 4,
 147                                         isr, env->exception_index,
 148                                         env->interrupt_request,
 149                                         env->pending_interrupts);
 150 #endif
 151                         }
 152
 153                 }
 154                 break;
 155         }
 156 }
 157
 158 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
 159 {
 160         uint32_t phy = addr;
 161         struct cris_mmu_result_t res;
 162         int miss;
 163         miss = cris_mmu_translate(&res, env, addr, 0, 0);
 164         if (!miss)
 165                 phy = res.phy;
 166         return phy;
 167 }
 168 #endif