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kvm: qemu: Fix compile error in non-x86 arch
[kvm-userspace.git] / qemu / vl.h
blob01aeabcaecb778a19df89277a75790969cb3f071
1 /*
2 * QEMU System Emulator header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #ifndef VL_H
25 #define VL_H
26
27 /* we put basic includes here to avoid repeating them in device drivers */
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <stdarg.h>
31 #include <string.h>
32 #include <inttypes.h>
33 #include <limits.h>
34 #include <time.h>
35 #include <ctype.h>
36 #include <errno.h>
37 #include <unistd.h>
38 #include <fcntl.h>
39 #include <sys/stat.h>
40
41 #ifndef O_LARGEFILE
42 #define O_LARGEFILE 0
43 #endif
44 #ifndef O_BINARY
45 #define O_BINARY 0
46 #endif
47
48 #ifndef ENOMEDIUM
49 #define ENOMEDIUM ENODEV
50 #endif
51
52 #ifdef _WIN32
53 #include <windows.h>
54 #define fsync _commit
55 #define lseek _lseeki64
56 #define ENOTSUP 4096
57 extern int qemu_ftruncate64(int, int64_t);
58 #define ftruncate qemu_ftruncate64
59
60
61 static inline char *realpath(const char *path, char *resolved_path)
62 {
63 _fullpath(resolved_path, path, _MAX_PATH);
64 return resolved_path;
65 }
66
67 #define PRId64 "I64d"
68 #define PRIx64 "I64x"
69 #define PRIu64 "I64u"
70 #define PRIo64 "I64o"
71 #endif
72
73 #ifdef QEMU_TOOL
74
75 /* we use QEMU_TOOL in the command line tools which do not depend on
76 the target CPU type */
77 #include "config-host.h"
78 #include <setjmp.h>
79 #include "osdep.h"
80 #include "bswap.h"
81
82 #else
83
84 #include "audio/audio.h"
85 #include "cpu.h"
86
87 #endif /* !defined(QEMU_TOOL) */
88
89 #ifndef glue
90 #define xglue(x, y) x ## y
91 #define glue(x, y) xglue(x, y)
92 #define stringify(s) tostring(s)
93 #define tostring(s) #s
94 #endif
95
96 #ifndef likely
97 #if __GNUC__ < 3
98 #define __builtin_expect(x, n) (x)
99 #endif
100
101 #define likely(x) __builtin_expect(!!(x), 1)
102 #define unlikely(x) __builtin_expect(!!(x), 0)
103 #endif
104
105 #ifndef MIN
106 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
107 #endif
108 #ifndef MAX
109 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
110 #endif
111
112 #ifndef always_inline
113 #if (__GNUC__ < 3) || defined(__APPLE__)
114 #define always_inline inline
115 #else
116 #define always_inline __attribute__ (( always_inline )) inline
117 #endif
118 #endif
119
120 /* cutils.c */
121 void pstrcpy(char *buf, int buf_size, const char *str);
122 char *pstrcat(char *buf, int buf_size, const char *s);
123 int strstart(const char *str, const char *val, const char **ptr);
124 int stristart(const char *str, const char *val, const char **ptr);
125 int hex2bin(char ch);
126 char *urldecode(const char *ptr);
127
128 /* vl.c */
129 void qemu_get_launch_info(int *argc, char ***argv, int *opt_daemonize, const char **opt_incoming);
130
131 uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
132
133 void hw_error(const char *fmt, ...);
134
135 extern const char *bios_dir;
136
137 extern int vm_running;
138 extern const char *qemu_name;
139
140 typedef struct vm_change_state_entry VMChangeStateEntry;
141 typedef void VMChangeStateHandler(void *opaque, int running);
142 typedef void VMStopHandler(void *opaque, int reason);
143
144 VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
145 void *opaque);
146 void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
147
148 int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
149 void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
150
151 void vm_start(void);
152 void vm_stop(int reason);
153
154 typedef void QEMUResetHandler(void *opaque);
155
156 void qemu_register_reset(QEMUResetHandler *func, void *opaque);
157 void qemu_system_reset(void);
158 void qemu_system_reset_request(void);
159 void qemu_system_shutdown_request(void);
160 void qemu_system_powerdown_request(void);
161 int qemu_shutdown_requested(void);
162 int qemu_reset_requested(void);
163 int qemu_powerdown_requested(void);
164
165 #if !defined(TARGET_SPARC)
166 // Please implement a power failure function to signal the OS
167 #define qemu_system_powerdown() do{}while(0)
168 #else
169 void qemu_system_powerdown(void);
170 #endif
171
172 void main_loop_wait(int timeout);
173
174 extern int64_t ram_size;
175 extern int bios_size;
176 extern int rtc_utc;
177 extern int cirrus_vga_enabled;
178 extern int vmsvga_enabled;
179 extern int graphic_width;
180 extern int graphic_height;
181 extern int graphic_depth;
182 extern const char *keyboard_layout;
183 extern int kqemu_allowed;
184 extern int kvm_allowed;
185 extern int kvm_irqchip;
186 extern int win2k_install_hack;
187 extern int alt_grab;
188 extern int usb_enabled;
189 extern int smp_cpus;
190 extern int cursor_hide;
191 extern int graphic_rotate;
192 extern int no_quit;
193 extern int semihosting_enabled;
194 extern int autostart;
195 extern int time_drift_fix;
196 extern int old_param;
197 extern const char *bootp_filename;
198
199 #define MAX_OPTION_ROMS 16
200 extern const char *option_rom[MAX_OPTION_ROMS];
201 extern int nb_option_roms;
202
203 #ifdef TARGET_SPARC
204 #define MAX_PROM_ENVS 128
205 extern const char *prom_envs[MAX_PROM_ENVS];
206 extern unsigned int nb_prom_envs;
207 #endif
208
209 /* XXX: make it dynamic */
210 #define MAX_BIOS_SIZE (4 * 1024 * 1024)
211 #if defined (TARGET_PPC) || defined (TARGET_SPARC64)
212 #define BIOS_SIZE ((512 + 32) * 1024)
213 #elif defined(TARGET_MIPS)
214 #define BIOS_SIZE (4 * 1024 * 1024)
215 #endif
216
217 #if USE_KVM
218 #define KVM_EXTRA_PAGES 3
219 #endif
220
221 /* keyboard/mouse support */
222
223 #define MOUSE_EVENT_LBUTTON 0x01
224 #define MOUSE_EVENT_RBUTTON 0x02
225 #define MOUSE_EVENT_MBUTTON 0x04
226
227 typedef void QEMUPutKBDEvent(void *opaque, int keycode);
228 typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
229
230 typedef struct QEMUPutMouseEntry {
231 QEMUPutMouseEvent *qemu_put_mouse_event;
232 void *qemu_put_mouse_event_opaque;
233 int qemu_put_mouse_event_absolute;
234 char *qemu_put_mouse_event_name;
235
236 /* used internally by qemu for handling mice */
237 struct QEMUPutMouseEntry *next;
238 } QEMUPutMouseEntry;
239
240 void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
241 QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
242 void *opaque, int absolute,
243 const char *name);
244 void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
245
246 void kbd_put_keycode(int keycode);
247 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
248 int kbd_mouse_is_absolute(void);
249
250 void do_info_mice(void);
251 void do_mouse_set(int index);
252
253 /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
254 constants) */
255 #define QEMU_KEY_ESC1(c) ((c) | 0xe100)
256 #define QEMU_KEY_BACKSPACE 0x007f
257 #define QEMU_KEY_UP QEMU_KEY_ESC1('A')
258 #define QEMU_KEY_DOWN QEMU_KEY_ESC1('B')
259 #define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C')
260 #define QEMU_KEY_LEFT QEMU_KEY_ESC1('D')
261 #define QEMU_KEY_HOME QEMU_KEY_ESC1(1)
262 #define QEMU_KEY_END QEMU_KEY_ESC1(4)
263 #define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5)
264 #define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6)
265 #define QEMU_KEY_DELETE QEMU_KEY_ESC1(3)
266
267 #define QEMU_KEY_CTRL_UP 0xe400
268 #define QEMU_KEY_CTRL_DOWN 0xe401
269 #define QEMU_KEY_CTRL_LEFT 0xe402
270 #define QEMU_KEY_CTRL_RIGHT 0xe403
271 #define QEMU_KEY_CTRL_HOME 0xe404
272 #define QEMU_KEY_CTRL_END 0xe405
273 #define QEMU_KEY_CTRL_PAGEUP 0xe406
274 #define QEMU_KEY_CTRL_PAGEDOWN 0xe407
275
276 void kbd_put_keysym(int keysym);
277
278 /* async I/O support */
279
280 typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
281 typedef int IOCanRWHandler(void *opaque);
282 typedef void IOHandler(void *opaque);
283
284 int qemu_set_fd_handler2(int fd,
285 IOCanRWHandler *fd_read_poll,
286 IOHandler *fd_read,
287 IOHandler *fd_write,
288 void *opaque);
289 int qemu_set_fd_handler(int fd,
290 IOHandler *fd_read,
291 IOHandler *fd_write,
292 void *opaque);
293
294 /* Polling handling */
295
296 /* return TRUE if no sleep should be done afterwards */
297 typedef int PollingFunc(void *opaque);
298
299 int qemu_add_polling_cb(PollingFunc *func, void *opaque);
300 void qemu_del_polling_cb(PollingFunc *func, void *opaque);
301
302 #ifdef _WIN32
303 /* Wait objects handling */
304 typedef void WaitObjectFunc(void *opaque);
305
306 int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
307 void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
308 #endif
309
310 typedef struct QEMUBH QEMUBH;
311
312 /* character device */
313
314 #define CHR_EVENT_BREAK 0 /* serial break char */
315 #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
316 #define CHR_EVENT_RESET 2 /* new connection established */
317
318
319 #define CHR_IOCTL_SERIAL_SET_PARAMS 1
320 typedef struct {
321 int speed;
322 int parity;
323 int data_bits;
324 int stop_bits;
325 } QEMUSerialSetParams;
326
327 #define CHR_IOCTL_SERIAL_SET_BREAK 2
328
329 #define CHR_IOCTL_PP_READ_DATA 3
330 #define CHR_IOCTL_PP_WRITE_DATA 4
331 #define CHR_IOCTL_PP_READ_CONTROL 5
332 #define CHR_IOCTL_PP_WRITE_CONTROL 6
333 #define CHR_IOCTL_PP_READ_STATUS 7
334 #define CHR_IOCTL_PP_EPP_READ_ADDR 8
335 #define CHR_IOCTL_PP_EPP_READ 9
336 #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
337 #define CHR_IOCTL_PP_EPP_WRITE 11
338
339 typedef void IOEventHandler(void *opaque, int event);
340
341 typedef struct CharDriverState {
342 int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
343 void (*chr_update_read_handler)(struct CharDriverState *s);
344 int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
345 IOEventHandler *chr_event;
346 IOCanRWHandler *chr_can_read;
347 IOReadHandler *chr_read;
348 void *handler_opaque;
349 void (*chr_send_event)(struct CharDriverState *chr, int event);
350 void (*chr_close)(struct CharDriverState *chr);
351 void *opaque;
352 int focus;
353 QEMUBH *bh;
354 } CharDriverState;
355
356 CharDriverState *qemu_chr_open(const char *filename);
357 void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
358 int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
359 void qemu_chr_send_event(CharDriverState *s, int event);
360 void qemu_chr_add_handlers(CharDriverState *s,
361 IOCanRWHandler *fd_can_read,
362 IOReadHandler *fd_read,
363 IOEventHandler *fd_event,
364 void *opaque);
365 int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
366 void qemu_chr_reset(CharDriverState *s);
367 int qemu_chr_can_read(CharDriverState *s);
368 void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
369
370 /* consoles */
371
372 typedef struct DisplayState DisplayState;
373 typedef struct TextConsole TextConsole;
374
375 typedef void (*vga_hw_update_ptr)(void *);
376 typedef void (*vga_hw_invalidate_ptr)(void *);
377 typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
378
379 TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
380 vga_hw_invalidate_ptr invalidate,
381 vga_hw_screen_dump_ptr screen_dump,
382 void *opaque);
383 void vga_hw_update(void);
384 void vga_hw_invalidate(void);
385 void vga_hw_screen_dump(const char *filename);
386
387 int is_graphic_console(void);
388 CharDriverState *text_console_init(DisplayState *ds, const char *p);
389 void console_select(unsigned int index);
390
391 /* vmchannel devices */
392
393 #define MAX_VMCHANNEL_DEVICES 4
394
395 /* serial ports */
396
397 #define MAX_SERIAL_PORTS 4
398
399 extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
400
401 /* parallel ports */
402
403 #define MAX_PARALLEL_PORTS 3
404
405 extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
406
407 struct ParallelIOArg {
408 void *buffer;
409 int count;
410 };
411
412 /* VLANs support */
413
414 typedef struct VLANClientState VLANClientState;
415
416 struct VLANClientState {
417 IOReadHandler *fd_read;
418 /* Packets may still be sent if this returns zero. It's used to
419 rate-limit the slirp code. */
420 IOCanRWHandler *fd_can_read;
421 void *opaque;
422 struct VLANClientState *next;
423 struct VLANState *vlan;
424 char info_str[256];
425 };
426
427 typedef struct VLANState {
428 int id;
429 VLANClientState *first_client;
430 struct VLANState *next;
431 unsigned int nb_guest_devs, nb_host_devs;
432 } VLANState;
433
434 VLANState *qemu_find_vlan(int id);
435 VLANClientState *qemu_new_vlan_client(VLANState *vlan,
436 IOReadHandler *fd_read,
437 IOCanRWHandler *fd_can_read,
438 void *opaque);
439 int qemu_can_send_packet(VLANClientState *vc);
440 void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
441 void qemu_handler_true(void *opaque);
442
443 void do_info_network(void);
444
445 /* TAP win32 */
446 int tap_win32_init(VLANState *vlan, const char *ifname);
447
448 /* NIC info */
449
450 #define MAX_NICS 8
451
452 typedef struct NICInfo {
453 uint8_t macaddr[6];
454 const char *model;
455 VLANState *vlan;
456 } NICInfo;
457
458 extern int nb_nics;
459 extern NICInfo nd_table[MAX_NICS];
460
461 /* timers */
462
463 typedef struct QEMUClock QEMUClock;
464 typedef struct QEMUTimer QEMUTimer;
465 typedef void QEMUTimerCB(void *opaque);
466
467 /* The real time clock should be used only for stuff which does not
468 change the virtual machine state, as it is run even if the virtual
469 machine is stopped. The real time clock has a frequency of 1000
470 Hz. */
471 extern QEMUClock *rt_clock;
472
473 /* The virtual clock is only run during the emulation. It is stopped
474 when the virtual machine is stopped. Virtual timers use a high
475 precision clock, usually cpu cycles (use ticks_per_sec). */
476 extern QEMUClock *vm_clock;
477
478 int64_t qemu_get_clock(QEMUClock *clock);
479
480 QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
481 void qemu_free_timer(QEMUTimer *ts);
482 void qemu_del_timer(QEMUTimer *ts);
483 void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
484 int qemu_timer_pending(QEMUTimer *ts);
485
486 extern int64_t ticks_per_sec;
487
488 int64_t cpu_get_ticks(void);
489 void cpu_enable_ticks(void);
490 void cpu_disable_ticks(void);
491
492 /* VM Load/Save */
493
494 typedef struct QEMUFile QEMUFile;
495
496 typedef void (QEMUFilePutBufferFunc)(void *opaque, const uint8_t *buf, int64_t pos, int size);
497 typedef int (QEMUFileGetBufferFunc)(void *opaque, uint8_t *buf, int64_t pos, int size);
498 typedef void (QEMUFileCloseFunc)(void *opaque);
499
500 QEMUFile *qemu_fopen(void *opaque, QEMUFilePutBufferFunc *put_buffer,
501 QEMUFileGetBufferFunc *get_buffer, QEMUFileCloseFunc *close);
502 QEMUFile *qemu_fopen_file(const char *filename, const char *mode);
503 QEMUFile *qemu_fopen_fd(int fd);
504 void qemu_fflush(QEMUFile *f);
505 void qemu_fclose(QEMUFile *f);
506 void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
507 void qemu_put_byte(QEMUFile *f, int v);
508 void qemu_put_be16(QEMUFile *f, unsigned int v);
509 void qemu_put_be32(QEMUFile *f, unsigned int v);
510 void qemu_put_be64(QEMUFile *f, uint64_t v);
511 int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
512 int qemu_get_byte(QEMUFile *f);
513 unsigned int qemu_get_be16(QEMUFile *f);
514 unsigned int qemu_get_be32(QEMUFile *f);
515 uint64_t qemu_get_be64(QEMUFile *f);
516
517 static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
518 {
519 qemu_put_be64(f, *pv);
520 }
521
522 static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
523 {
524 qemu_put_be32(f, *pv);
525 }
526
527 static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
528 {
529 qemu_put_be16(f, *pv);
530 }
531
532 static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
533 {
534 qemu_put_byte(f, *pv);
535 }
536
537 static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
538 {
539 *pv = qemu_get_be64(f);
540 }
541
542 static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
543 {
544 *pv = qemu_get_be32(f);
545 }
546
547 static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
548 {
549 *pv = qemu_get_be16(f);
550 }
551
552 static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
553 {
554 *pv = qemu_get_byte(f);
555 }
556
557 #if TARGET_LONG_BITS == 64
558 #define qemu_put_betl qemu_put_be64
559 #define qemu_get_betl qemu_get_be64
560 #define qemu_put_betls qemu_put_be64s
561 #define qemu_get_betls qemu_get_be64s
562 #else
563 #define qemu_put_betl qemu_put_be32
564 #define qemu_get_betl qemu_get_be32
565 #define qemu_put_betls qemu_put_be32s
566 #define qemu_get_betls qemu_get_be32s
567 #endif
568
569 int64_t qemu_ftell(QEMUFile *f);
570 int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
571
572 typedef void SaveStateHandler(QEMUFile *f, void *opaque);
573 typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
574
575 int register_savevm(const char *idstr,
576 int instance_id,
577 int version_id,
578 SaveStateHandler *save_state,
579 LoadStateHandler *load_state,
580 void *opaque);
581 void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
582 void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
583
584 void cpu_save(QEMUFile *f, void *opaque);
585 int cpu_load(QEMUFile *f, void *opaque, int version_id);
586
587 void do_savevm(const char *name);
588 void do_loadvm(const char *name);
589 void do_delvm(const char *name);
590 void do_info_snapshots(void);
591
592 int qemu_live_savevm_state(QEMUFile *f);
593 int qemu_live_loadvm_state(QEMUFile *f);
594
595 /* bottom halves */
596 typedef void QEMUBHFunc(void *opaque);
597
598 QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
599 void qemu_bh_schedule(QEMUBH *bh);
600 void qemu_bh_cancel(QEMUBH *bh);
601 void qemu_bh_delete(QEMUBH *bh);
602 int qemu_bh_poll(void);
603
604 /* block.c */
605 typedef struct BlockDriverState BlockDriverState;
606 typedef struct BlockDriver BlockDriver;
607
608 extern BlockDriver bdrv_raw;
609 extern BlockDriver bdrv_host_device;
610 extern BlockDriver bdrv_cow;
611 extern BlockDriver bdrv_qcow;
612 extern BlockDriver bdrv_vmdk;
613 extern BlockDriver bdrv_cloop;
614 extern BlockDriver bdrv_dmg;
615 extern BlockDriver bdrv_bochs;
616 extern BlockDriver bdrv_vpc;
617 extern BlockDriver bdrv_vvfat;
618 extern BlockDriver bdrv_qcow2;
619 extern BlockDriver bdrv_parallels;
620
621 typedef struct BlockDriverInfo {
622 /* in bytes, 0 if irrelevant */
623 int cluster_size;
624 /* offset at which the VM state can be saved (0 if not possible) */
625 int64_t vm_state_offset;
626 } BlockDriverInfo;
627
628 typedef struct QEMUSnapshotInfo {
629 char id_str[128]; /* unique snapshot id */
630 /* the following fields are informative. They are not needed for
631 the consistency of the snapshot */
632 char name[256]; /* user choosen name */
633 uint32_t vm_state_size; /* VM state info size */
634 uint32_t date_sec; /* UTC date of the snapshot */
635 uint32_t date_nsec;
636 uint64_t vm_clock_nsec; /* VM clock relative to boot */
637 } QEMUSnapshotInfo;
638
639 typedef struct DiskIOStatistics {
640 uint64_t read_byte_counter;
641 uint64_t write_byte_counter;
642 }DiskIOStatistics;
643
644 #define BDRV_O_RDONLY 0x0000
645 #define BDRV_O_RDWR 0x0002
646 #define BDRV_O_ACCESS 0x0003
647 #define BDRV_O_CREAT 0x0004 /* create an empty file */
648 #define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */
649 #define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to
650 use a disk image format on top of
651 it (default for
652 bdrv_file_open()) */
653
654 void bdrv_init(void);
655 BlockDriver *bdrv_find_format(const char *format_name);
656 int bdrv_create(BlockDriver *drv,
657 const char *filename, int64_t size_in_sectors,
658 const char *backing_file, int flags);
659 BlockDriverState *bdrv_new(const char *device_name);
660 void bdrv_delete(BlockDriverState *bs);
661 int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
662 int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
663 int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
664 BlockDriver *drv);
665 void bdrv_close(BlockDriverState *bs);
666 int bdrv_read(BlockDriverState *bs, int64_t sector_num,
667 uint8_t *buf, int nb_sectors);
668 int bdrv_write(BlockDriverState *bs, int64_t sector_num,
669 const uint8_t *buf, int nb_sectors);
670 int bdrv_pread(BlockDriverState *bs, int64_t offset,
671 void *buf, int count);
672 int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
673 const void *buf, int count);
674 int bdrv_truncate(BlockDriverState *bs, int64_t offset);
675 int64_t bdrv_getlength(BlockDriverState *bs);
676 void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
677 int bdrv_commit(BlockDriverState *bs);
678 void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
679 void bdrv_flush_all(void);
680 /* async block I/O */
681 typedef struct BlockDriverAIOCB BlockDriverAIOCB;
682 typedef void BlockDriverCompletionFunc(void *opaque, int ret);
683
684 BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
685 uint8_t *buf, int nb_sectors,
686 BlockDriverCompletionFunc *cb, void *opaque);
687 BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
688 const uint8_t *buf, int nb_sectors,
689 BlockDriverCompletionFunc *cb, void *opaque);
690 void bdrv_aio_cancel(BlockDriverAIOCB *acb);
691
692 void qemu_aio_init(void);
693 void qemu_aio_poll(void);
694 void qemu_aio_flush(void);
695 void qemu_aio_wait_start(void);
696 void qemu_aio_wait(void);
697 void qemu_aio_wait_end(void);
698
699 int qemu_key_check(BlockDriverState *bs, const char *name);
700
701 /* Ensure contents are flushed to disk. */
702 void bdrv_flush(BlockDriverState *bs);
703
704 #define BDRV_TYPE_HD 0
705 #define BDRV_TYPE_CDROM 1
706 #define BDRV_TYPE_FLOPPY 2
707 #define BIOS_ATA_TRANSLATION_AUTO 0
708 #define BIOS_ATA_TRANSLATION_NONE 1
709 #define BIOS_ATA_TRANSLATION_LBA 2
710 #define BIOS_ATA_TRANSLATION_LARGE 3
711 #define BIOS_ATA_TRANSLATION_RECHS 4
712
713 void bdrv_set_geometry_hint(BlockDriverState *bs,
714 int cyls, int heads, int secs);
715 void bdrv_set_type_hint(BlockDriverState *bs, int type);
716 void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
717 void bdrv_get_geometry_hint(BlockDriverState *bs,
718 int *pcyls, int *pheads, int *psecs);
719 int bdrv_get_type_hint(BlockDriverState *bs);
720 int bdrv_get_translation_hint(BlockDriverState *bs);
721 int bdrv_is_removable(BlockDriverState *bs);
722 int bdrv_is_read_only(BlockDriverState *bs);
723 int bdrv_is_inserted(BlockDriverState *bs);
724 int bdrv_media_changed(BlockDriverState *bs);
725 int bdrv_is_locked(BlockDriverState *bs);
726 void bdrv_set_locked(BlockDriverState *bs, int locked);
727 void bdrv_eject(BlockDriverState *bs, int eject_flag);
728 void bdrv_set_change_cb(BlockDriverState *bs,
729 void (*change_cb)(void *opaque), void *opaque);
730 void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
731 void bdrv_info(void);
732 BlockDriverState *bdrv_find(const char *name);
733 void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
734 int bdrv_is_encrypted(BlockDriverState *bs);
735 int bdrv_set_key(BlockDriverState *bs, const char *key);
736 void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
737 void *opaque);
738 const char *bdrv_get_device_name(BlockDriverState *bs);
739 int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
740 const uint8_t *buf, int nb_sectors);
741 int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
742
743 void bdrv_get_backing_filename(BlockDriverState *bs,
744 char *filename, int filename_size);
745 int bdrv_snapshot_create(BlockDriverState *bs,
746 QEMUSnapshotInfo *sn_info);
747 int bdrv_snapshot_goto(BlockDriverState *bs,
748 const char *snapshot_id);
749 int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
750 int bdrv_snapshot_list(BlockDriverState *bs,
751 QEMUSnapshotInfo **psn_info);
752 char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
753
754 char *get_human_readable_size(char *buf, int buf_size, int64_t size);
755 int path_is_absolute(const char *path);
756 void path_combine(char *dest, int dest_size,
757 const char *base_path,
758 const char *filename);
759
760 #ifndef QEMU_TOOL
761
762 typedef void QEMUMachineInitFunc(ram_addr_t ram_size, int vga_ram_size,
763 int boot_device,
764 DisplayState *ds, const char **fd_filename, int snapshot,
765 const char *kernel_filename, const char *kernel_cmdline,
766 const char *initrd_filename, const char *cpu_model);
767
768 typedef struct QEMUMachine {
769 const char *name;
770 const char *desc;
771 QEMUMachineInitFunc *init;
772 struct QEMUMachine *next;
773 } QEMUMachine;
774
775 int qemu_register_machine(QEMUMachine *m);
776
777 typedef void SetIRQFunc(void *opaque, int irq_num, int level);
778
779 #if defined(TARGET_PPC)
780 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
781 #endif
782
783 #if defined(TARGET_MIPS)
784 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
785 #endif
786
787 #include "hw/irq.h"
788
789 /* ISA bus */
790
791 extern target_phys_addr_t isa_mem_base;
792
793 typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
794 typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
795
796 int register_ioport_read(int start, int length, int size,
797 IOPortReadFunc *func, void *opaque);
798 int register_ioport_write(int start, int length, int size,
799 IOPortWriteFunc *func, void *opaque);
800 void isa_unassign_ioport(int start, int length);
801
802 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
803
804 /* PCI bus */
805
806 extern target_phys_addr_t pci_mem_base;
807
808 typedef struct PCIBus PCIBus;
809 typedef struct PCIDevice PCIDevice;
810
811 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
812 uint32_t address, uint32_t data, int len);
813 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
814 uint32_t address, int len);
815 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
816 uint32_t addr, uint32_t size, int type);
817
818 #define PCI_ADDRESS_SPACE_MEM 0x00
819 #define PCI_ADDRESS_SPACE_IO 0x01
820 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
821
822 typedef struct PCIIORegion {
823 uint32_t addr; /* current PCI mapping address. -1 means not mapped */
824 uint32_t size;
825 uint8_t type;
826 PCIMapIORegionFunc *map_func;
827 } PCIIORegion;
828
829 #define PCI_ROM_SLOT 6
830 #define PCI_NUM_REGIONS 7
831
832 #define PCI_DEVICES_MAX 64
833
834 #define PCI_VENDOR_ID 0x00 /* 16 bits */
835 #define PCI_DEVICE_ID 0x02 /* 16 bits */
836 #define PCI_COMMAND 0x04 /* 16 bits */
837 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
838 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
839 #define PCI_CLASS_DEVICE 0x0a /* Device class */
840 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
841 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
842 #define PCI_MIN_GNT 0x3e /* 8 bits */
843 #define PCI_MAX_LAT 0x3f /* 8 bits */
844
845 struct PCIDevice {
846 /* PCI config space */
847 uint8_t config[256];
848
849 /* the following fields are read only */
850 PCIBus *bus;
851 int devfn;
852 char name[64];
853 PCIIORegion io_regions[PCI_NUM_REGIONS];
854
855 /* do not access the following fields */
856 PCIConfigReadFunc *config_read;
857 PCIConfigWriteFunc *config_write;
858 /* ??? This is a PC-specific hack, and should be removed. */
859 int irq_index;
860
861 /* IRQ objects for the INTA-INTD pins. */
862 qemu_irq *irq;
863
864 /* Current IRQ levels. Used internally by the generic PCI code. */
865 int irq_state[4];
866 };
867
868 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
869 int instance_size, int devfn,
870 PCIConfigReadFunc *config_read,
871 PCIConfigWriteFunc *config_write);
872
873 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
874 uint32_t size, int type,
875 PCIMapIORegionFunc *map_func);
876
877 uint32_t pci_default_read_config(PCIDevice *d,
878 uint32_t address, int len);
879 void pci_default_write_config(PCIDevice *d,
880 uint32_t address, uint32_t val, int len);
881 void pci_device_save(PCIDevice *s, QEMUFile *f);
882 int pci_device_load(PCIDevice *s, QEMUFile *f);
883
884 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
885 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
886 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
887 qemu_irq *pic, int devfn_min, int nirq);
888
889 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
890 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
891 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
892 int pci_bus_num(PCIBus *s);
893 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
894
895 void pci_info(void);
896 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
897 pci_map_irq_fn map_irq, const char *name);
898
899 /* prep_pci.c */
900 PCIBus *pci_prep_init(qemu_irq *pic);
901
902 /* grackle_pci.c */
903 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
904
905 /* unin_pci.c */
906 PCIBus *pci_pmac_init(qemu_irq *pic);
907
908 /* apb_pci.c */
909 PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
910 qemu_irq *pic);
911
912 PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
913
914 /* piix_pci.c */
915 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
916 void i440fx_set_smm(PCIDevice *d, int val);
917 int piix3_init(PCIBus *bus, int devfn);
918 void i440fx_init_memory_mappings(PCIDevice *d);
919
920 int piix4_init(PCIBus *bus, int devfn);
921
922 /* openpic.c */
923 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
924 enum {
925 OPENPIC_OUTPUT_INT = 0, /* IRQ */
926 OPENPIC_OUTPUT_CINT, /* critical IRQ */
927 OPENPIC_OUTPUT_MCK, /* Machine check event */
928 OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
929 OPENPIC_OUTPUT_RESET, /* Core reset event */
930 OPENPIC_OUTPUT_NB,
931 };
932 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
933 qemu_irq **irqs, qemu_irq irq_out);
934
935 /* heathrow_pic.c */
936 qemu_irq *heathrow_pic_init(int *pmem_index);
937
938 /* gt64xxx.c */
939 PCIBus *pci_gt64120_init(qemu_irq *pic);
940
941 #ifdef HAS_AUDIO
942 struct soundhw {
943 const char *name;
944 const char *descr;
945 int enabled;
946 int isa;
947 union {
948 int (*init_isa) (AudioState *s, qemu_irq *pic);
949 int (*init_pci) (PCIBus *bus, AudioState *s);
950 } init;
951 };
952
953 extern struct soundhw soundhw[];
954 #endif
955
956 /* vga.c */
957
958 #ifndef TARGET_SPARC
959 #define VGA_RAM_SIZE (8192 * 1024)
960 #else
961 #define VGA_RAM_SIZE (9 * 1024 * 1024)
962 #endif
963
964 struct DisplayState {
965 uint8_t *data;
966 int linesize;
967 int depth;
968 int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
969 int width;
970 int height;
971 void *opaque;
972 QEMUTimer *gui_timer;
973
974 void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
975 void (*dpy_resize)(struct DisplayState *s, int w, int h);
976 void (*dpy_refresh)(struct DisplayState *s);
977 void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
978 int dst_x, int dst_y, int w, int h);
979 void (*dpy_fill)(struct DisplayState *s, int x, int y,
980 int w, int h, uint32_t c);
981 void (*mouse_set)(int x, int y, int on);
982 void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
983 uint8_t *image, uint8_t *mask);
984 };
985
986 static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
987 {
988 s->dpy_update(s, x, y, w, h);
989 }
990
991 static inline void dpy_resize(DisplayState *s, int w, int h)
992 {
993 s->dpy_resize(s, w, h);
994 }
995
996 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
997 unsigned long vga_ram_offset, int vga_ram_size);
998 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
999 unsigned long vga_ram_offset, int vga_ram_size,
1000 unsigned long vga_bios_offset, int vga_bios_size);
1001 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
1002 unsigned long vga_ram_offset, int vga_ram_size,
1003 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
1004 int it_shift);
1005
1006 /* cirrus_vga.c */
1007 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1008 unsigned long vga_ram_offset, int vga_ram_size);
1009 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
1010 unsigned long vga_ram_offset, int vga_ram_size);
1011
1012 /* vmware_vga.c */
1013 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1014 unsigned long vga_ram_offset, int vga_ram_size);
1015
1016 /* sdl.c */
1017 void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
1018
1019 /* cocoa.m */
1020 void cocoa_display_init(DisplayState *ds, int full_screen);
1021
1022 /* vnc.c */
1023 void vnc_display_init(DisplayState *ds);
1024 void vnc_display_close(DisplayState *ds);
1025 int vnc_display_open(DisplayState *ds, const char *display);
1026 int vnc_display_password(DisplayState *ds, const char *password);
1027 void do_info_vnc(void);
1028
1029 /* x_keymap.c */
1030 extern uint8_t _translate_keycode(const int key);
1031
1032 /* ide.c */
1033 #define MAX_DISKS 4
1034
1035 extern BlockDriverState *bs_table[MAX_DISKS + 1];
1036 extern BlockDriverState *sd_bdrv;
1037 extern BlockDriverState *mtd_bdrv;
1038
1039 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
1040 BlockDriverState *hd0, BlockDriverState *hd1);
1041 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
1042 int secondary_ide_enabled);
1043 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1044 qemu_irq *pic);
1045 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1046 qemu_irq *pic);
1047 int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
1048
1049 /* cdrom.c */
1050 int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
1051 int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
1052
1053 /* ds1225y.c */
1054 typedef struct ds1225y_t ds1225y_t;
1055 ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1056
1057 /* es1370.c */
1058 int es1370_init (PCIBus *bus, AudioState *s);
1059
1060 /* sb16.c */
1061 int SB16_init (AudioState *s, qemu_irq *pic);
1062
1063 /* adlib.c */
1064 int Adlib_init (AudioState *s, qemu_irq *pic);
1065
1066 /* gus.c */
1067 int GUS_init (AudioState *s, qemu_irq *pic);
1068
1069 /* dma.c */
1070 typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1071 int DMA_get_channel_mode (int nchan);
1072 int DMA_read_memory (int nchan, void *buf, int pos, int size);
1073 int DMA_write_memory (int nchan, void *buf, int pos, int size);
1074 void DMA_hold_DREQ (int nchan);
1075 void DMA_release_DREQ (int nchan);
1076 void DMA_schedule(int nchan);
1077 void DMA_run (void);
1078 void DMA_init (int high_page_enable);
1079 void DMA_register_channel (int nchan,
1080 DMA_transfer_handler transfer_handler,
1081 void *opaque);
1082 /* fdc.c */
1083 #define MAX_FD 2
1084 extern BlockDriverState *fd_table[MAX_FD];
1085
1086 typedef struct fdctrl_t fdctrl_t;
1087
1088 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1089 target_phys_addr_t io_base,
1090 BlockDriverState **fds);
1091 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1092
1093 /* eepro100.c */
1094
1095 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1096 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1097 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1098
1099 /* ne2000.c */
1100
1101 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1102 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1103
1104 /* rtl8139.c */
1105
1106 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1107
1108 /* pcnet.c */
1109
1110 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1111 void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1112 qemu_irq irq, qemu_irq *reset);
1113
1114 /* vmmouse.c */
1115 void *vmmouse_init(void *m);
1116
1117 /* vmport.c */
1118 #ifdef TARGET_I386
1119 void vmport_init(CPUState *env);
1120 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
1121 #endif
1122
1123 /* pckbd.c */
1124
1125 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1126 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1127 target_phys_addr_t base, int it_shift);
1128
1129 /* mc146818rtc.c */
1130
1131 typedef struct RTCState RTCState;
1132
1133 RTCState *rtc_init(int base, qemu_irq irq);
1134 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1135 void rtc_set_memory(RTCState *s, int addr, int val);
1136 void rtc_set_date(RTCState *s, const struct tm *tm);
1137
1138 /* serial.c */
1139
1140 typedef struct SerialState SerialState;
1141 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1142 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1143 qemu_irq irq, CharDriverState *chr,
1144 int ioregister);
1145 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1146 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1147 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1148 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1149 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1150 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1151
1152 /* parallel.c */
1153
1154 typedef struct ParallelState ParallelState;
1155 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1156 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1157
1158 /* i8259.c */
1159
1160 typedef struct PicState2 PicState2;
1161 extern PicState2 *isa_pic;
1162 void pic_set_irq(int irq, int level);
1163 void pic_set_irq_new(void *opaque, int irq, int level);
1164 qemu_irq *i8259_init(qemu_irq parent_irq);
1165 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1166 void *alt_irq_opaque);
1167 int pic_read_irq(PicState2 *s);
1168 void pic_update_irq(PicState2 *s);
1169 uint32_t pic_intack_read(PicState2 *s);
1170 void pic_info(void);
1171 void irq_info(void);
1172
1173 /* APIC */
1174 typedef struct IOAPICState IOAPICState;
1175
1176 int apic_init(CPUState *env);
1177 int apic_get_interrupt(CPUState *env);
1178 int apic_accept_pic_intr(CPUState *env);
1179 IOAPICState *ioapic_init(void);
1180 void ioapic_set_irq(void *opaque, int vector, int level);
1181
1182 /* i8254.c */
1183
1184 #define PIT_FREQ 1193182
1185
1186 typedef struct PITState PITState;
1187
1188 PITState *pit_init(int base, qemu_irq irq);
1189 void pit_set_gate(PITState *pit, int channel, int val);
1190 int pit_get_gate(PITState *pit, int channel);
1191 int pit_get_initial_count(PITState *pit, int channel);
1192 int pit_get_mode(PITState *pit, int channel);
1193 int pit_get_out(PITState *pit, int channel, int64_t current_time);
1194
1195 /* jazz_led.c */
1196 extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1197
1198 /* pcspk.c */
1199 void pcspk_init(PITState *);
1200 int pcspk_audio_init(AudioState *, qemu_irq *pic);
1201
1202 #include "hw/i2c.h"
1203
1204 #include "hw/smbus.h"
1205
1206 /* acpi.c */
1207 extern int acpi_enabled;
1208 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1209 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1210 void acpi_bios_init(void);
1211
1212 /* pc.c */
1213 extern QEMUMachine pc_machine;
1214 extern QEMUMachine isapc_machine;
1215 extern int fd_bootchk;
1216
1217 void ioport_set_a20(int enable);
1218 int ioport_get_a20(void);
1219
1220 /* ppc.c */
1221 extern QEMUMachine prep_machine;
1222 extern QEMUMachine core99_machine;
1223 extern QEMUMachine heathrow_machine;
1224 extern QEMUMachine ref405ep_machine;
1225 extern QEMUMachine taihu_machine;
1226
1227 /* mips_r4k.c */
1228 extern QEMUMachine mips_machine;
1229
1230 /* mips_malta.c */
1231 extern QEMUMachine mips_malta_machine;
1232
1233 /* mips_int.c */
1234 extern void cpu_mips_irq_init_cpu(CPUState *env);
1235
1236 /* mips_pica61.c */
1237 extern QEMUMachine mips_pica61_machine;
1238
1239 /* mips_timer.c */
1240 extern void cpu_mips_clock_init(CPUState *);
1241 extern void cpu_mips_irqctrl_init (void);
1242
1243 /* shix.c */
1244 extern QEMUMachine shix_machine;
1245
1246 /* r2d.c */
1247 extern QEMUMachine r2d_machine;
1248
1249 #ifdef TARGET_PPC
1250 /* PowerPC hardware exceptions management helpers */
1251 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1252 typedef struct clk_setup_t clk_setup_t;
1253 struct clk_setup_t {
1254 clk_setup_cb cb;
1255 void *opaque;
1256 };
1257 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1258 {
1259 if (clk->cb != NULL)
1260 (*clk->cb)(clk->opaque, freq);
1261 }
1262
1263 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1264 /* Embedded PowerPC DCR management */
1265 typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1266 typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1267 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1268 int (*dcr_write_error)(int dcrn));
1269 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1270 dcr_read_cb drc_read, dcr_write_cb dcr_write);
1271 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1272 /* Embedded PowerPC reset */
1273 void ppc40x_core_reset (CPUState *env);
1274 void ppc40x_chip_reset (CPUState *env);
1275 void ppc40x_system_reset (CPUState *env);
1276 #endif
1277 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1278
1279 extern CPUWriteMemoryFunc *PPC_io_write[];
1280 extern CPUReadMemoryFunc *PPC_io_read[];
1281 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1282
1283 /* sun4m.c */
1284 extern QEMUMachine ss5_machine, ss10_machine;
1285
1286 /* iommu.c */
1287 void *iommu_init(target_phys_addr_t addr);
1288 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1289 uint8_t *buf, int len, int is_write);
1290 static inline void sparc_iommu_memory_read(void *opaque,
1291 target_phys_addr_t addr,
1292 uint8_t *buf, int len)
1293 {
1294 sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1295 }
1296
1297 static inline void sparc_iommu_memory_write(void *opaque,
1298 target_phys_addr_t addr,
1299 uint8_t *buf, int len)
1300 {
1301 sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1302 }
1303
1304 /* tcx.c */
1305 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1306 unsigned long vram_offset, int vram_size, int width, int height,
1307 int depth);
1308
1309 /* slavio_intctl.c */
1310 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1311 const uint32_t *intbit_to_level,
1312 qemu_irq **irq, qemu_irq **cpu_irq,
1313 qemu_irq **parent_irq, unsigned int cputimer);
1314 void slavio_pic_info(void *opaque);
1315 void slavio_irq_info(void *opaque);
1316
1317 /* loader.c */
1318 int get_image_size(const char *filename);
1319 int load_image(const char *filename, uint8_t *addr);
1320 int load_elf(const char *filename, int64_t virt_to_phys_addend,
1321 uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1322 int load_aout(const char *filename, uint8_t *addr);
1323 int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1324
1325 /* slavio_timer.c */
1326 void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode);
1327
1328 /* slavio_serial.c */
1329 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1330 CharDriverState *chr1, CharDriverState *chr2);
1331 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1332
1333 /* slavio_misc.c */
1334 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1335 qemu_irq irq);
1336 void slavio_set_power_fail(void *opaque, int power_failing);
1337
1338 /* esp.c */
1339 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1340 void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1341 void *dma_opaque, qemu_irq irq, qemu_irq *reset);
1342
1343 /* sparc32_dma.c */
1344 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1345 void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
1346 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1347 uint8_t *buf, int len, int do_bswap);
1348 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1349 uint8_t *buf, int len, int do_bswap);
1350 void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1351 void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1352
1353 /* cs4231.c */
1354 void cs_init(target_phys_addr_t base, int irq, void *intctl);
1355
1356 /* sun4u.c */
1357 extern QEMUMachine sun4u_machine;
1358
1359 /* NVRAM helpers */
1360 #include "hw/m48t59.h"
1361
1362 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1363 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1364 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1365 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1366 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1367 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1368 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1369 const unsigned char *str, uint32_t max);
1370 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1371 void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1372 uint32_t start, uint32_t count);
1373 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1374 const unsigned char *arch,
1375 uint32_t RAM_size, int boot_device,
1376 uint32_t kernel_image, uint32_t kernel_size,
1377 const char *cmdline,
1378 uint32_t initrd_image, uint32_t initrd_size,
1379 uint32_t NVRAM_image,
1380 int width, int height, int depth);
1381
1382 /* adb.c */
1383
1384 #define MAX_ADB_DEVICES 16
1385
1386 #define ADB_MAX_OUT_LEN 16
1387
1388 typedef struct ADBDevice ADBDevice;
1389
1390 /* hypercall.c */
1391
1392 void pci_hypercall_init(PCIBus *bus);
1393 void vmchannel_init(CharDriverState *hd, uint32_t deviceid, uint32_t index);
1394
1395 /* buf = NULL means polling */
1396 typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1397 const uint8_t *buf, int len);
1398 typedef int ADBDeviceReset(ADBDevice *d);
1399
1400 struct ADBDevice {
1401 struct ADBBusState *bus;
1402 int devaddr;
1403 int handler;
1404 ADBDeviceRequest *devreq;
1405 ADBDeviceReset *devreset;
1406 void *opaque;
1407 };
1408
1409 typedef struct ADBBusState {
1410 ADBDevice devices[MAX_ADB_DEVICES];
1411 int nb_devices;
1412 int poll_index;
1413 } ADBBusState;
1414
1415 int adb_request(ADBBusState *s, uint8_t *buf_out,
1416 const uint8_t *buf, int len);
1417 int adb_poll(ADBBusState *s, uint8_t *buf_out);
1418
1419 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1420 ADBDeviceRequest *devreq,
1421 ADBDeviceReset *devreset,
1422 void *opaque);
1423 void adb_kbd_init(ADBBusState *bus);
1424 void adb_mouse_init(ADBBusState *bus);
1425
1426 /* cuda.c */
1427
1428 extern ADBBusState adb_bus;
1429 int cuda_init(qemu_irq irq);
1430
1431 #include "hw/usb.h"
1432
1433 /* usb ports of the VM */
1434
1435 void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1436 usb_attachfn attach);
1437
1438 #define VM_USB_HUB_SIZE 8
1439
1440 void do_usb_add(const char *devname);
1441 void do_usb_del(const char *devname);
1442 void usb_info(void);
1443
1444 /* scsi-disk.c */
1445 enum scsi_reason {
1446 SCSI_REASON_DONE, /* Command complete. */
1447 SCSI_REASON_DATA /* Transfer complete, more data required. */
1448 };
1449
1450 typedef struct SCSIDevice SCSIDevice;
1451 typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1452 uint32_t arg);
1453
1454 SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1455 int tcq,
1456 scsi_completionfn completion,
1457 void *opaque);
1458 void scsi_disk_destroy(SCSIDevice *s);
1459
1460 int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1461 /* SCSI data transfers are asynchrnonous. However, unlike the block IO
1462 layer the completion routine may be called directly by
1463 scsi_{read,write}_data. */
1464 void scsi_read_data(SCSIDevice *s, uint32_t tag);
1465 int scsi_write_data(SCSIDevice *s, uint32_t tag);
1466 void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1467 uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1468
1469 /* lsi53c895a.c */
1470 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1471 void *lsi_scsi_init(PCIBus *bus, int devfn);
1472
1473 /* integratorcp.c */
1474 extern QEMUMachine integratorcp_machine;
1475
1476 /* versatilepb.c */
1477 extern QEMUMachine versatilepb_machine;
1478 extern QEMUMachine versatileab_machine;
1479
1480 /* realview.c */
1481 extern QEMUMachine realview_machine;
1482
1483 /* spitz.c */
1484 extern QEMUMachine akitapda_machine;
1485 extern QEMUMachine spitzpda_machine;
1486 extern QEMUMachine borzoipda_machine;
1487 extern QEMUMachine terrierpda_machine;
1488
1489 /* palm.c */
1490 extern QEMUMachine palmte_machine;
1491
1492 /* ps2.c */
1493 void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1494 void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1495 void ps2_write_mouse(void *, int val);
1496 void ps2_write_keyboard(void *, int val);
1497 uint32_t ps2_read_data(void *);
1498 void ps2_queue(void *, int b);
1499 void ps2_keyboard_set_translation(void *opaque, int mode);
1500 void ps2_mouse_fake_event(void *opaque);
1501
1502 /* smc91c111.c */
1503 void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1504
1505 /* pl031.c */
1506 void pl031_init(uint32_t base, qemu_irq irq);
1507
1508 /* pl110.c */
1509 void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1510
1511 /* pl011.c */
1512 void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1513
1514 /* pl050.c */
1515 void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1516
1517 /* pl080.c */
1518 void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1519
1520 /* pl181.c */
1521 void pl181_init(uint32_t base, BlockDriverState *bd,
1522 qemu_irq irq0, qemu_irq irq1);
1523
1524 /* pl190.c */
1525 qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1526
1527 /* arm-timer.c */
1528 void sp804_init(uint32_t base, qemu_irq irq);
1529 void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1530
1531 /* arm_sysctl.c */
1532 void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1533
1534 /* arm_gic.c */
1535 qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1536
1537 /* arm_boot.c */
1538
1539 void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1540 const char *kernel_cmdline, const char *initrd_filename,
1541 int board_id, target_phys_addr_t loader_start);
1542
1543 /* sh7750.c */
1544 struct SH7750State;
1545
1546 struct SH7750State *sh7750_init(CPUState * cpu);
1547
1548 typedef struct {
1549 /* The callback will be triggered if any of the designated lines change */
1550 uint16_t portamask_trigger;
1551 uint16_t portbmask_trigger;
1552 /* Return 0 if no action was taken */
1553 int (*port_change_cb) (uint16_t porta, uint16_t portb,
1554 uint16_t * periph_pdtra,
1555 uint16_t * periph_portdira,
1556 uint16_t * periph_pdtrb,
1557 uint16_t * periph_portdirb);
1558 } sh7750_io_device;
1559
1560 int sh7750_register_io_device(struct SH7750State *s,
1561 sh7750_io_device * device);
1562 /* sh_timer.c */
1563 #define TMU012_FEAT_TOCR (1 << 0)
1564 #define TMU012_FEAT_3CHAN (1 << 1)
1565 #define TMU012_FEAT_EXTCLK (1 << 2)
1566 void tmu012_init(uint32_t base, int feat, uint32_t freq);
1567
1568 /* sh_serial.c */
1569 #define SH_SERIAL_FEAT_SCIF (1 << 0)
1570 void sh_serial_init (target_phys_addr_t base, int feat,
1571 uint32_t freq, CharDriverState *chr);
1572
1573 /* tc58128.c */
1574 int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1575
1576 /* NOR flash devices */
1577 #define MAX_PFLASH 4
1578 extern BlockDriverState *pflash_table[MAX_PFLASH];
1579 typedef struct pflash_t pflash_t;
1580
1581 pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1582 BlockDriverState *bs,
1583 uint32_t sector_len, int nb_blocs, int width,
1584 uint16_t id0, uint16_t id1,
1585 uint16_t id2, uint16_t id3);
1586
1587 /* nand.c */
1588 struct nand_flash_s;
1589 struct nand_flash_s *nand_init(int manf_id, int chip_id);
1590 void nand_done(struct nand_flash_s *s);
1591 void nand_setpins(struct nand_flash_s *s,
1592 int cle, int ale, int ce, int wp, int gnd);
1593 void nand_getpins(struct nand_flash_s *s, int *rb);
1594 void nand_setio(struct nand_flash_s *s, uint8_t value);
1595 uint8_t nand_getio(struct nand_flash_s *s);
1596
1597 #define NAND_MFR_TOSHIBA 0x98
1598 #define NAND_MFR_SAMSUNG 0xec
1599 #define NAND_MFR_FUJITSU 0x04
1600 #define NAND_MFR_NATIONAL 0x8f
1601 #define NAND_MFR_RENESAS 0x07
1602 #define NAND_MFR_STMICRO 0x20
1603 #define NAND_MFR_HYNIX 0xad
1604 #define NAND_MFR_MICRON 0x2c
1605
1606 /* ecc.c */
1607 struct ecc_state_s {
1608 uint8_t cp; /* Column parity */
1609 uint16_t lp[2]; /* Line parity */
1610 uint16_t count;
1611 };
1612
1613 uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
1614 void ecc_reset(struct ecc_state_s *s);
1615 void ecc_put(QEMUFile *f, struct ecc_state_s *s);
1616 void ecc_get(QEMUFile *f, struct ecc_state_s *s);
1617
1618 /* GPIO */
1619 typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1620
1621 /* ads7846.c */
1622 struct ads7846_state_s;
1623 uint32_t ads7846_read(void *opaque);
1624 void ads7846_write(void *opaque, uint32_t value);
1625 struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1626
1627 /* max111x.c */
1628 struct max111x_s;
1629 uint32_t max111x_read(void *opaque);
1630 void max111x_write(void *opaque, uint32_t value);
1631 struct max111x_s *max1110_init(qemu_irq cb);
1632 struct max111x_s *max1111_init(qemu_irq cb);
1633 void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1634
1635 /* PCMCIA/Cardbus */
1636
1637 struct pcmcia_socket_s {
1638 qemu_irq irq;
1639 int attached;
1640 const char *slot_string;
1641 const char *card_string;
1642 };
1643
1644 void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1645 void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1646 void pcmcia_info(void);
1647
1648 struct pcmcia_card_s {
1649 void *state;
1650 struct pcmcia_socket_s *slot;
1651 int (*attach)(void *state);
1652 int (*detach)(void *state);
1653 const uint8_t *cis;
1654 int cis_len;
1655
1656 /* Only valid if attached */
1657 uint8_t (*attr_read)(void *state, uint32_t address);
1658 void (*attr_write)(void *state, uint32_t address, uint8_t value);
1659 uint16_t (*common_read)(void *state, uint32_t address);
1660 void (*common_write)(void *state, uint32_t address, uint16_t value);
1661 uint16_t (*io_read)(void *state, uint32_t address);
1662 void (*io_write)(void *state, uint32_t address, uint16_t value);
1663 };
1664
1665 #define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */
1666 #define CISTPL_NO_LINK 0x14 /* No Link Tuple */
1667 #define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */
1668 #define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */
1669 #define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */
1670 #define CISTPL_CONFIG 0x1a /* Configuration Tuple */
1671 #define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */
1672 #define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */
1673 #define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */
1674 #define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */
1675 #define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */
1676 #define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */
1677 #define CISTPL_FUNCID 0x21 /* Function ID Tuple */
1678 #define CISTPL_FUNCE 0x22 /* Function Extension Tuple */
1679 #define CISTPL_END 0xff /* Tuple End */
1680 #define CISTPL_ENDMARK 0xff
1681
1682 /* dscm1xxxx.c */
1683 struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1684
1685 /* ptimer.c */
1686 typedef struct ptimer_state ptimer_state;
1687 typedef void (*ptimer_cb)(void *opaque);
1688
1689 ptimer_state *ptimer_init(QEMUBH *bh);
1690 void ptimer_set_period(ptimer_state *s, int64_t period);
1691 void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1692 void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1693 uint64_t ptimer_get_count(ptimer_state *s);
1694 void ptimer_set_count(ptimer_state *s, uint64_t count);
1695 void ptimer_run(ptimer_state *s, int oneshot);
1696 void ptimer_stop(ptimer_state *s);
1697 void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1698 void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1699
1700 #include "hw/pxa.h"
1701
1702 #include "hw/omap.h"
1703
1704 /* mcf_uart.c */
1705 uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1706 void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1707 void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1708 void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1709 CharDriverState *chr);
1710
1711 /* mcf_intc.c */
1712 qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1713
1714 /* mcf_fec.c */
1715 void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1716
1717 /* mcf5206.c */
1718 qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1719
1720 /* an5206.c */
1721 extern QEMUMachine an5206_machine;
1722
1723 /* mcf5208.c */
1724 extern QEMUMachine mcf5208evb_machine;
1725
1726 #include "gdbstub.h"
1727
1728 #endif /* defined(QEMU_TOOL) */
1729
1730 /* migration.c */
1731 void do_info_migration(void);
1732 void do_migrate(int detach, const char *uri);
1733 void do_migrate_cancel(void);
1734 void do_migrate_set_speed(const char *value);
1735 int migrate_incoming(const char *device);
1736
1737 /* monitor.c */
1738 void monitor_init(CharDriverState *hd, int show_banner);
1739 void term_puts(const char *str);
1740 void term_vprintf(const char *fmt, va_list ap);
1741 void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1742 void term_print_filename(const char *filename);
1743 void term_flush(void);
1744 void term_print_help(void);
1745 void monitor_readline(const char *prompt, int is_password,
1746 char *buf, int buf_size);
1747 void monitor_suspend(void);
1748 void monitor_resume(void);
1749
1750 /* readline.c */
1751 typedef void ReadLineFunc(void *opaque, const char *str);
1752
1753 extern int completion_index;
1754 void add_completion(const char *str);
1755 void readline_handle_byte(int ch);
1756 void readline_find_completion(const char *cmdline);
1757 const char *readline_get_history(unsigned int index);
1758 void readline_start(const char *prompt, int is_password,
1759 ReadLineFunc *readline_func, void *opaque);
1760
1761 void kqemu_record_dump(void);
1762
1763 #endif /* VL_H */
kvm userspace components