2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2018 Elias Oenal <sigrok@eliasoenal.com>
5 ## All rights reserved.
7 ## Redistribution and use in source and binary forms, with or without
8 ## modification, are permitted provided that the following conditions are met:
10 ## 1. Redistributions of source code must retain the above copyright notice,
11 ## this list of conditions and the following disclaimer.
12 ## 2. Redistributions in binary form must reproduce the above copyright notice,
13 ## this list of conditions and the following disclaimer in the documentation
14 ## and/or other materials provided with the distribution.
16 ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 ## POSSIBILITY OF SUCH DAMAGE.
29 import sigrokdecode
as srd
32 0x00: 'Unknown or unspecified',
34 0x02: 'Module/connector soldered to motherboard',
52 class Decoder(srd
.Decoder
):
56 longname
= '100 Gigabit C form-factor pluggable'
57 desc
= '100 Gigabit C form-factor pluggable (CFP) protocol.'
63 ('register', 'Register'),
67 ('registers', 'Registers', (0,)),
68 ('decodes', 'Decodes', (1,)),
78 self
.out_ann
= self
.register(srd
.OUTPUT_ANN
)
81 self
.put(self
.ss
, self
.es
, self
.out_ann
, data
)
83 def decode(self
, ss
, es
, data
):
84 self
.ss
, self
.es
= ss
, es
85 for (clause45
, clause45_addr
, is_read
, portad
, devad
, reg
) in data
:
88 if clause45_addr
in range(0x8000, 0x807F + 1):
89 self
.putx([0, ['CFP NVR 1: Basic ID register', 'NVR1']])
90 if clause45_addr
== 0x8000:
91 self
.putx([1, ['Module identifier: %s' % \
92 MODULE_ID
.get(reg
, 'Reserved')]])
93 elif clause45_addr
in range(0x8080, 0x80FF + 1):
94 self
.putx([0, ['CFP NVR 2: Extended ID register', 'NVR2']])
95 elif clause45_addr
in range(0x8100, 0x817F + 1):
96 self
.putx([0, ['CFP NVR 3: Network lane specific register', 'NVR3']])
97 elif clause45_addr
in range(0x8180, 0x81FF + 1):
98 self
.putx([0, ['CFP NVR 4', 'NVR4']])
99 elif clause45_addr
in range(0x8400, 0x847F + 1):
100 self
.putx([0, ['Vendor NVR 1: Vendor data register', 'V-NVR1']])
101 elif clause45_addr
in range(0x8480, 0x84FF + 1):
102 self
.putx([0, ['Vendor NVR 2: Vendor data register', 'V-NVR2']])
103 elif clause45_addr
in range(0x8800, 0x887F + 1):
104 self
.putx([0, ['User NVR 1: User data register', 'U-NVR1']])
105 elif clause45_addr
in range(0x8880, 0x88FF + 1):
106 self
.putx([0, ['User NVR 2: User data register', 'U-NVR2']])
107 elif clause45_addr
in range(0xA000, 0xA07F + 1):
108 self
.putx([0, ['CFP Module VR 1: CFP Module level control and DDM register', 'Mod-VR1']])
109 elif clause45_addr
in range(0xA080, 0xA0FF + 1):
110 self
.putx([0, ['MLG VR 1: MLG Management Interface register', 'MLG-VR1']])