?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / net / wireless / rtlink / Module / rt2560.h
bloba19eaedd193fa780339321d417e44e7a42276409
1 /*
2 ***************************************************************************
3 * Ralink Tech Inc.
4 * 4F, No. 2 Technology 5th Rd.
5 * Science-based Industrial Park
6 * Hsin-chu, Taiwan, R.O.C.
7 *
8 * (c) Copyright 2002, Ralink Technology, Inc.
9 *
10 * All rights reserved. Ralink's source code is an unpublished work and the
11 * use of a copyright notice does not imply otherwise. This source code
12 * contains confidential trade secret material of Ralink Tech. Any attemp
13 * or participation in deciphering, decoding, reverse engineering or in any
14 * way altering the source code is stricitly prohibited, unless the prior
15 * written consent of Ralink Technology, Inc. is obtained.
16 ***************************************************************************
17
18 Module Name:
19 rt2560.h
20
21 Abstract:
22 RT2560 ASIC related definition & structures
23
24 Revision History:
25 Who When What
26 -------- ---------- ----------------------------------------------
27
28 */
29
30 #ifndef __RT2560_H__
31 #define __RT2560_H__
32
33 //
34 // Control/Status Registers (CSR)
35 //
36 #define CSR0 0x0000 // ASIC revision number
37 #define CSR1 0x0004 // System control register
38 #define CSR2 0x0008 // System admin status register (invalid)
39 #define CSR3 0x000C // STA MAC address register 0
40 #define CSR4 0x0010 // STA MAC address register 1
41 #define CSR5 0x0014 // BSSID register 0
42 #define CSR6 0x0018 // BSSID register 1
43 #define CSR7 0x001C // Interrupt source register
44 #define CSR8 0x0020 // Interrupt mask register
45 #define CSR9 0x0024 // Maximum frame length register
46 #define CSR11 0x002C // Back-off control register
47 #define CSR12 0x0030 // Synchronization configuration register 0
48 #define CSR13 0x0034 // Synchronization configuration register 1
49 #define CSR14 0x0038 // Synchronization control register
50 #define CSR15 0x003C // Synchronization status register
51 #define CSR16 0x0040 // TSF timer register 0
52 #define CSR17 0x0044 // TSF timer register 1
53 #define CSR18 0x0048 // IFS timer register 0
54 #define CSR19 0x004C // IFS timer register 1
55 #define CSR20 0x0050 // WakeUp register
56 #define CSR21 0x0054 // EEPROM control register
57 #define CSR22 0x0058 // CFP Control Register
58
59 // Security coprocessor registers
60 #define SECCSR0 0x0028 // WEP control register
61 #define SECCSR1 0x0158 // WEP control register
62 #define SECCSR3 0x00fc // AES control register
63
64 // Transmit related CSRs
65 #define TXCSR0 0x0060 // TX cintrol register
66 #define TXCSR1 0x0064 // TX configuration register
67 #define TXCSR2 0x0068 // TX descriptor configuratioon register
68 #define TXCSR3 0x006C // TX Ring Base address register
69 #define TXCSR4 0x0070 // Atim Ring Base address register
70 #define TXCSR5 0x0074 // Prio Ring Base address register
71 #define TXCSR6 0x0078 // Beacon base address
72 #define TXCSR7 0x007C // AutoResponder Control Register
73 #define TXCSR8 0x0098 // CCK TX BBP registers
74 #define TXCSR9 0x0094 // OFDM TX BBP registers
75
76 // Receive related CSRs
77 #define RXCSR0 0x0080 // RX control register
78 #define RXCSR1 0x0084 // RX descriptorconfiguration register
79 #define RXCSR2 0x0088 // RX Ring base address register
80 #define RXCSR3 0x0090 // BBP ID register 0
81 //#define RXCSR4 0x0094 // BBP ID register 1
82 //#define ARCSR0 0x0098 // Auto responder PLCP config register 1
83 #define ARCSR1 0x009C // Auto responder PLCP config register 1
84
85 // PCI control CSRs
86 #define PCICSR 0x008C // PCI control register
87
88 //
89 // Alias to all ring base registers. Easier to understand constant definition
90 // within codes.
91 //
92 #define RX_RING_BASE_REG (RXCSR2)
93 #define TX_RING_BASE_REG (TXCSR3)
94 #define ATIM_RING_BASE_REG (TXCSR4)
95 #define PRIO_RING_BASE_REG (TXCSR5)
96 #define BEACON_BASE_REG (TXCSR6)
97
98 // Statistic Register
99 #define CNT0 0x00A0 // Dot11 FCS error count
100 #define CNT1 0x00AC // Dot11 PLCP error count
101 #define CNT2 0x00B0 // Dot11 long error count
102 #define CNT3 0x00B8 // Dot11 CCA false alarm count
103 #define CNT4 0x00BC // Dot11 Rx FIFO overflow count
104 #define CNT5 0x00C0 // Dot11 Tx FIFO underrun count
105
106 // Baseband Control Register
107 #define PWRCSR0 0x00C4
108 #define PSCSR0 0x00C8
109 #define PSCSR1 0x00CC
110 #define PSCSR2 0x00D0
111 #define PSCSR3 0x00D4
112 #define PWRCSR1 0x00D8
113 #define TIMECSR 0x00DC
114 #define MACCSR0 0x00E0
115 #define MACCSR1 0x00E4
116 #define RALINKCSR 0x00E8 // Ralink Auto-reset register
117 #define BCNCSR 0x00EC
118
119 // BBP/RF/IF Control Register
120 #define BBPCSR 0x00F0
121 #define RFCSR 0x00F4
122 #define LEDCSR 0x00F8
123
124 // ASIC pointer information
125 #define RXPTR 0x0100 // Current RX ring address
126 #define TXPTR 0x0104 // Current Tx ring address
127 #define PRIPTR 0x0108 // Current Priority ring address
128 #define ATIMPTR 0x010c // Current ATIM ring address
129
130 // some others
131 #define TXACKCSR0 0x0110 // TX ACK timeout
132 #define ACKCNT0 0x0114 // TX ACK timeout count
133 #define ACKCNT1 0x0118 // RX ACK timeout count
134
135 // GPIO and others
136 #define GPIOCSR 0x0120 // GPIO direction & in/out
137 #define FIFOCSR0 0x0128 // TX FIFO pointer
138 #define FIFOCSR1 0x012C // RX FIFO pointer
139 #define BCNCSR1 0x0130 // Tx BEACON offset time, unit: 1 usec
140 #define MACCSR2 0x0134 // TX_PE to RX_PE delay time, unit: 1 PCI clock cycle
141 #define TESTCSR 0x0138 // TEST mode selection register
142
143 #define PLCP1MCSR 0x013c // 1 Mbps ACK/CTS PLCP
144 #define PLCP2MCSR 0x0140 // 2 Mbps ACK/CTS PLCP
145 #define PLCP5MCSR 0x0144 // 5.5 Mbps ACK/CTS PLCP
146 #define PLCP11MCSR 0x0148 // 11 Mbps ACK/CTS PLCP
147
148 #define ARTCSR0 0x014c // ACK/CTS payload consumed time for 1/2/5.5/11 mbps
149 #define ARTCSR1 0x0150 // OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps
150 #define ARTCSR2 0x0154 // OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps
151 #define SECCSR1 0x0158 // security control register
152 #define BBPCSR1 0x015c // BBP TX configuration
153
154 #define DBANDCSR0 0x0160 // Dual band configuration register 0
155 #define DBANDCSR1 0x0164 // Dual band configuration register 1
156 #define BBPPCSR 0x0168 // BBP pin control register
157 #define DBGSEL0 0x016c // MAC special debug mode selection register 0
158 #define DBGSEL1 0x0170 // MAC special debug mode selection register 1
159 #define BISTCSR 0x0174 // BBP BIST register
160
161 #define MCAST0 0x0178 // multicast filter register 0
162 #define MCAST1 0x017c // multicast filter register 1
163
164 #define UARTCSR0 0x0180 // UART1 TX register
165 #define UARTCSR1 0x0184 // UART1 RX register
166 #define UARTCSR3 0x0188 // UART1 frame control register
167 #define UARTCSR4 0x018c // UART1 buffer control register
168 #define UART2CSR0 0x0190 // UART2 TX register
169 #define UART2CSR1 0x0194 // UART2 RX register
170 #define UART2CSR3 0x0198 // UART2 frame control register
171 #define UART2CSR4 0x019c // UART2 buffer control register
172
173 #define TIMECSR2 0x00a8
174 #define TIMECSR3 0x00b4
175
176 //
177 // Tx / Rx / Prio / Atim ring descriptor definition
178 //
179 #define DESC_OWN_HOST 0
180 #define DESC_OWN_NIC 1
181 #define DESC_VALID_TRUE 1
182 #define DESC_VALID_FALSE 0
183
184 //
185 // BBP & RF definition
186 //
187 #define BUSY 1
188 #define IDLE 0
189
190 #define BBP_Version 0x00
191 #define BBP_Tx_Configure 2 // R2
192 #define BBP_Tx_Tssi 1 // R1
193 #define BBP_Rx_Configure 14 // R14
194
195 #define PHY_TR_SWITCH_TIME 5 // usec
196
197 #define RT2560_VER_B 2
198 #define RT2560_VER_C 3
199 #define RT2560_VER_D 4
200 #define BBP_R17_LOW_SENSIBILITY 0x50
201 #define BBP_R17_MID_SENSIBILITY 0x41
202 #define BBP_R17_DYNAMIC_UP_BOUND 0x40
203 #define RSSI_FOR_LOW_SENSIBILITY -58
204 #define RSSI_FOR_MID_SENSIBILITY -74
205 //#define RSSI_HIGH_WATERMARK -53
206 //#define RSSI_LOW_WATERMARK -58
207
208 //-------------------------------------------------------------------------
209 // EEPROM definition
210 //-------------------------------------------------------------------------
211 #define EEDO 0x10
212 #define EEDI 0x08
213 #define EECS 0x04
214 #define EESK 0x02
215 #define EERL 0x01
216
217 #define EEPROM_WRITE_OPCODE 0x05
218 #define EEPROM_READ_OPCODE 0x06
219 #define EEPROM_EWDS_OPCODE 0x10
220 #define EEPROM_EWEN_OPCODE 0x13
221
222 #define NUM_EEPROM_BBP_PARMS 19
223 #define NUM_EEPROM_TX_PARMS 7
224 #define EEPROM_BBP_BASE_OFFSET 0x20 // 0x16
225 #define EEPROM_TX_PWR_OFFSET 0x46 // 0x3c
226 #define EEPROM_TSSI_REF_OFFSET 0x54
227 #define EEPROM_TSSI_DELTA_OFFSET 0x24
228 #define EEPROM_CALIBRATE_OFFSET 0x7c
229 #define EEPROM_VERSION_OFFSET 0x7e
230 #define VALID_EEPROM_VERSION 1
231
232 // =================================================================================
233 // TX / RX ring descriptor format
234 // =================================================================================
235
236 //
237 // TX descriptor format, Tx ring, Atim ring & Priority Ring
238 //
239 typedef struct _TXD_STRUC {
240 // Word 0
241 #ifdef BIG_ENDIAN
242 ULONG CipherAlg:3;
243 ULONG Rsv1:1; //RTS:1;
244 ULONG DataByteCnt:12;
245 ULONG RetryMd:1;
246 ULONG IFS:2;
247 ULONG CipherOwn:1;
248 ULONG Ofdm:1;
249 ULONG Timestamp:1;
250 ULONG ACK:1;
251 ULONG MoreFrag:1; // More fragment following this tx ring
252 ULONG RetryCount:3; // Retry result
253 ULONG TxResult:3; // Filled by MAC ASIC
254 ULONG Valid:1; // Entry valid bit
255 ULONG Owner:1; // Descriptor owner bit
256 #else
257 ULONG Owner:1; // Descriptor owner bit
258 ULONG Valid:1; // Entry valid bit
259 ULONG TxResult:3; // Filled by MAC ASIC
260 ULONG RetryCount:3; // Retry result
261 ULONG MoreFrag:1; // More fragment following this tx ring
262 ULONG ACK:1;
263 ULONG Timestamp:1;
264 ULONG Ofdm:1;
265 ULONG CipherOwn:1;
266 ULONG IFS:2;
267 ULONG RetryMd:1;
268 ULONG DataByteCnt:12;
269 ULONG Rsv1:1; //RTS:1;
270 ULONG CipherAlg:3;
271 #endif
272
273 // Word 1
274 ULONG BufferAddressPa;
275
276 // Word 2
277 #ifdef BIG_ENDIAN
278 ULONG Rsv2:16;
279 ULONG CWmax:4;
280 ULONG CWmin:4;
281 ULONG Aifs:2;
282 ULONG IvOffset:6;
283 #else
284 ULONG IvOffset:6;
285 ULONG Aifs:2;
286 ULONG CWmin:4;
287 ULONG CWmax:4;
288 ULONG Rsv2:16;
289 #endif
290
291 // Word 3
292 ULONG PlcpSignal:8;
293 ULONG PlcpService:8;
294 ULONG PlcpLengthLow:8;
295 ULONG PlcpLengthHigh:8;
296
297 // Word 4
298 ULONG Iv;
299
300 // Word 5
301 ULONG Eiv;
302
303 // Word 6-9
304 UCHAR Key[16];
305
306 // Word 10 - 11 Reserved, not necessary to put into the structure.
307 #ifdef BIG_ENDIAN
308 ULONG Rsv3:24;
309 ULONG TxRate:7; // for software use to track per-rate TX result, RATE_1, ...
310 ULONG RTS:1;
311 #else
312 ULONG RTS:1;
313 ULONG TxRate:7; // software use only. keep record of the Tx rate, RATE_1,...
314 ULONG Rsv3:24;
315 #endif
316 } TXD_STRUC, *PTXD_STRUC;
317
318 //
319 // Rx descriptor format, Rx Ring
320 //
321 typedef struct _RXD_STRUC {
322 // Word 0
323 #ifdef BIG_ENDIAN
324 ULONG CipherAlg:3;
325 ULONG Rsv1:1; // Drop:1; // Drop this frame after NULL cipher operation
326 ULONG DataByteCnt:12;
327 ULONG IvOffset:6;
328 ULONG IcvError:1;
329 ULONG CipherOwner:1;
330 ULONG PhyErr:1;
331 ULONG Ofdm:1;
332 ULONG Crc:1;
333 ULONG MyBss:1;
334 ULONG Bcast:1;
335 ULONG Mcast:1;
336 ULONG U2M:1;
337 ULONG Owner:1;
338 #else
339 ULONG Owner:1;
340 ULONG U2M:1;
341 ULONG Mcast:1;
342 ULONG Bcast:1;
343 ULONG MyBss:1;
344 ULONG Crc:1;
345 ULONG Ofdm:1;
346 ULONG PhyErr:1;
347 ULONG CipherOwner:1;
348 ULONG IcvError:1;
349 ULONG IvOffset:6;
350 ULONG DataByteCnt:12;
351 ULONG Rsv1:1; // Drop:1; // Drop this frame after NULL cipher operation
352 ULONG CipherAlg:3;
353 #endif
354
355 // Word 1
356 ULONG BufferAddressPa;
357
358 // Word 2 - 3
359 UCHAR BBR0;
360 UCHAR BBR1; // suppose to read back RSSI
361 UCHAR TA[6];
362
363 // Word 4
364 ULONG Iv;
365
366 // Word 5
367 ULONG Eiv;
368
369 // Word 6-9
370 UCHAR Key[16];
371
372 // Word 10 - 11 Reserved, not necessary to put into the structure.
373 #ifdef BIG_ENDIAN
374 ULONG Rsv2:31;
375 ULONG Drop:1;
376 #else
377 ULONG Drop:1;
378 ULONG Rsv2:31;
379 #endif
380 } RXD_STRUC, *PRXD_STRUC;
381
382 // =================================================================================
383 // CSR Registers
384 // =================================================================================
385
386 //
387 // CSR1: System control register
388 //
389 typedef union _CSR1_STRUC {
390 struct {
391 #ifdef BIG_ENDIAN
392 ULONG Rsvd1:29;
393 ULONG HostReady:1; // Host is ready after initialization, 1: ready
394 ULONG BbpReset:1; // Hardware reset BBP
395 ULONG SoftReset:1; // Software reset bit, 1: reset, 0: normal
396 #else
397 ULONG SoftReset:1; // Software reset bit, 1: reset, 0: normal
398 ULONG BbpReset:1; // Hardware reset BBP
399 ULONG HostReady:1; // Host is ready after initialization, 1: ready
400 ULONG Rsvd1:29;
401 #endif
402 } field;
403 ULONG word;
404 } CSR1_STRUC, *PCSR1_STRUC;
405
406 //
407 // CSR3: STA MAC register 0
408 //
409 typedef union _CSR3_STRUC {
410 struct {
411 #ifdef BIG_ENDIAN
412 UCHAR Byte3; // MAC address byte 3
413 UCHAR Byte2; // MAC address byte 2
414 UCHAR Byte1; // MAC address byte 1
415 UCHAR Byte0; // MAC address byte 0
416 #else
417 UCHAR Byte0; // MAC address byte 0
418 UCHAR Byte1; // MAC address byte 1
419 UCHAR Byte2; // MAC address byte 2
420 UCHAR Byte3; // MAC address byte 3
421 #endif
422 } field;
423 ULONG word;
424 } CSR3_STRUC, *PCSR3_STRUC;
425
426 //
427 // CSR4: STA MAC register 1
428 //
429 typedef union _CSR4_STRUC {
430 struct {
431 #ifdef BIG_ENDIAN
432 UCHAR Rsvd1;
433 UCHAR Rsvd0;
434 UCHAR Byte5; // MAC address byte 5
435 UCHAR Byte4; // MAC address byte 4
436 #else
437 UCHAR Byte4; // MAC address byte 4
438 UCHAR Byte5; // MAC address byte 5
439 UCHAR Rsvd0;
440 UCHAR Rsvd1;
441 #endif
442 } field;
443 ULONG word;
444 } CSR4_STRUC, *PCSR4_STRUC;
445
446 //
447 // CSR5: BSSID register 0
448 //
449 typedef union _CSR5_STRUC {
450 struct {
451 #ifdef BIG_ENDIAN
452 UCHAR Byte3; // BSSID byte 3
453 UCHAR Byte2; // BSSID byte 2
454 UCHAR Byte1; // BSSID byte 1
455 UCHAR Byte0; // BSSID byte 0
456 #else
457 UCHAR Byte0; // BSSID byte 0
458 UCHAR Byte1; // BSSID byte 1
459 UCHAR Byte2; // BSSID byte 2
460 UCHAR Byte3; // BSSID byte 3
461 #endif
462 } field;
463 ULONG word;
464 } CSR5_STRUC, *PCSR5_STRUC;
465
466 //
467 // CSR6: BSSID register 1
468 //
469 typedef union _CSR6_STRUC {
470 struct {
471 #ifdef BIG_ENDIAN
472 UCHAR Rsvd1;
473 UCHAR Rsvd0;
474 UCHAR Byte5; // BSSID byte 5
475 UCHAR Byte4; // BSSID byte 4
476 #else
477 UCHAR Byte4; // BSSID byte 4
478 UCHAR Byte5; // BSSID byte 5
479 UCHAR Rsvd0;
480 UCHAR Rsvd1;
481 #endif
482 } field;
483 ULONG word;
484 } CSR6_STRUC, *PCSR6_STRUC;
485
486 //
487 // CSR7: Interrupt source register
488 // Write one to clear corresponding bit
489 //
490 typedef union _CSR7_STRUC {
491 struct {
492 #ifdef BIG_ENDIAN
493 ULONG Rsvd:12;
494 ULONG Timecsr3Expired:1; // TIMECSR3 hardware timer expired (for 802.1H quiet period)
495 ULONG Uart2RxBufferError:1; // UART2 RX buffer error
496 ULONG Uart2TxBufferError:1; // UART2 TX buffer error
497 ULONG Uart2IdleThreshold:1; // UART2 IDLE over threshold
498 ULONG Uart2RxThreshold:1; // UART2 RX reaches threshold
499 ULONG Uart2TxThreshold:1; // UART2 TX reaches threshold
500 ULONG UartRxBufferError:1; // UART1 RX buffer error
501 ULONG UartTxBufferError:1; // UART1 TX buffer error
502 ULONG UartIdleThreshold:1; // UART1 IDLE over threshold
503 ULONG UartRxThreshold:1; // UART1 RX reaches threshold
504 ULONG UartTxThreshold:1; // UART1 TX reaches threshold
505 ULONG EncryptionDone:1; // Encryption done interrupt
506 ULONG DecryptionDone:1; // Decryption done interrupt
507 ULONG RxDone:1; // Receive done interrupt
508 ULONG PrioRingTxDone:1; // Priority ring transmit done interrupt
509 ULONG AtimRingTxDone:1; // Atim ring transmit done interrupt
510 ULONG TxRingTxDone:1; // Tx ring transmit done interrupt
511 ULONG TatimwExpire:1; // Timer of atim window expired interrupt
512 ULONG TwakeExpire:1; // Wakeup timer expired interrupt
513 ULONG TbcnExpire:1; // Beacon timer expired interrupt
514 #else
515 ULONG TbcnExpire:1; // Beacon timer expired interrupt
516 ULONG TwakeExpire:1; // Wakeup timer expired interrupt
517 ULONG TatimwExpire:1; // Timer of atim window expired interrupt
518 ULONG TxRingTxDone:1; // Tx ring transmit done interrupt
519 ULONG AtimRingTxDone:1; // Atim ring transmit done interrupt
520 ULONG PrioRingTxDone:1; // Priority ring transmit done interrupt
521 ULONG RxDone:1; // Receive done interrupt
522 ULONG DecryptionDone:1; // Decryption done interrupt
523 ULONG EncryptionDone:1; // Encryption done interrupt
524 ULONG UartTxThreshold:1; // UART1 TX reaches threshold
525 ULONG UartRxThreshold:1; // UART1 RX reaches threshold
526 ULONG UartIdleThreshold:1; // UART1 IDLE over threshold
527 ULONG UartTxBufferError:1; // UART1 TX buffer error
528 ULONG UartRxBufferError:1; // UART1 RX buffer error
529 ULONG Uart2TxThreshold:1; // UART2 TX reaches threshold
530 ULONG Uart2RxThreshold:1; // UART2 RX reaches threshold
531 ULONG Uart2IdleThreshold:1; // UART2 IDLE over threshold
532 ULONG Uart2TxBufferError:1; // UART2 TX buffer error
533 ULONG Uart2RxBufferError:1; // UART2 RX buffer error
534 ULONG Timecsr3Expired:1; // TIMECSR3 hardware timer expired (for 802.1H quiet period)
535 ULONG Rsvd:12;
536 #endif
537 } field;
538 ULONG word;
539 } CSR7_STRUC, *PCSR7_STRUC, INTSRC_STRUC, *PINTSRC_STRUC;
540
541 //
542 // CSR8: Interrupt Mask register
543 // Write one to mask off interrupt
544 //
545 typedef union _CSR8_STRUC {
546 struct {
547 #ifdef BIG_ENDIAN
548 ULONG Rsvd:12;
549 ULONG Timecsr3Expired:1; // TIMECSR3 hardware timer expired (for 802.1H quiet period)
550 ULONG Uart2RxBufferError:1; // UART2 RX buffer error
551 ULONG Uart2TxBufferError:1; // UART2 TX buffer error
552 ULONG Uart2IdleThreshold:1; // UART2 IDLE over threshold
553 ULONG Uart2RxThreshold:1; // UART2 RX reaches threshold
554 ULONG Uart2TxThreshold:1; // UART2 TX reaches threshold
555 ULONG UartRxBufferError:1; // UART1 RX buffer error
556 ULONG UartTxBufferError:1; // UART1 TX buffer error
557 ULONG UartIdleThreshold:1; // UART1 IDLE over threshold
558 ULONG UartRxThreshold:1; // UART1 RX reaches threshold
559 ULONG UartTxThreshold:1; // UART1 TX reaches threshold
560 ULONG EncryptionDone:1; // Encryption done interrupt
561 ULONG DecryptionDone:1; // Decryption done interrupt
562 ULONG RxDone:1; // Receive done interrupt mask
563 ULONG PrioRingTxDone:1; // Priority ring transmit done interrupt mask
564 ULONG AtimRingTxDone:1; // Atim ring transmit done interrupt mask
565 ULONG TxRingTxDone:1; // Tx ring transmit done interrupt mask
566 ULONG TatimwExpire:1; // Timer of atim window expired interrupt mask
567 ULONG TwakeExpire:1; // Wakeup timer expired interrupt mask
568 ULONG TbcnExpire:1; // Beacon timer expired interrupt mask
569 #else
570 ULONG TbcnExpire:1; // Beacon timer expired interrupt mask
571 ULONG TwakeExpire:1; // Wakeup timer expired interrupt mask
572 ULONG TatimwExpire:1; // Timer of atim window expired interrupt mask
573 ULONG TxRingTxDone:1; // Tx ring transmit done interrupt mask
574 ULONG AtimRingTxDone:1; // Atim ring transmit done interrupt mask
575 ULONG PrioRingTxDone:1; // Priority ring transmit done interrupt mask
576 ULONG RxDone:1; // Receive done interrupt mask
577 ULONG DecryptionDone:1; // Decryption done interrupt
578 ULONG EncryptionDone:1; // Encryption done interrupt
579 ULONG UartTxThreshold:1; // UART1 TX reaches threshold
580 ULONG UartRxThreshold:1; // UART1 RX reaches threshold
581 ULONG UartIdleThreshold:1; // UART1 IDLE over threshold
582 ULONG UartTxBufferError:1; // UART1 TX buffer error
583 ULONG UartRxBufferError:1; // UART1 RX buffer error
584 ULONG Uart2TxThreshold:1; // UART2 TX reaches threshold
585 ULONG Uart2RxThreshold:1; // UART2 RX reaches threshold
586 ULONG Uart2IdleThreshold:1; // UART2 IDLE over threshold
587 ULONG Uart2TxBufferError:1; // UART2 TX buffer error
588 ULONG Uart2RxBufferError:1; // UART2 RX buffer error
589 ULONG Timecsr3Expired:1; // TIMECSR3 hardware timer expired (for 802.1H quiet period)
590 ULONG Rsvd:12;
591 #endif
592 } field;
593 ULONG word;
594 } CSR8_STRUC, *PCSR8_STRUC, INTMSK_STRUC, *PINTMSK_STRUC;
595
596 //
597 // CSR9: Maximum frame length register
598 //
599 typedef union _CSR9_STRUC {
600 struct {
601 #ifdef BIG_ENDIAN
602 ULONG Rsvd1:20;
603 ULONG MaxFrameUnit:5; // Maximum frame legth in 128B unit, default is 12 = 0xC.
604 ULONG Rsvd0:7;
605 #else
606 ULONG Rsvd0:7;
607 ULONG MaxFrameUnit:5; // Maximum frame legth in 128B unit, default is 12 = 0xC.
608 ULONG Rsvd1:20;
609 #endif
610 } field;
611 ULONG word;
612 } CSR9_STRUC, *PCSR9_STRUC;
613
614 //
615 // SECCSR0: WEP control register
616 //
617 typedef union _SECCSR0_STRUC {
618 struct {
619 #ifdef BIG_ENDIAN
620 ULONG DescAddress:30; // Descriptor physical address of frame in one-shot-mode.
621 ULONG OneShotMode:1; // 1: One shot only mode, 0: ring mode
622 ULONG KickDecypt:1; // Kick decryption engine, self-clear
623 #else
624 ULONG KickDecypt:1; // Kick decryption engine, self-clear
625 ULONG OneShotMode:1; // 1: One shot only mode, 0: ring mode
626 ULONG DescAddress:30; // Descriptor physical address of frame in one-shot-mode.
627 #endif
628 } field;
629 ULONG word;
630 } SECCSR0_STRUC, *PSECCSR0_STRUC;
631
632 //
633 // SECCSR1: WEP control register
634 //
635 typedef union _SECCSR1_STRUC {
636 struct {
637 #ifdef BIG_ENDIAN
638 ULONG DescAddress:30; // Descriptor physical address of frame in one-shot-mode.
639 ULONG OneShotMode:1; // 1: One shot only mode, 0: ring mode
640 ULONG KickEncypt:1; // Kick encryption engine, self-clear
641 #else
642 ULONG KickEncypt:1; // Kick encryption engine, self-clear
643 ULONG OneShotMode:1; // 1: One shot only mode, 0: ring mode
644 ULONG DescAddress:30; // Descriptor physical address of frame in one-shot-mode.
645 #endif
646 } field;
647 ULONG word;
648 } SECCSR1_STRUC, *PSECCSR1_STRUC;
649
650 //
651 // CSR11: Back-Off control register
652 //
653 typedef union _CSR11_STRUC {
654 struct {
655 #ifdef BIG_ENDIAN
656 ULONG ShortRetry:8; // Short retry count
657 ULONG LongRetry:8; // Long retry count
658 ULONG Rsvd:2;
659 ULONG CWSelect:1; // 1: CWmin/CWmax select from register, 0: select from TxD
660 ULONG SlotTime:5; // Slot time, default is 20us for 802.11B
661 ULONG CWMax:4; // Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
662 ULONG CWMin:4; // Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
663 #else
664 ULONG CWMin:4; // Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
665 ULONG CWMax:4; // Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
666 ULONG SlotTime:5; // Slot time, default is 20us for 802.11B
667 ULONG CWSelect:1; // 1: CWmin/Cwmax select from register, 0:select from TxD
668 ULONG Rsvd:2;
669 ULONG LongRetry:8; // Long retry count
670 ULONG ShortRetry:8; // Short retry count
671 #endif
672 } field;
673 ULONG word;
674 } CSR11_STRUC, *PCSR11_STRUC;
675
676 //
677 // CSR12: Synchronization configuration register 0
678 // All uint in 1/16 TU
679 //
680 typedef union _CSR12_STRUC {
681 struct {
682 #ifdef BIG_ENDIAN
683 ULONG CfpMaxDuration:16; // Beacon interval, default is 100 TU
684 ULONG BeaconInterval:16; // CFP maximum duration, default is 100 TU
685 #else
686 ULONG BeaconInterval:16; // CFP maximum duration, default is 100 TU
687 ULONG CfpMaxDuration:16; // Beacon interval, default is 100 TU
688 #endif
689 } field;
690 ULONG word;
691 } CSR12_STRUC, *PCSR12_STRUC;
692
693 //
694 // CSR13: Synchronization configuration register 1
695 // All uint in 1/16 TU
696 //
697 typedef union _CSR13_STRUC {
698 struct {
699 #ifdef BIG_ENDIAN
700 ULONG Rsvd:8;
701 ULONG CfpPeriod:8; // CFP period, default is 0 TU
702 ULONG AtimwDuration:16; // ATIM window duration, default is 10 TU
703 #else
704 ULONG AtimwDuration:16; // ATIM window duration, default is 10 TU
705 ULONG CfpPeriod:8; // CFP period, default is 0 TU
706 ULONG Rsvd:8;
707 #endif
708 } field;
709 ULONG word;
710 } CSR13_STRUC, *PCSR13_STRUC;
711
712 //
713 // CSR14: Synchronization control register
714 //
715 typedef union _CSR14_STRUC {
716 struct {
717 #ifdef BIG_ENDIAN
718 ULONG TbcnPreload:16; // Tbcn preload value
719 ULONG CfpCntPreload:8; // Cfp count preload value
720 ULONG Rsvd:1;
721 ULONG BeaconGen:1; // Enable beacon generator
722 ULONG Tatimw:1; // Enable Tatimw & ATIM window switching
723 ULONG Tcfp:1; // Enable Tcfp & CFP / CP switching
724 ULONG Tbcn:1; // Enable Tbcn with reload value
725 ULONG TsfSync:2; // Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
726 ULONG TsfCount:1; // Enable TSF auto counting
727 #else
728 ULONG TsfCount:1; // Enable TSF auto counting
729 ULONG TsfSync:2; // Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
730 ULONG Tbcn:1; // Enable Tbcn with reload value
731 ULONG Tcfp:1; // Enable Tcfp & CFP / CP switching
732 ULONG Tatimw:1; // Enable Tatimw & ATIM window switching
733 ULONG BeaconGen:1; // Enable beacon generator
734 ULONG Rsvd:1;
735 ULONG CfpCntPreload:8; // Cfp count preload value
736 ULONG TbcnPreload:16; // Tbcn preload value
737 #endif
738 } field;
739 ULONG word;
740 } CSR14_STRUC, *PCSR14_STRUC;
741
742 //
743 // CSR15: Synchronization status register
744 //
745 typedef union _CSR15_STRUC {
746 struct {
747 #ifdef BIG_ENDIAN
748 ULONG Rsvd:29;
749 ULONG BeaconSent:1; // Beacon sent
750 ULONG Atimw:1; // Atim window period
751 ULONG Cfp:1; // CFP period
752 #else
753 ULONG Cfp:1; // CFP period
754 ULONG Atimw:1; // Atim window period
755 ULONG BeaconSent:1; // Beacon sent
756 ULONG Rsvd:29;
757 #endif
758 } field;
759 ULONG word;
760 } CSR15_STRUC, *PCSR15_STRUC;
761
762 //
763 // CSR18: IFS Timer register 0
764 //
765 typedef union _CSR18_STRUC {
766 struct {
767 #ifdef BIG_ENDIAN
768 ULONG Rsvd1:7;
769 ULONG PIFS:9; // PIFS, default is 30 TU
770 ULONG Rsvd0:7;
771 ULONG SIFS:9; // SIFS, default is 10 TU
772 #else
773 ULONG SIFS:9; // SIFS, default is 10 TU
774 ULONG Rsvd0:7;
775 ULONG PIFS:9; // PIFS, default is 30 TU
776 ULONG Rsvd1:7;
777 #endif
778 } field;
779 ULONG word;
780 } CSR18_STRUC, *PCSR18_STRUC;
781
782 //
783 // CSR19: IFS Timer register 1
784 //
785 typedef union _CSR19_STRUC {
786 struct {
787 #ifdef BIG_ENDIAN
788 ULONG EIFS:16; // EIFS, default is 364 TU
789 ULONG DIFS:16; // DIFS, default is 50 TU
790 #else
791 ULONG DIFS:16; // DIFS, default is 50 TU
792 ULONG EIFS:16; // EIFS, default is 364 TU
793 #endif
794 } field;
795 ULONG word;
796 } CSR19_STRUC, *PCSR19_STRUC;
797
798 //
799 // CSR20: Wakeup timer register
800 //
801 typedef union _CSR20_STRUC {
802 struct {
803 #ifdef BIG_ENDIAN
804 ULONG Rsvd:7;
805 ULONG AutoWake:1; // Enable auto wakeup / sleep mechanism
806 ULONG NumBcnBeforeWakeup:8; // Number of beacon before wakeup
807 ULONG DelayAfterBcn:16; // Delay after Tbcn expired in units of 1/16 TU
808 #else
809 ULONG DelayAfterBcn:16; // Delay after Tbcn expired in units of 1/16 TU
810 ULONG NumBcnBeforeWakeup:8; // Number of beacon before wakeup
811 ULONG AutoWake:1; // Enable auto wakeup / sleep mechanism
812 ULONG Rsvd:7;
813 #endif
814 } field;
815 ULONG word;
816 } CSR20_STRUC, *PCSR20_STRUC;
817
818 //
819 // CSR21: EEPROM control register
820 //
821 typedef union _CSR21_STRUC {
822 struct {
823 #ifdef BIG_ENDIAN
824 ULONG Rsvd:26;
825 ULONG Type:1; // 1: 93C46, 0:93C66
826 ULONG EepromDO:1;
827 ULONG EepromDI:1;
828 ULONG EepromCS:1;
829 ULONG EepromSK:1;
830 ULONG Reload:1; // Reload EEPROM content, write one to reload, self-cleared.
831 #else
832 ULONG Reload:1; // Reload EEPROM content, write one to reload, self-cleared.
833 ULONG EepromSK:1;
834 ULONG EepromCS:1;
835 ULONG EepromDI:1;
836 ULONG EepromDO:1;
837 ULONG Type:1; // 1: 93C46, 0:93C66
838 ULONG Rsvd:26;
839 #endif
840 } field;
841 ULONG word;
842 } CSR21_STRUC, *PCSR21_STRUC;
843
844 //
845 // CSR22: CFP control register
846 //
847 typedef union _CSR22_STRUC {
848 struct {
849 #ifdef BIG_ENDIAN
850 ULONG Rsvd:15;
851 ULONG ReloadCfpDurRemain:1; // Reload CFP duration remain, write one to reload, self-cleared
852 ULONG CfpDurRemain:16; // CFP duration remain, in units of TU
853 #else
854 ULONG CfpDurRemain:16; // CFP duration remain, in units of TU
855 ULONG ReloadCfpDurRemain:1; // Reload CFP duration remain, write one to reload, self-cleared
856 ULONG Rsvd:15;
857 #endif
858 } field;
859 ULONG word;
860 } CSR22_STRUC, *PCSR22_STRUC;
861
862 // =================================================================================
863 // TX / RX Registers
864 // =================================================================================
865
866 //
867 // TXCSR0 <0x0060> : TX Control Register
868 //
869 typedef union _TXCSR0_STRUC {
870 struct {
871 #ifdef BIG_ENDIAN
872 ULONG Rsvd:28;
873 ULONG Abort:1; // Abort all transmit related ring operation
874 ULONG KickPrio:1; // Kick priority ring
875 ULONG KickAtim:1; // Kick ATIM ring
876 ULONG KickTx:1; // Kick Tx ring
877 #else
878 ULONG KickTx:1; // Kick Tx ring
879 ULONG KickAtim:1; // Kick ATIM ring
880 ULONG KickPrio:1; // Kick priority ring
881 ULONG Abort:1; // Abort all transmit related ring operation
882 ULONG Rsvd:28;
883 #endif
884 } field;
885 ULONG word;
886 } TXCSR0_STRUC, *PTXCSR0_STRUC;
887
888 //
889 // TXCSR1 <0x0064> : TX Configuration Register
890 //
891 typedef union _TXCSR1_STRUC {
892 struct {
893 #ifdef BIG_ENDIAN
894 ULONG Reserved:7;
895 ULONG AutoResponder:1; // enable auto responder which include ACK & CTS
896 ULONG TsFOffset:6; // Insert Tsf offset
897 ULONG AckConsumeTime:9; // ACK consume time, default = SIFS + ACKtime @ 1Mbps
898 ULONG AckTimeOut:9; // Ack timeout, default = SIFS + 2*SLOT_ACKtime @ 1Mbps
899 #else
900 ULONG AckTimeOut:9; // Ack timeout, default = SIFS + 2*SLOT_ACKtime @ 1Mbps
901 ULONG AckConsumeTime:9; // ACK consume time, default = SIFS + ACKtime @ 1Mbps
902 ULONG TsFOffset:6; // Insert Tsf offset
903 ULONG AutoResponder:1; // enable auto responder which include ACK & CTS
904 ULONG Reserved:7;
905 #endif
906 } field;
907 ULONG word;
908 } TXCSR1_STRUC, *PTXCSR1_STRUC;
909
910 //
911 // TXCSR2: Tx descriptor configuration register
912 //
913 typedef union _TXCSR2_STRUC {
914 struct {
915 #ifdef BIG_ENDIAN
916 ULONG NumPrioD:8; // Number of PriorityD in ring
917 ULONG NumAtimD:8; // Number of AtimD in ring
918 ULONG NumTxD:8; // Number of TxD in ring
919 ULONG TxDSize:8; // Tx descriptor size, default is 48
920 #else
921 ULONG TxDSize:8; // Tx descriptor size, default is 48
922 ULONG NumTxD:8; // Number of TxD in ring
923 ULONG NumAtimD:8; // Number of AtimD in ring
924 ULONG NumPrioD:8; // Number of PriorityD in ring
925 #endif
926 } field;
927 ULONG word;
928 } TXCSR2_STRUC, *PTXCSR2_STRUC;
929
930 //
931 // TXCSR7: Auto responder control register
932 //
933 typedef union _TXCSR7_STRUC {
934 struct {
935 #ifdef BIG_ENDIAN
936 ULONG Rsvd:31;
937 ULONG ARPowerManage:1; // Auto responder power management bit
938 #else
939 ULONG ARPowerManage:1; // Auto responder power management bit
940 ULONG Rsvd:31;
941 #endif
942 } field;
943 ULONG word;
944 } TXCSR7_STRUC, *PTXCSR7_STRUC;
945
946 //
947 // TXCSR8: CCK Tx BBP register
948 //
949 typedef union _TXCSR8_STRUC {
950 struct {
951 #ifdef BIG_ENDIAN
952 ULONG CckLenHigh:8; // BBP length high byte address for CCK
953 ULONG CckLenLow:8; // BBP length low byte address for CCK
954 ULONG CckService:8; // BBP service field address for CCK
955 ULONG CckSignal:8; // BBP signal field address for CCK
956 #else
957 ULONG CckSignal:8; // BBP signal field address for CCK
958 ULONG CckService:8; // BBP service field address for CCK
959 ULONG CckLenLow:8; // BBP length low byte address for CCK
960 ULONG CckLenHigh:8; // BBP length high byte address for CCK
961 #endif
962 } field;
963 ULONG word;
964 } TXCSR8_STRUC, *PTXCSR8_STRUC;
965
966 //
967 // TXCSR9: OFDM Tx BBP register
968 //
969 typedef union _TXCSR9_STRUC {
970 struct {
971 #ifdef BIG_ENDIAN
972 ULONG OfdmLenHigh:8; // BBP length high byte address for OFDM
973 ULONG OfdmLenLow:8; // BBP length low byte address for OFDM
974 ULONG OfdmService:8; // BBP service field address for OFDM
975 ULONG OfdmRate:8; // BBP rate field address for OFDM
976 #else
977 ULONG OfdmRate:8; // BBP rate field address for OFDM
978 ULONG OfdmService:8; // BBP service field address for OFDM
979 ULONG OfdmLenLow:8; // BBP length low byte address for OFDM
980 ULONG OfdmLenHigh:8; // BBP length high byte address for OFDM
981 #endif
982 } field;
983 ULONG word;
984 } TXCSR9_STRUC, *PTXCSR9_STRUC;
985
986 //
987 // RXCSR0 <0x0080> : RX Control Register
988 //
989 typedef union _RXCSR0_STRUC {
990 struct {
991 #ifdef BIG_ENDIAN
992 ULONG Reserved:20;
993 ULONG EnableQos:1; // 1: accept QOS data frame format and parse the QOS field
994 ULONG DropBcast:1; // Drop broadcast frames
995 ULONG DropMcast:1; // Drop multicast frames
996 ULONG PassPlcp:1; // Pass all receive packet with 4 bytes PLCP attached
997 ULONG PassCRC:1; // Pass all receive packet to host with CRC attached
998 ULONG DropVersionErr:1; // Drop version error frame
999 ULONG DropToDs:1; // Drop fram ToDs bit is true
1000 ULONG DropNotToMe:1; // Drop not to me unicast frame
1001 ULONG DropControl:1; // Drop control frame
1002 ULONG DropPhysical:1; // Drop physical error
1003 ULONG DropCRC:1; // Drop CRC error
1004 ULONG DisableRx:1; // Disable Rx engine
1005 #else
1006 ULONG DisableRx:1; // Disable Rx engine
1007 ULONG DropCRC:1; // Drop CRC error
1008 ULONG DropPhysical:1; // Drop physical error
1009 ULONG DropControl:1; // Drop control frame
1010 ULONG DropNotToMe:1; // Drop not to me unicast frame
1011 ULONG DropToDs:1; // Drop fram ToDs bit is true
1012 ULONG DropVersionErr:1; // Drop version error frame
1013 ULONG PassCRC:1; // Pass all receive packet to host with CRC attached
1014 ULONG PassPlcp:1; // Pass all receive packet with 4 bytes PLCP attached
1015 ULONG DropMcast:1; // Drop multicast frames
1016 ULONG DropBcast:1; // Drop broadcast frames
1017 ULONG EnableQos:1; // 1: accept QOS data frame format and parse the QOS field
1018 ULONG Reserved:20;
1019 #endif
1020 } field;
1021 ULONG word;
1022 } RXCSR0_STRUC, *PRXCSR0_STRUC;
1023
1024 //
1025 // RXCSR1: RX descriptor configuration register
1026 //
1027 typedef union _RXCSR1_STRUC {
1028 struct {
1029 #ifdef BIG_ENDIAN
1030 ULONG Rsvd:16;
1031 ULONG NumRxD:8; // Number of RxD in ring.
1032 ULONG RxDSize:8; // Rx descriptor size, default is 32B.
1033 #else
1034 ULONG RxDSize:8; // Rx descriptor size, default is 32B.
1035 ULONG NumRxD:8; // Number of RxD in ring.
1036 ULONG Rsvd:16;
1037 #endif
1038 } field;
1039 ULONG word;
1040 } RXCSR1_STRUC, *PRXCSR1_STRUC;
1041
1042 //
1043 // RXCSR3: BBP ID register for Rx operation
1044 //
1045 typedef union _RXCSR3_STRUC {
1046 struct {
1047 #ifdef BIG_ENDIAN
1048 ULONG ValidBbp3:1; // BBP register 3 ID is valid or not
1049 ULONG IdBbp3:7; // BBP register 3 ID
1050 ULONG ValidBbp2:1; // BBP register 2 ID is valid or not
1051 ULONG IdBbp2:7; // BBP register 2 ID
1052 ULONG ValidBbp1:1; // BBP register 1 ID is valid or not
1053 ULONG IdBbp1:7; // BBP register 1 ID
1054 ULONG ValidBbp0:1; // BBP register 0 ID is valid or not
1055 ULONG IdBbp0:7; // BBP register 0 ID
1056 #else
1057 ULONG IdBbp0:7; // BBP register 0 ID
1058 ULONG ValidBbp0:1; // BBP register 0 ID is valid or not
1059 ULONG IdBbp1:7; // BBP register 1 ID
1060 ULONG ValidBbp1:1; // BBP register 1 ID is valid or not
1061 ULONG IdBbp2:7; // BBP register 2 ID
1062 ULONG ValidBbp2:1; // BBP register 2 ID is valid or not
1063 ULONG IdBbp3:7; // BBP register 3 ID
1064 ULONG ValidBbp3:1; // BBP register 3 ID is valid or not
1065 #endif
1066 } field;
1067 ULONG word;
1068 } RXCSR3_STRUC, *PRXCSR3_STRUC;
1069 #if 0
1070 //
1071 // RXCSR4: BBP ID register for Rx operation
1072 //
1073 typedef union _RXCSR4_STRUC {
1074 struct {
1075 ULONG IdBbp4:7; // BBP register 4 ID
1076 ULONG ValidBbp4:1; // BBP register 4 ID is valid or not
1077 ULONG IdBbp5:7; // BBP register 5 ID
1078 ULONG ValidBbp5:1; // BBP register 5 ID is valid or not
1079 ULONG Rsvd:16;
1080 } field;
1081 ULONG word;
1082 } RXCSR4_STRUC, *PRXCSR4_STRUC;
1083
1084 //
1085 // ARCSR0: Auto Responder PLCP value register 0
1086 //
1087 typedef union _ARCSR0_STRUC {
1088 struct {
1089 ULONG ArBbpData0:8; // Auto responder BBP register 0 data
1090 ULONG ArBbpId0:8; // Auto responder BBP register 0 Id
1091 ULONG ArBbpData1:8; // Auto responder BBP register 1 data
1092 ULONG ArBbpId1:8; // Auto responder BBP register 1 Id
1093 } field;
1094 ULONG word;
1095 } ARCSR0_STRUC, *PARCSR0_STRUC;
1096
1097 //
1098 // ARCSR0: Auto Responder PLCP value register 1
1099 //
1100 typedef union _ARCSR1_STRUC {
1101 struct {
1102 ULONG ArBbpData2:8; // Auto responder BBP register 2 data
1103 ULONG ArBbpId2:8; // Auto responder BBP register 2 Id
1104 ULONG ArBbpData3:8; // Auto responder BBP register 3 data
1105 ULONG ArBbpId3:8; // Auto responder BBP register 3 Id
1106 } field;
1107 ULONG word;
1108 } ARCSR1_STRUC, *PARCSR1_STRUC;
1109 #endif
1110 // =================================================================================
1111 // Miscellaneous Registers
1112 // =================================================================================
1113
1114 //
1115 // PCISR: PCI control register
1116 //
1117 typedef union _PCICSR_STRUC {
1118 struct {
1119 #ifdef BIG_ENDIAN
1120 ULONG Rsvd:22;
1121 ULONG WriteInvalid:1; // Enable memory write & invalid
1122 ULONG ReadMultiple:1; // Enable memory read multiple
1123 ULONG EnableClk:1; // Enable CLK_RUN, PCI clock can't going down to non-operational
1124 ULONG BurstLength:2; // PCI burst length
1125 // 01: 8DW, 10: 16DW, 11:32DW, default 00: 4DW
1126 ULONG TxThreshold:2; // Tx threshold in DW to start PCI access
1127 // 01: 1DW, 10: 4DW, 11: store & forward, default 00: 0DW
1128 ULONG RxThreshold:2; // Rx threshold in DW to start PCI access
1129 // 01: 8DW, 10: 4DW, 11: 32DW, default 00: 16DW
1130 ULONG BigEndian:1; // 1: big endian, 0: little endian
1131 #else
1132 ULONG BigEndian:1; // 1: big endian, 0: little endian
1133 ULONG RxThreshold:2; // Rx threshold in DW to start PCI access
1134 // 01: 8DW, 10: 4DW, 11: 32DW, default 00: 16DW
1135 ULONG TxThreshold:2; // Tx threshold in DW to start PCI access
1136 // 01: 1DW, 10: 4DW, 11: store & forward, default 00: 0DW
1137 ULONG BurstLength:2; // PCI burst length
1138 // 01: 8DW, 10: 16DW, 11:32DW, default 00: 4DW
1139 ULONG EnableClk:1; // Enable CLK_RUN, PCI clock can't going down to non-operational
1140 ULONG ReadMultiple:1; // Enable memory read multiple
1141 ULONG WriteInvalid:1; // Enable memory write & invalid
1142 ULONG Rsvd:22;
1143 #endif
1144 } field;
1145 ULONG word;
1146 } PCICSR_STRUC, *PPCICSR_STRUC;
1147
1148 //
1149 // PWRCSR0: Power mode configuration register
1150 // Driver did not control it for now.
1151
1152 //
1153 // PSCSR0: Power saving delay time register 0
1154 // Driver did not control it for now.
1155
1156 //
1157 // PSCSR1: Power saving delay time register 1
1158 // Driver did not control it for now.
1159
1160 //
1161 // PSCSR2: Power saving delay time register 2
1162 // Driver did not control it for now.
1163
1164 //
1165 // PSCSR3: Power saving delay time register 3
1166 // Driver did not control it for now.
1167
1168 //
1169 // PWRCSR1: Manual power control / status register
1170 //
1171 typedef union _PWRCSR1_STRUC {
1172 struct {
1173 #ifdef BIG_ENDIAN
1174 ULONG Rsvd:22;
1175 ULONG PutToSleep:1;
1176 ULONG RfCurrState:2;
1177 ULONG BbpCurrState:2;
1178 ULONG RfDesireState:2;
1179 ULONG BbpDesireState:2;
1180 ULONG SetState:1;
1181 #else
1182 ULONG SetState:1;
1183 ULONG BbpDesireState:2;
1184 ULONG RfDesireState:2;
1185 ULONG BbpCurrState:2;
1186 ULONG RfCurrState:2;
1187 ULONG PutToSleep:1;
1188 ULONG Rsvd:22;
1189 #endif
1190 } field;
1191 ULONG word;
1192 } PWRCSR1_STRUC, *PPWRCSR1_STRUC;
1193
1194 //
1195 // TIMECSR: Timer control register
1196 //
1197 typedef union _TIMECSR_STRUC {
1198 struct {
1199 #ifdef BIG_ENDIAN
1200 ULONG Rsvd:13;
1201 ULONG BeaconExpect:3; // Beacon expect window
1202 ULONG Us64Cnt:8; // 64 us timer count in units of 1 us timer
1203 ULONG UsCnt:8; // 1 us timer count in units of clock cycles
1204 #else
1205 ULONG UsCnt:8; // 1 us timer count in units of clock cycles
1206 ULONG Us64Cnt:8; // 64 us timer count in units of 1 us timer
1207 ULONG BeaconExpect:3; // Beacon expect window
1208 ULONG Rsvd:13;
1209 #endif
1210 } field;
1211 ULONG word;
1212 } TIMECSR_STRUC, *PTIMECSR_STRUC;
1213
1214 //
1215 // MACCSR0: MAC configuration register 0
1216 //
1217
1218 //
1219 // MACCSR1: MAC configuration register 1
1220 //
1221 typedef union _MACCSR1_STRUC {
1222 struct {
1223 #ifdef BIG_ENDIAN
1224 ULONG Rsvd:24;
1225 ULONG IntersilIF:1; // Intersil IF calibration pin
1226 ULONG LoopBack:2; // Loopback mode. 00: normal, 01: internal, 10: external, 11:rsvd.
1227 ULONG AutoRxBbp:1; // Auto Rx logic access BBP control register
1228 ULONG AutoTxBbp:1; // Auto Tx logic access BBP control register
1229 ULONG BbpRxResetMode:1; // Ralink BBP RX reset mode
1230 ULONG OneShotRxMode:1; // Enable one-shot Rx mode for debugging
1231 ULONG KickRx:1; // Kick one-shot Rx in one-shot Rx mode
1232 #else
1233 ULONG KickRx:1; // Kick one-shot Rx in one-shot Rx mode
1234 ULONG OneShotRxMode:1; // Enable one-shot Rx mode for debugging
1235 ULONG BbpRxResetMode:1; // Ralink BBP RX reset mode
1236 ULONG AutoTxBbp:1; // Auto Tx logic access BBP control register
1237 ULONG AutoRxBbp:1; // Auto Rx logic access BBP control register
1238 ULONG LoopBack:2; // Loopback mode. 00: normal, 01: internal, 10: external, 11:rsvd.
1239 ULONG IntersilIF:1; // Intersil IF calibration pin
1240 ULONG Rsvd:24;
1241 #endif
1242 } field;
1243 ULONG word;
1244 } MACCSR1_STRUC, *PMACCSR1_STRUC;
1245
1246 //
1247 // RALINKCSR: Ralink Rx auto-reset BBCR
1248 //
1249 typedef union _RALINKCSR_STRUC {
1250 struct {
1251 #ifdef BIG_ENDIAN
1252 ULONG ArBbpValid1:1; // Auto reset BBP register 1 is valid
1253 ULONG ArBbpId1:7; // Auto reset BBP register 1 Id
1254 ULONG ArBbpData1:8; // Auto reset BBP register 1 data
1255 ULONG ArBbpValid0:1; // Auto reset BBP register 0 is valid
1256 ULONG ArBbpId0:7; // Auto reset BBP register 0 Id
1257 ULONG ArBbpData0:8; // Auto reset BBP register 0 data
1258 #else
1259 ULONG ArBbpData0:8; // Auto reset BBP register 0 data
1260 ULONG ArBbpId0:7; // Auto reset BBP register 0 Id
1261 ULONG ArBbpValid0:1; // Auto reset BBP register 0 is valid
1262 ULONG ArBbpData1:8; // Auto reset BBP register 1 data
1263 ULONG ArBbpId1:7; // Auto reset BBP register 1 Id
1264 ULONG ArBbpValid1:1; // Auto reset BBP register 1 is valid
1265 #endif
1266 } field;
1267 ULONG word;
1268 } RALINKCSR_STRUC, *PRALINKCSR_STRUC;
1269
1270 //
1271 // BCNCSR: Beacon interval control register
1272 //
1273 typedef union _BCNCSR_STRUC {
1274 struct {
1275 #ifdef BIG_ENDIAN
1276 ULONG Rsvd:16;
1277 ULONG Plus:1; // plus or minus delta time value
1278 ULONG Mode:2; // please refer to ASIC specs.
1279 ULONG NumBcn:8; // Delta time value or number of beacon according to mode
1280 ULONG DeltaTime:4; // The delta time value
1281 ULONG Change:1; // Write one to change beacon interval
1282 #else
1283 ULONG Change:1; // Write one to change beacon interval
1284 ULONG DeltaTime:4; // The delta time value
1285 ULONG NumBcn:8; // Delta time value or number of beacon according to mode
1286 ULONG Mode:2; // please refer to ASIC specs.
1287 ULONG Plus:1; // plus or minus delta time value
1288 ULONG Rsvd:16;
1289 #endif
1290 } field;
1291 ULONG word;
1292 } BCNCSR_STRUC, *PBCNCSR_STRUC;
1293
1294 //
1295 // BBPCSR: BBP serial control register
1296 //
1297 typedef union _BBPCSR_STRUC {
1298 struct {
1299 #ifdef BIG_ENDIAN
1300 ULONG Rsvd:15;
1301 ULONG WriteControl:1; // 1: Write BBP, 0: Read BBP
1302 ULONG Busy:1; // 1: ASIC is busy execute BBP programming.
1303 ULONG RegNum:7; // Selected BBP register
1304 ULONG Value:8; // Register value to program into BBP
1305 #else
1306 ULONG Value:8; // Register value to program into BBP
1307 ULONG RegNum:7; // Selected BBP register
1308 ULONG Busy:1; // 1: ASIC is busy execute BBP programming.
1309 ULONG WriteControl:1; // 1: Write BBP, 0: Read BBP
1310 ULONG Rsvd:15;
1311 #endif
1312 } field;
1313 ULONG word;
1314 } BBPCSR_STRUC, *PBBPCSR_STRUC;
1315
1316 //
1317 // RFCSR: RF serial control register
1318 //
1319 typedef union _RFCSR_STRUC {
1320 struct {
1321 #ifdef BIG_ENDIAN
1322 ULONG Busy:1; // 1: ASIC is busy execute RF programming.
1323 ULONG PLL_LD:1; // RF PLL_LD status
1324 ULONG IFSelect:1; // 1: select IF to program, 0: select RF to program
1325 ULONG NumberOfBits:5; // Number of bits used in RFRegValue (I:20, RFMD:22)
1326 ULONG RFRegValue:24; // Register value (include register id) serial out to RF/IF chip.
1327 #else
1328 ULONG RFRegValue:24; // Register value (include register id) serial out to RF/IF chip.
1329 ULONG NumberOfBits:5; // Number of bits used in RFRegValue (I:20, RFMD:22)
1330 ULONG IFSelect:1; // 1: select IF to program, 0: select RF to program
1331 ULONG PLL_LD:1; // RF PLL_LD status
1332 ULONG Busy:1; // 1: ASIC is busy execute RF programming.
1333 #endif
1334 } field;
1335 ULONG word;
1336 } RFCSR_STRUC, *PRFCSR_STRUC;
1337
1338 //
1339 // LEDCSR: LED control register
1340 //
1341 typedef union _LEDCSR_STRUC {
1342 struct {
1343 #ifdef BIG_ENDIAN
1344 ULONG Rsvd:11;
1345 ULONG LedADefault:1; // LED A default value for "enable" state. 0: LED ON, 1: LED OFF
1346 ULONG LedBPolarity:1; // 0: active low, 1: active high
1347 ULONG LedAPolarity:1; // 0: active low, 1: active high
1348 ULONG LedB:1; // controlled by software, 1: ON, 0: OFF
1349 ULONG LedA:1; // indicate TX activity, 1: enable, 0: disable
1350 ULONG OffPeriod:8; // Off period, default 30ms
1351 ULONG OnPeriod:8; // On period, default 70ms
1352 #else
1353 ULONG OnPeriod:8; // On period, default 70ms
1354 ULONG OffPeriod:8; // Off period, default 30ms
1355 ULONG LedA:1; // indicate TX activity, 1: enable, 0: disable
1356 ULONG LedB:1; // controlled by software, 1: ON, 0: OFF
1357 ULONG LedAPolarity:1; // 0: active low, 1: active high
1358 ULONG LedBPolarity:1; // 0: active low, 1: active high
1359 ULONG LedADefault:1; // LED A default value for "enable" state. 0: LED ON, 1: LED OFF
1360 ULONG Rsvd:11;
1361 #endif
1362 } field;
1363 ULONG word;
1364 } LEDCSR_STRUC, *PLEDCSR_STRUC;
1365
1366 //
1367 // GPIOCSR: GPIO control register
1368 //
1369 typedef union _GPIOCSR_STRUC {
1370 struct {
1371 #ifdef BIG_ENDIAN
1372 ULONG Rsvd:16;
1373 ULONG Dir7:1;
1374 ULONG Dir6:1;
1375 ULONG Dir5:1;
1376 ULONG Dir4:1;
1377 ULONG Dir3:1;
1378 ULONG Dir2:1;
1379 ULONG Dir1:1;
1380 ULONG Dir0:1;
1381 ULONG Bit7:1;
1382 ULONG Bit6:1;
1383 ULONG Bit5:1;
1384 ULONG Bit4:1;
1385 ULONG Bit3:1;
1386 ULONG Bit2:1;
1387 ULONG Bit1:1;
1388 ULONG Bit0:1;
1389 #else
1390 ULONG Bit0:1;
1391 ULONG Bit1:1;
1392 ULONG Bit2:1;
1393 ULONG Bit3:1;
1394 ULONG Bit4:1;
1395 ULONG Bit5:1;
1396 ULONG Bit6:1;
1397 ULONG Bit7:1;
1398 ULONG Dir0:1;
1399 ULONG Dir1:1;
1400 ULONG Dir2:1;
1401 ULONG Dir3:1;
1402 ULONG Dir4:1;
1403 ULONG Dir5:1;
1404 ULONG Dir6:1;
1405 ULONG Dir7:1;
1406 ULONG Rsvd:16;
1407 #endif
1408 } field;
1409 ULONG word;
1410 } GPIOCSR_STRUC, *PGPIOCSR_STRUC;
1411
1412 //
1413 // BCNCSR1: Tx BEACON offset time control register
1414 //
1415 typedef union _BCNCSR1_STRUC {
1416 struct {
1417 #ifdef BIG_ENDIAN
1418 ULONG Rsvd:12;
1419 ULONG BeaconCwMin:4; // 2^CwMin
1420 ULONG Preload:16; // in units of usec
1421 #else
1422 ULONG Preload:16; // in units of usec
1423 ULONG BeaconCwMin:4; // 2^CwMin
1424 ULONG Rsvd:12;
1425 #endif
1426 } field;
1427 ULONG word;
1428 } BCNCSR1_STRUC, *PBCNCSR1_STRUC;
1429
1430 //
1431 // MACCSR2: TX_PE to RX_PE turn-around time control register
1432 //
1433 typedef union _MACCSR2_STRUC {
1434 struct {
1435 #ifdef BIG_ENDIAN
1436 ULONG Rsvd:24;
1437 ULONG Delay:8; // in units of PCI clock cycle
1438 #else
1439 ULONG Delay:8; // in units of PCI clock cycle
1440 ULONG Rsvd:24;
1441 #endif
1442 } field;
1443 ULONG word;
1444 } MACCSR2_STRUC, *PMACCSR2_STRUC;
1445
1446 //
1447 // EEPROM antenna select format
1448 //
1449 typedef union _EEPROM_ANTENNA_STRUC {
1450 struct {
1451 #ifdef BIG_ENDIAN
1452 USHORT RfType:5; // see E2PROM document for RF IC selection
1453 USHORT HardwareRadioControl:1; // 1: Hardware controlled radio enabled, Read GPIO0 required.
1454 USHORT DynamicTxAgcControl:1;
1455 USHORT LedMode:3; // 0-default mode, 1:TX/RX activity mode, 2: Single LED (didn't care about link), 3: reserved
1456 USHORT RxDefaultAntenna:2; // default of antenna, 0: diversity, 1:antenna-A, 2:antenna-B reserved (default = 0)
1457 USHORT TxDefaultAntenna:2; // default of antenna, 0: diversity, 1:antenna-A, 2:antenna-B reserved (default = 0)
1458 USHORT NumOfAntenna:2; // Number of antenna
1459 #else
1460 USHORT NumOfAntenna:2; // Number of antenna
1461 USHORT TxDefaultAntenna:2; // default of antenna, 0: diversity, 1:antenna-A, 2:antenna-B reserved (default = 0)
1462 USHORT RxDefaultAntenna:2; // default of antenna, 0: diversity, 1:antenna-A, 2:antenna-B reserved (default = 0)
1463 USHORT LedMode:3; // 0-default mode, 1:TX/RX activity mode, 2: Single LED (didn't care about link), 3: reserved
1464 USHORT DynamicTxAgcControl:1;
1465 USHORT HardwareRadioControl:1; // 1: Hardware controlled radio enabled, Read GPIO0 required.
1466 USHORT RfType:5; // see E2PROM document for RF IC selection
1467 #endif
1468 } field;
1469 USHORT word;
1470 } EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
1471
1472 typedef union _EEPROM_NIC_CINFIG2_STRUC {
1473 struct {
1474 #ifdef BIG_ENDIAN
1475 USHORT Rsv:12; // must be 0
1476 USHORT CckTxPower:2; // CCK TX power compensation
1477 USHORT DynamicBbpTuning:1; // !!! NOTE: 0 - enable, 1 - disable
1478 USHORT CardbusAcceleration:1; // !!! NOTE: 0 - enable, 1 - disable
1479 #else
1480 USHORT CardbusAcceleration:1; // !!! NOTE: 0 - enable, 1 - disable
1481 USHORT DynamicBbpTuning:1; // !!! NOTE: 0 - enable, 1 - disable
1482 USHORT CckTxPower:2; // CCK TX power compensation
1483 USHORT Rsv:12; // must be 0
1484 #endif
1485 } field;
1486 USHORT word;
1487 } EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
1488
1489 typedef union _EEPROM_TX_PWR_STRUC {
1490 struct {
1491 #ifdef BIG_ENDIAN
1492 UCHAR Byte1; // High Byte
1493 UCHAR Byte0; // Low Byte
1494 #else
1495 UCHAR Byte0; // Low Byte
1496 UCHAR Byte1; // High Byte
1497 #endif
1498 } field;
1499 USHORT word;
1500 } EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
1501
1502 typedef union _EEPROM_VERSION_STRUC {
1503 struct {
1504 #ifdef BIG_ENDIAN
1505 UCHAR Version; // High Byte
1506 UCHAR FaeReleaseNumber; // Low Byte
1507 #else
1508 UCHAR FaeReleaseNumber; // Low Byte
1509 UCHAR Version; // High Byte
1510 #endif
1511 } field;
1512 USHORT word;
1513 } EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
1514
1515 #endif // __RT2560_H__
MOXA 2.6.9 from sdlinux-moxaart.tgz