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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / usb / net / Zydas / zdhw.c
blob6d89c8e251890a1cdfb5b1e2194861518afc5ecf
1 #ifndef __ZDHW_C__
2 #define __ZDHW_C__
3
4 #include "zdtypes.h"
5 #include "zdequates.h"
6 #include "zdapi.h"
7 #include "zdhw.h"
8 #include "zddebug.h"
9 #include "zd1211.h"
10 #include "zd1205.h"
11 #include "zdglobal.h"
12 extern struct net_device *g_dev;
13 extern u8 mMacMode;
14 extern u8 a_OSC_get_cal_int( u8 ch, u32 rate, u8 *intValue, u8 *calValue);
15 extern u8 *mTxOFDMType;
16 extern const U16 dot11A_Channel[];
17 extern const U16 dot11A_Channel_Amount;
18
19 u8 LastSetChannel=1;
20 u8 LastMacMode=0;
21 /*
22 U32 GRF5101T[] = {
23 0x1A0000, //Null
24 0x1A0000, //Ch 1
25 0x1A8000, //Ch 2
26 0x1A4000, //Ch 3
27 0x1AC000, //Ch 4
28 0x1A2000, //Ch 5
29 0x1AA000, //Ch 6
30 0x1A6000, //Ch 7
31 0x1AE000, //Ch 8
32 0x1A1000, //Ch 9
33 0x1A9000, //Ch 10
34 0x1A5000, //Ch 11
35 0x1AD000, //Ch 12
36 0x1A3000, //Ch 13
37 0x1AB000 //Ch 14
38 };
39
40
41 U32 AL2210TB[] = {
42 0x2396c0, //;Null
43 0x0196c0, //;Ch 1
44 0x019710, //;Ch 2
45 0x019760, //;Ch 3
46 0x0197b0, //;Ch 4
47 0x019800, //;Ch 5
48 0x019850, //;Ch 6
49 0x0198a0, //;Ch 7
50 0x0198f0, //;Ch 8
51 0x019940, //;Ch 9
52 0x019990, //;Ch 10
53 0x0199e0, //;Ch 11
54 0x019a30, //;Ch 12
55 0x019a80, //;Ch 13
56 0x019b40 //;Ch 14
57 };
58
59
60 U32 M2827BF[] = {
61 0x0ccd4, //;Null
62 0x0ccd4, //;Ch 1
63 0x22224, //;Ch 2
64 0x37774, //;Ch 3
65 0x0ccd4, //;Ch 4
66 0x22224, //;Ch 5
67 0x37774, //;Ch 6
68 0x0ccd4, //;Ch 7
69 0x22224, //;Ch 8
70 0x37774, //;Ch 9
71 0x0ccd4, //;Ch 10
72 0x22224, //;Ch 11
73 0x37774, //;Ch 12
74 0x0ccd4, //;Ch 13
75 0x199a4 //;Ch 14
76 };
77
78
79 U32 M2827BN[] = {
80 0x30a03, //;Null
81 0x30a03, //;Ch 1
82 0x00a13, //;Ch 2
83 0x10a13, //;Ch 3
84 0x30a13, //;Ch 4
85 0x00a23, //;Ch 5
86 0x10a23, //;Ch 6
87 0x30a23, //;Ch 7
88 0x00a33, //;Ch 8
89 0x10a33, //;Ch 9
90 0x30a33, //;Ch 10
91 0x00a43, //;Ch 11
92 0x10a43, //;Ch 12
93 0x30a43, //;Ch 13
94 0x20a53 //;Ch 14
95 };
96
97
98 U32 M2827BF2[] = {
99 0x33334, //;Null
100 0x33334, //;Ch 1
101 0x08884, //;Ch 2
102 0x1ddd4, //;Ch 3
103 0x33334, //;Ch 4
104 0x08884, //;Ch 5
105 0x1ddd4, //;Ch 6
106 0x33334, //;Ch 7
107 0x08884, //;Ch 8
108 0x1ddd4, //;Ch 9
109 0x33334, //;Ch 10
110 0x08884, //;Ch 11
111 0x1ddd4, //;Ch 12
112 0x33334, //;Ch 13
113 0x26664 //;Ch 14
114 };
115
116 U32 M2827BN2[] = {
117 0x10a03, //;Null
118 0x10a03, //;Ch 1
119 0x20a13, //;Ch 2
120 0x30a13, //;Ch 3
121 0x10a13, //;Ch 4
122 0x20a23, //;Ch 5
123 0x30a23, //;Ch 6
124 0x10a23, //;Ch 7
125 0x20a33, //;Ch 8
126 0x30a33, //;Ch 9
127 0x10a33, //;Ch 10
128 0x20a43, //;Ch 11
129 0x30a43, //;Ch 12
130 0x10a43, //;Ch 13
131 0x20a53 //;Ch 14
132 };
133 */
134 U32 UW2453RF_dongle[][45] = {
135 //talbe 1
136 {
137 0x100047, 0x200999, 0x34664D, //;Null
138 0x100047, 0x200999, 0x34664D, //;Ch 1 2412
139 0x100047, 0x20099b, 0x34664D, //;Ch 2 2417
140 0x100067, 0x200998, 0x34604D, //;Ch 3 2422
141 0x100067, 0x20099a, 0x34604D, //;Ch 4 2427
142 0x100067, 0x200999, 0x346675, //;Ch 5 2432
143 0x100067, 0x20099b, 0x346675, //;Ch 6 2437
144 0x100057, 0x200998, 0x346475, //;Ch 7 2442
145 0x100057, 0x20099a, 0x346475, //;Ch 8 2447
146 0x100057, 0x200999, 0x346655, //;Ch 9 2452
147 0x100057, 0x20099b, 0x346655, //;Ch 10 2457
148 0x100077, 0x200998, 0x346455, //;Ch 11 2462
149 0x100077, 0x20099a, 0x346455, //;Ch 12 2467
150 0x100077, 0x200999, 0x346665, //;Ch 13 2472
151 0x10004f, 0x200ccc, 0x346665 //;Ch 14 2484
152 },
153 //talbe 2
154 {
155 0x100047, 0x200999, 0x34666D, //;Null
156 0x100047, 0x200999, 0x34666D, //;Ch 1 2412
157 0x100047, 0x20099b, 0x34666D, //;Ch 2 2417
158 0x100067, 0x200998, 0x34606D, //;Ch 3 2422
159 0x100067, 0x20099a, 0x34606D, //;Ch 4 2427
160 0x100067, 0x200999, 0x34664D, //;Ch 5 2432
161 0x100067, 0x20099b, 0x34664D, //;Ch 6 2437
162 0x100057, 0x200998, 0x34644D, //;Ch 7 2442
163 0x100057, 0x20099a, 0x34644D, //;Ch 8 2447
164 0x100057, 0x200999, 0x346675, //;Ch 9 2452
165 0x100057, 0x20099b, 0x346675, //;Ch 10 2457
166 0x100077, 0x200998, 0x346475, //;Ch 11 2462
167 0x100077, 0x20099a, 0x346475, //;Ch 12 2467
168 0x100077, 0x200999, 0x346655, //;Ch 13 2472
169 0x10004f, 0x200ccc, 0x346655 //;Ch 14 2484
170 },
171 //talbe 3
172 {
173 0x100047, 0x200999, 0x34665D, //;Null
174 0x100047, 0x200999, 0x34665D, //;Ch 1 2412
175 0x100047, 0x20099b, 0x34665D, //;Ch 2 2417
176 0x100067, 0x200998, 0x34605D, //;Ch 3 2422
177 0x100067, 0x20099a, 0x34605D, //;Ch 4 2427
178 0x100067, 0x200999, 0x34666D, //;Ch 5 2432
179 0x100067, 0x20099b, 0x34666D, //;Ch 6 2437
180 0x100057, 0x200998, 0x34646D, //;Ch 7 2442
181 0x100057, 0x20099a, 0x34646D, //;Ch 8 2447
182 0x100057, 0x200999, 0x34664D, //;Ch 9 2452
183 0x100057, 0x20099b, 0x34664D, //;Ch 10 2457
184 0x100077, 0x200998, 0x34644D, //;Ch 11 2462
185 0x100077, 0x20099a, 0x34644D, //;Ch 12 2467
186 0x100077, 0x200999, 0x346675, //;Ch 13 2472
187 0x10004f, 0x200ccc, 0x346675 //;Ch 14 2484
188 },
189 //table 4
190 {
191 0x100047, 0x200999, 0x34667D, //;Null
192 0x100047, 0x200999, 0x34667D, //;Ch 1 2412
193 0x100047, 0x20099b, 0x34667D, //;Ch 2 2417
194 0x100067, 0x200998, 0x34607D, //;Ch 3 2422
195 0x100067, 0x20099a, 0x34607D, //;Ch 4 2427
196 0x100067, 0x200999, 0x34665D, //;Ch 5 2432
197 0x100067, 0x20099b, 0x34665D, //;Ch 6 2437
198 0x100057, 0x200998, 0x34645D, //;Ch 7 2442
199 0x100057, 0x20099a, 0x34645D, //;Ch 8 2447
200 0x100057, 0x200999, 0x34666D, //;Ch 9 2452
201 0x100057, 0x20099b, 0x34666D, //;Ch 10 2457
202 0x100077, 0x200998, 0x34646D, //;Ch 11 2462
203 0x100077, 0x20099a, 0x34646D, //;Ch 12 2467
204 0x100077, 0x200999, 0x34664D, //;Ch 13 2472
205 0x10004f, 0x200ccc, 0x34664D //;Ch 14 2484
206 },
207 //table 5
208 {
209 0x100047, 0x200999, 0x346643, //;Null
210 0x100047, 0x200999, 0x346643, //;Ch 1 2412
211 0x100047, 0x20099b, 0x346643, //;Ch 2 2417
212 0x100067, 0x200998, 0x346043, //;Ch 3 2422
213 0x100067, 0x20099a, 0x346043, //;Ch 4 2427
214 0x100067, 0x200999, 0x34667D, //;Ch 5 2432
215 0x100067, 0x20099b, 0x34667D, //;Ch 6 2437
216 0x100057, 0x200998, 0x34647D, //;Ch 7 2442
217 0x100057, 0x20099a, 0x34647D, //;Ch 8 2447
218 0x100057, 0x200999, 0x34665D, //;Ch 9 2452
219 0x100057, 0x20099b, 0x34665D, //;Ch 10 2457
220 0x100077, 0x200998, 0x34645D, //;Ch 11 2462
221 0x100077, 0x20099a, 0x34645D, //;Ch 12 2467
222 0x100077, 0x200999, 0x34666D, //;Ch 13 2472
223 0x10004f, 0x200ccc, 0x34666D //;Ch 14 2484
224 },
225 //table 6
226 {
227 0x100047, 0x200999, 0x346663, //;Null
228 0x100047, 0x200999, 0x346663, //;Ch 1 2412
229 0x100047, 0x20099b, 0x346663, //;Ch 2 2417
230 0x100067, 0x200998, 0x346063, //;Ch 3 2422
231 0x100067, 0x20099a, 0x346063, //;Ch 4 2427
232 0x100067, 0x200999, 0x346643, //;Ch 5 2432
233 0x100067, 0x20099b, 0x346643, //;Ch 6 2437
234 0x100057, 0x200998, 0x346443, //;Ch 7 2442
235 0x100057, 0x20099a, 0x346443, //;Ch 8 2447
236 0x100057, 0x200999, 0x34667D, //;Ch 9 2452
237 0x100057, 0x20099b, 0x34667D, //;Ch 10 2457
238 0x100077, 0x200998, 0x34647D, //;Ch 11 2462
239 0x100077, 0x20099a, 0x34647D, //;Ch 12 2467
240 0x100077, 0x200999, 0x34665D, //;Ch 13 2472
241 0x10004f, 0x200ccc, 0x34665D //;Ch 14 2484
242 },
243 //table 7
244 {
245 0x100047, 0x200999, 0x346653, //;Null
246 0x100047, 0x200999, 0x346653, //;Ch 1 2412
247 0x100047, 0x20099b, 0x346653, //;Ch 2 2417
248 0x100067, 0x200998, 0x346053, //;Ch 3 2422
249 0x100067, 0x20099a, 0x346053, //;Ch 4 2427
250 0x100067, 0x200999, 0x346663, //;Ch 5 2432
251 0x100067, 0x20099b, 0x346663, //;Ch 6 2437
252 0x100057, 0x200998, 0x346463, //;Ch 7 2442
253 0x100057, 0x20099a, 0x346463, //;Ch 8 2447
254 0x100057, 0x200999, 0x346643, //;Ch 9 2452
255 0x100057, 0x20099b, 0x346643, //;Ch 10 2457
256 0x100077, 0x200998, 0x346443, //;Ch 11 2462
257 0x100077, 0x20099a, 0x346443, //;Ch 12 2467
258 0x100077, 0x200999, 0x34667D, //;Ch 13 2472
259 0x10004f, 0x200ccc, 0x34667D //;Ch 14 2484
260 },
261 //table 8
262 {
263 0x100047, 0x200999, 0x346673, //;Null
264 0x100047, 0x200999, 0x346673, //;Ch 1 2412
265 0x100047, 0x20099b, 0x346673, //;Ch 2 2417
266 0x100067, 0x200998, 0x346073, //;Ch 3 2422
267 0x100067, 0x20099a, 0x346073, //;Ch 4 2427
268 0x100067, 0x200999, 0x346653, //;Ch 5 2432
269 0x100067, 0x20099b, 0x346653, //;Ch 6 2437
270 0x100057, 0x200998, 0x346453, //;Ch 7 2442
271 0x100057, 0x20099a, 0x346453, //;Ch 8 2447
272 0x100057, 0x200999, 0x346663, //;Ch 9 2452
273 0x100057, 0x20099b, 0x346663, //;Ch 10 2457
274 0x100077, 0x200998, 0x346463, //;Ch 11 2462
275 0x100077, 0x20099a, 0x346463, //;Ch 12 2467
276 0x100077, 0x200999, 0x346643, //;Ch 13 2472
277 0x10004f, 0x200ccc, 0x346643 //;Ch 14 2484
278 },
279 //table 9
280 {
281 0x100047, 0x200999, 0x34664B, //;Null
282 0x100047, 0x200999, 0x34664B, //;Ch 1 2412
283 0x100047, 0x20099b, 0x34664B, //;Ch 2 2417
284 0x100067, 0x200998, 0x34604B, //;Ch 3 2422
285 0x100067, 0x20099a, 0x34604B, //;Ch 4 2427
286 0x100067, 0x200999, 0x346673, //;Ch 5 2432
287 0x100067, 0x20099b, 0x346673, //;Ch 6 2437
288 0x100057, 0x200998, 0x346473, //;Ch 7 2442
289 0x100057, 0x20099a, 0x346473, //;Ch 8 2447
290 0x100057, 0x200999, 0x346653, //;Ch 9 2452
291 0x100057, 0x20099b, 0x346653, //;Ch 10 2457
292 0x100077, 0x200998, 0x346453, //;Ch 11 2462
293 0x100077, 0x20099a, 0x346453, //;Ch 12 2467
294 0x100077, 0x200999, 0x346663, //;Ch 13 2472
295 0x10004f, 0x200ccc, 0x346663 //;Ch 14 2484
296 },
297 //table 10
298 {
299 0x100047, 0x200999, 0x34666B, //;Null
300 0x100047, 0x200999, 0x34666B, //;Ch 1 2412
301 0x100047, 0x20099b, 0x34666B, //;Ch 2 2417
302 0x100067, 0x200998, 0x34606B, //;Ch 3 2422
303 0x100067, 0x20099a, 0x34606B, //;Ch 4 2427
304 0x100067, 0x200999, 0x34664B, //;Ch 5 2432
305 0x100067, 0x20099b, 0x34664B, //;Ch 6 2437
306 0x100057, 0x200998, 0x34644B, //;Ch 7 2442
307 0x100057, 0x20099a, 0x34644B, //;Ch 8 2447
308 0x100057, 0x200999, 0x346673, //;Ch 9 2452
309 0x100057, 0x20099b, 0x346673, //;Ch 10 2457
310 0x100077, 0x200998, 0x346473, //;Ch 11 2462
311 0x100077, 0x20099a, 0x346473, //;Ch 12 2467
312 0x100077, 0x200999, 0x346653, //;Ch 13 2472
313 0x10004f, 0x200ccc, 0x346653 //;Ch 14 2484
314 },
315 //table 11
316 {
317 0x100047, 0x200999, 0x34665B, //;Null
318 0x100047, 0x200999, 0x34665B, //;Ch 1 2412
319 0x100047, 0x20099b, 0x34665B, //;Ch 2 2417
320 0x100067, 0x200998, 0x34605B, //;Ch 3 2422
321 0x100067, 0x20099a, 0x34605B, //;Ch 4 2427
322 0x100067, 0x200999, 0x34666B, //;Ch 5 2432
323 0x100067, 0x20099b, 0x34666B, //;Ch 6 2437
324 0x100057, 0x200998, 0x34646B, //;Ch 7 2442
325 0x100057, 0x20099a, 0x34646B, //;Ch 8 2447
326 0x100057, 0x200999, 0x34664B, //;Ch 9 2452
327 0x100057, 0x20099b, 0x34664B, //;Ch 10 2457
328 0x100077, 0x200998, 0x34644B, //;Ch 11 2462
329 0x100077, 0x20099a, 0x34644B, //;Ch 12 2467
330 0x100077, 0x200999, 0x346673, //;Ch 13 2472
331 0x10004f, 0x200ccc, 0x346673 //;Ch 14 2484
332 },
333 //table AUTOCAL
334 {
335 0x106847, 0x200999, 0x346662, //;Null
336 0x106847, 0x200999, 0x346662, //;Ch 1 2412
337 0x106847, 0x20099b, 0x346662, //;Ch 2 2417
338 0x106867, 0x200998, 0x346662, //;Ch 3 2422
339 0x106867, 0x20099a, 0x346662, //;Ch 4 2427
340 0x106867, 0x200999, 0x346662, //;Ch 5 2432
341 0x106867, 0x20099b, 0x346662, //;Ch 6 2437
342 0x106857, 0x200998, 0x346662, //;Ch 7 2442
343 0x106857, 0x20099a, 0x346662, //;Ch 8 2447
344 0x106857, 0x200999, 0x346662, //;Ch 9 2452
345 0x106857, 0x20099b, 0x346662, //;Ch 10 2457
346 0x106877, 0x200998, 0x346662, //;Ch 11 2462
347 0x106877, 0x20099a, 0x346662, //;Ch 12 2467
348 0x106877, 0x200999, 0x346662, //;Ch 13 2472
349 0x10684f, 0x200ccc, 0x346662 //;Ch 14 2484
350 }
351 };
352 U32 UW2453RF[] = {
353
354 0x100047, 0x200999, 0x307602, //;Null
355 0x100047, 0x200999, 0x307602, //;Ch 1 2412
356 0x100047, 0x20099b, 0x307602, //;Ch 2 2417
357 0x100067, 0x200998, 0x307002, //;Ch 3 2422
358 0x100067, 0x20099a, 0x307002, //;Ch 4 2427
359 0x100067, 0x200999, 0x307002, //;Ch 5 2432
360 0x100067, 0x20099b, 0x307002, //;Ch 6 2437
361 0x100057, 0x200998, 0x307742, //;Ch 7 2442
362 0x100057, 0x20099a, 0x307002, //;Ch 8 2447
363 0x100057, 0x200999, 0x307002, //;Ch 9 2452
364 0x100057, 0x20099b, 0x307002, //;Ch 10 2457
365 0x100077, 0x200998, 0x307002, //;Ch 11 2462
366 0x100077, 0x20099a, 0x307742, //;Ch 12 2467
367 0x100077, 0x200999, 0x307002, //;Ch 13 2472
368 0x10004f, 0x200ccc, 0x307002 //;Ch 14 2484
369 };
370
371 U32 AL2232TB[] =
372 {
373 0x03f790, 0x033331, 0x00000d, //;Null
374 0x03f790, 0x033331, 0x00000d, //;Ch 1
375 0x03f790, 0x0b3331, 0x00000d, //;Ch 2
376 0x03e790, 0x033331, 0x00000d, //;Ch 3
377 0x03e790, 0x0b3331, 0x00000d, //;Ch 4
378 0x03f7a0, 0x033331, 0x00000d, //;Ch 5
379 0x03f7a0, 0x0b3331, 0x00000d, //;Ch 6
380 0x03e7a0, 0x033331, 0x00000d, //;Ch 7
381 0x03e7a0, 0x0b3331, 0x00000d, //;Ch 8
382 0x03f7b0, 0x033331, 0x00000d, //;Ch 9
383 0x03f7b0, 0x0b3331, 0x00000d, //;Ch 10
384 0x03E7b0, 0x033331, 0x00000d, //;Ch 11
385 0x03e7b0, 0x0b3331, 0x00000d, //;Ch 12
386 0x03f7c0, 0x033331, 0x00000d, //;Ch 13
387 0x03e7c0, 0x066661, 0x00000d //;Ch 14
388 };
389
390 U32 AL2230TB_1211[] = {
391 0x03f790, 0x033331, 0x00000d, //;Null
392 0x03f790, 0x033331, 0x00000d, //;Ch 1
393 0x03f790, 0x0b3331, 0x00000d, //;Ch 2
394 0x03e790, 0x033331, 0x00000d, //;Ch 3
395 0x03e790, 0x0b3331, 0x00000d, //;Ch 4
396 0x03f7a0, 0x033331, 0x00000d, //;Ch 5
397 0x03f7a0, 0x0b3331, 0x00000d, //;Ch 6
398 0x03e7a0, 0x033331, 0x00000d, //;Ch 7
399 0x03e7a0, 0x0b3331, 0x00000d, //;Ch 8
400 0x03f7b0, 0x033331, 0x00000d, //;Ch 9
401 0x03f7b0, 0x0b3331, 0x00000d, //;Ch 10
402 0x03E7b0, 0x033331, 0x00000d, //;Ch 11
403 0x03e7b0, 0x0b3331, 0x00000d, //;Ch 12
404 0x03f7c0, 0x033331, 0x00000d, //;Ch 13
405 0x03e7c0, 0x066661, 0x00000d //;Ch 14
406 };
407
408 U32 AL2230TB[] = {
409 0x09efc0, 0x8cccc0, 0xb00000, //;Null
410 0x09efc0, 0x8cccc0, 0xb00000, //;Ch 1
411 0x09efc0, 0x8cccd0, 0xb00000, //;Ch 2
412 0x09e7c0, 0x8cccc0, 0xb00000, //;Ch 3
413 0x09e7c0, 0x8cccd0, 0xb00000, //;Ch 4
414 0x05efc0, 0x8cccc0, 0xb00000, //;Ch 5
415 0x05efc0, 0x8cccd0, 0xb00000, //;Ch 6
416 0x05e7c0, 0x8cccc0, 0xb00000, //;Ch 7
417 0x05e7c0, 0x8cccd0, 0xb00000, //;Ch 8
418 0x0defc0, 0x8cccc0, 0xb00000, //;Ch 9
419 0x0defc0, 0x8cccd0, 0xb00000, //;Ch 10
420 0x0de7c0, 0x8cccc0, 0xb00000, //;Ch 11
421 0x0de7c0, 0x8cccd0, 0xb00000, //;Ch 12
422 0x03efc0, 0x8cccc0, 0xb00000, //;Ch 13
423 0x03e7c0, 0x866660, 0xb00000 //;Ch 14
424 };
425 U32 AL7230BTB[] = {
426 0x09ec04, 0x8cccc8, //;Null
427 0x09ec00, 0x8cccc8, //;Ch 1
428 0x09ec00, 0x8cccd8, //;Ch 2
429 0x09ec00, 0x8cccc0, //;Ch 3
430 0x09ec00, 0x8cccd0, //;Ch 4
431 0x05ec00, 0x8cccc8, //;Ch 5
432 0x05ec00, 0x8cccd8, //;Ch 6
433 0x05ec00, 0x8cccc0, //;Ch 7
434 0x05ec00, 0x8cccd0, //;Ch 8
435 0x0dec00, 0x8cccc8, //;Ch 9
436 0x0dec00, 0x8cccd8, //;Ch 10
437 0x0dec00, 0x8cccc0, //;Ch 11
438 0x0dec00, 0x8cccd0, //;Ch 12
439 0x03ec00, 0x8cccc8, //;Ch 13
440 0x03ec00, 0x866660 //;Ch 14
441 };
442
443 U32 AL7230BTB_a[] = {
444 0x06aff4, 0x855550, 0x47f8a2, 0x21ebfe, //;Null
445 0x02aff0, 0x800000, 0x47f8a2, 0x21ebf6, //;CH 8 , 5040MHz
446 0x02aff0, 0x855550, 0x47f8a2, 0x21ebfe, //;CH 12, 5060MHz
447 0x0aaff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;CH 16, 5080MHz
448 0x06aff0, 0x8aaaa0, 0x47f8a2, 0x21ebfe, //;CH 34, 5170MHz
449 0x06aff0, 0x855550, 0x47f8a2, 0x21ebfe, //;Ch 36, 5180MHz
450 0x0eaff0, 0x800008, 0x47f8a2, 0x21ebfe, //;Ch 38, 5190MHz
451 0x0eaff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 40, 5200MHz
452 0x0eaff0, 0x855558, 0x47f8a2, 0x21ebfe, //;Ch 42, 5210MHz
453 0x0eaff0, 0x800000, 0x47f8a2, 0x21ebf6, //;Ch 44, 5220MHz, current support
454 0x0eaff0, 0x8aaaa0, 0x47f8a2, 0x21ebfe, //;Ch 46, 5230MHz
455 0x0eaff0, 0x855550, 0x47f8a2, 0x21ebfe, //;Ch 48, 5240MHz
456 0x01aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 52, 5260MHz
457 0x01aff0, 0x800000, 0x47f8a2, 0x21ebf6, //;Ch 56, 5280MHz, current support
458 0x01aff0, 0x855550, 0x47f8a2, 0x21ebfe, //;Ch 60, 5300MHz
459 0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 64, 5320MHz
460 0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 68, 5320MHz,dummy
461 0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 72, 5320MHz,dummy
462 0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 76, 5320MHz,dummy
463 0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 80, 5320MHz,dummy
464 0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 84, 5320MHz,dummy
465 0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 88, 5320MHz,dummy
466 0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 92, 5320MHz,dummy
467 0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 96, 5320MHz,dummy
468 0x03aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 100, 5500MHz
469 0x03aff0, 0x800000, 0x47f8a2, 0x21ebf6, //;Ch 104, 5520MHz
470 0x03aff0, 0x855550, 0x47f8a2, 0x21ebfe, //;Ch 108, 5540MHz
471 0x0baff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 112, 5560MHz
472 0x0baff0, 0x800000, 0x47f8a2, 0x21ebf6, //;Ch 116, 5580MHz
473 0x0baff0, 0x855550, 0x47f8a2, 0x21ebfe, //;Ch 120, 5600MHz
474 0x07aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 124, 5620MHz
475 0x07aff0, 0x800000, 0x47f8a2, 0x21ebf6, //;Ch 128, 5640MHz
476 0x07aff0, 0x855550, 0x47f8a2, 0x21ebfe, //;Ch 132, 5660MHz
477 0x0faff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 136, 5680MHz
478 0x0faff0, 0x800000, 0x47f8a2, 0x21ebf6, //;Ch 140, 5700MHz
479 0x0faff0, 0x800000, 0x47f8a2, 0x21ebf6, //;Ch 144, 5700MHz, dummy
480 0x006ff0, 0x800018, 0x47f8a2, 0x21ebfe, //;Ch 149, 5745MHz
481 0x006ff0, 0x855540, 0x47f8a2, 0x21ebfe, //;Ch 153, 5765MHz
482 0x006ff0, 0x8aaab0, 0x47f8a2, 0x21ebfe, //;Ch 157, 5785MHz
483 0x086ff0, 0x800018, 0x47f8a2, 0x21ebfe, //;Ch 161, 5805MHz
484 0x086ff0, 0x855540, 0x47f8a2, 0x21ebfe, //;Ch 165, 5825MHz
485 0x086ff0, 0x8d5540, 0x47f8a2, 0x21ebfe, //;Ch 168, 5825MHz,dummy
486 0x086ff0, 0x8d5540, 0x47f8a2, 0x21ebfe, //;Ch 172, 5825MHz,dummy
487 0x086ff0, 0x8d5540, 0x47f8a2, 0x21ebfe, //;Ch 176, 5825MHz,dummy
488 0x086ff0, 0x8d5540, 0x47f8a2, 0x21ebfe, //;Ch 180, 5825MHz,dummy
489 0x04aff0, 0x800000, 0x47f8a2, 0x21ebf6, //;Ch 184, 4920MHz
490 0x04aff0, 0x855550, 0x47f8a2, 0x21ebfe, //;Ch 188, 4940MHz
491 0x0caff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 192, 4960MHz
492 0x0caff0, 0x800000, 0x47f8a2, 0x21ebf6 //;Ch 196, 4980MHz
493 };
494
495 U32 RFMD2958t[] = {
496 0x1422BD, //Null
497 0x185D17, //Null
498 0x181979, //Ch 1
499 0x1e6666, //Ch 1
500 0x181989, //Ch 2
501 0x1e6666, //Ch 2
502 0x181999, //Ch 3
503 0x1e6666, //Ch 3
504 0x1819a9, //Ch 4
505 0x1e6666, //Ch 4
506 0x1819b9, //Ch 5
507 0x1e6666, //Ch 5
508 0x1819c9, //Ch 6
509 0x1e6666, //Ch 6
510 0x1819d9, //Ch 7
511 0x1e6666, //Ch 7
512 0x1819e9, //Ch 8
513 0x1e6666, //Ch 8
514 0x1819f9, //Ch 9
515 0x1e6666, //Ch 9
516 0x181a09, //Ch 10
517 0x1e6666, //Ch 10
518 0x181a19, //Ch 11
519 0x1e6666, //Ch 11
520 0x181a29, //Ch 12
521 0x1e6666, //Ch 12
522 0x181a39, //Ch 13
523 0x1e6666, //Ch 13
524 0x181a60, //Ch 14
525 0x1c0000 //Ch 14
526 };
527
528
529 ZDTYPE_UWTxGain ZD_UWTxGain[] =
530 {
531 {0x12,0x73FFFF},
532 {0x11,0x73FB3F},
533 {0x10,0x73FF33},
534 {0x0F,0x73FF8B},
535 {0x0E,0x737FBF},
536 {0x0D,0x7361D7},
537 {0x0C,0x71FFFF},
538 {0x0B,0x71FF3F},
539 {0x0A,0x71E6DB},
540 {0x09,0x71F35B},
541 {0x08,0x71F393},
542 {0x07,0x71F693},
543 {0x06,0x71F493},
544 {0x05,0x71F093},
545 {0x04,0x70EA93},
546 {0x03,0x70F893},
547 {0x02,0x70E093},
548 {0x01,0x70FB13},
549 {0x00,0x70E313},
550 };
551
552 #define SET_IF_SYNTHESIZER(macp, InputValue) \
553 { \
554 mFILL_WRITE_REGISTER( ZD_CR244, (U8) ((InputValue & 0xff0000)>>16)); \
555 mFILL_WRITE_REGISTER( ZD_CR243, (U8) ((InputValue & 0xff00) >> 8)); \
556 mFILL_WRITE_REGISTER( ZD_CR242, (U8) ((InputValue & 0xff))); \
557 }
558 #define mFILL_WRITE_REGISTER(addr0, value0) \
559 { \
560 WriteAddr[WriteIndex] = addr0; \
561 WriteData[WriteIndex ++] = value0; \
562 }
563
564 /*
565 #ifndef HOST_IF_USB
566 void
567 HW_Set_IF_Synthesizer(zd_80211Obj_t *pObj, U32 InputValue)
568 {
569 U32 S_bit_cnt;
570 U32 tmpvalue;
571 void *reg = pObj->reg;
572 int i;
573
574
575 S_bit_cnt = pObj->S_bit_cnt;
576
577 InputValue = InputValue << (31 - S_bit_cnt);
578
579 #if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )
580 pObj->SetReg(reg, ZD_LE2, 0);
581 pObj->SetReg(reg, ZD_RF_IF_CLK, 0);
582
583 while(S_bit_cnt){
584 InputValue = InputValue << 1;
585 if (InputValue & 0x80000000){
586 pObj->SetReg(reg, ZD_RF_IF_DATA, 1);
587 }
588 else{
589 pObj->SetReg(reg, ZD_RF_IF_DATA, 0);
590 }
591 pObj->SetReg(reg, ZD_RF_IF_CLK, 1);
592 //pObj->DelayUs(50);
593 pObj->SetReg(reg, ZD_RF_IF_CLK, 0);
594
595 //pObj->DelayUs(50);
596 S_bit_cnt --;
597 }
598
599 pObj->SetReg(reg, ZD_LE2, 1);
600
601 if (pObj->S_bit_cnt == 20){ //Is it Intersil's chipset
602 pObj->SetReg(reg, ZD_LE2, 0);
603 }
604 return;
605 #else
606 LockPhyReg(pObj);
607 tmpvalue = pObj->GetReg(reg, ZD_CR203);
608 tmpvalue &= ~BIT_1;
609 pObj->SetReg(reg, ZD_CR203, tmpvalue);
610
611 tmpvalue = pObj->GetReg(reg, ZD_CR240);
612 tmpvalue = 0x80;
613 if (tmpvalue & BIT_7){ // Configure RF by Software
614 tmpvalue = pObj->GetReg(reg, ZD_CR203);
615 tmpvalue &= ~BIT_2;
616 pObj->SetReg(reg, ZD_CR203, tmpvalue);
617
618
619 while(S_bit_cnt){
620 InputValue = InputValue << 1;
621 if (InputValue & 0x80000000){
622 tmpvalue = pObj->GetReg(reg, ZD_CR203);
623 tmpvalue |= BIT_3;
624 pObj->SetReg(reg, ZD_CR203, tmpvalue);
625 }
626 else{
627 tmpvalue = pObj->GetReg(reg, ZD_CR203);
628 tmpvalue &= ~BIT_3;
629 pObj->SetReg(reg, ZD_CR203, tmpvalue);
630 }
631
632 tmpvalue = pObj->GetReg(reg, ZD_CR203);
633 tmpvalue |= BIT_2;
634 pObj->SetReg(reg, ZD_CR203, tmpvalue);
635
636 tmpvalue = pObj->GetReg(reg, ZD_CR203);
637
638 tmpvalue &= ~BIT_2;
639 pObj->SetReg(reg, ZD_CR203, tmpvalue);
640 S_bit_cnt --;
641 }
642 }
643 else{ // Configure RF by Hardware
644 // Make Bit-reverse to meet hardware requirement.
645 tmpvalue = 0;
646 for (i=0; i<S_bit_cnt; i++){
647 InputValue = InputValue << 1;
648 if (InputValue & 0x80000000){
649 tmpvalue |= (0x1 << i);
650 }
651 }
652 InputValue = tmpvalue;
653
654 // Setup Command-Length
655 // wait until command-queue is available
656 tmpvalue = pObj->GetReg(reg, ZD_CR241);
657 while(tmpvalue & BIT_0){
658 pObj->DelayUs(1);
659 FPRINT("Command-Queue busy...");
660 }
661
662 // write command (from high-byte to low-byte)
663 pObj->SetReg(reg, ZD_CR245, InputValue >> 24);
664 pObj->SetReg(reg, ZD_CR244, InputValue >> 16);
665 pObj->SetReg(reg, ZD_CR243, InputValue >> 8);
666 pObj->SetReg(reg, ZD_CR242, InputValue);
667 }
668
669
670 tmpvalue = pObj->GetReg(reg, ZD_CR203);
671 tmpvalue |= BIT_1;
672 pObj->SetReg(reg, ZD_CR203, tmpvalue);
673
674 if (pObj->S_bit_cnt == 20){ //Is it Intersil's chipset
675 tmpvalue = pObj->GetReg(reg, ZD_CR203);
676 tmpvalue &= ~BIT_1;
677 pObj->SetReg(reg, ZD_CR203, tmpvalue);
678 }
679
680 UnLockPhyReg(pObj);
681 return;
682 #endif
683 }
684 #endif
685 */
686
687 void
688 LockPhyReg(zd_80211Obj_t *pObj)
689 {
690 #ifndef fQuickPhySet
691
692 void *reg = pObj->reg;
693 U32 tmpvalue;
694
695 tmpvalue = pObj->GetReg(reg, ZD_CtlReg1);
696 tmpvalue &= ~0x80;
697 pObj->SetReg(reg, ZD_CtlReg1, tmpvalue);
698 #endif
699 }
700
701
702 void
703 UnLockPhyReg(zd_80211Obj_t *pObj)
704 {
705 #ifndef fQuickPhySet
706 void *reg = pObj->reg;
707 U32 tmpvalue;
708
709 tmpvalue = pObj->GetReg(reg, ZD_CtlReg1);
710 tmpvalue |= 0x80;
711 pObj->SetReg(reg, ZD_CtlReg1, tmpvalue);
712 #endif
713 }
714 void PHY_UWTxPower(zd_80211Obj_t *pObj, U8 TxLevel)
715 {
716 int i;
717 for(i=0;i<19;i++)
718 {
719 if(TxLevel == ZD_UWTxGain[i].UWTxGainLevel)
720 break;
721 }
722 if(i<19)
723 {
724 HW_Set_IF_Synthesizer(pObj, ZD_UWTxGain[i].UWTxGainValue);
725 pObj->UWCurrentTxLevel = ZD_UWTxGain[i].UWTxGainLevel;
726 }
727 }
728
729 /*
730 void
731 HW_Set_Maxim_New_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
732 {
733 void *reg = pObj->reg;
734 U32 tmpvalue;
735
736 LockPhyReg(pObj);
737
738 #ifdef HOST_IF_USB
739 pObj->SetReg(reg, ZD_CR23, 0x40);
740 pObj->SetReg(reg, ZD_CR15, 0x20);
741 pObj->SetReg(reg, ZD_CR28, 0x3e);
742 pObj->SetReg(reg, ZD_CR29, 0x00);
743 pObj->SetReg(reg, ZD_CR26, 0x11);
744 pObj->SetReg(reg, ZD_CR44, 0x33);
745 pObj->SetReg(reg, ZD_CR106, 0x2a);
746 pObj->SetReg(reg, ZD_CR107, 0x1a);
747
748 pObj->SetReg(reg, ZD_CR109, 0x2b);
749 pObj->SetReg(reg, ZD_CR110, 0x2b);
750 pObj->SetReg(reg, ZD_CR111, 0x2b);
751 pObj->SetReg(reg, ZD_CR112, 0x2b);
752 pObj->SetReg(reg, ZD_CR10, 0x89);
753 pObj->SetReg(reg, ZD_CR17, 0x20);
754 pObj->SetReg(reg, ZD_CR26, 0x93);
755 pObj->SetReg(reg, ZD_CR34, 0x30);
756 pObj->SetReg(reg, ZD_CR35, 0x40);
757 pObj->SetReg(reg, ZD_CR41, 0x24);
758 pObj->SetReg(reg, ZD_CR44, 0x32);
759 pObj->SetReg(reg, ZD_CR46, 0x90);
760 pObj->SetReg(reg, ZD_CR89, 0x18);
761 pObj->SetReg(reg, ZD_CR92, 0x0a);
762
763 pObj->SetReg(reg, ZD_CR101, 0x13);
764 pObj->SetReg(reg, ZD_CR102, 0x27);
765 pObj->SetReg(reg, ZD_CR106, 0x20);
766 pObj->SetReg(reg, ZD_CR107, 0x24);
767 pObj->SetReg(reg, ZD_CR109, 0x09);
768 pObj->SetReg(reg, ZD_CR110, 0x13);
769 pObj->SetReg(reg, ZD_CR111, 0x13);
770 pObj->SetReg(reg, ZD_CR112, 0x13);
771 pObj->SetReg(reg, ZD_CR113, 0x27);
772 pObj->SetReg(reg, ZD_CR114, 0x27);
773 pObj->SetReg(reg, ZD_CR115, 0x24);
774 pObj->SetReg(reg, ZD_CR116, 0x24);
775 pObj->SetReg(reg, ZD_CR117, 0xf4);
776 pObj->SetReg(reg, ZD_CR118, 0xfa);
777 pObj->SetReg(reg, ZD_CR120, 0x4f);
778 pObj->SetReg(reg, ZD_CR121, 0x77);
779 pObj->SetReg(reg, ZD_CR122, 0xfe);
780 #else
781 pObj->SetReg(reg, ZD_CR23, 0x40);
782 pObj->SetReg(reg, ZD_CR15, 0x20);
783 pObj->SetReg(reg, ZD_CR28, 0x3e);
784 pObj->SetReg(reg, ZD_CR29, 0x00);
785 pObj->SetReg(reg, ZD_CR26, 0x11);
786 pObj->SetReg(reg, ZD_CR44, 0x34); //4112
787 pObj->SetReg(reg, ZD_CR106, 0x2a);
788 pObj->SetReg(reg, ZD_CR107, 0x1a);
789 pObj->SetReg(reg, ZD_CR109, 0x2b);
790 pObj->SetReg(reg, ZD_CR110, 0x2b);
791 pObj->SetReg(reg, ZD_CR111, 0x2b);
792 pObj->SetReg(reg, ZD_CR112, 0x2b);
793
794 #if (defined(GCCK) && defined(OFDM))
795 pObj->SetReg(reg, ZD_CR10, 0x89);
796 pObj->SetReg(reg, ZD_CR17, 0x20);
797 pObj->SetReg(reg, ZD_CR26, 0x93);
798 pObj->SetReg(reg, ZD_CR34, 0x30);
799 pObj->SetReg(reg, ZD_CR35, 0x40);
800
801 pObj->SetReg(reg, ZD_CR41, 0x24);
802 pObj->SetReg(reg, ZD_CR44, 0x32);
803 pObj->SetReg(reg, ZD_CR46, 0x90);
804 pObj->SetReg(reg, ZD_CR89, 0x18);
805 pObj->SetReg(reg, ZD_CR92, 0x0a);
806 pObj->SetReg(reg, ZD_CR101, 0x13);
807 pObj->SetReg(reg, ZD_CR102, 0x27);
808 pObj->SetReg(reg, ZD_CR106, 0x20);
809 pObj->SetReg(reg, ZD_CR107, 0x24);
810 //pObj->SetReg(reg, ZD_CR109, 0x09);
811 //pObj->SetReg(reg, ZD_CR110, 0x13);
812 //pObj->SetReg(reg, ZD_CR111, 0x13);
813
814
815
816
817 pObj->SetReg(reg, ZD_CR109, 0x13); //4326
818 pObj->SetReg(reg, ZD_CR110, 0x27); //4326
819 pObj->SetReg(reg, ZD_CR111, 0x27); //4326
820 pObj->SetReg(reg, ZD_CR112, 0x13);
821 pObj->SetReg(reg, ZD_CR113, 0x27);
822 pObj->SetReg(reg, ZD_CR114, 0x27);
823 pObj->SetReg(reg, ZD_CR115, 0x24);
824 pObj->SetReg(reg, ZD_CR116, 0x24);
825 pObj->SetReg(reg, ZD_CR117, 0xf4);
826 //pObj->SetReg(reg, ZD_CR118, 0xfa);
827 pObj->SetReg(reg, ZD_CR118, 0x00); //4326
828 pObj->SetReg(reg, ZD_CR120, 0x4f);
829 //pObj->SetReg(reg, ZD_CR121, 0x77); //3n12
830 //pObj->SetReg(reg, ZD_CR121, 0x13); //3d24
831 pObj->SetReg(reg, ZD_CR121, 0x06); //4326
832 pObj->SetReg(reg, ZD_CR122, 0xfe);
833 pObj->SetReg(reg, ZD_CR150, 0x0d); //4407
834
835 #elif (defined(ECCK_60_5))
836 pObj->SetReg(reg, ZD_CR26, 0x91);
837 pObj->SetReg(reg, ZD_CR47, 0x1E);
838 pObj->SetReg(reg, ZD_CR106, 0x44);
839 pObj->SetReg(reg, ZD_CR107, 0x00);
840 pObj->SetReg(reg, ZD_CR14, 0x80);
841 pObj->SetReg(reg, ZD_CR10, 0x89);
842 pObj->SetReg(reg, ZD_CR11, 0x00);
843 pObj->SetReg(reg, ZD_CR24, 0x0e);
844 pObj->SetReg(reg, ZD_CR41, 0x24);
845 pObj->SetReg(reg, ZD_CR159, 0x93);
846 pObj->SetReg(reg, ZD_CR160, 0xfc);
847 pObj->SetReg(reg, ZD_CR161, 0x1e);
848 pObj->SetReg(reg, ZD_CR162, 0x24);
849 #endif
850 #endif
851
852 pObj->CR122Flag = 2;
853 pObj->CR31Flag = 2;
854
855 //UnLockPhyReg(pObj);
856
857 #if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )
858 pObj->SetReg(reg, ZD_PE1_PE2, 0x02);
859 #else
860 //LockPhyReg(pObj);
861 tmpvalue = pObj->GetReg(reg, ZD_CR203);
862 tmpvalue &= ~BIT_4;
863 pObj->SetReg(reg, ZD_CR203, tmpvalue);
864 //UnLockPhyReg(pObj);
865 #endif
866
867 HW_Set_IF_Synthesizer(pObj, M2827BF[ChannelNo]);
868 HW_Set_IF_Synthesizer(pObj, M2827BN[ChannelNo]);
869 HW_Set_IF_Synthesizer(pObj, 0x00400);
870 HW_Set_IF_Synthesizer(pObj, 0x00ca1);
871 HW_Set_IF_Synthesizer(pObj, 0x10072);
872 HW_Set_IF_Synthesizer(pObj, 0x18645);
873 HW_Set_IF_Synthesizer(pObj, 0x04006);
874 HW_Set_IF_Synthesizer(pObj, 0x000a7);
875 HW_Set_IF_Synthesizer(pObj, 0x08258);
876 HW_Set_IF_Synthesizer(pObj, 0x03fc9);
877 HW_Set_IF_Synthesizer(pObj, 0x0040a);
878 HW_Set_IF_Synthesizer(pObj, 0x0000b);
879 HW_Set_IF_Synthesizer(pObj, 0x0026c);
880 #if defined(ECCK_60_5)
881 HW_Set_IF_Synthesizer(pObj, 0x04258);
882 #endif
883
884 #if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )
885 pObj->SetReg(reg, ZD_PE1_PE2, 0x03);
886 #else
887 //LockPhyReg(pObj);
888 tmpvalue = pObj->GetReg(reg, ZD_CR203);
889 tmpvalue |= BIT_4;
890
891 pObj->SetReg(reg, ZD_CR203, tmpvalue);;
892 //UnLockPhyReg(pObj);
893 #endif
894
895 UnLockPhyReg(pObj);
896 }
897
898
899
900 void
901 HW_Set_Maxim_New_Chips2(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
902 {
903 void *reg = pObj->reg;
904 U32 tmpvalue;
905
906 // Get Phy-Config permission
907 LockPhyReg(pObj);
908
909 #ifdef HOST_IF_USB
910 pObj->SetReg(reg, ZD_CR23, 0x40);
911 pObj->SetReg(reg, ZD_CR15, 0x20);
912 pObj->SetReg(reg, ZD_CR28, 0x3e);
913 pObj->SetReg(reg, ZD_CR29, 0x00);
914 pObj->SetReg(reg, ZD_CR26, 0x11);
915 pObj->SetReg(reg, ZD_CR44, 0x33);
916 pObj->SetReg(reg, ZD_CR106, 0x2a);
917 pObj->SetReg(reg, ZD_CR107, 0x1a);
918 pObj->SetReg(reg, ZD_CR109, 0x2b);
919 pObj->SetReg(reg, ZD_CR110, 0x2b);
920 pObj->SetReg(reg, ZD_CR111, 0x2b);
921 pObj->SetReg(reg, ZD_CR112, 0x2b);
922 pObj->SetReg(reg, ZD_CR10, 0x89);
923 pObj->SetReg(reg, ZD_CR17, 0x20);
924 pObj->SetReg(reg, ZD_CR26, 0x93);
925 pObj->SetReg(reg, ZD_CR34, 0x30);
926 pObj->SetReg(reg, ZD_CR35, 0x40);
927 pObj->SetReg(reg, ZD_CR41, 0x24);
928 pObj->SetReg(reg, ZD_CR44, 0x32);
929 pObj->SetReg(reg, ZD_CR46, 0x90);
930 pObj->SetReg(reg, ZD_CR89, 0x18);
931 pObj->SetReg(reg, ZD_CR92, 0x0a);
932 pObj->SetReg(reg, ZD_CR101, 0x13);
933 pObj->SetReg(reg, ZD_CR102, 0x27);
934 pObj->SetReg(reg, ZD_CR106, 0x20);
935 pObj->SetReg(reg, ZD_CR107, 0x24);
936 pObj->SetReg(reg, ZD_CR109, 0x09);
937 pObj->SetReg(reg, ZD_CR110, 0x13);
938 pObj->SetReg(reg, ZD_CR111, 0x13);
939 pObj->SetReg(reg, ZD_CR112, 0x13);
940 pObj->SetReg(reg, ZD_CR113, 0x27);
941 pObj->SetReg(reg, ZD_CR114, 0x27);
942 pObj->SetReg(reg, ZD_CR115, 0x24);
943 pObj->SetReg(reg, ZD_CR116, 0x24);
944
945 pObj->SetReg(reg, ZD_CR117, 0xf4);
946 pObj->SetReg(reg, ZD_CR118, 0xfa);
947 pObj->SetReg(reg, ZD_CR120, 0x4f);
948
949 pObj->SetReg(reg, ZD_CR121, 0x77);
950
951
952 pObj->SetReg(reg, ZD_CR122, 0xfe);
953
954 #else
955 pObj->SetReg(reg, ZD_CR23, 0x40);
956 pObj->SetReg(reg, ZD_CR15, 0x20);
957 pObj->SetReg(reg, ZD_CR28, 0x3e);
958 pObj->SetReg(reg, ZD_CR29, 0x00);
959 pObj->SetReg(reg, ZD_CR26, 0x11);
960 pObj->SetReg(reg, ZD_CR44, 0x33);
961 pObj->SetReg(reg, ZD_CR106, 0x2a);
962 pObj->SetReg(reg, ZD_CR107, 0x1a);
963 pObj->SetReg(reg, ZD_CR109, 0x2b);
964 pObj->SetReg(reg, ZD_CR110, 0x2b);
965 pObj->SetReg(reg, ZD_CR111, 0x2b);
966 pObj->SetReg(reg, ZD_CR112, 0x2b);
967
968 #if (defined(GCCK) && defined(OFDM))
969 pObj->SetReg(reg, ZD_CR10, 0x89);
970 pObj->SetReg(reg, ZD_CR17, 0x20);
971 pObj->SetReg(reg, ZD_CR26, 0x93);
972 pObj->SetReg(reg, ZD_CR34, 0x30);
973 pObj->SetReg(reg, ZD_CR35, 0x40);
974 pObj->SetReg(reg, ZD_CR41, 0x24);
975 pObj->SetReg(reg, ZD_CR44, 0x32);
976
977 pObj->SetReg(reg, ZD_CR46, 0x90);
978 pObj->SetReg(reg, ZD_CR79, 0x58); //for Atheros compability 4415
979 pObj->SetReg(reg, ZD_CR80, 0x30); //for Atheros compability
980 pObj->SetReg(reg, ZD_CR81, 0x30); //for Atheros compability
981 pObj->SetReg(reg, ZD_CR89, 0x18);
982
983
984
985
986
987
988
989 pObj->SetReg(reg, ZD_CR92, 0x0a);
990 pObj->SetReg(reg, ZD_CR101, 0x13);
991 pObj->SetReg(reg, ZD_CR102, 0x27);
992 pObj->SetReg(reg, ZD_CR106, 0x20);
993 pObj->SetReg(reg, ZD_CR107, 0x24);
994 pObj->SetReg(reg, ZD_CR109, 0x09);
995 pObj->SetReg(reg, ZD_CR110, 0x13);
996 pObj->SetReg(reg, ZD_CR111, 0x13);
997 pObj->SetReg(reg, ZD_CR112, 0x13);
998 pObj->SetReg(reg, ZD_CR113, 0x27);
999 pObj->SetReg(reg, ZD_CR114, 0x27);
1000 pObj->SetReg(reg, ZD_CR115, 0x24);
1001 pObj->SetReg(reg, ZD_CR116, 0x24);
1002 pObj->SetReg(reg, ZD_CR117, 0xf4);
1003 //pObj->SetReg(reg, ZD_CR118, 0xfa);
1004 pObj->SetReg(reg, ZD_CR118, 0x00); //4326
1005 pObj->SetReg(reg, ZD_CR120, 0x4f);
1006 //pObj->SetReg(reg, ZD_CR121, 0x77); //3n12
1007 //pObj->SetReg(reg, ZD_CR121, 0x13); //3d24
1008 pObj->SetReg(reg, ZD_CR121, 0x06); //4326
1009 pObj->SetReg(reg, ZD_CR122, 0xfe);
1010 #elif (defined(ECCK_60_5))
1011
1012 pObj->SetReg(reg, ZD_CR47, 0x1E);
1013 pObj->SetReg(reg, ZD_CR106, 0x04);
1014 pObj->SetReg(reg, ZD_CR107, 0x00);
1015 pObj->SetReg(reg, ZD_CR14, 0x80);
1016 pObj->SetReg(reg, ZD_CR10, 0x89);
1017
1018 pObj->SetReg(reg, ZD_CR11, 0x00);
1019 pObj->SetReg(reg, ZD_CR161, 0x28);
1020 pObj->SetReg(reg, ZD_CR162, 0x26);
1021
1022 pObj->SetReg(reg, ZD_CR24, 0x0e);
1023 pObj->SetReg(reg, ZD_CR41, 0x24);
1024 pObj->SetReg(reg, ZD_CR159, 0x93);
1025 pObj->SetReg(reg, ZD_CR160, 0xfc);
1026 pObj->SetReg(reg, ZD_CR161, 0x20);
1027 pObj->SetReg(reg, ZD_CR162, 0x26);
1028 #endif
1029 #endif
1030
1031 pObj->CR122Flag = 2;
1032 pObj->CR31Flag = 2;
1033
1034 //UnLockPhyReg(pObj);
1035
1036 #if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )
1037 pObj->SetReg(reg, ZD_PE1_PE2, 2);
1038 #else
1039 //LockPhyReg(pObj);
1040 tmpvalue = pObj->GetReg(reg, ZD_CR203);
1041 tmpvalue &= ~BIT_4;
1042 pObj->SetReg(reg, ZD_CR203, tmpvalue);
1043 //UnLockPhyReg(pObj);
1044 #endif
1045
1046 HW_Set_IF_Synthesizer(pObj, M2827BF2[ChannelNo]);
1047 HW_Set_IF_Synthesizer(pObj, M2827BN2[ChannelNo]);
1048 HW_Set_IF_Synthesizer(pObj, 0x00400);
1049 HW_Set_IF_Synthesizer(pObj, 0x00ca1);
1050 HW_Set_IF_Synthesizer(pObj, 0x10072);
1051 HW_Set_IF_Synthesizer(pObj, 0x18645);
1052 HW_Set_IF_Synthesizer(pObj, 0x04006);
1053 HW_Set_IF_Synthesizer(pObj, 0x000a7);
1054 HW_Set_IF_Synthesizer(pObj, 0x08258);
1055
1056 HW_Set_IF_Synthesizer(pObj, 0x03fc9);
1057 HW_Set_IF_Synthesizer(pObj, 0x0040a);
1058 HW_Set_IF_Synthesizer(pObj, 0x0000b);
1059 HW_Set_IF_Synthesizer(pObj, 0x0026c);
1060 #if defined(ECCK_60_5)
1061 HW_Set_IF_Synthesizer(pObj, 0x04258);
1062 #endif
1063
1064 #if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )
1065
1066 pObj->SetReg(reg, ZD_PE1_PE2, 3);
1067
1068 #else
1069 //LockPhyReg(pObj);
1070 tmpvalue = pObj->GetReg(reg, ZD_CR203);
1071 tmpvalue |= BIT_4;
1072 pObj->SetReg(reg, ZD_CR203, tmpvalue);
1073 //UnLockPhyReg(pObj);
1074 #endif
1075 UnLockPhyReg(pObj);
1076 }
1077
1078
1079 void
1080 HW_Set_GCT_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
1081 {
1082 void *reg = pObj->reg;
1083
1084 if (!InitChOnly){
1085 LockPhyReg(pObj);
1086 pObj->SetReg(reg, ZD_CR47, 0x1E);
1087 pObj->SetReg(reg, ZD_CR15, 0xdc);
1088 pObj->SetReg(reg, ZD_CR113, 0xc0); //3910
1089 pObj->SetReg(reg, ZD_CR20, 0x0c);
1090 pObj->SetReg(reg, ZD_CR17, 0x65);
1091 pObj->SetReg(reg, ZD_CR34, 0x04);
1092 pObj->SetReg(reg, ZD_CR35, 0x35);
1093 pObj->SetReg(reg, ZD_CR24, 0x20);
1094 pObj->SetReg(reg, ZD_CR9, 0xe0);
1095 pObj->SetReg(reg, ZD_CR127, 0x02);
1096 pObj->SetReg(reg, ZD_CR10, 0x91);
1097 pObj->SetReg(reg, ZD_CR23, 0x7f);
1098 pObj->SetReg(reg, ZD_CR27, 0x10);
1099 pObj->SetReg(reg, ZD_CR28, 0x7a);
1100 pObj->SetReg(reg, ZD_CR79, 0xb5);
1101 pObj->SetReg(reg, ZD_CR64, 0x80);
1102 //++ Enable D.C cancellation (CR33 Bit_5) to avoid
1103 // CCA always high.
1104 pObj->SetReg(reg, ZD_CR33, 0x28);
1105 //--
1106
1107 pObj->SetReg(reg, ZD_CR38, 0x30);
1108
1109 UnLockPhyReg(pObj);
1110
1111 HW_Set_IF_Synthesizer(pObj, 0x1F0000);
1112 HW_Set_IF_Synthesizer(pObj, 0x1F0000);
1113 HW_Set_IF_Synthesizer(pObj, 0x1F0200);
1114 HW_Set_IF_Synthesizer(pObj, 0x1F0600);
1115 HW_Set_IF_Synthesizer(pObj, 0x1F8600);
1116 HW_Set_IF_Synthesizer(pObj, 0x1F8600);
1117 HW_Set_IF_Synthesizer(pObj, 0x002050);
1118 HW_Set_IF_Synthesizer(pObj, 0x1F8000);
1119 HW_Set_IF_Synthesizer(pObj, 0x1F8200);
1120 HW_Set_IF_Synthesizer(pObj, 0x1F8600);
1121 HW_Set_IF_Synthesizer(pObj, 0x1c0000);
1122 HW_Set_IF_Synthesizer(pObj, 0x10c458);
1123
1124 HW_Set_IF_Synthesizer(pObj, 0x088e92);
1125 HW_Set_IF_Synthesizer(pObj, 0x187b82);
1126 HW_Set_IF_Synthesizer(pObj, 0x0401b4);
1127 HW_Set_IF_Synthesizer(pObj, 0x140816);
1128 HW_Set_IF_Synthesizer(pObj, 0x0c7000);
1129 HW_Set_IF_Synthesizer(pObj, 0x1c0000);
1130 HW_Set_IF_Synthesizer(pObj, 0x02ccae);
1131 HW_Set_IF_Synthesizer(pObj, 0x128023);
1132 HW_Set_IF_Synthesizer(pObj, 0x0a0000);
1133 HW_Set_IF_Synthesizer(pObj, GRF5101T[ChannelNo]);
1134 HW_Set_IF_Synthesizer(pObj, 0x06e380);
1135 HW_Set_IF_Synthesizer(pObj, 0x16cb94);
1136 HW_Set_IF_Synthesizer(pObj, 0x0e1740);
1137 HW_Set_IF_Synthesizer(pObj, 0x014980);
1138 HW_Set_IF_Synthesizer(pObj, 0x116240);
1139 HW_Set_IF_Synthesizer(pObj, 0x090000);
1140 HW_Set_IF_Synthesizer(pObj, 0x192304);
1141 HW_Set_IF_Synthesizer(pObj, 0x05112f);
1142 HW_Set_IF_Synthesizer(pObj, 0x0d54a8);
1143 HW_Set_IF_Synthesizer(pObj, 0x0f8000);
1144 HW_Set_IF_Synthesizer(pObj, 0x1c0008);
1145 HW_Set_IF_Synthesizer(pObj, 0x1c0000);
1146
1147 HW_Set_IF_Synthesizer(pObj, GRF5101T[ChannelNo]);
1148 HW_Set_IF_Synthesizer(pObj, 0x1c0008);
1149 HW_Set_IF_Synthesizer(pObj, 0x150000);
1150 HW_Set_IF_Synthesizer(pObj, 0x0c7000);
1151 HW_Set_IF_Synthesizer(pObj, 0x150800);
1152 HW_Set_IF_Synthesizer(pObj, 0x150000);
1153 }
1154 else{
1155 HW_Set_IF_Synthesizer(pObj, 0x1c0000);
1156 HW_Set_IF_Synthesizer(pObj, GRF5101T[ChannelNo]);
1157
1158 HW_Set_IF_Synthesizer(pObj, 0x1c0008);
1159 }
1160 }
1161
1162
1163 void
1164 HW_Set_AL2210MPVB_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
1165 {
1166 void *reg = pObj->reg;
1167 U32 tmpvalue;
1168
1169 pObj->SetReg(reg, ZD_PE1_PE2, 2);
1170
1171 if (!InitChOnly){
1172 LockPhyReg(pObj);
1173 pObj->SetReg(reg, ZD_CR9, 0xe0);
1174 pObj->SetReg(reg, ZD_CR10, 0x91);
1175 pObj->SetReg(reg, ZD_CR12, 0x90);
1176 pObj->SetReg(reg, ZD_CR15, 0xd0);
1177 pObj->SetReg(reg, ZD_CR16, 0x40);
1178 pObj->SetReg(reg, ZD_CR17, 0x58);
1179 pObj->SetReg(reg, ZD_CR18, 0x04);
1180 pObj->SetReg(reg, ZD_CR23, 0x66);
1181 pObj->SetReg(reg, ZD_CR24, 0x14);
1182 pObj->SetReg(reg, ZD_CR26, 0x90);
1183 pObj->SetReg(reg, ZD_CR27, 0x30);
1184 pObj->SetReg(reg, ZD_CR31, 0x80);
1185 pObj->SetReg(reg, ZD_CR34, 0x06);
1186 pObj->SetReg(reg, ZD_CR35, 0x3e);
1187 pObj->SetReg(reg, ZD_CR38, 0x38);
1188 pObj->SetReg(reg, ZD_CR46, 0x90);
1189 pObj->SetReg(reg, ZD_CR47, 0x1E);
1190 pObj->SetReg(reg, ZD_CR64, 0x64);
1191 pObj->SetReg(reg, ZD_CR79, 0xb5);
1192 pObj->SetReg(reg, ZD_CR80, 0x38);
1193 pObj->SetReg(reg, ZD_CR81, 0x30);
1194 pObj->SetReg(reg, ZD_CR113, 0xc0);
1195 pObj->SetReg(reg, ZD_CR127, 0x03);
1196 UnLockPhyReg(pObj);
1197
1198 HW_Set_IF_Synthesizer(pObj, AL2210TB[ChannelNo]);
1199 HW_Set_IF_Synthesizer(pObj, 0x00fcb1);
1200 HW_Set_IF_Synthesizer(pObj, 0x358132);
1201 HW_Set_IF_Synthesizer(pObj, 0x0108b3);
1202 HW_Set_IF_Synthesizer(pObj, 0xc77804);
1203 HW_Set_IF_Synthesizer(pObj, 0x456415);
1204 HW_Set_IF_Synthesizer(pObj, 0xff2226);
1205 HW_Set_IF_Synthesizer(pObj, 0x806667);
1206 HW_Set_IF_Synthesizer(pObj, 0x7860f8);
1207 HW_Set_IF_Synthesizer(pObj, 0xbb01c9);
1208 HW_Set_IF_Synthesizer(pObj, 0x00000A);
1209 HW_Set_IF_Synthesizer(pObj, 0x00000B);
1210
1211 LockPhyReg(pObj);
1212 pObj->SetReg(reg, ZD_CR47, 0x1E);
1213 tmpvalue = pObj->GetReg(reg, ZD_RADIO_PD);
1214
1215 tmpvalue &= ~BIT_0;
1216 pObj->SetReg(reg, ZD_RADIO_PD, tmpvalue);
1217 tmpvalue |= BIT_0;
1218 pObj->SetReg(reg, ZD_RADIO_PD, tmpvalue);
1219 pObj->SetReg(reg, ZD_RFCFG, 0x5);
1220 pObj->DelayUs(100);
1221 pObj->SetReg(reg, ZD_RFCFG, 0x0);
1222 pObj->SetReg(reg, ZD_CR47, 0x1E);
1223 UnLockPhyReg(pObj);
1224 }
1225 else {
1226 LockPhyReg(pObj);
1227 pObj->SetReg(reg, ZD_CR47, 0x1E);
1228 tmpvalue = pObj->GetReg(reg, ZD_RADIO_PD);
1229 tmpvalue &= ~BIT_0;
1230
1231 pObj->SetReg(reg, ZD_RADIO_PD, tmpvalue);
1232 tmpvalue |= BIT_0;
1233
1234
1235
1236 pObj->SetReg(reg, ZD_RADIO_PD, tmpvalue);
1237 pObj->SetReg(reg, ZD_RFCFG, 0x5);
1238 pObj->DelayUs(100);
1239 pObj->SetReg(reg, ZD_RFCFG, 0x0);
1240 pObj->SetReg(reg, ZD_CR47, 0x1E);
1241 UnLockPhyReg(pObj);
1242 HW_Set_IF_Synthesizer(pObj, AL2210TB[ChannelNo]);
1243 }
1244
1245 pObj->SetReg(reg, ZD_PE1_PE2, 3);
1246 }
1247
1248
1249 void
1250 HW_Set_AL2210_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
1251
1252 {
1253 void *reg = pObj->reg;
1254 U32 tmpvalue;
1255
1256 pObj->SetReg(reg, ZD_PE1_PE2, 2);
1257
1258 if (!InitChOnly){
1259 LockPhyReg(pObj);
1260
1261
1262
1263 pObj->SetReg(reg, ZD_CR9, 0xe0);
1264 pObj->SetReg(reg, ZD_CR10, 0x91);
1265 pObj->SetReg(reg, ZD_CR12, 0x90);
1266 pObj->SetReg(reg, ZD_CR15, 0xd0);
1267 pObj->SetReg(reg, ZD_CR16, 0x40);
1268 pObj->SetReg(reg, ZD_CR17, 0x58);
1269 pObj->SetReg(reg, ZD_CR18, 0x04);
1270 pObj->SetReg(reg, ZD_CR23, 0x66);
1271 pObj->SetReg(reg, ZD_CR24, 0x14);
1272
1273 pObj->SetReg(reg, ZD_CR26, 0x90);
1274
1275 pObj->SetReg(reg, ZD_CR31, 0x80);
1276 pObj->SetReg(reg, ZD_CR34, 0x06);
1277 pObj->SetReg(reg, ZD_CR35, 0x3e);
1278 pObj->SetReg(reg, ZD_CR38, 0x38);
1279 pObj->SetReg(reg, ZD_CR46, 0x90);
1280 pObj->SetReg(reg, ZD_CR47, 0x1E);
1281 pObj->SetReg(reg, ZD_CR64, 0x64);
1282 pObj->SetReg(reg, ZD_CR79, 0xb5);
1283 pObj->SetReg(reg, ZD_CR80, 0x38);
1284 pObj->SetReg(reg, ZD_CR81, 0x30);
1285 pObj->SetReg(reg, ZD_CR113, 0xc0);
1286 pObj->SetReg(reg, ZD_CR127, 0x3);
1287 UnLockPhyReg(pObj);
1288
1289 HW_Set_IF_Synthesizer(pObj, AL2210TB[ChannelNo]);
1290
1291 HW_Set_IF_Synthesizer(pObj, 0x00fcb1);
1292 HW_Set_IF_Synthesizer(pObj, 0x358132);
1293 HW_Set_IF_Synthesizer(pObj, 0x0108b3);
1294 HW_Set_IF_Synthesizer(pObj, 0xc77804);
1295 HW_Set_IF_Synthesizer(pObj, 0x456415);
1296 HW_Set_IF_Synthesizer(pObj, 0xff2226);
1297 HW_Set_IF_Synthesizer(pObj, 0x806667);
1298 HW_Set_IF_Synthesizer(pObj, 0x7860f8);
1299 HW_Set_IF_Synthesizer(pObj, 0xbb01c9);
1300 HW_Set_IF_Synthesizer(pObj, 0x00000A);
1301 HW_Set_IF_Synthesizer(pObj, 0x00000B);
1302
1303 LockPhyReg(pObj);
1304 pObj->SetReg(reg, ZD_CR47, 0x1E);
1305 tmpvalue = pObj->GetReg(reg, ZD_RADIO_PD);
1306 tmpvalue &= ~BIT_0;
1307 pObj->SetReg(reg, ZD_RADIO_PD, tmpvalue);
1308
1309 tmpvalue |= BIT_0;
1310 pObj->SetReg(reg, ZD_RADIO_PD, tmpvalue);
1311 pObj->SetReg(reg, ZD_RFCFG, 0x5);
1312 pObj->DelayUs(100);
1313 pObj->SetReg(reg, ZD_RFCFG, 0x0);
1314 pObj->SetReg(reg, ZD_CR47, 0x1E);
1315 UnLockPhyReg(pObj);
1316 }
1317 else {
1318 LockPhyReg(pObj);
1319 pObj->SetReg(reg, ZD_CR47, 0x1E);
1320 tmpvalue = pObj->GetReg(reg, ZD_RADIO_PD);
1321 tmpvalue &= ~BIT_0;
1322 pObj->SetReg(reg, ZD_RADIO_PD, tmpvalue);
1323 tmpvalue |= BIT_0;
1324 pObj->SetReg(reg, ZD_RADIO_PD, tmpvalue);
1325 pObj->SetReg(reg, ZD_RFCFG, 0x5);
1326 pObj->DelayUs(100);
1327 pObj->SetReg(reg, ZD_RFCFG, 0x0);
1328 pObj->SetReg(reg, ZD_CR47, 0x1E);
1329 UnLockPhyReg(pObj);
1330 HW_Set_IF_Synthesizer(pObj, AL2210TB[ChannelNo]);
1331 }
1332
1333 pObj->SetReg(reg, ZD_PE1_PE2, 3);
1334 }
1335 */
1336 //------------------------------------------------------------------------------
1337 // Procedure: HW_Set_UW2453_RF_Chips
1338 //
1339 // Description:
1340 //
1341 // Arguments:
1342 // Adapter - ptr to Adapter object instance
1343 // ChannelNo
1344 // Initial Channel only
1345 //
1346 // Returns: (none)
1347 //
1348 // Note:
1349 //-------------------------------------------------------------------------------
1350 void
1351 HW_Set_UW2453_RF_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
1352 {
1353 U32 tmpvalue;
1354 U32 ChannelNo_temp;
1355 int i;
1356 BOOLEAN bLocked;
1357 void *reg = pObj->reg;
1358
1359 #if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )
1360 pObj->SetReg(reg, PE1_PE2, 2);
1361 #else
1362 LockPhyReg(pObj);
1363 //pObj->GetReg(reg, ZD_CR203, &tmpvalue);
1364 tmpvalue &= ~BIT_4;
1365 //pObj->SetReg(reg, ZD_CR203, tmpvalue);
1366 UnLockPhyReg(pObj);
1367 #endif
1368 /*
1369 if(pObj->UW2453MiniCard)
1370 {
1371 if(pObj->UW2453NoTXfollowRX)
1372 {
1373 LockPhyReg(pObj);
1374 if(pObj->CardSetting.BSSType != PSEUDO_IBSS)
1375 {
1376 if(!pObj->UWDeafaltAntennt)
1377 {
1378 if(!(pObj->UW2453ChannelSelectAntennaAUX[ChannelNo-1]))
1379 {
1380 ZD1205_WRITE_REGISTER(Adapter, CR9, 0xe0);
1381 }
1382 if(pObj->UW2453ChannelSelectAntennaAUX[ChannelNo-1])
1383 {
1384 ZD1205_WRITE_REGISTER(Adapter, CR9, 0xe4);
1385 }
1386 }
1387 else
1388 {
1389 if(!(pObj->UW2453ChannelSelectAntennaAUX[ChannelNo-1]))
1390 {
1391 ZD1205_WRITE_REGISTER(Adapter, CR9, 0xe4);
1392 }
1393 if(pObj->UW2453ChannelSelectAntennaAUX[ChannelNo-1])
1394 {
1395 ZD1205_WRITE_REGISTER(Adapter, CR9, 0xe0);
1396 }
1397 }
1398 pObj->UW2453SWDeafaultAntenna = TRUE;
1399
1400 }
1401 UnLockPhyReg(pObj);
1402 }
1403 }
1404 */
1405 if (!InitChOnly){
1406 LockPhyReg(pObj);
1407 pObj->SetReg(reg, ZD_CR10, 0x89);
1408 pObj->SetReg(reg, ZD_CR15, 0x20);
1409 pObj->SetReg(reg, ZD_CR17, 0x28); //6112 no change
1410 pObj->SetReg(reg, ZD_CR23, 0x38);
1411 pObj->SetReg(reg, ZD_CR24, 0x20);
1412 pObj->SetReg(reg, ZD_CR26, 0x93);
1413 pObj->SetReg(reg, ZD_CR27, 0x15);
1414 pObj->SetReg(reg, ZD_CR28, 0x3e);
1415 pObj->SetReg(reg, ZD_CR29, 0x00);
1416 pObj->SetReg(reg, ZD_CR33, 0x28);
1417 pObj->SetReg(reg, ZD_CR34, 0x30);
1418 pObj->SetReg(reg, ZD_CR35, 0x43); //6112 3E->43
1419 pObj->SetReg(reg, ZD_CR41, 0x24);
1420 pObj->SetReg(reg, ZD_CR44, 0x32);
1421 pObj->SetReg(reg, ZD_CR46, 0x92); //6112 96->92
1422 pObj->SetReg(reg, ZD_CR47, 0x1E);
1423 pObj->SetReg(reg, ZD_CR48, 0x04); //5602 Roger
1424 pObj->SetReg(reg, ZD_CR49, 0xfa);
1425 pObj->SetReg(reg, ZD_CR79, 0x58);
1426 pObj->SetReg(reg, ZD_CR80, 0x30);
1427 pObj->SetReg(reg, ZD_CR81, 0x30);
1428 pObj->SetReg(reg, ZD_CR87, 0x0A);
1429 pObj->SetReg(reg, ZD_CR89, 0x04);
1430 pObj->SetReg(reg, ZD_CR91, 0x00);
1431 pObj->SetReg(reg, ZD_CR92, 0x0a);
1432 pObj->SetReg(reg, ZD_CR98, 0x8d);
1433 pObj->SetReg(reg, ZD_CR99, 0x28);
1434 pObj->SetReg(reg, ZD_CR100, 0x02);
1435 pObj->SetReg(reg, ZD_CR101, 0x09); //6112 13->1f //6220 1f->13 //6407 13->9
1436 pObj->SetReg(reg, ZD_CR102, 0x27);
1437 pObj->SetReg(reg, ZD_CR106, 0x1c); //5d07 //6112 1f->1c //6220 1c->1f //6221 1f->1c
1438 pObj->SetReg(reg, ZD_CR107, 0x1c); //6220 1c->1a //6221 1a->1c
1439 pObj->SetReg(reg, ZD_CR109, 0x13);
1440 pObj->SetReg(reg, ZD_CR110, 0x1f); //6112 13->1f //6221 1f->13 //6407 13->0x09
1441 pObj->SetReg(reg, ZD_CR111, 0x13);
1442 pObj->SetReg(reg, ZD_CR112, 0x1f);
1443 pObj->SetReg(reg, ZD_CR113, 0x27);
1444 pObj->SetReg(reg, ZD_CR114, 0x23); //6221 27->23
1445 pObj->SetReg(reg, ZD_CR115, 0x24); //6112 24->1c //6220 1c->24
1446 pObj->SetReg(reg, ZD_CR116, 0x24); //6220 1c->24
1447 pObj->SetReg(reg, ZD_CR117, 0xfa); //6112 fa->f8 //6220 f8->f4 //6220 f4->fa
1448 pObj->SetReg(reg, ZD_CR118, 0xf0); //5d07 //6112 f0->f2 //6220 f2->f0
1449 pObj->SetReg(reg, ZD_CR119, 0x1a); //6112 1a->10 //6220 10->14 //6220 14->1a
1450 pObj->SetReg(reg, ZD_CR120, 0x4f);
1451 pObj->SetReg(reg, ZD_CR121, 0x1f); //6220 4f->1f
1452 pObj->SetReg(reg, ZD_CR122, 0xf0);
1453 pObj->SetReg(reg, ZD_CR123, 0x57);
1454 pObj->SetReg(reg, ZD_CR125, 0xad);
1455 pObj->SetReg(reg, ZD_CR126, 0x6c);
1456 pObj->SetReg(reg, ZD_CR127, 0x03);
1457 pObj->SetReg(reg, ZD_CR128, 0x14); //6302 12->11
1458 pObj->SetReg(reg, ZD_CR129, 0x12); //6301 10->0F
1459 pObj->SetReg(reg, ZD_CR130, 0x10);
1460 pObj->SetReg(reg, ZD_CR137, 0x50);
1461 pObj->SetReg(reg, ZD_CR138, 0xa8);
1462 pObj->SetReg(reg, ZD_CR144, 0xac);
1463 pObj->SetReg(reg, ZD_CR146, 0x20);
1464
1465 pObj->SetReg(reg, ZD_CR252, 0xff);
1466 pObj->SetReg(reg, ZD_CR253, 0xff);
1467
1468 UnLockPhyReg(pObj);
1469
1470 HW_Set_IF_Synthesizer(pObj, 0x40002b);
1471 HW_Set_IF_Synthesizer(pObj, 0x519e4f);
1472 //Set_IF_Synthesizer(Adapter, 0x509e4f); //5d02
1473 HW_Set_IF_Synthesizer(pObj, 0x6f81AD); //6221 6f81ac-> 6f81ff //6418 6f81ff -> 6f81ac
1474 HW_Set_IF_Synthesizer(pObj, 0x73fffe);
1475 //Set_IF_Synthesizer(Adapter, 0x025fcc); // 5d01 cal_fil
1476 HW_Set_IF_Synthesizer(pObj, 0x025f9c); // 5d01 cal_fil
1477
1478 HW_Set_IF_Synthesizer(pObj, 0x100047);
1479 HW_Set_IF_Synthesizer(pObj, 0x200999);
1480 HW_Set_IF_Synthesizer(pObj, 0x307602); //5d01
1481
1482 HW_Set_IF_Synthesizer(pObj, 0x346063);
1483 HW_Set_IF_Synthesizer(pObj, 0x025f98); //idle
1484 HW_Set_IF_Synthesizer(pObj, 0x025f9a); //cal_vco
1485 HW_Set_IF_Synthesizer(pObj, 0x025f94); //rxtx_en (4)
1486 HW_Set_IF_Synthesizer(pObj, 0x027FD4);
1487 //Set_IF_Synthesizer(Adapter, 0x307602); //5d01 //6109
1488
1489 //Auto Lock RF Procedure
1490 pObj->UW2453RFTableIndex=0;
1491 bLocked=FALSE;
1492 for (i=0;i<10;i++) {
1493 //always try channel 1
1494 /*
1495 if(pObj->UW2453MiniCard)
1496 {
1497 Set_IF_Synthesizer(Adapter, UW2453RF_minicard[i][1*3]);
1498 Set_IF_Synthesizer(Adapter, UW2453RF_minicard[i][1*3+1]);
1499 Set_IF_Synthesizer(Adapter, UW2453RF_minicard[i][1*3+2]);
1500 }
1501 else
1502 */
1503 {
1504 HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[i][1*3]);
1505 HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[i][1*3+1]);
1506 HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[i][1*3+2]);
1507 }
1508 //ack interrupt event
1509 pObj->SetReg(reg, 0x85C1, 0x0F);
1510 //ZD1211_WRITE_REGISTER(Adapter, 0x85C1, 0x0F, FALSE);
1511 tmpvalue = pObj->GetReg(reg, 0x85C1);
1512 //ZD1211_READ_REGISTER(Adapter, 0x85C1, &tmpvalue, FALSE);
1513 if ((tmpvalue & 0xf) == 0x0 ) {
1514 bLocked=TRUE;
1515 pObj->UW2453RFTableIndex = i+1;
1516 break;
1517 }
1518 }
1519 if(!bLocked)
1520 {
1521 pObj->UW2453RFTableIndex = i+1;
1522 }
1523
1524
1525 //if (bLocked) {
1526 /*
1527 if(pObj->UW2453MiniCard)
1528 {
1529 Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][1*3]);
1530 Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][1*3+1]);
1531 Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][1*3+2]);
1532 }
1533 else
1534 */
1535 {
1536 HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][1*3]);
1537 HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][1*3+1]);
1538 HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][1*3+2]);
1539 }
1540 //} else { //turn off RF when we can't lock
1541 // Set_IF_Synthesizer(Adapter, 0x025f90);
1542 // LockPhyReg(pObj);
1543 // ZD1205_WRITE_REGISTER(Adapter, CR11, 0x04);
1544 // ZD1205_WRITE_REGISTER(Adapter, CR251, 0x2f);
1545 // UnLockPhyReg(pObj);
1546 //}
1547
1548 }
1549 else{
1550 //Set_IF_Synthesizer(Adapter, 0x40002b);//6109
1551 //Set_IF_Synthesizer(Adapter, 0x519e4f);//6109
1552 //Set_IF_Synthesizer(Adapter, 0x6f81ac);//6109
1553 //Set_IF_Synthesizer(Adapter, 0x73fffe);//6109
1554 //Set_IF_Synthesizer(Adapter, 0x025f9c);//6109
1555 //Set_IF_Synthesizer(Adapter, 0x025fcc); // 5d01 //6109
1556 /*
1557 if(pObj->UW2453MiniCard)
1558 {
1559 Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][ChannelNo*3]);
1560 Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][ChannelNo*3+1]);
1561 Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][ChannelNo*3+2]);
1562 }
1563 else
1564 */
1565 {
1566 HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][ChannelNo*3]);
1567 HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][ChannelNo*3+1]);
1568 HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][ChannelNo*3+2]);
1569 }
1570 //Set_IF_Synthesizer(Adapter, 0x340060);
1571 HW_Set_IF_Synthesizer(pObj, 0x025f98); //5d02
1572 HW_Set_IF_Synthesizer(pObj, 0x025f9a);
1573 HW_Set_IF_Synthesizer(pObj, 0x025f94);
1574 HW_Set_IF_Synthesizer(pObj, 0x027FD4);
1575 //Set_IF_Synthesizer(Adapter, UW2453RF[ChannelNo*3+2]); //5d02//6109
1576
1577
1578 }
1579 LockPhyReg(pObj);
1580 //Band Edge issue
1581 if(PURE_A_MODE != mMacMode)
1582 {
1583 if(pObj->HWFeature & BIT_21)
1584 {
1585 if(ChannelNo == 1 || ChannelNo == 11)
1586 {
1587 if(pObj->PHY_Decrease_CR128_state)
1588 {
1589 pObj->SetReg(reg, ZD_CR128, 0x12);
1590 pObj->SetReg(reg, ZD_CR129, 0x12);
1591 pObj->SetReg(reg, ZD_CR130, 0x10);
1592 }
1593 else
1594 {
1595 pObj->SetReg(reg, ZD_CR128, 0x10);
1596 pObj->SetReg(reg, ZD_CR129, 0x10);
1597 pObj->SetReg(reg, ZD_CR130, 0x10);
1598 }
1599 }
1600 else
1601 {
1602 pObj->SetReg(reg, ZD_CR128, 0x14);
1603 pObj->SetReg(reg, ZD_CR129, 0x12);
1604 pObj->SetReg(reg, ZD_CR130, 0x10);
1605 }
1606 }
1607 else
1608 {
1609 pObj->SetReg(reg, ZD_CR128, 0x14);
1610 pObj->SetReg(reg, ZD_CR129, 0x12);
1611 pObj->SetReg(reg, ZD_CR130, 0x10);
1612 }
1613 }
1614 pObj->SetReg(reg, ZD_CR80, 0x30);
1615 pObj->SetReg(reg, ZD_CR81, 0x30);
1616 pObj->SetReg(reg, ZD_CR79, 0x58);
1617 pObj->SetReg(reg, ZD_CR12, 0xF0);
1618 pObj->SetReg(reg, ZD_CR77, 0x1B);
1619 pObj->SetReg(reg, ZD_CR78, 0x58);
1620
1621 UnLockPhyReg(pObj);
1622 //UW Tx Power
1623 for(i=0;i<19;i++)
1624 {
1625 if(pObj->IntValue[ChannelNo - 1] == ZD_UWTxGain[i].UWTxGainLevel)
1626 break;
1627 }
1628 if(i<19)
1629 {
1630 pObj->UWCurrentTxLevel = ZD_UWTxGain[i].UWTxGainLevel;
1631 pObj->UWDefaulTxLevel = ZD_UWTxGain[i].UWTxGainLevel;
1632 PHY_UWTxPower(pObj, pObj->UWDefaulTxLevel);
1633 }
1634 LockPhyReg(pObj);
1635 //ZD1205_WRITE_REGISTER(Adapter, CR203, 0x06);
1636 pObj->SetReg(reg, ZD_CR203, 0x06);
1637 UnLockPhyReg(pObj);
1638 pObj->CR203Flag = 2;
1639 pObj->CR31Flag = 2;
1640 //pObj->PHY_G_BandEdge_Flag = 0;
1641 //pObj->UWStrongSingalFlag = 2;
1642 //pObj->UW2453CCKSetFlag = 0;
1643 //pObj->UW24532MIssue = 0;
1644
1645
1646 #if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )
1647 pObj->SetReg(reg, PE1_PE2, 3);
1648 #endif
1649 }
1650
1651 //------------------------------------------------------------------------------
1652 // Procedure: HW_Set_AL7230B_Chips
1653 //
1654 // Description:
1655 //
1656 // Arguments:
1657 // Adapter - ptr to Adapter object instance
1658 // ChannelNo
1659 // Initial Channel only
1660 //
1661 // Returns: (none)
1662 //
1663 // Note:
1664 //-------------------------------------------------------------------------------
1665 #ifndef ZD1211B
1666 // 1211
1667 void HW_Set_AL7230B_RF_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly, U8 MAC_Mode)
1668 {
1669 void *reg = pObj->reg;
1670 U32 tmpValue;
1671 U32 ChannelNo_temp;
1672 //int i;
1673 static u8 mOldMacMode = MIXED_MODE;
1674 U16 WriteAddr[256];
1675 U16 WriteData[256];
1676 U16 WriteIndex = 0;
1677
1678 LockPhyReg(pObj);
1679 pObj->SetReg(reg, ZD_CR240, 0x57);
1680 UnLockPhyReg(pObj);
1681
1682 tmpValue = pObj->GetReg(reg, CtlReg1);
1683 tmpValue &= ~0x80;
1684 pObj->SetReg(reg, CtlReg1, tmpValue);
1685
1686 if (!InitChOnly){
1687 mFILL_WRITE_REGISTER( ZD_CR15, 0x20);
1688 mFILL_WRITE_REGISTER( ZD_CR23, 0x40);
1689 mFILL_WRITE_REGISTER( ZD_CR24, 0x20);
1690 mFILL_WRITE_REGISTER( ZD_CR26, 0x11);
1691 mFILL_WRITE_REGISTER( ZD_CR28, 0x3e);
1692 mFILL_WRITE_REGISTER( ZD_CR29, 0x00);
1693 mFILL_WRITE_REGISTER( ZD_CR44, 0x33);
1694 mFILL_WRITE_REGISTER( ZD_CR106, 0x22); //from 0x2a to 0x22 for AL7230B
1695 mFILL_WRITE_REGISTER( ZD_CR107, 0x1a);
1696 mFILL_WRITE_REGISTER( ZD_CR109, 0x9);
1697 mFILL_WRITE_REGISTER( ZD_CR110, 0x27);
1698 mFILL_WRITE_REGISTER( ZD_CR111, 0x2b);
1699 mFILL_WRITE_REGISTER( ZD_CR112, 0x2b);
1700 mFILL_WRITE_REGISTER( ZD_CR119, 0xa);
1701 mFILL_WRITE_REGISTER( ZD_CR122, 0xfc); //from /e0 to fc for AL7230B
1702 mFILL_WRITE_REGISTER( ZD_CR10, 0x89);
1703 mFILL_WRITE_REGISTER( ZD_CR17, 0x28);
1704 mFILL_WRITE_REGISTER( ZD_CR26, 0x93);
1705 mFILL_WRITE_REGISTER( ZD_CR34, 0x30);
1706 mFILL_WRITE_REGISTER( ZD_CR35, 0x3E);
1707 mFILL_WRITE_REGISTER( ZD_CR41, 0x24);
1708 mFILL_WRITE_REGISTER( ZD_CR44, 0x32);
1709 mFILL_WRITE_REGISTER( ZD_CR46, 0x96);
1710 mFILL_WRITE_REGISTER( ZD_CR47, 0x1e);
1711 mFILL_WRITE_REGISTER( ZD_CR79, 0x58);
1712 mFILL_WRITE_REGISTER( ZD_CR80, 0x30);
1713 mFILL_WRITE_REGISTER( ZD_CR81, 0x30);
1714 mFILL_WRITE_REGISTER( ZD_CR87, 0x0A);
1715 mFILL_WRITE_REGISTER( ZD_CR89, 0x04);
1716 mFILL_WRITE_REGISTER( ZD_CR92, 0x0a);
1717 mFILL_WRITE_REGISTER( ZD_CR99, 0x28);
1718 mFILL_WRITE_REGISTER( ZD_CR100, 0x02);
1719 mFILL_WRITE_REGISTER( ZD_CR101, 0x13);
1720 mFILL_WRITE_REGISTER( ZD_CR102, 0x27);
1721 mFILL_WRITE_REGISTER( ZD_CR106, 0x22); //from 0x20 to 0x22 for AL7230B
1722 mFILL_WRITE_REGISTER( ZD_CR107, 0x3f);
1723 mFILL_WRITE_REGISTER( ZD_CR109, 0x09);
1724 mFILL_WRITE_REGISTER( ZD_CR110, 0x1f);
1725 mFILL_WRITE_REGISTER( ZD_CR111, 0x1f);
1726 mFILL_WRITE_REGISTER( ZD_CR112, 0x1f);
1727 mFILL_WRITE_REGISTER( ZD_CR113, 0x27);
1728 mFILL_WRITE_REGISTER( ZD_CR114, 0x27);
1729 mFILL_WRITE_REGISTER( ZD_CR115, 0x24);
1730 mFILL_WRITE_REGISTER( ZD_CR116, 0x3f);
1731 mFILL_WRITE_REGISTER( ZD_CR117, 0xfa);
1732 mFILL_WRITE_REGISTER( ZD_CR118, 0xfc);
1733 mFILL_WRITE_REGISTER( ZD_CR119, 0x10);
1734 mFILL_WRITE_REGISTER( ZD_CR120, 0x4f);
1735 mFILL_WRITE_REGISTER( ZD_CR121, 0x77);
1736 mFILL_WRITE_REGISTER( ZD_CR137, 0x88);
1737 mFILL_WRITE_REGISTER( ZD_CR138, 0xa8);
1738 mFILL_WRITE_REGISTER( ZD_CR252, 0x34);
1739 mFILL_WRITE_REGISTER( ZD_CR253, 0x34);
1740 // mFILL_WRITE_REGISTER( ZD_CR240, 0x57);
1741
1742 if( MAC_Mode != PURE_A_MODE )
1743 {
1744 mFILL_WRITE_REGISTER( ZD_CR251, 0x2f); //PLL_OFF
1745 SET_IF_SYNTHESIZER(macp, AL7230BTB[ChannelNo*2]);
1746 SET_IF_SYNTHESIZER(macp, AL7230BTB[ChannelNo*2+1]);
1747 //SET_IF_SYNTHESIZER(macp, 0x8cccd0);
1748 SET_IF_SYNTHESIZER(macp, 0x4ff821);
1749 SET_IF_SYNTHESIZER(macp, 0xc5fbfc);
1750 SET_IF_SYNTHESIZER(macp, 0x21ebfe);
1751 SET_IF_SYNTHESIZER(macp, 0xafd401); //freq shift 0xaad401
1752 SET_IF_SYNTHESIZER(macp, 0x6cf56a);
1753 SET_IF_SYNTHESIZER(macp, 0xe04073);
1754 SET_IF_SYNTHESIZER(macp, 0x193d76);
1755 SET_IF_SYNTHESIZER(macp, 0x9dd844);
1756 SET_IF_SYNTHESIZER(macp, 0x500007);
1757 SET_IF_SYNTHESIZER(macp, 0xd8c010);
1758 SET_IF_SYNTHESIZER(macp, 0x3c9000);
1759 //Adapter->AL7230CCKSetFlag=0;
1760 SET_IF_SYNTHESIZER(macp, 0xbfffff);
1761 SET_IF_SYNTHESIZER(macp, 0x700000);
1762 SET_IF_SYNTHESIZER(macp, 0xf15d58);
1763 //AcquireCtrOfPhyReg(Adapter);
1764 //ZD1205_WRITE_REGISTER(Adapter, CR251, 0x2f); //PLL_OFF
1765 mFILL_WRITE_REGISTER( ZD_CR251, 0x3f); //PLL_ON
1766 mFILL_WRITE_REGISTER( ZD_CR128, 0x14);
1767 mFILL_WRITE_REGISTER( ZD_CR129, 0x12);
1768 mFILL_WRITE_REGISTER( ZD_CR130, 0x10);
1769 mFILL_WRITE_REGISTER( ZD_CR38, 0x38);
1770 mFILL_WRITE_REGISTER( ZD_CR136, 0xdf);
1771 ///ZD1211_WRITE_MULTI_REG(Adapter, WriteAddr, WriteData, &WriteIndex);
1772 ///NdisStallExecution(1000);
1773 SET_IF_SYNTHESIZER(macp, 0xf15d59);
1774 ///ZD1211_WRITE_MULTI_REG(Adapter, WriteAddr, WriteData, &WriteIndex);
1775 ///NdisStallExecution(10000);
1776 SET_IF_SYNTHESIZER(macp, 0xf15d5c);
1777 ///ZD1211_WRITE_MULTI_REG(Adapter, WriteAddr, WriteData, &WriteIndex);
1778 ///NdisStallExecution(10000);
1779 SET_IF_SYNTHESIZER(macp, 0xf15d58);
1780 }
1781 else
1782 {
1783 mFILL_WRITE_REGISTER( ZD_CR251, 0x2f); // shdnb(PLL_ON)=0
1784 if((34 <= ChannelNo) && (ChannelNo <= 48)){
1785 ChannelNo_temp=(ChannelNo/2)-13;
1786 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4]);
1787 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+1]);
1788 }
1789 else{
1790 ChannelNo_temp=(ChannelNo/4)-1;
1791 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4]);
1792 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+1]);
1793 }
1794 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+3]);
1795 SET_IF_SYNTHESIZER(macp, 0x47f8a2);
1796 SET_IF_SYNTHESIZER(macp, 0xc5fbfa);
1797 //SET_IF_SYNTHESIZER(macp, 0x21ebf6);
1798 SET_IF_SYNTHESIZER(macp, 0xaafca1);
1799 SET_IF_SYNTHESIZER(macp, 0x6cf56a);
1800 SET_IF_SYNTHESIZER(macp, 0xe04073);
1801 SET_IF_SYNTHESIZER(macp, 0x193d76);
1802 SET_IF_SYNTHESIZER(macp, 0x9dd844);
1803 SET_IF_SYNTHESIZER(macp, 0x500607);
1804 SET_IF_SYNTHESIZER(macp, 0xd8c010);
1805 if((48 < ChannelNo) && (ChannelNo < 184)){
1806 SET_IF_SYNTHESIZER(macp, 0x3c2800);
1807 }
1808 else{
1809 SET_IF_SYNTHESIZER(macp, 0x3e2800);
1810 }
1811 SET_IF_SYNTHESIZER(macp, 0xbfffff);
1812 SET_IF_SYNTHESIZER(macp, 0x700000);
1813 SET_IF_SYNTHESIZER(macp, 0xf35d48);
1814 //AcquireCtrOfPhyReg(Adapter);
1815 //ZD1205_WRITE_REGISTER(Adapter, CR251, 0x2f); // shdnb(PLL_ON)=0
1816 mFILL_WRITE_REGISTER( ZD_CR251, 0x3f); // shdnb(PLL_ON)=1
1817 mFILL_WRITE_REGISTER( ZD_CR128, 0x12);
1818 mFILL_WRITE_REGISTER( ZD_CR129, 0x10);
1819 mFILL_WRITE_REGISTER( ZD_CR130, 0x10);
1820 mFILL_WRITE_REGISTER( ZD_CR38, 0x7f);
1821 mFILL_WRITE_REGISTER( ZD_CR136, 0x5f);
1822 ///ZD1211_WRITE_MULTI_REG(Adapter, WriteAddr, WriteData, &WriteIndex);
1823 ///NdisStallExecution(1000);
1824 SET_IF_SYNTHESIZER(macp, 0xf15d59);
1825 ///ZD1211_WRITE_MULTI_REG(Adapter, WriteAddr, WriteData, &WriteIndex);
1826 ///NdisStallExecution(10000);
1827 SET_IF_SYNTHESIZER(macp, 0xf15d5c);
1828 ///ZD1211_WRITE_MULTI_REG(Adapter, WriteAddr, WriteData, &WriteIndex);
1829 ///NdisStallExecution(10000);
1830 SET_IF_SYNTHESIZER(macp, 0xf35d48);
1831 }
1832
1833 }
1834 else{
1835 if( MAC_Mode != PURE_A_MODE )
1836 {
1837 mFILL_WRITE_REGISTER( ZD_CR251, 0x2f); //PLL_OFF
1838 //SET_IF_SYNTHESIZER(macp, 0x0b3331);
1839 if ( 1 || mOldMacMode != MAC_Mode )
1840 {
1841 SET_IF_SYNTHESIZER(macp, 0x4ff821);
1842 SET_IF_SYNTHESIZER(macp, 0xc5fbfc);
1843 SET_IF_SYNTHESIZER(macp, 0x21ebfe);
1844 SET_IF_SYNTHESIZER(macp, 0xafd401); //fix freq shift, 0xaad401
1845 SET_IF_SYNTHESIZER(macp, 0x6cf56a);
1846 SET_IF_SYNTHESIZER(macp, 0xe04073);
1847 SET_IF_SYNTHESIZER(macp, 0x193d76);
1848 SET_IF_SYNTHESIZER(macp, 0x9dd844);
1849 SET_IF_SYNTHESIZER(macp, 0x500007);
1850 SET_IF_SYNTHESIZER(macp, 0xd8c010);
1851 SET_IF_SYNTHESIZER(macp, 0x3c9000);
1852 SET_IF_SYNTHESIZER(macp, 0xf15d58);
1853
1854 mFILL_WRITE_REGISTER( ZD_CR128, 0x14);
1855 mFILL_WRITE_REGISTER( ZD_CR129, 0x12);
1856 mFILL_WRITE_REGISTER( ZD_CR130, 0x10);
1857 mFILL_WRITE_REGISTER( ZD_CR38, 0x38);
1858 mFILL_WRITE_REGISTER( ZD_CR136, 0xdf);
1859 mOldMacMode = MAC_Mode;
1860 }
1861 //Adapter->AL7230CCKSetFlag=0;
1862 SET_IF_SYNTHESIZER(macp, AL7230BTB[ChannelNo*2]);
1863 SET_IF_SYNTHESIZER(macp, AL7230BTB[ChannelNo*2+1]);
1864 SET_IF_SYNTHESIZER(macp, 0x3c9000);
1865 mFILL_WRITE_REGISTER( ZD_CR251, 0x3f); //PLL_ON
1866 }
1867 else
1868 {
1869 mFILL_WRITE_REGISTER( ZD_CR251, 0x2f); // shdnb(PLL_ON)=0
1870
1871 if ( 1 || mOldMacMode != MAC_Mode )
1872 {
1873 SET_IF_SYNTHESIZER(macp, 0x47f8a2);
1874 SET_IF_SYNTHESIZER(macp, 0xc5fbfa);
1875 SET_IF_SYNTHESIZER(macp, 0xaafca1);
1876 SET_IF_SYNTHESIZER(macp, 0x6cf56a);
1877 SET_IF_SYNTHESIZER(macp, 0xe04073);
1878 SET_IF_SYNTHESIZER(macp, 0x193d76);
1879 SET_IF_SYNTHESIZER(macp, 0x9dd844);
1880 SET_IF_SYNTHESIZER(macp, 0x500607);
1881 SET_IF_SYNTHESIZER(macp, 0xd8c010);
1882 SET_IF_SYNTHESIZER(macp, 0xf35d48);
1883 mFILL_WRITE_REGISTER( ZD_CR128, 0x12);
1884 mFILL_WRITE_REGISTER( ZD_CR129, 0x10);
1885 mFILL_WRITE_REGISTER( ZD_CR130, 0x10);
1886 mFILL_WRITE_REGISTER( ZD_CR38, 0x7f);
1887 mFILL_WRITE_REGISTER( ZD_CR136, 0x5f);
1888 mOldMacMode = MAC_Mode;
1889 }
1890
1891 if((48 < ChannelNo) && (ChannelNo < 184))
1892 {
1893 SET_IF_SYNTHESIZER(macp, 0x3c2800);
1894 }
1895 else
1896 {
1897 SET_IF_SYNTHESIZER(macp, 0x3e2800);
1898 }
1899
1900 if((34 <= ChannelNo) && (ChannelNo <= 48))
1901 {
1902 ChannelNo_temp=(ChannelNo/2)-13;
1903 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4]);
1904 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+1]);
1905 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+3]);
1906 }
1907 else
1908 {
1909 ChannelNo_temp=(ChannelNo/4)-1;
1910 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4]);
1911 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+1]);
1912 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+3]);
1913 }
1914
1915 mFILL_WRITE_REGISTER( ZD_CR251, 0x3f); //PLL_ON
1916 }
1917
1918 }
1919
1920 mFILL_WRITE_REGISTER( ZD_CR203, 0x06);
1921 ZD1211_WRITE_MULTI_REG(WriteAddr, WriteData, &WriteIndex);
1922
1923
1924
1925 tmpValue = pObj->GetReg(reg, CtlReg1);
1926 tmpValue |= ~0x80;
1927 pObj->SetReg(reg, CtlReg1, tmpValue);
1928
1929 LockPhyReg(pObj);
1930 pObj->SetReg(reg, ZD_CR240, 0x80);
1931
1932 pObj->CR203Flag = 2;
1933 if (pObj->HWFeature & BIT_8) //CR47 CCK gain patch
1934 {
1935 tmpValue = pObj->GetReg(reg, E2P_PHY_REG);
1936 pObj->SetReg(reg, ZD_CR47, (tmpValue & 0xff)); //This feature is OK to be overwritten with a lower value by other feature
1937 }
1938 if (pObj->HWFeature & BIT_21) //6321 for FCC regulation, enabled per HWFeature 6M band edge bit (for AL2230, AL2230S)
1939 {
1940 if (ChannelNo == 1 || ChannelNo == 11) //MARK_003, band edge, these may depend on PCB layout
1941 {
1942 pObj->SetReg(reg, ZD_CR128, 0x12);
1943 pObj->SetReg(reg, ZD_CR129, 0x12);
1944 pObj->SetReg(reg, ZD_CR130, 0x10);
1945 pObj->SetReg(reg, ZD_CR47, 0x1E);
1946 }
1947 else //(ChannelNo 2 ~ 10, 12 ~ 14)
1948 {
1949 pObj->SetReg(reg, ZD_CR128, 0x14);
1950 pObj->SetReg(reg, ZD_CR129, 0x12);
1951 pObj->SetReg(reg, ZD_CR130, 0x10);
1952 pObj->SetReg(reg, ZD_CR47, 0x1E);
1953 }
1954 }
1955
1956 UnLockPhyReg(pObj);
1957
1958 // pObj->CR31Flag = 2;
1959 // macp->PHY_G_6M_BandEdge_Flag = 0;
1960 // if(macp->PHY_36M_Setpoint_Flag != 0)
1961 // {
1962 // for(i=0;i<16;i++)
1963 // macp->a_Calibration_Data[2][i] = macp->PHY_36M_A_Calibration_Setpoint[i];
1964 // for(i=0;i<32;i++)
1965 // macp->a_Interpolation_Data[2][i] = macp->PHY_36M_A_Interpolation_Setpoint[i];
1966 // macp->PHY_36M_Setpoint_Flag = 0;
1967 // }
1968
1969 }
1970 #else
1971 // 1215
1972 void HW_Set_AL7230B_RF_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly, U8 MAC_Mode)
1973 {
1974
1975 void *reg = pObj->reg;
1976 U32 tmpvalue;
1977 U32 ChannelNo_temp;
1978 int i;
1979 U16 WriteAddr[256];
1980 U16 WriteData[256];
1981 U16 WriteIndex = 0;
1982 LockPhyReg(pObj);
1983 pObj->SetReg(reg, ZD_CR240, 0x57);
1984 if (1) //(!pObj->CurrentAntenna) // 0-->Main
1985 pObj->SetReg(reg, ZD_CR9, 0xe4);
1986 else
1987 pObj->SetReg(reg, ZD_CR9, 0xe0);
1988 UnLockPhyReg(pObj);
1989 tmpvalue = pObj->GetReg(pObj,CtlReg1);
1990 tmpvalue &= ~0x80;
1991 pObj->SetReg(reg, CtlReg1, tmpvalue);
1992
1993
1994 if (!InitChOnly){
1995 //mFILL_WRITE_REGISTER(ZD_CR9, 0xe0);//5119
1996 mFILL_WRITE_REGISTER(ZD_CR10, 0x8B);
1997 mFILL_WRITE_REGISTER(ZD_CR15, 0x20);
1998 mFILL_WRITE_REGISTER(ZD_CR17, 0x2B);//for newest(3rd cut)AL2230
1999 mFILL_WRITE_REGISTER(ZD_CR20, 0x10);//4N25->Stone Request
2000 mFILL_WRITE_REGISTER(ZD_CR23, 0x40);
2001 mFILL_WRITE_REGISTER(ZD_CR24, 0x20);
2002 mFILL_WRITE_REGISTER(ZD_CR26, 0x93);
2003 mFILL_WRITE_REGISTER(ZD_CR28, 0x3e);
2004 mFILL_WRITE_REGISTER(ZD_CR29, 0x00);
2005 mFILL_WRITE_REGISTER(ZD_CR33, 0x28); //5613
2006 mFILL_WRITE_REGISTER(ZD_CR34, 0x30);
2007 mFILL_WRITE_REGISTER(ZD_CR35, 0x3e); //for newest(3rd cut) AL2230
2008 mFILL_WRITE_REGISTER(ZD_CR41, 0x24);
2009 mFILL_WRITE_REGISTER(ZD_CR44, 0x32);
2010 mFILL_WRITE_REGISTER(ZD_CR46, 0x99); //for newest(3rd cut) AL2230
2011 mFILL_WRITE_REGISTER(ZD_CR47, 0x1e);
2012 mFILL_WRITE_REGISTER(ZD_CR48, 0x00); //ZD1215 5610
2013 mFILL_WRITE_REGISTER(ZD_CR49, 0x00); //ZD1215 5610
2014 mFILL_WRITE_REGISTER(ZD_CR51, 0x01); //ZD1215 5610
2015 mFILL_WRITE_REGISTER(ZD_CR52, 0x80); //ZD1215 5610
2016 mFILL_WRITE_REGISTER(ZD_CR53, 0x7e); //ZD1215 5610
2017 mFILL_WRITE_REGISTER(ZD_CR65, 0x00); //ZD1215 5610
2018 mFILL_WRITE_REGISTER(ZD_CR66, 0x00); //ZD1215 5610
2019 mFILL_WRITE_REGISTER(ZD_CR67, 0x00); //ZD1215 5610
2020 mFILL_WRITE_REGISTER(ZD_CR68, 0x00); //ZD1215 5610
2021 mFILL_WRITE_REGISTER(ZD_CR69, 0x28); //ZD1215 5610
2022 mFILL_WRITE_REGISTER(ZD_CR79, 0x58);
2023 mFILL_WRITE_REGISTER(ZD_CR80, 0x30);
2024 mFILL_WRITE_REGISTER(ZD_CR81, 0x30);
2025 mFILL_WRITE_REGISTER(ZD_CR87, 0x0A);
2026 mFILL_WRITE_REGISTER(ZD_CR89, 0x04);
2027 mFILL_WRITE_REGISTER(ZD_CR90, 0x58); //5112
2028 mFILL_WRITE_REGISTER(ZD_CR91, 0x00); //5613
2029 mFILL_WRITE_REGISTER(ZD_CR92, 0x0a);
2030 mFILL_WRITE_REGISTER(ZD_CR98, 0x8d); //4804, for 1212 new algorithm
2031 mFILL_WRITE_REGISTER(ZD_CR99, 0x00);
2032 mFILL_WRITE_REGISTER(ZD_CR100, 0x02);
2033 mFILL_WRITE_REGISTER(ZD_CR101, 0x13);
2034 mFILL_WRITE_REGISTER(ZD_CR102, 0x27);
2035 mFILL_WRITE_REGISTER(ZD_CR106, 0x20); // change to 0x24 for AL7230B
2036 mFILL_WRITE_REGISTER(ZD_CR109, 0x13); //4804, for 1212 new algorithm
2037 mFILL_WRITE_REGISTER(ZD_CR112, 0x1f);
2038 if(pObj->PHYNEWLayout)
2039 {
2040 mFILL_WRITE_REGISTER(ZD_CR107, 0x28);
2041 mFILL_WRITE_REGISTER(ZD_CR110, 0x1f); //5127, 0x13->0x1f
2042 mFILL_WRITE_REGISTER(ZD_CR111, 0x1f); //0x13 to 0x1f for AL7230B
2043 mFILL_WRITE_REGISTER(ZD_CR116, 0x2a);
2044 mFILL_WRITE_REGISTER(ZD_CR118, 0xfa);
2045 mFILL_WRITE_REGISTER(ZD_CR119, 0x12);
2046 mFILL_WRITE_REGISTER(ZD_CR121, 0x6c); //5613
2047 }
2048 else
2049 {
2050 mFILL_WRITE_REGISTER(ZD_CR107, 0x24);
2051 mFILL_WRITE_REGISTER(ZD_CR110, 0x13); //5127, 0x13->0x1f
2052 mFILL_WRITE_REGISTER(ZD_CR111, 0x13); //0x13 to 0x1f for AL7230B
2053 mFILL_WRITE_REGISTER(ZD_CR116, 0x24);
2054 mFILL_WRITE_REGISTER(ZD_CR118, 0xfc);
2055 mFILL_WRITE_REGISTER(ZD_CR119, 0x11);
2056 mFILL_WRITE_REGISTER(ZD_CR121, 0x6a); //5613
2057 }
2058 mFILL_WRITE_REGISTER(ZD_CR113, 0x27);
2059 mFILL_WRITE_REGISTER(ZD_CR114, 0x27);
2060 mFILL_WRITE_REGISTER(ZD_CR115, 0x24);
2061 mFILL_WRITE_REGISTER(ZD_CR117, 0xfa);
2062 mFILL_WRITE_REGISTER(ZD_CR120, 0x4f);
2063 mFILL_WRITE_REGISTER(ZD_CR122, 0xfc); // E0->FCh at 4901
2064 mFILL_WRITE_REGISTER(ZD_CR123, 0x57); //5613
2065 mFILL_WRITE_REGISTER(ZD_CR125, 0xad); //4804, for 1212 new algorithm
2066 mFILL_WRITE_REGISTER(ZD_CR126, 0x6c); //5613
2067 mFILL_WRITE_REGISTER(ZD_CR127, 0x03); //4804, for 1212 new algorithm
2068 mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
2069 mFILL_WRITE_REGISTER(ZD_CR131, 0x00); //5112
2070 mFILL_WRITE_REGISTER(ZD_CR137, 0x50); //5613
2071 mFILL_WRITE_REGISTER(ZD_CR138, 0xa8); //5112
2072 mFILL_WRITE_REGISTER(ZD_CR144, 0xac); //5613
2073 mFILL_WRITE_REGISTER(ZD_CR148, 0x40); //5112
2074 mFILL_WRITE_REGISTER(ZD_CR149, 0x40); //4O07, 50->40
2075 mFILL_WRITE_REGISTER(ZD_CR150, 0x1a); //5112, 0C->1A
2076
2077
2078 mFILL_WRITE_REGISTER(ZD_CR252, 0x34);
2079 mFILL_WRITE_REGISTER(ZD_CR253, 0x34);
2080 //mFILL_WRITE_REGISTER(ZD_CR240, 0x57);
2081 //
2082 if( mMacMode != PURE_A_MODE)
2083 {
2084 mFILL_WRITE_REGISTER(ZD_CR251, 0x2f); //PLL_OFF
2085 SET_IF_SYNTHESIZER(macp, AL7230BTB[ChannelNo*2]);
2086 SET_IF_SYNTHESIZER(macp, AL7230BTB[ChannelNo*2+1]);
2087 //SET_IF_SYNTHESIZER(macp, 0x8cccd0);
2088 SET_IF_SYNTHESIZER(macp, 0x4ff821);
2089 SET_IF_SYNTHESIZER(macp, 0xc5fbfc);
2090 SET_IF_SYNTHESIZER(macp, 0x21ebfe);
2091 SET_IF_SYNTHESIZER(macp, 0xafd401);
2092 SET_IF_SYNTHESIZER(macp, 0x6cf56a);
2093 SET_IF_SYNTHESIZER(macp, 0xe04073);
2094 SET_IF_SYNTHESIZER(macp, 0x190d76);
2095 SET_IF_SYNTHESIZER(macp, 0x9dd844);
2096 SET_IF_SYNTHESIZER(macp, 0x500007);
2097 SET_IF_SYNTHESIZER(macp, 0xd8c010);
2098 SET_IF_SYNTHESIZER(macp, 0x3c9000);
2099 //pObj->AL7230CCKSetFlag=0;
2100 SET_IF_SYNTHESIZER(macp, 0xbfffff);
2101 SET_IF_SYNTHESIZER(macp, 0x700000);
2102 SET_IF_SYNTHESIZER(macp, 0xf15d58);
2103 //LockPhyReg(pObj);
2104 //mFILL_WRITE_REGISTER(ZD_CR251, 0x2f); //PLL_OFF
2105 mFILL_WRITE_REGISTER(ZD_CR251, 0x7f); //PLL_ON
2106 mFILL_WRITE_REGISTER(ZD_CR128, 0x14);
2107 mFILL_WRITE_REGISTER(ZD_CR129, 0x12);
2108 mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
2109 mFILL_WRITE_REGISTER(ZD_CR38, 0x38);
2110 mFILL_WRITE_REGISTER(ZD_CR136, 0xdf);
2111 //NdisStallExecution(1000);
2112 SET_IF_SYNTHESIZER(macp, 0xf15d59);
2113 //NdisStallExecution(10000);
2114 SET_IF_SYNTHESIZER(macp, 0xf15d5c);
2115 //NdisStallExecution(10000);
2116 SET_IF_SYNTHESIZER(macp, 0xf15d58);
2117 }
2118 else
2119 {
2120 mFILL_WRITE_REGISTER(ZD_CR251, 0x2f); // shdnb(PLL_ON)=0
2121 if((34 <= ChannelNo) && (ChannelNo <= 48)){
2122 ChannelNo_temp=(ChannelNo/2)-13;
2123 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4]);
2124 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+1]);
2125 }
2126 else{
2127 ChannelNo_temp=(ChannelNo/4)-1;
2128 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4]);
2129 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+1]);
2130 }
2131 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+3]);
2132 SET_IF_SYNTHESIZER(macp, 0x47f8a2);
2133 SET_IF_SYNTHESIZER(macp, 0xc5fbfa);
2134 //SET_IF_SYNTHESIZER(macp, 0x21ebf6);
2135 SET_IF_SYNTHESIZER(macp, 0xaffca1);
2136 SET_IF_SYNTHESIZER(macp, 0x6cf56a);
2137 SET_IF_SYNTHESIZER(macp, 0xe04073);
2138 SET_IF_SYNTHESIZER(macp, 0x190d36);
2139 SET_IF_SYNTHESIZER(macp, 0x9dd844);
2140 SET_IF_SYNTHESIZER(macp, 0x500607);
2141 SET_IF_SYNTHESIZER(macp, 0xd8c010);
2142 if((48 < ChannelNo) && (ChannelNo < 184)){
2143 SET_IF_SYNTHESIZER(macp, 0x3c2800);
2144 }
2145 else{
2146 SET_IF_SYNTHESIZER(macp, 0x3e2800);
2147 }
2148 SET_IF_SYNTHESIZER(macp, 0xbfffff);
2149 SET_IF_SYNTHESIZER(macp, 0x700000);
2150 SET_IF_SYNTHESIZER(macp, 0xf35d48);
2151 //LockPhyReg(pObj);
2152 //mFILL_WRITE_REGISTER(ZD_CR251, 0x2f); // shdnb(PLL_ON)=0
2153 mFILL_WRITE_REGISTER(ZD_CR251, 0x7f); // shdnb(PLL_ON)=1
2154 mFILL_WRITE_REGISTER(ZD_CR128, 0x12);
2155 mFILL_WRITE_REGISTER(ZD_CR129, 0x10);
2156 mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
2157 mFILL_WRITE_REGISTER(ZD_CR38, 0x7f);
2158 mFILL_WRITE_REGISTER(ZD_CR136, 0x5f);
2159 //mFILL_WRITE_REGISTER(ZD_CR31, 0x58);
2160
2161 //NdisStallExecution(1000);
2162 SET_IF_SYNTHESIZER(macp, 0xf15d59);
2163 //NdisStallExecution(10000);
2164 SET_IF_SYNTHESIZER(macp, 0xf15d5c);
2165 //NdisStallExecution(10000);
2166 SET_IF_SYNTHESIZER(macp, 0xf35d48);
2167 }
2168
2169 }
2170 else{
2171
2172 if( mMacMode != PURE_A_MODE)
2173 {
2174 mFILL_WRITE_REGISTER(ZD_CR251, 0x2f); //PLL_OFF
2175 //Set_IF_Synthesizer(Adapter, 0x8cccd0);
2176 if (1)//pObj->OldNetworkType != pObj->CardSetting.NetworkTypeInUse )
2177 {
2178 SET_IF_SYNTHESIZER(macp, 0x4ff821);
2179 SET_IF_SYNTHESIZER(macp, 0xc5fbfc);
2180 SET_IF_SYNTHESIZER(macp, 0x21ebfe);
2181 SET_IF_SYNTHESIZER(macp, 0xafd401);
2182 SET_IF_SYNTHESIZER(macp, 0x6cf56a);
2183 SET_IF_SYNTHESIZER(macp, 0xe04073);
2184 SET_IF_SYNTHESIZER(macp, 0x190d76);
2185 SET_IF_SYNTHESIZER(macp, 0x9dd844);
2186 SET_IF_SYNTHESIZER(macp, 0x500007);
2187 SET_IF_SYNTHESIZER(macp, 0xd8c010);
2188 SET_IF_SYNTHESIZER(macp, 0x3c9000);
2189 SET_IF_SYNTHESIZER(macp, 0xf15d58);
2190 //LockPhyReg(pObj);
2191 //mFILL_WRITE_REGISTER(ZD_CR251, 0x2f); //PLL_OFF
2192 //mFILL_WRITE_REGISTER(ZD_CR251, 0x3f); //PLL_ON
2193 mFILL_WRITE_REGISTER(ZD_CR128, 0x14);
2194 mFILL_WRITE_REGISTER(ZD_CR129, 0x12);
2195 mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
2196 mFILL_WRITE_REGISTER(ZD_CR38, 0x38);
2197 mFILL_WRITE_REGISTER(ZD_CR136, 0xdf);
2198 //pObj->OldNetworkType = pObj->CardSetting.NetworkTypeInUse;
2199 }
2200 //pObj->AL7230CCKSetFlag=0;
2201 SET_IF_SYNTHESIZER(macp, AL7230BTB[ChannelNo*2]);
2202 SET_IF_SYNTHESIZER(macp, AL7230BTB[ChannelNo*2+1]);
2203 SET_IF_SYNTHESIZER(macp, 0x3c9000);
2204 mFILL_WRITE_REGISTER(ZD_CR251, 0x7f); //PLL_ON
2205
2206 //NdisStallExecution(10);
2207 //SET_IF_SYNTHESIZER(macp, 0xf15d59);
2208 //NdisStallExecution(100);
2209 //SET_IF_SYNTHESIZER(macp, 0xf15d5c);
2210 //NdisStallExecution(100);
2211 //SET_IF_SYNTHESIZER(macp, 0xf15d58);
2212 }
2213 else
2214 {
2215 mFILL_WRITE_REGISTER(ZD_CR251, 0x2f); // shdnb(PLL_ON)=0
2216 SET_IF_SYNTHESIZER(macp, 0x190d36);
2217
2218 if (1)//pObj->OldNetworkType != pObj->CardSetting.NetworkTypeInUse )
2219 {
2220 SET_IF_SYNTHESIZER(macp, 0x47f8a2);
2221 SET_IF_SYNTHESIZER(macp, 0xc5fbfa);
2222 //SET_IF_SYNTHESIZER(macp, 0x21ebf6);
2223 SET_IF_SYNTHESIZER(macp, 0xaffca1);
2224 SET_IF_SYNTHESIZER(macp, 0x6cf56a);
2225 SET_IF_SYNTHESIZER(macp, 0xe04073);
2226 //SET_IF_SYNTHESIZER(macp, 0x190d36);
2227 SET_IF_SYNTHESIZER(macp, 0x9dd844);
2228 SET_IF_SYNTHESIZER(macp, 0x500607);
2229 SET_IF_SYNTHESIZER(macp, 0xd8c010);
2230 SET_IF_SYNTHESIZER(macp, 0xf35d48);
2231 //LockPhyReg(pObj);
2232 //mFILL_WRITE_REGISTER(ZD_CR251, 0x2f); // shdnb(PLL_ON)=0
2233 //mFILL_WRITE_REGISTER(ZD_CR251, 0x3f); // shdnb(PLL_ON)=1
2234 mFILL_WRITE_REGISTER(ZD_CR128, 0x12);
2235 mFILL_WRITE_REGISTER(ZD_CR129, 0x10);
2236 mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
2237 mFILL_WRITE_REGISTER(ZD_CR38, 0x7f);
2238 mFILL_WRITE_REGISTER(ZD_CR136, 0x5f);
2239 //pObj->OldNetworkType = pObj->CardSetting.NetworkTypeInUse;
2240 }
2241 if((48 < ChannelNo) && (ChannelNo < 184)){
2242 SET_IF_SYNTHESIZER(macp, 0x3c2800);
2243 }
2244 else{
2245 SET_IF_SYNTHESIZER(macp, 0x3e2800);
2246 }
2247 if((34 <= ChannelNo) && (ChannelNo <= 48)){
2248 ChannelNo_temp=(ChannelNo/2)-13;
2249 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4]);
2250 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+1]);
2251 //SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+2]);
2252 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+3]);
2253 // SET_IF_SYNTHESIZER(macp, 0x3c2800);
2254 }
2255 else{
2256 ChannelNo_temp=(ChannelNo/4)-1;
2257 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4]);
2258 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+1]);
2259 //SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+2]);
2260 SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+3]);
2261 //SET_IF_SYNTHESIZER(macp, 0x3c2800);
2262 }
2263 mFILL_WRITE_REGISTER(ZD_CR251, 0x7f); //PLL_ON
2264 //ZD1205_WRITE_REGISTER(Adapter, CR31, 0x58);
2265
2266 //NdisStallExecution(10);
2267 //SET_IF_SYNTHESIZER(macp, 0xf15d59);
2268 //NdisStallExecution(100);
2269 //SET_IF_SYNTHESIZER(macp, 0xf15d5c);
2270 //NdisStallExecution(100);
2271 //SET_IF_SYNTHESIZER(macp, 0xf35d58);
2272 }
2273
2274 }
2275 if(mBssType == INDEPENDENT_BSS)
2276 {
2277 mFILL_WRITE_REGISTER(ZD_CR80, 0x0C);
2278 mFILL_WRITE_REGISTER(ZD_CR81, 0x0C);
2279 mFILL_WRITE_REGISTER(ZD_CR79, 0x16);
2280 mFILL_WRITE_REGISTER(ZD_CR12, 0x54);
2281 mFILL_WRITE_REGISTER(ZD_CR77, 0x1B);
2282 mFILL_WRITE_REGISTER(ZD_CR78, 0x58);
2283 }
2284 else
2285 {
2286 mFILL_WRITE_REGISTER(ZD_CR80, 0x30);
2287 mFILL_WRITE_REGISTER(ZD_CR81, 0x30);
2288 mFILL_WRITE_REGISTER(ZD_CR79, 0x58);
2289 mFILL_WRITE_REGISTER(ZD_CR12, 0xF0);
2290 mFILL_WRITE_REGISTER(ZD_CR77, 0x1B);
2291 mFILL_WRITE_REGISTER(ZD_CR78, 0x58);
2292 }
2293
2294 if(pObj->HWFeature & BIT_21)
2295 {
2296 if(ChannelNo == 1)
2297 {
2298 mFILL_WRITE_REGISTER(ZD_CR128, 0x0e);
2299 mFILL_WRITE_REGISTER(ZD_CR129, 0x10);
2300 }
2301 else if(ChannelNo == 11)
2302 {
2303 mFILL_WRITE_REGISTER(ZD_CR128, 0x10);
2304 mFILL_WRITE_REGISTER(ZD_CR129, 0x10);
2305 }
2306 else if(ChannelNo != 1 && ChannelNo != 11)
2307 {
2308 mFILL_WRITE_REGISTER(ZD_CR128, 0x14);
2309 mFILL_WRITE_REGISTER(ZD_CR129, 0x12);
2310 }
2311 }
2312 //pObj->SetReg(reg, ZD_CR138, 0x28);
2313 mFILL_WRITE_REGISTER(ZD_CR203, 0x04);
2314 ZD1211_WRITE_MULTI_REG(WriteAddr, WriteData, &WriteIndex);
2315
2316 tmpvalue = pObj->GetReg(reg ,CtlReg1);
2317 tmpvalue |= 0x80;
2318 pObj->SetReg(reg, CtlReg1, tmpvalue);
2319 LockPhyReg(pObj);
2320 pObj->SetReg(reg, ZD_CR240, 0x80);
2321 if(pObj->PHYNEWLayout)
2322 {
2323 if (1)//!pObj->CurrentAntenna) // CurrentAntenna = 0 ->Main
2324 pObj->SetReg(reg, ZD_CR9, 0xe5);
2325 else
2326 pObj->SetReg(reg, ZD_CR9, 0xe1);
2327 }
2328 pObj->SetReg(reg, ZD_CR203, 0x04);
2329 UnLockPhyReg(pObj);
2330 pObj->CR203Flag = 2;
2331 pObj->CR31Flag = 2;
2332 //pObj->Change_SetPoint = 2;
2333 //pObj->PHY_G_6M_BandEdge_Flag = 0;
2334 /*
2335 if(pObj->PHY_36M_Setpoint_Flag != 0)
2336 {
2337 //for(i=0;i<14;i++)
2338 // pObj->SetPointOFDM[0][i] = pObj->PHY_36M_G_Setpoint[i];
2339 for(i=0;i<16;i++)
2340 pObj->a_Calibration_Data[2][i] = pObj->PHY_36M_A_Calibration_Setpoint[i];
2341 for(i=0;i<32;i++)
2342 pObj->a_Interpolation_Data[2][i] = pObj->PHY_36M_A_Interpolation_Setpoint[i];
2343 pObj->PHY_36M_Setpoint_Flag = 0;
2344 }
2345 */
2346
2347 #if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )
2348 pObj->SetReg(reg, PE1_PE2, 3);
2349 #endif
2350
2351
2352
2353 }
2354
2355 // end of AL7230B ZD1215
2356 #endif
2357
2358 //------------------------------------------------------------------------------
2359 // Procedure: HW_Set_AL2232_Chips
2360 //
2361 // Description:
2362 //
2363 // Arguments:
2364 // pObj - ptr to Adapter object instance
2365 // ChannelNo
2366 // Initial Channel only
2367 //
2368 // Returns: (none)
2369 //
2370 // Note:
2371 //-------------------------------------------------------------------------------
2372 void
2373 HW_Set_AL2232_RF_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
2374 {
2375 void *reg = pObj->reg;
2376 struct zd1205_private *macp = (struct zd1205_private *)g_dev->priv;
2377 U32 tmpValue;
2378
2379 if (!InitChOnly)
2380 {
2381 LockPhyReg(pObj);
2382 pObj->SetReg(reg,ZD_CR9, 0xE0); //5119
2383 pObj->SetReg(reg,ZD_CR15, 0x20);
2384 pObj->SetReg(reg,ZD_CR23, 0x40);
2385 pObj->SetReg(reg,ZD_CR24, 0x20);
2386 pObj->SetReg(reg,ZD_CR26, 0x11);
2387 pObj->SetReg(reg,ZD_CR28, 0x3e);
2388 pObj->SetReg(reg,ZD_CR29, 0x00);
2389 pObj->SetReg(reg,ZD_CR44, 0x33);
2390 pObj->SetReg(reg,ZD_CR106, 0x22); // 2004/10/19 0x2a -> 0x22
2391 pObj->SetReg(reg,ZD_CR107, 0x1a);
2392 pObj->SetReg(reg,ZD_CR109, 0x9);
2393 pObj->SetReg(reg,ZD_CR110, 0x27);
2394 pObj->SetReg(reg,ZD_CR111, 0x2b);
2395 pObj->SetReg(reg,ZD_CR112, 0x2b);
2396 pObj->SetReg(reg,ZD_CR119, 0xa);
2397
2398 pObj->SetReg(reg,ZD_CR10, 0x89);
2399 pObj->SetReg(reg,ZD_CR17, 0x2B); //for newest(3rd cut) AL2230
2400 pObj->SetReg(reg,ZD_CR20, 0x12); //4N25 -> Stone Request
2401 pObj->SetReg(reg,ZD_CR26, 0x93);
2402 pObj->SetReg(reg,ZD_CR34, 0x30);
2403 pObj->SetReg(reg,ZD_CR35, 0x3E); //for newest(3rd cut) AL2230
2404 pObj->SetReg(reg,ZD_CR41, 0x24);
2405 pObj->SetReg(reg,ZD_CR44, 0x32);
2406 pObj->SetReg(reg,ZD_CR46, 0x99); //for newest(3rd cut) AL2230
2407 pObj->SetReg(reg,ZD_CR47, 0x1e);
2408 pObj->SetReg(reg,ZD_CR79, 0x58);
2409 pObj->SetReg(reg,ZD_CR80, 0x30);
2410 pObj->SetReg(reg,ZD_CR81, 0x30);
2411 pObj->SetReg(reg,ZD_CR87, 0x0A);
2412 pObj->SetReg(reg,ZD_CR89, 0x04);
2413 pObj->SetReg(reg,ZD_CR90, 0x58); //5113
2414 pObj->SetReg(reg,ZD_CR92, 0x0a);
2415 pObj->SetReg(reg,ZD_CR98, 0x8d); //4804, for 1212 new algorithm
2416 pObj->SetReg(reg,ZD_CR99, 0x28);
2417 pObj->SetReg(reg,ZD_CR100, 0x00);
2418 pObj->SetReg(reg,ZD_CR101, 0x13);
2419 pObj->SetReg(reg,ZD_CR102, 0x27);
2420 pObj->SetReg(reg,ZD_CR106, 0x22); //for newest(3rd cut) AL2230
2421 // 2004/10/19 0x2a -> 0x22
2422 pObj->SetReg(reg,ZD_CR107, 0x2A);
2423 pObj->SetReg(reg,ZD_CR109, 0x13); //4804, for 1212 new algorithm
2424 pObj->SetReg(reg,ZD_CR110, 0x1F); //4804, for 1212 new algorithm
2425 pObj->SetReg(reg,ZD_CR111, 0x1F); //4804, for 1212 new algorithm
2426 pObj->SetReg(reg,ZD_CR112, 0x1f);
2427 pObj->SetReg(reg,ZD_CR113, 0x27);
2428 pObj->SetReg(reg,ZD_CR114, 0x27);
2429 pObj->SetReg(reg,ZD_CR115, 0x26); //24->26 at 4901
2430 pObj->SetReg(reg,ZD_CR116, 0x24); // 26->24 at 4901
2431 //rk pObj->SetReg(reg,ZD_CR117, 0xfa);
2432 pObj->SetReg(reg,ZD_CR118, 0xf8); //4O07, fa->f8
2433 pObj->SetReg(reg,ZD_CR119, 0x10);
2434 pObj->SetReg(reg,ZD_CR120, 0x4f);
2435 pObj->SetReg(reg,ZD_CR121, 0x0a); //4804, for 1212 new algorithm
2436 pObj->SetReg(reg,ZD_CR122, 0xFC); // E0->FCh at 4901
2437 pObj->SetReg(reg,ZD_CR125, 0xaD); //4804, for 1212 new algorithm
2438 pObj->SetReg(reg,ZD_CR127, 0x03); //4804, for 1212 new algorithm
2439 pObj->SetReg(reg,ZD_CR137, 0x88);
2440 pObj->SetReg(reg,ZD_CR131, 0x00); //5113
2441 pObj->SetReg(reg,ZD_CR148, 0x40); //5113
2442 pObj->SetReg(reg,ZD_CR149, 0x40); //4O07, 50->40
2443 pObj->SetReg(reg,ZD_CR150, 0x1A); //5113, 0C->1A
2444
2445 pObj->SetReg(reg,ZD_CR252, 0x34);
2446 pObj->SetReg(reg,ZD_CR253, 0x34);
2447
2448 UnLockPhyReg(pObj);
2449
2450 HW_Set_IF_Synthesizer(pObj, AL2232TB[ChannelNo*3]);
2451 HW_Set_IF_Synthesizer(pObj, AL2232TB[ChannelNo*3+1]);
2452 HW_Set_IF_Synthesizer(pObj, AL2232TB[ChannelNo*3+2]);
2453 HW_Set_IF_Synthesizer(pObj, 0x0b3331);
2454 HW_Set_IF_Synthesizer(pObj, 0x01b802);
2455 HW_Set_IF_Synthesizer(pObj, 0x00fff3);
2456 HW_Set_IF_Synthesizer(pObj, 0x0005a4);
2457 HW_Set_IF_Synthesizer(pObj, 0x044dc5);
2458 HW_Set_IF_Synthesizer(pObj, 0x0805b6);
2459 HW_Set_IF_Synthesizer(pObj, 0x0146C7);
2460 HW_Set_IF_Synthesizer(pObj, 0x000688);
2461 HW_Set_IF_Synthesizer(pObj, 0x0403b9);
2462 HW_Set_IF_Synthesizer(pObj, 0x00dbba);
2463 HW_Set_IF_Synthesizer(pObj, 0x00099b);
2464 HW_Set_IF_Synthesizer(pObj, 0x0bdffc);
2465 HW_Set_IF_Synthesizer(pObj, 0x00000d);
2466 HW_Set_IF_Synthesizer(pObj, 0x00580f);
2467
2468 LockPhyReg(pObj);
2469 pObj->SetReg(reg, ZD_CR251, 0x2f); // shdnb(PLL_ON)=0
2470 pObj->DelayUs(10);
2471 UnLockPhyReg(pObj);
2472
2473 //HW_Set_IF_Synthesizer(pObj, 0x000d00f);
2474 HW_Set_IF_Synthesizer(pObj, 0x000d80f);
2475 pObj->DelayUs(100);
2476 HW_Set_IF_Synthesizer(pObj, 0x00780f);
2477 pObj->DelayUs(100);
2478 //HW_Set_IF_Synthesizer(pObj, 0x00500f);
2479 HW_Set_IF_Synthesizer(pObj, 0x00580f);
2480 }
2481 else
2482 {
2483 HW_Set_IF_Synthesizer(pObj, AL2232TB[ChannelNo*3]);
2484 HW_Set_IF_Synthesizer(pObj, AL2232TB[ChannelNo*3+1]);
2485 HW_Set_IF_Synthesizer(pObj, AL2232TB[ChannelNo*3+2]);
2486 }
2487
2488 LockPhyReg(pObj);
2489 if (1 )//|| macp->bContinueTx == 0) // Do not modify CR203 during CAL mode
2490 {
2491 pObj->SetReg(reg, ZD_CR203, 0x06);
2492 }
2493
2494 if (pObj->HWFeature & BIT_8) //CR47 CCK gain patch
2495 {
2496 tmpValue = pObj->GetReg(reg, E2P_PHY_REG);
2497 pObj->SetReg(reg, ZD_CR47, (tmpValue & 0xff)); //This feature is OK to be overwritten with a lower value by other feature
2498 }
2499
2500 #if 0 //6321 TO DO
2501 if (pObj->HWFeature & BIT_22) //6321 High power band edge for FCC regulation, enabled per HWFeature
2502 {
2503 if (ChannelNo == 1 || ChannelNo == 11) //these may depend on PCB layout
2504 {
2505 pObj->SetReg(reg, ZD_CR128, );
2506 pObj->SetReg(reg, ZD_CR129, );
2507 pObj->SetReg(reg, ZD_CR130, );
2508 pObj->SetReg(reg, ZD_CR47, );
2509 }
2510 else //(ChannelNo 2 ~ 10, 12 ~ 14)
2511 {
2512 pObj->SetReg(reg, ZD_CR128, );
2513 pObj->SetReg(reg, ZD_CR129, );
2514 pObj->SetReg(reg, ZD_CR130, );
2515 pObj->SetReg(reg, ZD_CR47, );
2516 }
2517 }
2518 #endif
2519
2520 UnLockPhyReg(pObj);
2521
2522 pObj->CR203Flag = 2;
2523 pObj->CR31Flag = 2; //cCR31InitialState;
2524
2525 }
2526
2527 #ifdef ZD1211
2528 void
2529 HW_Set_AL2230_RF_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
2530 {
2531
2532 void *reg = pObj->reg;
2533 U32 tmpvalue;
2534
2535
2536 if (!InitChOnly){
2537 LockPhyReg(pObj);
2538 #ifdef ZD1211B
2539 pObj->SetReg(reg, ZD_CR10, 0x89);
2540 #endif
2541 pObj->SetReg(reg, ZD_CR15, 0x20);
2542 #ifdef ZD1211B
2543 pObj->SetReg(reg, ZD_CR17, 0x2B);
2544 #endif
2545 pObj->SetReg(reg, ZD_CR23, 0x40);
2546 pObj->SetReg(reg, ZD_CR24, 0x20);
2547 #ifdef ZD1211
2548 pObj->SetReg(reg, ZD_CR26, 0x11);
2549 #elif defined(ZD1211B)
2550 pObj->SetReg(reg, ZD_CR26, 0x93);
2551 #endif
2552 pObj->SetReg(reg, ZD_CR28, 0x3e);
2553 pObj->SetReg(reg, ZD_CR29, 0x00);
2554 #ifdef ZD1211B
2555 pObj->SetReg(reg, ZD_CR33, 0x28);
2556 #elif defined(ZD1211)
2557 pObj->SetReg(reg, ZD_CR44, 0x33);
2558 pObj->SetReg(reg, ZD_CR106, 0x2a);
2559 pObj->SetReg(reg, ZD_CR107, 0x1a);
2560 pObj->SetReg(reg, ZD_CR109, 0x9);
2561 pObj->SetReg(reg, ZD_CR110, 0x27);
2562 pObj->SetReg(reg, ZD_CR111, 0x2b);
2563 pObj->SetReg(reg, ZD_CR112, 0x2b);
2564 pObj->SetReg(reg, ZD_CR119, 0xa);
2565 #endif
2566
2567 #if (defined(GCCK) && defined(OFDM))
2568 pObj->SetReg(reg, ZD_CR10, 0x89);
2569 pObj->SetReg(reg, ZD_CR17, 0x28); //for newest (3rd cut) AL2300
2570 pObj->SetReg(reg, ZD_CR26, 0x93);
2571 pObj->SetReg(reg, ZD_CR34, 0x30);
2572 pObj->SetReg(reg, ZD_CR35, 0x3E); //for newest (3rd cut) AL2300
2573 pObj->SetReg(reg, ZD_CR41, 0x24);
2574
2575 #ifdef HOST_IF_USB
2576 pObj->SetReg(reg, ZD_CR44, 0x32);
2577 #else
2578 pObj->SetReg(reg, ZD_CR44, 0x32);
2579 #endif
2580 pObj->SetReg(reg, ZD_CR46, 0x96); //for newest (3rd cut) AL2300
2581 pObj->SetReg(reg, ZD_CR47, 0x1e);
2582 #ifdef ZD1211B
2583 pObj->SetReg(reg,ZD_CR48, 0x00); //ZD1211B 05.06.10
2584 pObj->SetReg(reg,ZD_CR49, 0x00); //ZD1211B 05.06.10
2585 pObj->SetReg(reg,ZD_CR51, 0x01); //ZD1211B 05.06.10
2586 pObj->SetReg(reg,ZD_CR52, 0x80); //ZD1211B 05.06.10
2587 pObj->SetReg(reg,ZD_CR53, 0x7e); //ZD1211B 05.06.10
2588 pObj->SetReg(reg,ZD_CR65, 0x00); //ZD1211B 05.06.10
2589 pObj->SetReg(reg,ZD_CR66, 0x00); //ZD1211B 05.06.10
2590 pObj->SetReg(reg,ZD_CR67, 0x00); //ZD1211B 05.06.10
2591 pObj->SetReg(reg,ZD_CR68, 0x00); //ZD1211B 05.06.10
2592 pObj->SetReg(reg,ZD_CR69, 0x28); //ZD1211B 05.06.10
2593 #endif
2594 pObj->SetReg(reg, ZD_CR79, 0x58);
2595 pObj->SetReg(reg, ZD_CR80, 0x30);
2596 pObj->SetReg(reg, ZD_CR81, 0x30);
2597 pObj->SetReg(reg, ZD_CR87, 0x0A);
2598 pObj->SetReg(reg, ZD_CR89, 0x04);
2599
2600
2601 pObj->SetReg(reg, ZD_CR92, 0x0a);
2602 pObj->SetReg(reg, ZD_CR99, 0x28);
2603 pObj->SetReg(reg, ZD_CR100, 0x00);
2604 pObj->SetReg(reg, ZD_CR101, 0x13);
2605 pObj->SetReg(reg, ZD_CR102, 0x27);
2606 pObj->SetReg(reg, ZD_CR106, 0x24);
2607 pObj->SetReg(reg, ZD_CR107, 0x2A);
2608 pObj->SetReg(reg, ZD_CR109, 0x09);
2609 pObj->SetReg(reg, ZD_CR110, 0x13);
2610 pObj->SetReg(reg, ZD_CR111, 0x1f);
2611 pObj->SetReg(reg, ZD_CR112, 0x1f);
2612 pObj->SetReg(reg, ZD_CR113, 0x27);
2613 pObj->SetReg(reg, ZD_CR114, 0x27);
2614 pObj->SetReg(reg, ZD_CR115, 0x24); //for newest (3rd cut) AL2300
2615 pObj->SetReg(reg, ZD_CR116, 0x24);
2616 #ifdef ZD1211
2617 pObj->SetReg(reg, ZD_CR117, 0xf4);
2618 pObj->SetReg(reg, ZD_CR118, 0xfc);
2619 #elif defined(ZD1211B)
2620 pObj->SetReg(reg, ZD_CR117, 0xfa);
2621 pObj->SetReg(reg, ZD_CR118, 0xfa);
2622 #endif
2623 pObj->SetReg(reg, ZD_CR119, 0x10);
2624 pObj->SetReg(reg, ZD_CR120, 0x4f);
2625 #ifdef ZD1211
2626 pObj->SetReg(reg, ZD_CR121, 0x77);
2627 pObj->SetReg(reg, ZD_CR122, 0xe0);
2628 #elif defined(ZD1211B)
2629 pObj->SetReg(reg, ZD_CR121, 0x6c);
2630 pObj->SetReg(reg, ZD_CR122, 0xfc);
2631 #endif
2632 pObj->SetReg(reg, ZD_CR137, 0x88);
2633 #ifndef HOST_IF_USB
2634 pObj->SetReg(reg, ZD_CR150, 0x0D);
2635 #endif
2636 #elif (defined(ECCK_60_5))
2637 pObj->SetReg(reg, ZD_CR47, 0x1E);
2638 pObj->SetReg(reg, ZD_CR106, 0x04);
2639 pObj->SetReg(reg, ZD_CR107, 0x00);
2640 pObj->SetReg(reg, ZD_CR14, 0x80);
2641 pObj->SetReg(reg, ZD_CR10, 0x89);
2642 pObj->SetReg(reg, ZD_CR11, 0x00);
2643 pObj->SetReg(reg, ZD_CR161, 0x28);
2644 pObj->SetReg(reg, ZD_CR162, 0x26);
2645
2646 pObj->SetReg(reg, ZD_CR24, 0x0e);
2647 pObj->SetReg(reg, ZD_CR41, 0x24);
2648 pObj->SetReg(reg, ZD_CR159, 0x93);
2649 pObj->SetReg(reg, ZD_CR160, 0xfc);
2650 pObj->SetReg(reg, ZD_CR161, 0x20);
2651 pObj->SetReg(reg, ZD_CR162, 0x26);
2652 #endif
2653
2654 pObj->SetReg(reg, ZD_CR252, 0xff);
2655 pObj->SetReg(reg, ZD_CR253, 0xff);
2656
2657 //UnLockPhyReg(pObj);
2658
2659 if (pObj->rfMode == AL2230S_RF)
2660 {
2661 pObj->SetReg(reg, ZD_CR47 , 0x1E); //MARK_002
2662 pObj->SetReg(reg, ZD_CR106, 0x22);
2663 pObj->SetReg(reg, ZD_CR107, 0x2A); //MARK_002
2664 pObj->SetReg(reg, ZD_CR109, 0x13); //MARK_002
2665 pObj->SetReg(reg, ZD_CR118, 0xF8); //MARK_002
2666 pObj->SetReg(reg, ZD_CR119, 0x12);
2667 pObj->SetReg(reg, ZD_CR122, 0xE0);
2668 pObj->SetReg(reg, ZD_CR128, 0x10); //MARK_001 from 0xe->0x10
2669 pObj->SetReg(reg, ZD_CR129, 0x0E); //MARK_001 from 0xd->0x0e
2670 pObj->SetReg(reg, ZD_CR130, 0x10); //MARK_001 from 0xb->0x0d
2671 }
2672 UnLockPhyReg(pObj);
2673 HW_Set_IF_Synthesizer(pObj, AL2230TB_1211[ChannelNo*3]);
2674 HW_Set_IF_Synthesizer(pObj, AL2230TB_1211[ChannelNo*3+1]);
2675 HW_Set_IF_Synthesizer(pObj, AL2230TB_1211[ChannelNo*3+2]);
2676 HW_Set_IF_Synthesizer(pObj, 0x0b3331);
2677 HW_Set_IF_Synthesizer(pObj, 0x03b812);
2678 HW_Set_IF_Synthesizer(pObj, 0x00fff3);
2679 if (pObj->rfMode == AL2230S_RF)
2680 HW_Set_IF_Synthesizer(pObj, 0x000824); //improve band edge for AL2230S
2681 else
2682 HW_Set_IF_Synthesizer(pObj, 0x0005a4);
2683
2684 HW_Set_IF_Synthesizer(pObj, 0x000da4);
2685 HW_Set_IF_Synthesizer(pObj, 0x0f4dc5); // fix freq shift, 0x04edc5, 1211 is differ from 1211B
2686 HW_Set_IF_Synthesizer(pObj, 0x0805b6);
2687 HW_Set_IF_Synthesizer(pObj, 0x011687);
2688 HW_Set_IF_Synthesizer(pObj, 0x000688);
2689 HW_Set_IF_Synthesizer(pObj, 0x0403b9); //External control TX power (CR31)
2690 HW_Set_IF_Synthesizer(pObj, 0x00dbba);
2691 HW_Set_IF_Synthesizer(pObj, 0x00099b);
2692 HW_Set_IF_Synthesizer(pObj, 0x0bdffc);
2693 HW_Set_IF_Synthesizer(pObj, 0x00000d);
2694 HW_Set_IF_Synthesizer(pObj, 0x00500f);
2695
2696 LockPhyReg(pObj);
2697 pObj->SetReg(reg, ZD_CR251, 0x2f); // shdnb(PLL_ON)=0
2698 pObj->SetReg(reg, ZD_CR251, 0x3f); // shdnb(PLL_ON)=1
2699 pObj->DelayUs(10);
2700 UnLockPhyReg(pObj);
2701 HW_Set_IF_Synthesizer(pObj, 0x000d00f);
2702 pObj->DelayUs(100);
2703 HW_Set_IF_Synthesizer(pObj, 0x0004c0f);
2704 pObj->DelayUs(100);
2705 HW_Set_IF_Synthesizer(pObj, 0x00540f);
2706 pObj->DelayUs(100);
2707 HW_Set_IF_Synthesizer(pObj, 0x00700f);
2708 pObj->DelayUs(100);
2709 HW_Set_IF_Synthesizer(pObj, 0x00500f);
2710
2711 }
2712 else{
2713 HW_Set_IF_Synthesizer(pObj, AL2230TB_1211[ChannelNo*3]);
2714 HW_Set_IF_Synthesizer(pObj, AL2230TB_1211[ChannelNo*3+1]);
2715 HW_Set_IF_Synthesizer(pObj, AL2230TB_1211[ChannelNo*3+2]);
2716 }
2717
2718 LockPhyReg(pObj);
2719 pObj->SetReg(reg, ZD_CR138, 0x28);
2720 pObj->SetReg(reg, ZD_CR203, 0x06);
2721 //UnLockPhyReg(pObj);
2722 pObj->CR203Flag = 2;
2723 pObj->CR31Flag = 2;
2724 if (pObj->HWFeature & BIT_8) //CR47 CCK gain patch
2725 {
2726 tmpvalue = pObj->GetReg(reg, E2P_PHY_REG);
2727 pObj->SetReg(reg, ZD_CR47, (tmpvalue & 0xff)); //This feature is OK to be overwritten with a lower value by other feature
2728 }
2729
2730 if (pObj->HWFeature & BIT_21) //6321 for FCC regulation, enabled per HWFeature 6M band edge bit (for AL2230, AL2230S)
2731 {
2732 if (ChannelNo == 1 || ChannelNo == 11) //MARK_003, band edge, these may depend on PCB layout
2733 {
2734 pObj->SetReg(reg, ZD_CR128, 0x12);
2735 pObj->SetReg(reg, ZD_CR129, 0x12);
2736 pObj->SetReg(reg, ZD_CR130, 0x10);
2737 pObj->SetReg(reg, ZD_CR47, 0x1E);
2738 }
2739 else //(ChannelNo 2 ~ 10, 12 ~ 14)
2740 {
2741 pObj->SetReg(reg, ZD_CR128, 0x14);
2742 pObj->SetReg(reg, ZD_CR129, 0x12);
2743 pObj->SetReg(reg, ZD_CR130, 0x10);
2744 pObj->SetReg(reg, ZD_CR47, 0x1E);
2745 }
2746 }
2747
2748
2749 #if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )
2750 pObj->SetReg(reg, ZD_PE1_PE2, 3);
2751 #endif
2752
2753 UnLockPhyReg(pObj);
2754 }
2755 #elif defined(ZD1211B)
2756 void
2757 HW_Set_AL2230_RF_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
2758 {
2759 U32 tmpvalue;
2760 U16 WriteAddr[256];
2761 U16 WriteData[256];
2762 U16 WriteIndex = 0;
2763 void *reg = pObj->reg;
2764
2765 LockPhyReg(pObj);
2766 pObj->SetReg(reg, ZD_CR240, 0x57);
2767 if (1)
2768 pObj->SetReg(reg, ZD_CR9, 0xe0);
2769 else
2770 pObj->SetReg(reg, ZD_CR9, 0xe4);
2771 UnLockPhyReg(pObj);
2772 tmpvalue = pObj->GetReg(reg,CtlReg1);
2773 tmpvalue &= ~0x80;
2774 pObj->SetReg(reg, CtlReg1, tmpvalue);
2775 if (!InitChOnly){
2776 //mFILL_WRITE_REGISTER(ZD_CR9, 0xe0);
2777 mFILL_WRITE_REGISTER(ZD_CR10, 0x89);
2778 mFILL_WRITE_REGISTER(ZD_CR15, 0x20);
2779 mFILL_WRITE_REGISTER(ZD_CR17, 0x2B); //for newest(3rd cut) AL2230
2780 mFILL_WRITE_REGISTER(ZD_CR23, 0x40);
2781 mFILL_WRITE_REGISTER(ZD_CR24, 0x20);
2782 mFILL_WRITE_REGISTER(ZD_CR26, 0x93);
2783 mFILL_WRITE_REGISTER(ZD_CR28, 0x3e);
2784 mFILL_WRITE_REGISTER(ZD_CR29, 0x00);
2785 mFILL_WRITE_REGISTER(ZD_CR33, 0x28); //5621
2786 mFILL_WRITE_REGISTER(ZD_CR34, 0x30);
2787 mFILL_WRITE_REGISTER(ZD_CR35, 0x3e); //for newest(3rd cut) AL2230
2788 mFILL_WRITE_REGISTER(ZD_CR41, 0x24);
2789 mFILL_WRITE_REGISTER(ZD_CR44, 0x32);
2790 mFILL_WRITE_REGISTER(ZD_CR46, 0x99); //for newest(3rd cut) AL2230
2791 mFILL_WRITE_REGISTER(ZD_CR47, 0x1e);
2792 mFILL_WRITE_REGISTER(ZD_CR48, 0x06); //ZD1215 05.06.10
2793 mFILL_WRITE_REGISTER(ZD_CR49, 0xf9); //ZD1215 05.06.10
2794 mFILL_WRITE_REGISTER(ZD_CR51, 0x01); //ZD1215 05.06.10
2795 mFILL_WRITE_REGISTER(ZD_CR52, 0x80); //ZD1215 05.06.10
2796 mFILL_WRITE_REGISTER(ZD_CR53, 0x7e); //ZD1215 05.06.10
2797 mFILL_WRITE_REGISTER(ZD_CR65, 0x00); //ZD1215 05.06.10
2798 mFILL_WRITE_REGISTER(ZD_CR66, 0x00); //ZD1215 05.06.10
2799 mFILL_WRITE_REGISTER(ZD_CR67, 0x00); //ZD1215 05.06.10
2800 mFILL_WRITE_REGISTER(ZD_CR68, 0x00); //ZD1215 05.06.10
2801 mFILL_WRITE_REGISTER(ZD_CR69, 0x28); //ZD1215 05.06.10
2802 mFILL_WRITE_REGISTER(ZD_CR79, 0x58);
2803 mFILL_WRITE_REGISTER(ZD_CR80, 0x30);
2804 mFILL_WRITE_REGISTER(ZD_CR81, 0x30);
2805 mFILL_WRITE_REGISTER(ZD_CR87, 0x0a);
2806 mFILL_WRITE_REGISTER(ZD_CR89, 0x04);
2807 mFILL_WRITE_REGISTER(ZD_CR91, 0x00); //5621
2808 mFILL_WRITE_REGISTER(ZD_CR92, 0x0a);
2809 mFILL_WRITE_REGISTER(ZD_CR98, 0x8d); //4804, for 1212 new algorithm
2810 mFILL_WRITE_REGISTER(ZD_CR99, 0x00); //5621
2811 mFILL_WRITE_REGISTER(ZD_CR101, 0x13);
2812 mFILL_WRITE_REGISTER(ZD_CR102, 0x27);
2813 mFILL_WRITE_REGISTER(ZD_CR106, 0x24); //for newest(3rd cut) AL2230
2814 mFILL_WRITE_REGISTER(ZD_CR107, 0x2a);
2815 mFILL_WRITE_REGISTER(ZD_CR109, 0x13); //4804, for 1212 new algorithm
2816 mFILL_WRITE_REGISTER(ZD_CR110, 0x1f); //4804, for 1212 new algorithm
2817 mFILL_WRITE_REGISTER(ZD_CR111, 0x1f);
2818 mFILL_WRITE_REGISTER(ZD_CR112, 0x1f);
2819 mFILL_WRITE_REGISTER(ZD_CR113, 0x27);
2820 mFILL_WRITE_REGISTER(ZD_CR114, 0x27);
2821 mFILL_WRITE_REGISTER(ZD_CR115, 0x26); //24->26 at 4902 for newest(3rd cut) AL2230
2822 mFILL_WRITE_REGISTER(ZD_CR116, 0x24);
2823 mFILL_WRITE_REGISTER(ZD_CR117, 0xfa); // for 1215
2824 mFILL_WRITE_REGISTER(ZD_CR118, 0xfa); // for 1215
2825 mFILL_WRITE_REGISTER(ZD_CR119, 0x10);
2826 mFILL_WRITE_REGISTER(ZD_CR120, 0x4f);
2827 mFILL_WRITE_REGISTER(ZD_CR121, 0x6c); // for 1215
2828 mFILL_WRITE_REGISTER(ZD_CR122, 0xfc); // E0->FC at 4902
2829 mFILL_WRITE_REGISTER(ZD_CR123, 0x57); //5623
2830 mFILL_WRITE_REGISTER(ZD_CR125, 0xad); //4804, for 1212 new algorithm
2831 mFILL_WRITE_REGISTER(ZD_CR126, 0x6c); //5614
2832 mFILL_WRITE_REGISTER(ZD_CR127, 0x03); //4804, for 1212 new algorithm
2833 mFILL_WRITE_REGISTER(ZD_CR137, 0x50); //5614
2834 mFILL_WRITE_REGISTER(ZD_CR138, 0xa8);
2835 mFILL_WRITE_REGISTER(ZD_CR144, 0xac); //5621
2836 mFILL_WRITE_REGISTER(ZD_CR150, 0x0d);
2837 mFILL_WRITE_REGISTER(ZD_CR252, 0x34);
2838 mFILL_WRITE_REGISTER(ZD_CR253, 0x34);
2839
2840 if(pObj->rfMode == AL2230S_RF)
2841 {
2842 mFILL_WRITE_REGISTER(ZD_CR47, 0x1E);
2843 mFILL_WRITE_REGISTER(ZD_CR106, 0x22);
2844 mFILL_WRITE_REGISTER(ZD_CR107, 0x2A);
2845 mFILL_WRITE_REGISTER(ZD_CR109, 0x13);
2846 mFILL_WRITE_REGISTER(ZD_CR118, 0xF8);
2847 mFILL_WRITE_REGISTER(ZD_CR119, 0x12);
2848 mFILL_WRITE_REGISTER(ZD_CR122, 0xE0);
2849 mFILL_WRITE_REGISTER(ZD_CR128, 0x10);
2850 mFILL_WRITE_REGISTER(ZD_CR129, 0x0E);
2851 mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
2852 }
2853 //mFILL_WRITE_REGISTER(ZD_CR240, 0x57);
2854 SET_IF_SYNTHESIZER(macp, AL2230TB[ChannelNo*3]);
2855 SET_IF_SYNTHESIZER(macp, AL2230TB[ChannelNo*3+1]);
2856 SET_IF_SYNTHESIZER(macp, AL2230TB[ChannelNo*3+2]);
2857 SET_IF_SYNTHESIZER(macp, 0x8cccd0);
2858 SET_IF_SYNTHESIZER(macp, 0x481dc0);
2859 SET_IF_SYNTHESIZER(macp, 0xcfff00);
2860 if(pObj->rfMode == AL2230S_RF)
2861 {
2862 SET_IF_SYNTHESIZER(macp, 0x241000);
2863 }
2864 else
2865 {
2866 SET_IF_SYNTHESIZER(macp, 0x25A000);
2867 }
2868
2869 //SET_IF_SYNTHESIZER(macp, 0x25b000); //Reg4 update for MP version
2870 SET_IF_SYNTHESIZER(macp, 0x25a000); //To improve AL2230 yield, improve phase noise, 4713
2871 //SET_IF_SYNTHESIZER(macp, 0xa3b720); //Reg5 update for MP version
2872 SET_IF_SYNTHESIZER(macp, 0xa3b2f0); //To improve AL2230 yield, improve phase noise, 4713
2873 SET_IF_SYNTHESIZER(macp, 0x6da010); //Reg6 update for MP versio
2874 //SET_IF_SYNTHESIZER(macp, 0xe16880);
2875 SET_IF_SYNTHESIZER(macp, 0xe36280); // Modified by jxiao for Bor-Chin on 2004/08/02
2876 SET_IF_SYNTHESIZER(macp, 0x116000);
2877 //SET_IF_SYNTHESIZER(macp, 0x9de000); //register control TX power
2878 SET_IF_SYNTHESIZER(macp, 0x9dc020); //External control TX power (ZD_CR31)
2879 SET_IF_SYNTHESIZER(macp, 0x5ddb00); //RegA update for MP version
2880 SET_IF_SYNTHESIZER(macp, 0xd99000); //RegB update for MP version
2881 SET_IF_SYNTHESIZER(macp, 0x3ffbd0); //RegC update for MP version
2882 SET_IF_SYNTHESIZER(macp, 0xb00000); //RegD update for MP version
2883 //SET_IF_SYNTHESIZER(macp, 0xf00a00);
2884 SET_IF_SYNTHESIZER(macp, 0xf01a00); //improve phase noise and remove phase calibration,4713
2885 /*
2886 mFILL_WRITE_REGISTER( CR47, 0x0);
2887 mFILL_WRITE_REGISTER( CR251, 0x2f); // shdnb(PLL_ON)=0
2888 mFILL_WRITE_REGISTER( CR251, 0x3f); // shdnb(PLL_ON)=1
2889 mFILL_WRITE_REGISTER( RFCFG1, 0x3); // Continuous TX
2890 pObj->DelayUs(10);
2891 SET_IF_SYNTHESIZER(macp, 0xf01100);
2892 pObj->DelayUs(100);
2893 SET_IF_SYNTHESIZER(macp, 0xf01000);
2894 pObj->DelayUs(100);
2895 mFILL_WRITE_REGISTER( RFCFG1, 0x0); // stop continuous TX
2896 mFILL_WRITE_REGISTER( CR47, 0x18);
2897 */
2898 mFILL_WRITE_REGISTER( ZD_CR251, 0x2f); // shdnb(PLL_ON)=0
2899 mFILL_WRITE_REGISTER( ZD_CR251, 0x7f); // shdnb(PLL_ON)=1
2900 //pObj->DelayUs(10);
2901 //SET_IF_SYNTHESIZER(macp, 0xf00b00);
2902 SET_IF_SYNTHESIZER(macp, 0xf01b00); //To improve AL2230 yield, 4713
2903 pObj->DelayUs(100);
2904 //SET_IF_SYNTHESIZER(macp, 0xf03200); //remove phase calibration, 4713
2905 //pObj->DelayUs(100);
2906 //SET_IF_SYNTHESIZER(macp, 0xf02a00); //remove phase calibration, 4713
2907 //pObj->DelayUs(100);
2908 //SET_IF_SYNTHESIZER(macp, 0xf00e00);
2909 SET_IF_SYNTHESIZER(macp, 0xf01e00); //To improve AL2230 yield, 4713
2910 pObj->DelayUs(100);
2911 //SET_IF_SYNTHESIZER(macp, 0xf00a00);
2912 SET_IF_SYNTHESIZER(macp, 0xf01a00); //To improve AL2230 yield,4713
2913 }
2914 else{
2915 SET_IF_SYNTHESIZER(macp, AL2230TB[ChannelNo*3]);
2916 SET_IF_SYNTHESIZER(macp, AL2230TB[ChannelNo*3+1]);
2917 SET_IF_SYNTHESIZER(macp, AL2230TB[ChannelNo*3+2]);
2918 }
2919 //Band Edge issue
2920 //if(pObj->CardSetting.NetworkTypeInUse == Ndis802_11OFDM24)
2921
2922 if(pObj->HWFeature & BIT_21)
2923 {
2924
2925 if(ChannelNo == 1 || ChannelNo == 11)
2926 {
2927 if(1)//Adapter->PHY_Decrease_CR128_state)
2928 {
2929 mFILL_WRITE_REGISTER(ZD_CR128, 0x12);
2930 mFILL_WRITE_REGISTER(ZD_CR129, 0x12);
2931 mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
2932 }
2933 else
2934 {
2935 mFILL_WRITE_REGISTER(ZD_CR128, 0x10);
2936 mFILL_WRITE_REGISTER(ZD_CR129, 0x10);
2937 mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
2938 }
2939 }
2940
2941 else
2942 {
2943 mFILL_WRITE_REGISTER(ZD_CR128, 0x14);
2944 mFILL_WRITE_REGISTER(ZD_CR129, 0x12);
2945 mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
2946 }
2947 }
2948 else
2949 {
2950 mFILL_WRITE_REGISTER(ZD_CR128, 0x14);
2951 mFILL_WRITE_REGISTER(ZD_CR129, 0x12);
2952 mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
2953 }
2954
2955
2956 mFILL_WRITE_REGISTER(ZD_CR80, 0x30);
2957 mFILL_WRITE_REGISTER(ZD_CR81, 0x30);
2958 mFILL_WRITE_REGISTER(ZD_CR79, 0x58);
2959 mFILL_WRITE_REGISTER(ZD_CR12, 0xF0);
2960 mFILL_WRITE_REGISTER(ZD_CR77, 0x1B);
2961 mFILL_WRITE_REGISTER(ZD_CR78, 0x58);
2962 //mFILL_WRITE_REGISTER(ZD_CR138, 0xa8);//Org:0x28//ComTrend:RalLink AP
2963 //if (!pObj->ZDEnterCALMode_Used) // Do not modify CR203 during CAL mode
2964 if(1)
2965 {
2966 //mFILL_WRITE_REGISTER(ZD_CR138, 0xa8);//Org:0x28//ComTrend:RalLink AP
2967 mFILL_WRITE_REGISTER( ZD_CR203, 0x06);
2968 }
2969 ZD1211_WRITE_MULTI_REG(WriteAddr, WriteData, &WriteIndex);
2970 //ZD1205_READ_REGISTER(Adapter,CtlReg1, &tmpvalue);
2971 tmpvalue = pObj->GetReg(reg, CtlReg1);
2972 tmpvalue |= 0x80;
2973 pObj->SetReg(reg, CtlReg1, tmpvalue);
2974
2975 LockPhyReg(pObj);
2976 pObj->SetReg(reg, ZD_CR240, 0x80);
2977 if(pObj->PHYNEWLayout)
2978 {
2979 if (1)
2980 pObj->SetReg(reg, ZD_CR9, 0xe1);
2981 else
2982 pObj->SetReg(reg, ZD_CR9, 0xe5);
2983 }
2984 if (pObj->HWFeature & BIT_8) //CR47 CCK gain patch
2985 {
2986 tmpvalue = pObj->GetReg(reg, E2P_PHY_REG);
2987 pObj->SetReg(reg, ZD_CR47, (tmpvalue & 0xff)); //This feature is OK to be overwritten with a lower value by other feature
2988 }
2989
2990 pObj->SetReg(reg, ZD_CR203, 0x06);
2991 UnLockPhyReg(pObj);
2992
2993 pObj->CR203Flag = 2;
2994 //pObj->CR31Flag = cCR31InitialState;
2995 //Adapter->Change_SetPoint = 2;
2996 //Adapter->PHY_G_BandEdge_Flag = 0;
2997
2998 #if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )
2999 pObj->SetReg(reg, PE1_PE2, 3);
3000 //ZD1205_WRITE_REGISTER(Adapter,PE1_PE2, 3);
3001 #endif
3002 }
3003
3004
3005 #endif
3006
3007
3008
3009 //2-step LNA for RF2959
3010 void
3011 HW_Set_RFMD_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
3012 {
3013 void *reg = pObj->reg;
3014
3015 LockPhyReg(pObj);
3016
3017 // Get Phy-Config permission
3018 if (!InitChOnly ){
3019 //LockPhyReg(pObj);
3020 pObj->SetReg(reg, ZD_CR2, 0x1E);
3021 pObj->SetReg(reg, ZD_CR9, 0x20);
3022 //pObj->SetReg(reg, ZD_CR10, 0xB1);
3023 pObj->SetReg(reg, ZD_CR10, 0x89);
3024 pObj->SetReg(reg, ZD_CR11, 0x00);
3025 pObj->SetReg(reg, ZD_CR15, 0xD0);
3026 #ifdef ZD1211
3027 pObj->SetReg(reg, ZD_CR17, 0x68);
3028 #elif defined(ZD1211B)
3029 pObj->SetReg(reg, ZD_CR17, 0x2b);
3030 #endif
3031 pObj->SetReg(reg, ZD_CR19, 0x4a);
3032 pObj->SetReg(reg, ZD_CR20, 0x0c);
3033 pObj->SetReg(reg, ZD_CR21, 0x0E);
3034 pObj->SetReg(reg, ZD_CR23, 0x48);
3035
3036 if (pObj->bIsNormalSize)
3037 pObj->SetReg(reg, ZD_CR24, 0x14);//cca threshold
3038 else
3039 pObj->SetReg(reg, ZD_CR24, 0x20);//cca threshold
3040
3041 pObj->SetReg(reg, ZD_CR26, 0x90);
3042 pObj->SetReg(reg, ZD_CR27, 0x30);
3043 pObj->SetReg(reg, ZD_CR29, 0x20);
3044 pObj->SetReg(reg, ZD_CR31, 0xb2);
3045 //pObj->SetReg(reg, ZD_CR31, 0xaa);
3046 pObj->SetReg(reg, ZD_CR32, 0x43);
3047 pObj->SetReg(reg, ZD_CR33, 0x28);
3048 pObj->SetReg(reg, ZD_CR38, 0x30);
3049 pObj->SetReg(reg, ZD_CR34, 0x0f);
3050 pObj->SetReg(reg, ZD_CR35, 0xF0);
3051 pObj->SetReg(reg, ZD_CR41, 0x2a);
3052 pObj->SetReg(reg, ZD_CR46, 0x7F);
3053 pObj->SetReg(reg, ZD_CR47, 0x1E);
3054 #ifdef ZD1211
3055 pObj->SetReg(reg, ZD_CR51, 0xc5);
3056 pObj->SetReg(reg, ZD_CR52, 0xc5);
3057 pObj->SetReg(reg, ZD_CR53, 0xc5);
3058 #elif defined(ZD1211B)
3059 pObj->SetReg(reg, ZD_CR51, 0x01);
3060 pObj->SetReg(reg, ZD_CR52, 0x80);
3061 pObj->SetReg(reg, ZD_CR53, 0x7e);
3062
3063 pObj->SetReg(reg,ZD_CR48, 0x00); //ZD1211B 05.06.10
3064 pObj->SetReg(reg,ZD_CR49, 0x00); //ZD1211B 05.06.10
3065 pObj->SetReg(reg,ZD_CR65, 0x00); //ZD1211B 05.06.10
3066 pObj->SetReg(reg,ZD_CR66, 0x00); //ZD1211B 05.06.10
3067 pObj->SetReg(reg,ZD_CR67, 0x00); //ZD1211B 05.06.10
3068 pObj->SetReg(reg,ZD_CR68, 0x00); //ZD1211B 05.06.10
3069 pObj->SetReg(reg,ZD_CR69, 0x28); //ZD1211B 05.06.10
3070
3071 #endif
3072 pObj->SetReg(reg, ZD_CR79, 0x58);
3073 pObj->SetReg(reg, ZD_CR80, 0x30);
3074 pObj->SetReg(reg, ZD_CR81, 0x30);
3075 pObj->SetReg(reg, ZD_CR82, 0x00);
3076 pObj->SetReg(reg, ZD_CR83, 0x24);
3077 pObj->SetReg(reg, ZD_CR84, 0x04);
3078 pObj->SetReg(reg, ZD_CR85, 0x00);
3079 pObj->SetReg(reg, ZD_CR86, 0x10);
3080 pObj->SetReg(reg, ZD_CR87, 0x2A);
3081 pObj->SetReg(reg, ZD_CR88, 0x10);
3082 pObj->SetReg(reg, ZD_CR89, 0x24);
3083 pObj->SetReg(reg, ZD_CR90, 0x18);
3084 //pObj->SetReg(reg, ZD_CR91, 0x18);
3085 pObj->SetReg(reg, ZD_CR91, 0x00); // to solve continuous CTS frames problem
3086 pObj->SetReg(reg, ZD_CR92, 0x0a);
3087 pObj->SetReg(reg, ZD_CR93, 0x00);
3088 pObj->SetReg(reg, ZD_CR94, 0x01);
3089 pObj->SetReg(reg, ZD_CR95, 0x00);
3090 pObj->SetReg(reg, ZD_CR96, 0x40);
3091
3092 pObj->SetReg(reg, ZD_CR97, 0x37);
3093 #ifdef HOST_IF_USB
3094 #ifdef ZD1211
3095 pObj->SetReg(reg, ZD_CR98, 0x05);
3096 #elif defined(ZD1211B)
3097 pObj->SetReg(reg, ZD_CR98, 0x8d);
3098 #endif
3099 #else
3100 pObj->SetReg(reg, ZD_CR98, 0x0D);
3101 pObj->SetReg(reg, ZD_CR121, 0x06);
3102 pObj->SetReg(reg, ZD_CR125, 0xAA);
3103 #endif
3104 pObj->SetReg(reg, ZD_CR99, 0x28);
3105 pObj->SetReg(reg, ZD_CR100, 0x00);
3106 pObj->SetReg(reg, ZD_CR101, 0x13);
3107 pObj->SetReg(reg, ZD_CR102, 0x27);
3108 pObj->SetReg(reg, ZD_CR103, 0x27);
3109 pObj->SetReg(reg, ZD_CR104, 0x18);
3110 pObj->SetReg(reg, ZD_CR105, 0x12);
3111
3112 if (pObj->bIsNormalSize)
3113
3114 pObj->SetReg(reg, ZD_CR106, 0x1a);
3115 else
3116 pObj->SetReg(reg, ZD_CR106, 0x22);
3117
3118 pObj->SetReg(reg, ZD_CR107, 0x24);
3119 pObj->SetReg(reg, ZD_CR108, 0x0a);
3120 pObj->SetReg(reg, ZD_CR109, 0x13);
3121 #ifdef ZD1211
3122 pObj->SetReg(reg, ZD_CR110, 0x2F);
3123 #elif defined(ZD1211B)
3124 pObj->SetReg(reg, ZD_CR110, 0x1F);
3125 #endif
3126 pObj->SetReg(reg, ZD_CR111, 0x27);
3127 pObj->SetReg(reg, ZD_CR112, 0x27);
3128 pObj->SetReg(reg, ZD_CR113, 0x27);
3129 pObj->SetReg(reg, ZD_CR114, 0x27);
3130 #ifdef ZD1211
3131 pObj->SetReg(reg, ZD_CR115, 0x40);
3132 pObj->SetReg(reg, ZD_CR116, 0x40);
3133 pObj->SetReg(reg, ZD_CR117, 0xF0);
3134 pObj->SetReg(reg, ZD_CR118, 0xF0);
3135 #elif defined(ZD1211B)
3136 pObj->SetReg(reg, ZD_CR115, 0x26);
3137 pObj->SetReg(reg, ZD_CR116, 0x40);
3138 pObj->SetReg(reg, ZD_CR117, 0xFA);
3139 pObj->SetReg(reg, ZD_CR118, 0xFA);
3140 pObj->SetReg(reg, ZD_CR121, 0x6C);
3141 #endif
3142 pObj->SetReg(reg, ZD_CR119, 0x16);
3143 //pObj->SetReg(reg, ZD_CR122, 0xfe);
3144 if (pObj->bContinueTx)
3145 pObj->SetReg(reg, ZD_CR122, 0xff);
3146 else
3147 pObj->SetReg(reg, ZD_CR122, 0x00);
3148 pObj->CR122Flag = 2;
3149 #ifdef ZD1211B
3150 pObj->SetReg(reg,ZD_CR125, 0xad); //4804, for 1212 new algorithm
3151 pObj->SetReg(reg,ZD_CR126, 0x6c); //5614
3152
3153 #endif
3154
3155 pObj->SetReg(reg, ZD_CR127, 0x03);
3156 pObj->SetReg(reg, ZD_CR131, 0x08);
3157 pObj->SetReg(reg, ZD_CR138, 0x28);
3158 pObj->SetReg(reg, ZD_CR148, 0x44);
3159 #ifdef ZD1211
3160 pObj->SetReg(reg, ZD_CR150, 0x10);
3161 #elif defined(ZD1211B)
3162 pObj->SetReg(reg, ZD_CR150, 0x14);
3163 #endif
3164 pObj->SetReg(reg, ZD_CR169, 0xBB);
3165 pObj->SetReg(reg, ZD_CR170, 0xBB);
3166 //pObj->SetReg(reg, ZD_CR38, 0x30);
3167 //UnLockPhyReg(pObj);
3168
3169 HW_Set_IF_Synthesizer(pObj, 0x000007); //REG0(CFG1)
3170 HW_Set_IF_Synthesizer(pObj, 0x07dd43); //REG1(IFPLL1)
3171 HW_Set_IF_Synthesizer(pObj, 0x080959); //REG2(IFPLL2)
3172 HW_Set_IF_Synthesizer(pObj, 0x0e6666);
3173 HW_Set_IF_Synthesizer(pObj, 0x116a57); //REG4
3174 HW_Set_IF_Synthesizer(pObj, 0x17dd43); //REG5
3175 HW_Set_IF_Synthesizer(pObj, 0x1819f9); //REG6
3176 HW_Set_IF_Synthesizer(pObj, 0x1e6666);
3177 HW_Set_IF_Synthesizer(pObj, 0x214554);
3178 HW_Set_IF_Synthesizer(pObj, 0x25e7fa);
3179 HW_Set_IF_Synthesizer(pObj, 0x27fffa);
3180 //HW_Set_IF_Synthesizer(pObj, 0x294128); //Register control TX power
3181 // set in Set_RF_Channel( )
3182 //HW_Set_IF_Synthesizer(pObj, 0x28252c); //External control TX power (CR31_CCK, CR51_6-36M, CR52_48M, CR53_54M
3183 HW_Set_IF_Synthesizer(pObj, 0x2c0000);
3184 HW_Set_IF_Synthesizer(pObj, 0x300000);
3185
3186
3187 HW_Set_IF_Synthesizer(pObj, 0x340000); //REG13(0xD)
3188 HW_Set_IF_Synthesizer(pObj, 0x381e0f); //REG14(0xE)
3189 HW_Set_IF_Synthesizer(pObj, 0x6c180f); //REG27(0x11)
3190 }
3191 else{
3192 //LockPhyReg(pObj);
3193 if (pObj->bContinueTx)
3194 pObj->SetReg(reg, ZD_CR122, 0xff);
3195 else
3196 pObj->SetReg(reg, ZD_CR122, 0x00);
3197 //UnLockPhyReg(pObj);
3198
3199 pObj->CR122Flag = 2;
3200 pObj->CR31Flag = 2;
3201
3202 HW_Set_IF_Synthesizer(pObj, RFMD2958t[ChannelNo*2]);
3203 HW_Set_IF_Synthesizer(pObj, RFMD2958t[ChannelNo*2+1]);
3204
3205 }
3206
3207
3208 UnLockPhyReg(pObj);
3209
3210 return;
3211 }
3212
3213 void HW_EnableBeacon(zd_80211Obj_t *pObj, U16 BeaconInterval, U16 DtimPeriod, U8 BssType)
3214 {
3215 U32 tmpValue;
3216 U32 Mode = 0;
3217 U16 Dtim = 0;
3218
3219 void *reg = pObj->reg;
3220
3221 if (BssType == INDEPENDENT_BSS){
3222 Mode = IBSS_MODE;
3223 /*==prince delete
3224 printk(KERN_ERR "Mode: IBSS_MODE\n");
3225 ================*/
3226 }
3227 else if (BssType == AP_BSS){
3228 Mode = AP_MODE;
3229 Dtim = DtimPeriod;
3230 /*==prince delete
3231 printk(KERN_ERR "Mode: AP_BSS\n");
3232 ================*/
3233 }
3234
3235 tmpValue = BeaconInterval | Mode | (Dtim<<16) ;
3236 pObj->SetReg(reg, ZD_BCNInterval, tmpValue);
3237 }
3238
3239
3240 void HW_SwitchChannel(zd_80211Obj_t *pObj, U16 channel, U8 InitChOnly, const U8 MAC_Mode)
3241 {
3242 void *reg = pObj->reg;
3243
3244
3245 pObj->SetReg(reg, ZD_CONFIGPhilips, 0x0);
3246
3247 //FPRINT_V("rfMode", pObj->rfMode);
3248
3249 switch(pObj->rfMode)
3250 {
3251 /*==prince delete
3252 default:
3253 printk("Invalid RF module parameter:%lu", pObj->rfMode);
3254
3255 break;
3256 prince delete====*/
3257 /*
3258 case MAXIM_NEW_RF:
3259 FPRINT_V("MAXIM_NEW_RF Channel", channel);
3260 pObj->S_bit_cnt = 18;
3261 HW_Set_Maxim_New_Chips(pObj, channel, 0);
3262
3263 #ifdef HOST_IF_USB
3264 HW_UpdateIntegrationValue(pObj, channel, MAC_Mode);
3265 #endif
3266 break;
3267 */
3268
3269 /*
3270 case GCT_RF:
3271 // FPRINT_V("GCT Channel", channel);
3272 pObj->S_bit_cnt = 21;
3273
3274 pObj->AcquireDoNotSleep();
3275 if (!pObj->bDeviceInSleep)
3276 HW_Set_GCT_Chips(pObj, channel, InitChOnly);
3277 pObj->ReleaseDoNotSleep();
3278 //HW_UpdateIntegrationValue(pObj, channel);
3279 break;
3280 */
3281 case UW2453_RF:
3282 pObj->S_bit_cnt = 24;
3283 HW_Set_UW2453_RF_Chips(pObj, channel, InitChOnly);
3284 break;
3285
3286 case AL2230_RF:
3287 case AL2230S_RF:
3288 //FPRINT_V("AL2210MPVB_RF Channel", channel);
3289 pObj->S_bit_cnt = 24;
3290 HW_Set_AL2230_RF_Chips(pObj, channel, InitChOnly);
3291 HW_UpdateIntegrationValue(pObj, channel, MAC_Mode);
3292 break;
3293 case AL7230B_RF: //For 802.11a/b/g
3294 FPRINT_V("AL7230B_RF",channel);
3295 pObj->S_bit_cnt = 24;
3296 // printk("Before AL7230BRF:C,%d,M,%d\n\n",channel,MAC_Mode);
3297 HW_Set_AL7230B_RF_Chips(pObj, channel, InitChOnly,MAC_Mode);
3298 break;
3299 /*
3300 case AL2210_RF:
3301 //FPRINT_V("AL2210_RF Channel", channel);
3302 pObj->S_bit_cnt = 24;
3303 HW_Set_AL2210_Chips(pObj, channel, 0);
3304 break;
3305
3306 case RALINK_RF:
3307 FPRINT_V("Ralink Channel", channel);
3308 break;
3309
3310 case INTERSIL_RF:
3311 FPRINT_V("Intersil Channel", channel);
3312 break;
3313 */
3314
3315 case RFMD_RF:
3316 FPRINT_V("RFMD Channel", channel);
3317 pObj->S_bit_cnt = 24;
3318 HW_Set_RFMD_Chips(pObj, channel, InitChOnly);
3319
3320
3321 if (!InitChOnly)
3322 HW_UpdateIntegrationValue(pObj, channel, MAC_Mode);
3323 break;
3324 /*
3325 case MAXIM_NEW_RF2:
3326 FPRINT_V("MAXIM_NEW_RF2 Channel", channel);
3327
3328 pObj->S_bit_cnt = 18;
3329 HW_Set_Maxim_New_Chips2(pObj, channel, 0);
3330 break;
3331
3332 case PHILIPS_RF:
3333 FPRINT_V("Philips SA2400 Channel", channel);
3334 break;
3335 */
3336 //prince add begin
3337 default:
3338 printk("Invalid RF module parameter:%lu", pObj->rfMode);
3339
3340 break;
3341 //prince add end
3342
3343 }
3344
3345 HW_OverWritePhyRegFromE2P(pObj);
3346
3347 return;
3348 }
3349
3350
3351
3352 void HW_SetRfChannel(zd_80211Obj_t *pObj, U16 channel, U8 InitChOnly, const U8 MAC_Mode)
3353 {
3354 void *reg = pObj->reg;
3355 //FPRINT_V("HW_SetRfChannel", channel);
3356
3357 // Check if this ChannelNo allowed?
3358 u32 i;
3359
3360 if (!((1 << (channel-1)) & pObj->AllowedChannel)){
3361 // Not an allowed channel, we use default channel.
3362 //printk("Channel = %d Not an allowed channel\n", channel);
3363 //printk("Set default channel = %d\n", (pObj->AllowedChannel >> 16));
3364 //channel = (pObj->AllowedChannel >> 16);
3365 if(PURE_A_MODE != MAC_Mode) {
3366 //printk("You use a non-allowed channel in HW_setRfChannel(%d)\n",channel);
3367 return;
3368 }
3369 }
3370
3371 //Check if channel is valid 2.4G Band
3372 if(MAC_Mode != PURE_A_MODE) {
3373 if ((channel > 14 ) || (channel < 1)){ // for the wrong content of the EEPROM
3374 printk(KERN_DEBUG "Error Channel Number in HW_SetRfChannel(11b/g)\n");
3375 return;
3376 }
3377
3378 //prince add begin
3379 // When channnel == 14 , enable Japan spectrum mask
3380 if (pObj->RegionCode == 0x40) { //Japan
3381 if (channel == 14){
3382 HW_Set_FilterBand(pObj, pObj->RegionCode); // for Japan, RegionCode = 0x40
3383 if (pObj->rfMode == RFMD_RF){
3384 LockPhyReg(pObj);
3385 pObj->SetReg(reg, ZD_CR47, 0x1E);
3386 //UnLockPhyReg(pObj);
3387
3388 HW_Set_IF_Synthesizer(pObj, 0x28252d); //External control TX power (CR31_CCK, CR51_6-36M, CR52_48M, CR53_54M
3389 UnLockPhyReg(pObj);
3390 }
3391
3392 }
3393 else{
3394
3395 // For other channels, use default filter.
3396 HW_Set_FilterBand(pObj, 0);
3397
3398 if (pObj->rfMode == RFMD_RF){
3399 // CR47 has been restored in Init_RF_Chips( ), its value is from EEPROM
3400 HW_Set_IF_Synthesizer(pObj, 0x28252d); //External control TX power (CR31_CCK, CR51_6-36M, CR52_48M, CR53_54M
3401 }
3402 }
3403 }
3404 //prince add end
3405
3406 }
3407 else if(MAC_Mode == PURE_A_MODE) {
3408 //Check is the A Band Channel is valid.
3409 for(i=0;i<dot11A_Channel_Amount;i++)
3410 if(dot11A_Channel[i] == channel)
3411 break;
3412 if(i>=dot11A_Channel_Amount) {
3413 printk(KERN_DEBUG "Error Channel Number in HW_SetRfChannel(11a,CH=%d)\n",channel);
3414 return;
3415 }
3416 }
3417 if(PURE_A_MODE == MAC_Mode) {
3418 pObj->SetReg(pObj->reg, ZD_IFS_Value, 0x1147c00a);
3419 pObj->SetReg(pObj->reg, ZD_RTS_CTS_Rate, 0x01090109);
3420 }
3421 else {
3422 pObj->SetReg(pObj->reg, ZD_IFS_Value, 0xa47c032);
3423 pObj->SetReg(pObj->reg, ZD_RTS_CTS_Rate, 0x30000);
3424 }
3425
3426 pObj->Channel = channel;
3427 HW_SwitchChannel(pObj, channel, InitChOnly,MAC_Mode);
3428 LastSetChannel = channel;
3429 LastMacMode = MAC_Mode;
3430
3431 //The UpdateIntegrationValue call should be called immediately
3432 //after HW_SetRfChannel
3433 HW_UpdateIntegrationValue(pObj, channel,MAC_Mode);
3434 /*===prince delete
3435 // When channnel == 14 , enable Japan spectrum mask
3436 if (pObj->RegionCode == 0x40) { //Japan
3437 if (channel == 14){
3438 HW_Set_FilterBand(pObj, pObj->RegionCode); // for Japan, RegionCode = 0x40
3439 if (pObj->rfMode == RFMD_RF){
3440 LockPhyReg(pObj);
3441 pObj->SetReg(reg, ZD_CR47, 0x1E);
3442 //UnLockPhyReg(pObj);
3443
3444 HW_Set_IF_Synthesizer(pObj, 0x28252d); //External control TX power (CR31_CCK, CR51_6-36M, CR52_48M, CR53_54M
3445 UnLockPhyReg(pObj);
3446 }
3447
3448 }
3449 else{
3450
3451 // For other channels, use default filter.
3452 HW_Set_FilterBand(pObj, 0);
3453
3454 if (pObj->rfMode == RFMD_RF){
3455 // CR47 has been restored in Init_RF_Chips( ), its value is from EEPROM
3456 HW_Set_IF_Synthesizer(pObj, 0x28252d); //External control TX power (CR31_CCK, CR51_6-36M, CR52_48M, CR53_54M
3457 }
3458 }
3459 }
3460 ===*/
3461
3462 pObj->DelayUs(100);
3463 }
3464
3465 void HW_SetBeaconFIFO(zd_80211Obj_t *pObj, U8 *pBeacon, U16 index)
3466 {
3467 U32 tmpValue, BCNPlcp;
3468 U16 j;
3469 void *reg = pObj->reg;
3470 U32 count = 1;
3471
3472 pObj->SetReg(reg, ZD_BCN_FIFO_Semaphore, 0x0);
3473 tmpValue = pObj->GetReg(reg, ZD_BCN_FIFO_Semaphore);
3474
3475 while (tmpValue & BIT_1){
3476 pObj->DelayUs(1000);
3477 tmpValue = pObj->GetReg(reg, ZD_BCN_FIFO_Semaphore);
3478
3479 if ((++count % 100) == 0)
3480 printk(KERN_ERR "Get ZD_BCN_FIFO_Semaphore not ready\n");
3481 }
3482
3483 /* Write (Beacon_Len -1) to Beacon-FIFO */
3484 pObj->SetReg(reg, ZD_BCNFIFO, (index - 1));
3485 #ifdef ZD1211B
3486 pObj->SetReg(reg,ZD_BCNLENGTH, (index - 1));
3487 #endif
3488
3489 for (j=0; j<index; j++){
3490 pObj->SetReg(reg, ZD_BCNFIFO, pBeacon[j]);
3491 }
3492 pObj->SetReg(reg, ZD_BCN_FIFO_Semaphore, 1);
3493
3494 /* Configure BCNPLCP */
3495 if(mMacMode == PURE_A_MODE) {
3496 BCNPlcp = 0x0000003b; //802.11a 5g OFDM 6Mb
3497 }
3498 else
3499 {
3500 index = (index << 3); //802.11b/g 2.4G CCK 1Mb
3501 BCNPlcp = 0x00000400;
3502 }
3503 BCNPlcp |= (((U32)index) << 16);
3504 pObj->SetReg(reg, ZD_BCNPLCPCfg, BCNPlcp);
3505 }
3506
3507
3508
3509 void HW_SetSupportedRate(zd_80211Obj_t *pObj, U8 *prates)
3510 {
3511 U8 HighestBasicRate = SR_1M;
3512 U8 HighestRate = SR_1M;
3513 U8 SRate;
3514 U32 tmpValue;
3515 U16 j;
3516 U8 MaxBasicRate;
3517
3518 void *reg = pObj->reg;
3519 MaxBasicRate = pObj->BasicRate;
3520
3521
3522 for (j=0; j<(*(prates+1)); j++){
3523 switch((*(prates+2+j)) & 0x7f){
3524 case SR_1M:
3525 SRate = SR_1M;
3526 #if defined(AMAC)
3527 if ((*(prates+2+j)) & 0x80){ //It's a basic rate
3528
3529 tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
3530 tmpValue |= BIT_0;
3531 pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
3532 }
3533 #endif
3534 break;
3535
3536 case SR_2M:
3537 SRate = SR_2M;
3538 #if defined(AMAC)
3539 if ((*(prates+2+j)) & 0x80){ //It's a basic rate
3540 tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
3541 tmpValue |= BIT_1;
3542 pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
3543 }
3544 #endif
3545 break;
3546
3547 case SR_5_5M:
3548 SRate = SR_5_5M;
3549 #if defined(AMAC)
3550 if ((*(prates+2+j)) & 0x80){ //It's a basic rate
3551 tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
3552
3553 tmpValue |= BIT_2;
3554 pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
3555 }
3556 #endif
3557 break;
3558
3559 case SR_11M:
3560 SRate = SR_11M;
3561 #if defined(AMAC)
3562 if ((*(prates+2+j)) & 0x80){ //It's a basic rate
3563 tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
3564 tmpValue |= BIT_3;
3565 pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
3566 }
3567
3568 #endif
3569 break;
3570
3571 #if (defined(GCCK) && defined(OFDM))
3572 case SR_6M:
3573 SRate = SR_6M;
3574 if ((*(prates+2+j)) & 0x80){ //It's a basic rate
3575 tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
3576 tmpValue |= BIT_8;
3577 pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
3578 }
3579 break;
3580
3581 case SR_9M:
3582 SRate = SR_9M;
3583 if ((*(prates+2+j)) & 0x80){ //It's a basic rate
3584 tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
3585 tmpValue |= BIT_9;
3586 pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
3587 }
3588 break;
3589
3590 case SR_12M:
3591 SRate = SR_12M;
3592 if ((*(prates+2+j)) & 0x80){ //It's a basic rate
3593 tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
3594 tmpValue |= BIT_10;
3595 pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
3596 }
3597 break;
3598
3599 case SR_18M:
3600 SRate = SR_18M;
3601 if ((*(prates+2+j)) & 0x80){ //It's a basic rate
3602 tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
3603 tmpValue |= BIT_11;
3604 pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
3605 }
3606 break;
3607
3608 case SR_24M:
3609 SRate = SR_24M;
3610 if ((*(prates+2+j)) & 0x80){ //It's a basic rate
3611 tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
3612 tmpValue |= BIT_12;
3613 pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
3614 }
3615 break;
3616
3617 case SR_36M:
3618 SRate = SR_36M;
3619 if ((*(prates+2+j)) & 0x80){ //It's a basic rate
3620 tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
3621 tmpValue |= BIT_13;
3622 pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
3623
3624 }
3625 break;
3626
3627 case SR_48M:
3628 SRate = SR_48M;
3629 if ((*(prates+2+j)) & 0x80){ //It's a basic rate
3630 tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
3631 tmpValue |= BIT_14;
3632 pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
3633 }
3634 break;
3635
3636 case SR_54M:
3637 SRate = SR_54M;
3638 if ((*(prates+2+j)) & 0x80){ //It's a basic rate
3639 tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
3640 tmpValue |= BIT_15;
3641 pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
3642 }
3643 break;
3644 #endif
3645
3646 default:
3647 SRate = SR_1M;
3648
3649 break;
3650 }
3651
3652 if (HighestRate < SRate)
3653 HighestRate = SRate;
3654
3655
3656 if ((*(prates+2+j)) & 0x80){
3657 /* It's a basic rate */
3658 if (HighestBasicRate < SRate)
3659 HighestBasicRate = SRate;
3660 }
3661 }
3662
3663 #if !defined(OFDM)
3664 tmpValue = pObj->GetReg(reg, ZD_CtlReg1);
3665
3666 if (pObj->BssType == INDEPENDENT_BSS){
3667 if (HighestBasicRate == SR_1M){
3668 // Workaround compatibility issue.
3669 // For resonable case, HighestBasicRate should larger than 2M if
3670
3671 // short-preamble is supported.
3672 HighestBasicRate = SR_2M;
3673 pObj->SetReg(reg, ZD_Ack_Timeout_Ext, 0x3f);
3674 }
3675 }
3676
3677 switch(HighestBasicRate){
3678 case SR_1M:
3679 tmpValue &= ~0x1c;
3680 tmpValue |= 0x00;
3681 pObj->SetReg(reg, ZD_CtlReg1, tmpValue);
3682 pObj->BasicRate = 0x0;
3683 break;
3684
3685 case SR_2M:
3686 tmpValue &= ~0x1c;
3687 tmpValue |= 0x04;
3688 pObj->SetReg(reg, ZD_CtlReg1, tmpValue);
3689 pObj->BasicRate = 0x1;
3690 break;
3691
3692 case SR_5_5M:
3693 tmpValue &= ~0x1c;
3694
3695 tmpValue |= 0x08;
3696 pObj->SetReg(reg, ZD_CtlReg1, tmpValue);
3697 pObj->BasicRate = 0x2;
3698 break;
3699
3700 case SR_11M:
3701 tmpValue &= ~0x1c;
3702 tmpValue |= 0x0c;
3703 pObj->SetReg(reg, ZD_CtlReg1, tmpValue);
3704 pObj->BasicRate = 0x3;
3705 break;
3706
3707 default:
3708 break;
3709 }
3710 #else
3711 switch(HighestBasicRate){
3712 case SR_1M:
3713 if (HighestBasicRate >= MaxBasicRate)
3714 pObj->BasicRate = 0x0;
3715 break;
3716
3717
3718 case SR_2M:
3719 if (HighestBasicRate >= MaxBasicRate)
3720 pObj->BasicRate = 0x1;
3721 break;
3722
3723 case SR_5_5M:
3724 if (HighestBasicRate >= MaxBasicRate)
3725 pObj->BasicRate = 0x2;
3726 break;
3727
3728 case SR_11M:
3729 if (HighestBasicRate >= MaxBasicRate)
3730 pObj->BasicRate = 0x3;
3731 break;
3732
3733 case SR_6M:
3734 if (HighestBasicRate >= MaxBasicRate)
3735 pObj->BasicRate = 0x4;
3736 break;
3737
3738 case SR_9M:
3739 if (HighestBasicRate >= MaxBasicRate)
3740 pObj->BasicRate = 0x5;
3741 break;
3742
3743 case SR_12M:
3744 if (HighestBasicRate >= MaxBasicRate)
3745 pObj->BasicRate = 0x6;
3746 break;
3747
3748 case SR_18M:
3749 if (HighestBasicRate >= MaxBasicRate)
3750 pObj->BasicRate = 0x7;
3751 break;
3752
3753 case SR_24M:
3754 if (HighestBasicRate >= MaxBasicRate)
3755 pObj->BasicRate = 0x8;
3756 break;
3757
3758 case SR_36M:
3759 if (HighestBasicRate >= MaxBasicRate)
3760 pObj->BasicRate = 0x9;
3761 break;
3762
3763 case SR_48M:
3764 if (HighestBasicRate >= MaxBasicRate)
3765
3766 pObj->BasicRate = 0xa;
3767 break;
3768
3769 case SR_54M:
3770 if (HighestBasicRate >= MaxBasicRate)
3771 pObj->BasicRate = 0xb;
3772 break;
3773
3774 default:
3775
3776 break;
3777 }
3778 #endif
3779
3780 //FPRINT_V("HighestBasicRate", pObj->BasicRate);
3781 }
3782
3783 extern U16 mBeaconPeriod;
3784
3785 void HW_SetSTA_PS(zd_80211Obj_t *pObj, U8 op)
3786 {
3787 void *reg = pObj->reg;
3788 U32 tmpValue;
3789
3790 tmpValue = pObj->GetReg(reg, ZD_BCNInterval);
3791
3792 /* Beacon interval check */
3793 if((tmpValue & 0xffff) != mBeaconPeriod) {
3794 printk(KERN_ERR "Beacon Interval not match\n");
3795 return ;
3796 }
3797
3798 //if (op)
3799 // tmpValue |= STA_PS;
3800 //else
3801 tmpValue &= ~STA_PS;
3802
3803 pObj->SetReg(reg, ZD_BCNInterval, tmpValue);
3804 }
3805
3806
3807 void HW_GetTsf(zd_80211Obj_t *pObj, U32 *loTsf, U32 *hiTsf)
3808 {
3809 void *reg = pObj->reg;
3810
3811
3812 *loTsf = pObj->GetReg(reg, ZD_TSF_LowPart);
3813 *hiTsf = pObj->GetReg(reg, ZD_TSF_HighPart);
3814 }
3815
3816 U32 HW_GetNow(zd_80211Obj_t *pObj)
3817 {
3818 #ifndef HOST_IF_USB
3819 void *reg = pObj->reg;
3820 return pObj->GetReg(reg, ZD_TSF_LowPart); //us unit
3821 #else
3822 return jiffies; //10ms unit
3823 #endif
3824 }
3825
3826 void HW_RadioOnOff(zd_80211Obj_t *pObj, U8 on)
3827 {
3828 void *reg = pObj->reg;
3829 U32 tmpvalue;
3830 U8 ii;
3831
3832
3833 if (on){
3834 //++ Turn on RF
3835 switch(pObj->rfMode){
3836 case RFMD_RF:
3837 if (!(pObj->PhyTest & BIT_2))
3838 HW_Set_IF_Synthesizer(pObj, 0x000007);
3839
3840 if (!(pObj->PhyTest & BIT_0)){
3841 LockPhyReg(pObj);
3842 pObj->SetReg(reg, ZD_CR10, 0x89);
3843
3844 pObj->SetReg(reg, ZD_CR11, 0x00);
3845 tmpvalue = pObj->GetReg(reg, ZD_CR11);
3846 tmpvalue &= 0xFF;
3847 if (tmpvalue != 0x00) {
3848 if (pObj->PhyTest & BIT_1) {
3849 for (ii = 0; ii < 10; ii ++){
3850 pObj->DelayUs(1000);
3851 pObj->SetReg(reg, ZD_CR11, 0x00);
3852 tmpvalue = pObj->GetReg(reg, ZD_CR11);
3853 if ((tmpvalue & 0xFF) == 0x00)
3854 break;
3855 }
3856 }
3857 }
3858
3859 UnLockPhyReg(pObj);
3860 }
3861 break;
3862 case UW2453_RF:
3863 case AL2230_RF:
3864 case AL2230S_RF:
3865 case AL7230B_RF:
3866
3867 if(UW2453_RF == pObj->rfMode)
3868 {
3869 HW_Set_IF_Synthesizer(pObj, 0x025f94);
3870 printk("RadioOn\n");
3871 }
3872
3873 LockPhyReg(pObj);
3874 tmpvalue &= 0xFF;
3875
3876 for (ii = 0; ii < 10; ii ++){
3877 pObj->DelayUs(1000);
3878 pObj->SetReg(reg, ZD_CR11, 0x00);
3879 tmpvalue = pObj->GetReg(reg, ZD_CR11);
3880 if ((tmpvalue & 0xFF) == 0x00)
3881 break;
3882 }
3883 #ifdef ZD1211
3884 pObj->SetReg(reg, ZD_CR251, 0x3f);
3885 #elif defined(ZD1211B)
3886 pObj->SetReg(reg, ZD_CR251, 0x7f);
3887 #else
3888 #error "You do not define ZD1211 Model"
3889 #endif
3890 UnLockPhyReg(pObj);
3891 break;
3892
3893
3894 default:
3895 break;
3896 }
3897 }
3898 else{
3899 //++ Turn off RF
3900 switch(pObj->rfMode){
3901 case RFMD_RF:
3902 if (!(pObj->PhyTest & BIT_0)){
3903 LockPhyReg(pObj);
3904
3905 pObj->SetReg(reg, ZD_CR11, 0x15);
3906 tmpvalue = pObj->GetReg(reg, ZD_CR11);
3907 pObj->SetReg(reg, ZD_CR10, 0x81);
3908 UnLockPhyReg(pObj);
3909 tmpvalue &= 0xFF;
3910 }
3911
3912 if (!(pObj->PhyTest & BIT_2)){
3913 LockPhyReg(pObj);
3914 HW_Set_IF_Synthesizer(pObj, 0x00000F);
3915 UnLockPhyReg(pObj);
3916 }
3917 break;
3918
3919 case UW2453_RF:
3920 case AL2230_RF:
3921 case AL2230S_RF:
3922 case AL7230B_RF:
3923 if(UW2453_RF == pObj->rfMode)
3924 {
3925 HW_Set_IF_Synthesizer(pObj, 0x025f90);
3926 printk("RadioOff\n");
3927 }
3928 LockPhyReg(pObj);
3929 pObj->SetReg(reg, ZD_CR11, 0x04);
3930 pObj->SetReg(reg, ZD_CR251, 0x2f);
3931 UnLockPhyReg(pObj);
3932 break;
3933
3934
3935 default:
3936 break;
3937 }
3938
3939 }
3940
3941 }
3942
3943 #ifdef ZD1211
3944 void HW_ResetPhy(zd_80211Obj_t *pObj)
3945 {
3946 void *reg = pObj->reg;
3947 U32 phyOverwrite;
3948
3949
3950 LockPhyReg(pObj);
3951 #ifdef ZD1211
3952 pObj->SetReg(reg, ZD_CR0, 0x0a);
3953 #elif defined(ZD1211B)
3954 pObj->SetReg(reg, ZD_CR0, 0x14);
3955 #endif
3956
3957 pObj->SetReg(reg, ZD_CR1, 0x06);
3958 pObj->SetReg(reg, ZD_CR2, 0x26);
3959 pObj->SetReg(reg, ZD_CR3, 0x38);
3960 pObj->SetReg(reg, ZD_CR4, 0x80);
3961 pObj->SetReg(reg, ZD_CR9, 0xa0);
3962 pObj->SetReg(reg, ZD_CR10, 0x81);
3963 #if fTX_PWR_CTRL && fTX_GAIN_OFDM
3964 //tmpvalue = pObj->GetReg(reg, ZD_CR11);
3965 //tmpvalue |= BIT_6;
3966 //pObj->SetReg(reg, ZD_CR11, tmpvalue);
3967 pObj->SetReg(reg, ZD_CR11, BIT_6);
3968 #else
3969 pObj->SetReg(reg, ZD_CR11, 0x00);
3970 #endif
3971
3972 pObj->SetReg(reg, ZD_CR12, 0x7f);
3973 pObj->SetReg(reg, ZD_CR13, 0x8c);
3974 pObj->SetReg(reg, ZD_CR14, 0x80);
3975 pObj->SetReg(reg, ZD_CR15, 0x3d);
3976 pObj->SetReg(reg, ZD_CR16, 0x20);
3977 pObj->SetReg(reg, ZD_CR17, 0x1e);
3978 pObj->SetReg(reg, ZD_CR18, 0x0a);
3979 pObj->SetReg(reg, ZD_CR19, 0x48);
3980 pObj->SetReg(reg, ZD_CR20, 0x0c);
3981 #ifdef ZD1211
3982 pObj->SetReg(reg, ZD_CR21, 0x0c);
3983 #elif defined(ZD1211B)
3984 pObj->SetReg(reg, ZD_CR21, 0x0e);
3985 #endif
3986 pObj->SetReg(reg, ZD_CR22, 0x23);
3987 pObj->SetReg(reg, ZD_CR23, 0x90);
3988 pObj->SetReg(reg, ZD_CR24, 0x14);
3989 pObj->SetReg(reg, ZD_CR25, 0x40);
3990 pObj->SetReg(reg, ZD_CR26, 0x10);
3991 pObj->SetReg(reg, ZD_CR27, 0x19);
3992 pObj->SetReg(reg, ZD_CR28, 0x7f);
3993 pObj->SetReg(reg, ZD_CR29, 0x80);
3994
3995 #ifndef ASIC
3996
3997 pObj->SetReg(reg, ZD_CR30, 0x4b);
3998 #else
3999 pObj->SetReg(reg, ZD_CR30, 0x49);
4000 #endif
4001
4002 pObj->SetReg(reg, ZD_CR31, 0x60);
4003 pObj->SetReg(reg, ZD_CR32, 0x43);
4004 pObj->SetReg(reg, ZD_CR33, 0x08);
4005 pObj->SetReg(reg, ZD_CR34, 0x06);
4006 pObj->SetReg(reg, ZD_CR35, 0x0a);
4007 pObj->SetReg(reg, ZD_CR36, 0x00);
4008 pObj->SetReg(reg, ZD_CR37, 0x00);
4009 pObj->SetReg(reg, ZD_CR38, 0x38);
4010 pObj->SetReg(reg, ZD_CR39, 0x0c);
4011 pObj->SetReg(reg, ZD_CR40, 0x84);
4012 pObj->SetReg(reg, ZD_CR41, 0x2a);
4013 pObj->SetReg(reg, ZD_CR42, 0x80);
4014 pObj->SetReg(reg, ZD_CR43, 0x10);
4015 #ifdef ZD1211
4016 pObj->SetReg(reg, ZD_CR44, 0x12);
4017 #elif defined(ZD1211B)
4018 pObj->SetReg(reg, ZD_CR44, 0x33);
4019 #endif
4020
4021 pObj->SetReg(reg, ZD_CR46, 0xff);
4022 #ifdef ZD1211
4023 pObj->SetReg(reg, ZD_CR47, 0x1E);
4024 #elif defined(ZD1211B)
4025 pObj->SetReg(reg, ZD_CR47, 0x1E);
4026 #endif
4027 pObj->SetReg(reg, ZD_CR48, 0x26);
4028 pObj->SetReg(reg, ZD_CR49, 0x5b);
4029
4030
4031 pObj->SetReg(reg, ZD_CR64, 0xd0);
4032 pObj->SetReg(reg, ZD_CR65, 0x04);
4033 pObj->SetReg(reg, ZD_CR66, 0x58);
4034 pObj->SetReg(reg, ZD_CR67, 0xc9);
4035 pObj->SetReg(reg, ZD_CR68, 0x88);
4036 pObj->SetReg(reg, ZD_CR69, 0x41);
4037 pObj->SetReg(reg, ZD_CR70, 0x23);
4038 pObj->SetReg(reg, ZD_CR71, 0x10);
4039 pObj->SetReg(reg, ZD_CR72, 0xff);
4040 pObj->SetReg(reg, ZD_CR73, 0x32);
4041 pObj->SetReg(reg, ZD_CR74, 0x30);
4042 pObj->SetReg(reg, ZD_CR75, 0x65);
4043
4044 pObj->SetReg(reg, ZD_CR76, 0x41);
4045 pObj->SetReg(reg, ZD_CR77, 0x1b);
4046 pObj->SetReg(reg, ZD_CR78, 0x30);
4047 #ifdef ZD1211
4048 pObj->SetReg(reg, ZD_CR79, 0x68);
4049 #elif defined(ZD1211B)
4050 pObj->SetReg(reg, ZD_CR79, 0xf0);
4051 #endif
4052 pObj->SetReg(reg, ZD_CR80, 0x64);
4053 pObj->SetReg(reg, ZD_CR81, 0x64);
4054 pObj->SetReg(reg, ZD_CR82, 0x00);
4055 #ifdef ZD1211
4056 pObj->SetReg(reg, ZD_CR83, 0x00);
4057 pObj->SetReg(reg, ZD_CR84, 0x00);
4058 pObj->SetReg(reg, ZD_CR85, 0x02);
4059 pObj->SetReg(reg, ZD_CR86, 0x00);
4060 pObj->SetReg(reg, ZD_CR87, 0x00);
4061 pObj->SetReg(reg, ZD_CR88, 0xff);
4062 pObj->SetReg(reg, ZD_CR89, 0xfc);
4063 pObj->SetReg(reg, ZD_CR90, 0x00);
4064 pObj->SetReg(reg, ZD_CR91, 0x00);
4065 #elif defined(ZD1211B)
4066 pObj->SetReg(reg, ZD_CR83, 0x24);
4067 pObj->SetReg(reg, ZD_CR84, 0x04);
4068 pObj->SetReg(reg, ZD_CR85, 0x00);
4069 pObj->SetReg(reg, ZD_CR86, 0x0c);
4070 pObj->SetReg(reg, ZD_CR87, 0x12);
4071 pObj->SetReg(reg, ZD_CR88, 0x0c);
4072 pObj->SetReg(reg, ZD_CR89, 0x00);
4073 pObj->SetReg(reg, ZD_CR90, 0x58);
4074 pObj->SetReg(reg, ZD_CR91, 0x04);
4075 #endif
4076
4077
4078 pObj->SetReg(reg, ZD_CR92, 0x00);
4079 pObj->SetReg(reg, ZD_CR93, 0x08);
4080 pObj->SetReg(reg, ZD_CR94, 0x00);
4081 #ifdef ZD1211
4082 pObj->SetReg(reg, ZD_CR95, 0x00);
4083 #elif defined(ZD1211B)
4084 pObj->SetReg(reg, ZD_CR95, 0x20);
4085 #endif
4086 pObj->SetReg(reg, ZD_CR96, 0xff);
4087 pObj->SetReg(reg, ZD_CR97, 0xe7);
4088 #ifdef ZD1211
4089 pObj->SetReg(reg, ZD_CR98, 0x00);
4090 #elif defined(ZD1211B)
4091 pObj->SetReg(reg, ZD_CR98, 0x35);
4092 #endif
4093 pObj->SetReg(reg, ZD_CR99, 0x00);
4094 pObj->SetReg(reg, ZD_CR100, 0x00);
4095 pObj->SetReg(reg, ZD_CR101, 0xae);
4096 pObj->SetReg(reg, ZD_CR102, 0x02);
4097 pObj->SetReg(reg, ZD_CR103, 0x00);
4098 pObj->SetReg(reg, ZD_CR104, 0x03);
4099 pObj->SetReg(reg, ZD_CR105, 0x65);
4100 pObj->SetReg(reg, ZD_CR106, 0x04);
4101 pObj->SetReg(reg, ZD_CR107, 0x00);
4102 pObj->SetReg(reg, ZD_CR108, 0x0a);
4103 #ifdef ZD1211
4104 pObj->SetReg(reg, ZD_CR109, 0xaa);
4105 pObj->SetReg(reg, ZD_CR110, 0xaa);
4106 pObj->SetReg(reg, ZD_CR111, 0x25);
4107 pObj->SetReg(reg, ZD_CR112, 0x25);
4108 pObj->SetReg(reg, ZD_CR113, 0x00);
4109
4110 pObj->SetReg(reg, ZD_CR119, 0x1e);
4111
4112 pObj->SetReg(reg, ZD_CR125, 0x90);
4113 pObj->SetReg(reg, ZD_CR126, 0x00);
4114 pObj->SetReg(reg, ZD_CR127, 0x00);
4115 #elif defined(ZD1211B)
4116 pObj->SetReg(reg,ZD_CR109, 0x27);
4117 pObj->SetReg(reg,ZD_CR110, 0x27);
4118 pObj->SetReg(reg,ZD_CR111, 0x27);
4119 pObj->SetReg(reg,ZD_CR112, 0x27);
4120 pObj->SetReg(reg,ZD_CR113, 0x27);
4121 pObj->SetReg(reg,ZD_CR114, 0x27);
4122 pObj->SetReg(reg,ZD_CR115, 0x26);
4123 pObj->SetReg(reg,ZD_CR116, 0x24);
4124 pObj->SetReg(reg,ZD_CR117, 0xfc);
4125 pObj->SetReg(reg,ZD_CR118, 0xfa);
4126 pObj->SetReg(reg,ZD_CR119, 0x1e);
4127 pObj->SetReg(reg,ZD_CR125, 0x90);
4128 pObj->SetReg(reg,ZD_CR126, 0x00);
4129 pObj->SetReg(reg,ZD_CR127, 0x00);
4130 pObj->SetReg(reg,ZD_CR128, 0x14);
4131 pObj->SetReg(reg,ZD_CR129, 0x12);
4132 pObj->SetReg(reg,ZD_CR130, 0x10);
4133 pObj->SetReg(reg,ZD_CR131, 0x0c);
4134 pObj->SetReg(reg,ZD_CR136, 0xdf);
4135 pObj->SetReg(reg,ZD_CR137, 0xa0);
4136 pObj->SetReg(reg,ZD_CR138, 0xa8);
4137 pObj->SetReg(reg,ZD_CR139, 0xb4);
4138 #endif
4139
4140
4141 #if (defined(GCCK) && defined(OFDM))
4142 #ifdef ZD1211
4143 pObj->SetReg(reg, ZD_CR5, 0x00);
4144 pObj->SetReg(reg, ZD_CR6, 0x00);
4145 pObj->SetReg(reg, ZD_CR7, 0x00);
4146 pObj->SetReg(reg, ZD_CR8, 0x00);
4147 #endif
4148 pObj->SetReg(reg, ZD_CR9, 0x20);
4149 pObj->SetReg(reg, ZD_CR12, 0xf0);
4150 pObj->SetReg(reg, ZD_CR20, 0x0e);
4151 pObj->SetReg(reg, ZD_CR21, 0x0e);
4152 pObj->SetReg(reg, ZD_CR27, 0x10);
4153 #ifdef HOST_IF_USB
4154 pObj->SetReg(reg, ZD_CR44, 0x33);
4155 #else
4156 pObj->SetReg(reg, ZD_CR44, 0x33);
4157 #endif
4158 pObj->SetReg(reg, ZD_CR47, 0x1E);
4159 pObj->SetReg(reg, ZD_CR83, 0x24);
4160 pObj->SetReg(reg, ZD_CR84, 0x04);
4161 pObj->SetReg(reg, ZD_CR85, 0x00);
4162 pObj->SetReg(reg, ZD_CR86, 0x0C);
4163 pObj->SetReg(reg, ZD_CR87, 0x12);
4164 pObj->SetReg(reg, ZD_CR88, 0x0C);
4165 pObj->SetReg(reg, ZD_CR89, 0x00);
4166 pObj->SetReg(reg, ZD_CR90, 0x10);
4167 pObj->SetReg(reg, ZD_CR91, 0x08);
4168 pObj->SetReg(reg, ZD_CR93, 0x00);
4169
4170 pObj->SetReg(reg, ZD_CR94, 0x01);
4171 #ifdef HOST_IF_USB
4172 pObj->SetReg(reg, ZD_CR95, 0x0);
4173 #else
4174
4175 pObj->SetReg(reg, ZD_CR95, 0x20); //3d24
4176
4177
4178 #endif
4179 pObj->SetReg(reg, ZD_CR96, 0x50);
4180 pObj->SetReg(reg, ZD_CR97, 0x37);
4181 #ifdef HOST_IF_USB
4182 pObj->SetReg(reg, ZD_CR98, 0x35);
4183 #else
4184 pObj->SetReg(reg, ZD_CR98, 0x8d); //4326
4185 #endif
4186 pObj->SetReg(reg, ZD_CR101, 0x13);
4187 pObj->SetReg(reg, ZD_CR102, 0x27);
4188 pObj->SetReg(reg, ZD_CR103, 0x27);
4189 pObj->SetReg(reg, ZD_CR104, 0x18);
4190 pObj->SetReg(reg, ZD_CR105, 0x12);
4191 pObj->SetReg(reg, ZD_CR109, 0x27);
4192 pObj->SetReg(reg, ZD_CR110, 0x27);
4193 pObj->SetReg(reg, ZD_CR111, 0x27);
4194 pObj->SetReg(reg, ZD_CR112, 0x27);
4195 pObj->SetReg(reg, ZD_CR113, 0x27);
4196 pObj->SetReg(reg, ZD_CR114, 0x27);
4197
4198 pObj->SetReg(reg, ZD_CR115, 0x26);
4199 pObj->SetReg(reg, ZD_CR116, 0x24);
4200
4201 pObj->SetReg(reg, ZD_CR117, 0xfc);
4202 pObj->SetReg(reg, ZD_CR118, 0xfa);
4203 pObj->SetReg(reg, ZD_CR120, 0x4f); //3d24
4204 #ifndef HOST_IF_USB
4205 pObj->SetReg(reg, ZD_CR123, 0x27); //3d24
4206 #endif
4207 pObj->SetReg(reg, ZD_CR125, 0xaa); //4326
4208 pObj->SetReg(reg, ZD_CR127, 0x03); //4326
4209 pObj->SetReg(reg, ZD_CR128, 0x14);
4210 pObj->SetReg(reg, ZD_CR129, 0x12);
4211 pObj->SetReg(reg, ZD_CR130, 0x10);
4212 pObj->SetReg(reg, ZD_CR131, 0x0C);
4213 pObj->SetReg(reg, ZD_CR136, 0xdf);
4214 pObj->SetReg(reg, ZD_CR137, 0x40);
4215 pObj->SetReg(reg, ZD_CR138, 0xa0);
4216 pObj->SetReg(reg, ZD_CR139, 0xb0);
4217 #ifdef ZD1211
4218 pObj->SetReg(reg, ZD_CR140, 0x99);
4219 #elif defined(ZD1211B)
4220 pObj->SetReg(reg, ZD_CR140, 0x98); //4407
4221 #endif
4222 pObj->SetReg(reg, ZD_CR141, 0x82);
4223 #ifdef ZD1211
4224 pObj->SetReg(reg, ZD_CR142, 0x54);
4225 #elif defined(ZD1211B)
4226 pObj->SetReg(reg, ZD_CR142, 0x53); //4407
4227 #endif
4228 pObj->SetReg(reg, ZD_CR143, 0x1c);
4229 pObj->SetReg(reg, ZD_CR144, 0x6c);
4230 pObj->SetReg(reg, ZD_CR147, 0x07);
4231 pObj->SetReg(reg, ZD_CR148, 0x4c);
4232 pObj->SetReg(reg, ZD_CR149, 0x50);
4233 pObj->SetReg(reg, ZD_CR150, 0x0e);
4234 pObj->SetReg(reg, ZD_CR151, 0x18);
4235 #ifdef ZD1211B
4236 pObj->SetReg(reg, ZD_CR159, 0x70); //3d24
4237 #endif
4238 pObj->SetReg(reg, ZD_CR160, 0xfe);
4239 pObj->SetReg(reg, ZD_CR161, 0xee);
4240 pObj->SetReg(reg, ZD_CR162, 0xaa);
4241 pObj->SetReg(reg, ZD_CR163, 0xfa);
4242 pObj->SetReg(reg, ZD_CR164, 0xfa);
4243
4244 pObj->SetReg(reg, ZD_CR165, 0xea);
4245 pObj->SetReg(reg, ZD_CR166, 0xbe);
4246 pObj->SetReg(reg, ZD_CR167, 0xbe);
4247 pObj->SetReg(reg, ZD_CR168, 0x6a);
4248 pObj->SetReg(reg, ZD_CR169, 0xba);
4249 pObj->SetReg(reg, ZD_CR170, 0xba);
4250 pObj->SetReg(reg, ZD_CR171, 0xba);
4251 // Note: CR204 must lead the CR203
4252 pObj->SetReg(reg, ZD_CR204, 0x7d);
4253 pObj->SetReg(reg, ZD_CR203, 0x30);
4254 #ifndef HOST_IF_USB
4255 pObj->SetReg(reg, ZD_CR240, 0x80);
4256 #endif
4257
4258 #endif
4259 //if (pObj->ChipVer == ZD_1211)
4260 {
4261 if (pObj->HWFeature & BIT_13) //6321 Bin 4 Tx IQ balance for ZD1212 only
4262 {
4263 phyOverwrite = pObj->GetReg(reg, E2P_PHY_REG);
4264 pObj->SetReg(reg, ZD_CR157, ((phyOverwrite >> 8) & 0xff)); //make sure no one will overwrite CR157 again
4265 }
4266 }
4267
4268
4269
4270 UnLockPhyReg(pObj);
4271 return;
4272 }
4273 #elif defined(ZD1211B)
4274 void HW_ResetPhy(zd_80211Obj_t *pObj)
4275 {
4276 void *reg = pObj->reg;
4277 u32 tmpvalue;
4278
4279 // Get Phy-Config permission
4280 LockPhyReg(pObj);
4281
4282 pObj->SetReg(reg,ZD_CR0, 0x14);
4283 pObj->SetReg(reg,ZD_CR1, 0x06);
4284 pObj->SetReg(reg,ZD_CR2, 0x26);
4285 pObj->SetReg(reg,ZD_CR3, 0x38);
4286 pObj->SetReg(reg,ZD_CR4, 0x80);
4287 pObj->SetReg(reg,ZD_CR9, 0xe0);
4288 pObj->SetReg(reg,ZD_CR10, 0x81);
4289 //``JWEI 2003/12/26
4290 #if fTX_PWR_CTRL && fTX_GAIN_OFDM
4291 pObj->SetReg(reg, ZD_CR11, BIT_6);
4292 #else
4293 pObj->SetReg(reg,ZD_CR11, 0x00);
4294 #endif
4295 pObj->SetReg(reg,ZD_CR12, 0xf0);
4296 pObj->SetReg(reg,ZD_CR13, 0x8c);
4297 pObj->SetReg(reg,ZD_CR14, 0x80);
4298 pObj->SetReg(reg,ZD_CR15, 0x3d);
4299 pObj->SetReg(reg,ZD_CR16, 0x20);
4300 pObj->SetReg(reg,ZD_CR17, 0x1e);
4301 pObj->SetReg(reg,ZD_CR18, 0x0a);
4302 pObj->SetReg(reg,ZD_CR19, 0x48);
4303 pObj->SetReg(reg,ZD_CR20, 0x10);//Org:0x0E,ComTrend:RalLink AP
4304 pObj->SetReg(reg,ZD_CR21, 0x0e);
4305 pObj->SetReg(reg,ZD_CR22, 0x23);
4306 pObj->SetReg(reg,ZD_CR23, 0x90);
4307 pObj->SetReg(reg,ZD_CR24, 0x14);
4308 pObj->SetReg(reg,ZD_CR25, 0x40);
4309 pObj->SetReg(reg,ZD_CR26, 0x10);
4310 pObj->SetReg(reg,ZD_CR27, 0x10);
4311 pObj->SetReg(reg,ZD_CR28, 0x7f);
4312 pObj->SetReg(reg,ZD_CR29, 0x80);
4313 #ifndef ASIC
4314 // For FWT
4315 pObj->SetReg(reg,ZD_CR30, 0x4b);
4316 #else
4317 // For Jointly decoder
4318 pObj->SetReg(reg,ZD_CR30, 0x49);
4319 #endif
4320 pObj->SetReg(reg,ZD_CR31, 0x60);
4321 pObj->SetReg(reg,ZD_CR32, 0x43);
4322 pObj->SetReg(reg,ZD_CR33, 0x08);
4323 pObj->SetReg(reg,ZD_CR34, 0x06);
4324 pObj->SetReg(reg,ZD_CR35, 0x0a);
4325 pObj->SetReg(reg,ZD_CR36, 0x00);
4326 pObj->SetReg(reg,ZD_CR37, 0x00);
4327 pObj->SetReg(reg,ZD_CR38, 0x38);
4328 pObj->SetReg(reg,ZD_CR39, 0x0c);
4329 pObj->SetReg(reg,ZD_CR40, 0x84);
4330 pObj->SetReg(reg,ZD_CR41, 0x2a);
4331 pObj->SetReg(reg,ZD_CR42, 0x80);
4332 pObj->SetReg(reg,ZD_CR43, 0x10);
4333 pObj->SetReg(reg,ZD_CR44, 0x33);
4334 pObj->SetReg(reg,ZD_CR46, 0xff);
4335 pObj->SetReg(reg,ZD_CR47, 0x1E);
4336 pObj->SetReg(reg,ZD_CR48, 0x26);
4337 pObj->SetReg(reg,ZD_CR49, 0x5b);
4338 pObj->SetReg(reg,ZD_CR64, 0xd0);
4339 pObj->SetReg(reg,ZD_CR65, 0x04);
4340 pObj->SetReg(reg,ZD_CR66, 0x58);
4341 pObj->SetReg(reg,ZD_CR67, 0xc9);
4342 pObj->SetReg(reg,ZD_CR68, 0x88);
4343 pObj->SetReg(reg,ZD_CR69, 0x41);
4344 pObj->SetReg(reg,ZD_CR70, 0x23);
4345 pObj->SetReg(reg,ZD_CR71, 0x10);
4346 pObj->SetReg(reg,ZD_CR72, 0xff);
4347 pObj->SetReg(reg,ZD_CR73, 0x32);
4348 pObj->SetReg(reg,ZD_CR74, 0x30);
4349 pObj->SetReg(reg,ZD_CR75, 0x65);
4350 pObj->SetReg(reg,ZD_CR76, 0x41);
4351 pObj->SetReg(reg,ZD_CR77, 0x1b);
4352 pObj->SetReg(reg,ZD_CR78, 0x30);
4353 pObj->SetReg(reg,ZD_CR79, 0xf0);
4354 pObj->SetReg(reg,ZD_CR80, 0x64);
4355 pObj->SetReg(reg,ZD_CR81, 0x64);
4356 pObj->SetReg(reg,ZD_CR82, 0x00);
4357 pObj->SetReg(reg,ZD_CR83, 0x24);
4358 pObj->SetReg(reg,ZD_CR84, 0x04);
4359 pObj->SetReg(reg,ZD_CR85, 0x00);
4360 pObj->SetReg(reg,ZD_CR86, 0x0c);
4361 pObj->SetReg(reg,ZD_CR87, 0x12);
4362 pObj->SetReg(reg,ZD_CR88, 0x0c);
4363 pObj->SetReg(reg,ZD_CR89, 0x00);
4364 pObj->SetReg(reg,ZD_CR90, 0x58);
4365 pObj->SetReg(reg,ZD_CR91, 0x04);
4366 pObj->SetReg(reg,ZD_CR92, 0x00);
4367 pObj->SetReg(reg,ZD_CR93, 0x00);
4368 pObj->SetReg(reg,ZD_CR94, 0x01);
4369 pObj->SetReg(reg,ZD_CR95, 0x20); // ZD1211B
4370 pObj->SetReg(reg,ZD_CR96, 0x50);
4371 pObj->SetReg(reg,ZD_CR97, 0x37);
4372 pObj->SetReg(reg,ZD_CR98, 0x35);
4373 pObj->SetReg(reg,ZD_CR99, 0x00);
4374 pObj->SetReg(reg,ZD_CR100, 0x01);
4375 pObj->SetReg(reg,ZD_CR101, 0x13);
4376 pObj->SetReg(reg,ZD_CR102, 0x27);
4377 pObj->SetReg(reg,ZD_CR103, 0x27);
4378 pObj->SetReg(reg,ZD_CR104, 0x18);
4379 pObj->SetReg(reg,ZD_CR105, 0x12);
4380 pObj->SetReg(reg,ZD_CR106, 0x04);
4381 pObj->SetReg(reg,ZD_CR107, 0x00);
4382 pObj->SetReg(reg,ZD_CR108, 0x0a);
4383 pObj->SetReg(reg,ZD_CR109, 0x27);
4384 pObj->SetReg(reg,ZD_CR110, 0x27);
4385 pObj->SetReg(reg,ZD_CR111, 0x27);
4386 pObj->SetReg(reg,ZD_CR112, 0x27);
4387 pObj->SetReg(reg,ZD_CR113, 0x27);
4388 pObj->SetReg(reg,ZD_CR114, 0x27);
4389 pObj->SetReg(reg,ZD_CR115, 0x26);
4390 pObj->SetReg(reg,ZD_CR116, 0x24);
4391 pObj->SetReg(reg,ZD_CR117, 0xfc);
4392 pObj->SetReg(reg,ZD_CR118, 0xfa);
4393 pObj->SetReg(reg,ZD_CR119, 0x1e);
4394 pObj->SetReg(reg,ZD_CR125, 0x90);
4395 pObj->SetReg(reg,ZD_CR126, 0x00);
4396 pObj->SetReg(reg,ZD_CR127, 0x00);
4397 pObj->SetReg(reg,ZD_CR128, 0x14);
4398 pObj->SetReg(reg,ZD_CR129, 0x12);
4399 pObj->SetReg(reg,ZD_CR130, 0x10);
4400 pObj->SetReg(reg,ZD_CR131, 0x0c);
4401 pObj->SetReg(reg,ZD_CR136, 0xdf);
4402 pObj->SetReg(reg,ZD_CR137, 0xa0);
4403 pObj->SetReg(reg,ZD_CR138, 0xa8);
4404 pObj->SetReg(reg,ZD_CR139, 0xb4);
4405 pObj->SetReg(reg,ZD_CR140, 0x98);
4406 pObj->SetReg(reg,ZD_CR141, 0x82);
4407 pObj->SetReg(reg,ZD_CR142, 0x53);
4408 pObj->SetReg(reg,ZD_CR143, 0x1c);
4409 pObj->SetReg(reg,ZD_CR144, 0x6c);
4410 pObj->SetReg(reg,ZD_CR147, 0x07);
4411 pObj->SetReg(reg,ZD_CR148, 0x40);
4412 pObj->SetReg(reg,ZD_CR149, 0x40); // Org:0x50 //ComTrend:RalLink AP
4413 pObj->SetReg(reg,ZD_CR150, 0x14);//Org:0x0E //ComTrend:RalLink AP
4414 pObj->SetReg(reg,ZD_CR151, 0x18);
4415 pObj->SetReg(reg,ZD_CR159, 0x70);
4416 pObj->SetReg(reg,ZD_CR160, 0xfe);
4417 pObj->SetReg(reg,ZD_CR161, 0xee);
4418 pObj->SetReg(reg,ZD_CR162, 0xaa);
4419 pObj->SetReg(reg,ZD_CR163, 0xfa);
4420 pObj->SetReg(reg,ZD_CR164, 0xfa);
4421 pObj->SetReg(reg,ZD_CR165, 0xea);
4422 pObj->SetReg(reg,ZD_CR166, 0xbe);
4423 pObj->SetReg(reg,ZD_CR167, 0xbe);
4424 pObj->SetReg(reg,ZD_CR168, 0x6a);
4425 pObj->SetReg(reg,ZD_CR169, 0xba);
4426 pObj->SetReg(reg,ZD_CR170, 0xba);
4427 pObj->SetReg(reg,ZD_CR171, 0xba);
4428 // Note: CR204 must lead the CR203
4429 pObj->SetReg(reg,ZD_CR204, 0x7d);
4430 pObj->SetReg(reg,ZD_CR203, 0x30);
4431
4432 // Release Phy-Config permission
4433 // if (pObj->ChipVer == ZD_1211)
4434 // {
4435 // if (pObj->HWFeature & BIT_13) //6321 Bin 4 Tx IQ balance for ZD1212 only
4436 // {
4437 // phyOverwrite = pObj->GetReg(reg, E2P_PHY_REG);
4438 // pObj->SetReg(reg, ZD_CR157, ((phyOverwrite >> 8) & 0xff)); //make sure no one will overwrite CR157 again
4439 // }
4440 // }
4441
4442 UnLockPhyReg(pObj);
4443
4444
4445 return;
4446 }
4447
4448 #endif
4449
4450 void HW_InitHMAC(zd_80211Obj_t *pObj)
4451 {
4452 void *reg = pObj->reg;
4453
4454 // Set GPI_EN be zero. ie. Disable GPI (Requested by Ahu)
4455 //pObj->SetReg(reg, ZD_GPI_EN, 0x00);
4456
4457 // Use Ack_Timeout_Ext to tolerance some peers that response slowly.
4458 // The influence is that the retry frame will be less competitive. It's acceptable.
4459 pObj->SetReg(reg, ZD_Ack_Timeout_Ext, 0x20); //only bit0-bit5 are valid
4460
4461 pObj->SetReg(reg, ZD_ADDA_MBIAS_WarmTime, 0x30000808);
4462
4463 /* Set RetryMax 8 */
4464 #ifdef ZD1211
4465 pObj->SetReg(reg, ZD_RetryMAX, 0x2);
4466 #elif defined(ZD1211B)
4467 pObj->SetReg(reg, ZD_RetryMAX, 0x02020202);
4468
4469 pObj->SetReg(reg,0xB0C,0x007f003f);
4470 pObj->SetReg(reg,0xB08,0x007f003f);
4471 pObj->SetReg(reg,0xB04,0x003f001f);
4472 pObj->SetReg(reg,0xB00,0x001f000f);
4473 //set AIFS AC0 - AC3
4474 pObj->SetReg(reg,0xB10,0x00280028);
4475 pObj->SetReg(reg,0xB14,0x008C003C);
4476 //set TXOP AC0 - AC3
4477 pObj->SetReg(reg,0xB20,0x01800824);
4478 //pObj->SetReg(reg,0xB20,0x00800a28);
4479
4480 #endif
4481
4482 /* Turn off sniffer mode */
4483 pObj->SetReg(reg, ZD_SnifferOn, 0);
4484
4485 /* Set Rx filter*/
4486 // filter Beacon and unfilter PS-Poll
4487 pObj->SetReg(reg, ZD_Rx_Filter, AP_RX_FILTER);
4488
4489 /* Set Hashing table */
4490 pObj->SetReg(reg, ZD_GroupHash_P1, 0x00);
4491 pObj->SetReg(reg, ZD_GroupHash_P2, 0x80000000);
4492
4493 pObj->SetReg(reg, ZD_CtlReg1, 0xa4);
4494 pObj->SetReg(reg, ZD_ADDA_PwrDwn_Ctrl, 0x7f);
4495
4496 /* Initialize BCNATIM needed registers */
4497 pObj->SetReg(reg, ZD_BCNPLCPCfg, 0x00f00401);
4498 pObj->SetReg(reg, ZD_PHYDelay, 0x00);
4499
4500 #if defined(OFDM)
4501 #ifdef HOST_IF_USB
4502 pObj->SetReg(reg, ZD_Ack_Timeout_Ext, 0x80);
4503 pObj->SetReg(reg, ZD_ADDA_PwrDwn_Ctrl, 0x0);
4504 #endif
4505
4506 //pObj->SetReg(reg, ZD_AckTime80211, 0x102);
4507 pObj->SetReg(reg, ZD_AckTime80211, 0x100);
4508 pObj->SetReg(reg, ZD_IFS_Value, 0x547c032); //0x547c032
4509
4510 // accept beacon for enable protection mode
4511
4512 //pObj->SetReg(reg, ZD_Rx_Filter, ((BIT_10 << 16) | (0xffff)));
4513 //pObj->SetReg(reg, ZD_Rx_Filter, ((BIT_10 << 16) | (0xffff & ~BIT_8))); //for pure G debug
4514
4515 // Set RX_PE_DELAY 0x10 to enlarge the time for decharging tx power.
4516 pObj->SetReg(reg, ZD_RX_PE_DELAY, 0x70);
4517
4518 //pObj->SetReg(reg, ZD_SnifferOn, 0x3000000); //enable HW Rx Retry filter, and HW MIC
4519 //pObj->SetReg(reg, ZD_Rx_OFFSET, 0x03); //to fit MIC engine's 4 byte alignment
4520
4521 // Keep 44MHz oscillator always on.
4522 pObj->SetReg(reg, ZD_PS_Ctrl, 0x10000000);
4523 #endif
4524
4525
4526 #if defined(AMAC)
4527 #if defined(ECCK_60_5)
4528 pObj->SetReg(reg, ZD_RTS_CTS_Rate, 0x00);
4529 #elif (defined(GCCK) && defined(OFDM))
4530 //pObj->SetReg(reg, ZD_RTS_CTS_Rate, 0x30000);
4531 pObj->SetReg(reg, ZD_RTS_CTS_Rate, 0x2030203);
4532 #endif
4533
4534 // Set Rx Threshold
4535 #ifdef ZD1211B
4536 pObj->SetReg(reg, ZD_RX_THRESHOLD, 0x000c0eff);
4537 #else
4538 pObj->SetReg(reg, ZD_RX_THRESHOLD, 0x000c0640);
4539 #endif
4540
4541 // Set Tx-Pwr-Control registers
4542 //pObj->SetReg(reg, ZD_TX_PWR_CTRL_1, 0x7f7f7f7f);
4543 //pObj->SetReg(reg, ZD_TX_PWR_CTRL_2, 0x7c7f7f7f);
4544 //pObj->SetReg(reg, ZD_TX_PWR_CTRL_3, 0x6c6c747c);
4545 //pObj->SetReg(reg, ZD_TX_PWR_CTRL_4, 0x00006064);
4546
4547 #ifdef HOST_IF_USB
4548 pObj->SetReg(reg, ZD_AfterPNP, 0x1);
4549 pObj->SetReg(reg, ZD_Wep_Protect, 0x114);
4550 #else
4551 pObj->SetReg(reg, ZD_AfterPNP, 0x64009);
4552 pObj->SetReg(reg, ZD_Wep_Protect, 0x118); //4315 for TKIP key mixing
4553 #endif
4554 #endif
4555 }
4556
4557 void HW_OverWritePhyRegFromE2P(zd_80211Obj_t *pObj)
4558 {
4559 U32 tmpvalue;
4560 void *reg = pObj->reg;
4561
4562 #ifdef HOST_IF_USB
4563 if (!pObj->bOverWritePhyRegFromE2P)
4564 return;
4565
4566 LockPhyReg(pObj);
4567 tmpvalue = pObj->GetReg(reg, E2P_PHY_REG);
4568 pObj->SetReg(reg, ZD_CR47, (tmpvalue & 0xFF));
4569 UnLockPhyReg(pObj);
4570 return;
4571 #endif
4572 }
4573
4574 void HW_WritePhyReg(zd_80211Obj_t *pObj, U8 PhyIdx, U8 PhyValue)
4575 {
4576 U32 IoAddress;
4577 void *reg = pObj->reg;
4578
4579 switch(PhyIdx){
4580 case 4:
4581 IoAddress = 0x20;
4582 break;
4583
4584 case 5:
4585 IoAddress = 0x10;
4586 break;
4587
4588 case 6:
4589 IoAddress = 0x14;
4590 break;
4591
4592 case 7:
4593 IoAddress = 0x18;
4594 break;
4595
4596 case 8:
4597 IoAddress = 0x1C;
4598 break;
4599
4600 default:
4601 IoAddress = (((U32)PhyIdx) << 2);
4602
4603 break;
4604 }
4605
4606 LockPhyReg(pObj);
4607 pObj->SetReg(reg, IoAddress, PhyValue);
4608 UnLockPhyReg(pObj);
4609 }
4610
4611
4612 void HW_UpdateIntegrationValue(zd_80211Obj_t *pObj, U32 ChannelNo, const U8 MAC_Mode)
4613 {
4614 void *reg = pObj->reg;
4615 struct zd1205_private *macp = (struct zd1205_private *) g_dev->priv;
4616 U32 tmpvalue;
4617 u8 Useless_set, intV;
4618
4619 if(macp->RF_Mode == UW2453_RF)
4620 return;
4621 #ifdef HOST_IF_USB
4622
4623 //tmpvalue = pObj->GetReg(reg, ZD_E2P_PWR_INT_VALUE1+((ChannelNo-1) & 0xc));
4624 //tmpvalue = (U8) (tmpvalue >> (((ChannelNo - 1) % 4) * 8));
4625 if(PURE_A_MODE != MAC_Mode)
4626 tmpvalue = pObj->IntValue[ChannelNo - 1];
4627 else if(PURE_A_MODE == MAC_Mode) {
4628 a_OSC_get_cal_int(ChannelNo, RATE_54M,&intV,&Useless_set);
4629 tmpvalue = intV;
4630 }
4631 else
4632 VerAssert("NULL");
4633 HW_Write_TxGain1(pObj, (U8) tmpvalue, cTX_CCK);
4634 #endif
4635 #ifdef ZD1211B
4636 LockPhyReg(pObj);
4637 if(PURE_A_MODE != MAC_Mode) {
4638 pObj->SetReg(reg,ZD_CR65,macp->SetPointOFDM[2][ChannelNo-1]);
4639 pObj->SetReg(reg,ZD_CR66,macp->SetPointOFDM[1][ChannelNo-1]);
4640 pObj->SetReg(reg,ZD_CR67,macp->SetPointOFDM[0][ChannelNo-1]);
4641 pObj->SetReg(reg,ZD_CR68,macp->EepSetPoint[ChannelNo-1]);
4642 }
4643 else {
4644 u8 set36,set48,set54, intValue;
4645 a_OSC_get_cal_int( ChannelNo, RATE_54M, &intValue, &set54);
4646 a_OSC_get_cal_int( ChannelNo, RATE_48M, &intValue, &set48);
4647 a_OSC_get_cal_int( ChannelNo, RATE_36M, &intValue, &set36);
4648 pObj->SetReg(reg,ZD_CR65,set54);
4649 pObj->SetReg(reg,ZD_CR66,set48);
4650 pObj->SetReg(reg,ZD_CR67,set36);
4651 pObj->SetReg(reg,ZD_CR68,macp->EepSetPoint[ChannelNo-1]);
4652 }
4653
4654 pObj->SetReg(reg,ZD_CR69,0x28);
4655 pObj->SetReg(reg,ZD_CR69,0x2a);
4656
4657 UnLockPhyReg(pObj);
4658 #endif
4659 }
4660
4661 void HW_Write_TxGain(zd_80211Obj_t *pObj, U32 txgain)
4662 {
4663 U32 tmpvalue;
4664 void *reg = pObj->reg;
4665 U8 i;
4666
4667 switch(pObj->rfMode){
4668 /*
4669 case GCT_RF:
4670 txgain &= 0x3f;
4671
4672 //FPRINT_V("Set tx gain", txgain);
4673 tmpvalue = 0;
4674 // Perform Bit-Reverse
4675 for (i=0; i<6; i++){
4676 if (txgain & BIT_0){
4677 tmpvalue |= (0x1 << (15-i));
4678 }
4679 txgain = (txgain >> 1);
4680 }
4681 tmpvalue |= 0x0c0000;
4682 HW_Set_IF_Synthesizer(pObj, tmpvalue);
4683 //FPRINT_V("HW_Set_IF_Synthesizer", tmpvalue);
4684 HW_Set_IF_Synthesizer(pObj, 0x150800);
4685 HW_Set_IF_Synthesizer(pObj, 0x150000);
4686 break;
4687 */
4688
4689 case AL2210_RF:
4690 case AL2210MPVB_RF:
4691 if (txgain > AL2210_MAX_TX_PWR_SET){
4692 txgain = AL2210_MAX_TX_PWR_SET;
4693 }
4694 else if (txgain < AL2210_MIN_TX_PWR_SET){
4695 txgain = AL2210_MIN_TX_PWR_SET;
4696 }
4697
4698 LockPhyReg(pObj);
4699 pObj->SetReg(reg, ZD_CR31, (U8)txgain);
4700 UnLockPhyReg(pObj);
4701 break;
4702
4703 default:
4704 break;
4705 }
4706 }
4707
4708
4709 void HW_Write_TxGain0(zd_80211Obj_t *pObj, U8 *pTxGain, U8 TxPwrType)
4710 {
4711 void *reg = pObj->reg;
4712
4713 switch (pObj->rfMode){
4714 /*
4715 case MAXIM_NEW_RF:
4716 *pTxGain &= MAXIM2_MAX_TX_PWR_SET;
4717 LockPhyReg(pObj);
4718
4719 if (TxPwrType != cTX_OFDM){
4720 pObj->SetReg(reg, ZD_CR31, *pTxGain);
4721 }
4722 else{
4723 #if !fTX_GAIN_OFDM
4724 pObj->SetReg(reg, ZD_CR31, *pTxGain);
4725 #else
4726 pObj->SetReg(reg, ZD_CR51, *pTxGain);
4727 pObj->SetReg(reg, ZD_CR52, *pTxGain);
4728 pObj->SetReg(reg, ZD_CR53, *pTxGain);
4729 #endif
4730 }
4731 UnLockPhyReg(pObj);
4732 break;
4733 */
4734
4735 case RFMD_RF:
4736 case AL2230_RF:
4737 case AL7230B_RF:
4738 case AL2230S_RF:
4739 LockPhyReg(pObj);
4740 if (TxPwrType != cTX_OFDM){
4741 pObj->SetReg(reg, ZD_CR31, *pTxGain);
4742 }
4743 else {
4744 #if !fTX_GAIN_OFDM
4745 pObj->SetReg(reg, ZD_CR31, *pTxGain);
4746 #else
4747 pObj->SetReg(reg, ZD_CR51, *pTxGain);
4748 pObj->SetReg(reg, ZD_CR52, *pTxGain);
4749 pObj->SetReg(reg, ZD_CR53, *pTxGain);
4750 #endif
4751 }
4752 UnLockPhyReg(pObj);
4753 break;
4754 default:
4755 break;
4756 }
4757 }
4758
4759 void HW_Write_TxGain1(zd_80211Obj_t *pObj, U8 txgain, U8 TxPwrType)
4760 {
4761 U8 *pTxGain;
4762
4763 HW_Write_TxGain0(pObj, &txgain, TxPwrType);
4764
4765 #if fTX_GAIN_OFDM
4766 if (TxPwrType != cTX_OFDM)
4767 pTxGain = &(pObj->TxGainSetting);
4768 else
4769 pTxGain = &(pObj->TxGainSetting2);
4770 #else
4771 pTxGain = &(pObj->TxGainSetting);
4772 #endif
4773
4774 *pTxGain = txgain;
4775 }
4776
4777 void HW_Write_TxGain2(zd_80211Obj_t *pObj, U8 TxPwrType)
4778 {
4779 U8 *pTxGain;
4780
4781
4782 if (TxPwrType != cTX_OFDM){
4783 pTxGain = &(pObj->TxGainSetting);
4784 }
4785 else
4786 {
4787 #if fTX_GAIN_OFDM
4788 pTxGain = &(pObj->TxGainSetting2);
4789 #else
4790 pTxGain = &(pObj->TxGainSetting);
4791 #endif
4792 }
4793
4794 HW_Write_TxGain0(pObj, pTxGain, TxPwrType);
4795 }
4796
4797 void HW_Set_FilterBand(zd_80211Obj_t *pObj, U32 region_code)
4798 {
4799 U32 tmpLong;
4800 void *reg = pObj->reg;
4801
4802 switch(region_code){
4803 case 0x40: // Japan
4804 LockPhyReg(pObj);
4805 //if (pObj->rfMode == MAXIM_NEW_RF)
4806 {
4807 tmpLong = pObj->GetReg(reg, ZD_CR5);
4808 tmpLong |= BIT_6; //japan
4809 pObj->SetReg(reg, ZD_CR5, tmpLong);
4810 }
4811
4812 UnLockPhyReg(pObj);
4813 break;
4814
4815 default:
4816 LockPhyReg(pObj);
4817 tmpLong = pObj->GetReg(reg, ZD_CR5);
4818 tmpLong &= ~BIT_6;//USA
4819
4820 pObj->SetReg(reg, ZD_CR5, tmpLong);
4821 UnLockPhyReg(pObj);
4822 break;
4823 }
4824 }
4825
4826
4827 void HW_UpdateBcnInterval(zd_80211Obj_t *pObj, U16 BcnInterval)
4828 {
4829 void *reg = pObj->reg;
4830 U32 tmpvalue;
4831 U32 ul_PreTBTT;
4832 U32 ul_ATIMWnd;
4833
4834
4835 //++
4836 // Make sure that BcnInterval > Pre_TBTT > ATIMWnd >= 0
4837 if (BcnInterval < 5){
4838 BcnInterval = 5;
4839 }
4840
4841 ul_PreTBTT = pObj->GetReg(reg, ZD_Pre_TBTT);
4842 if (ul_PreTBTT < 4){
4843 ul_PreTBTT = 4;
4844 }
4845
4846 if (ul_PreTBTT >= BcnInterval){
4847 ul_PreTBTT = BcnInterval-1;
4848
4849 }
4850 pObj->SetReg(reg, ZD_Pre_TBTT, ul_PreTBTT);
4851
4852 ul_ATIMWnd = pObj->GetReg(reg, ZD_ATIMWndPeriod);
4853 if (ul_ATIMWnd >= ul_PreTBTT){
4854 ul_ATIMWnd = ul_PreTBTT-1;
4855 }
4856 pObj->SetReg(reg, ZD_ATIMWndPeriod, ul_ATIMWnd);
4857
4858 tmpvalue = pObj->GetReg(reg, ZD_BCNInterval);
4859 tmpvalue &= ~0xffff;
4860 tmpvalue |= BcnInterval;
4861 pObj->SetReg(reg, ZD_BCNInterval, tmpvalue);
4862
4863 pObj->BeaconInterval = BcnInterval;
4864 }
4865
4866
4867
4868
4869 void HW_UpdateATIMWindow(zd_80211Obj_t *pObj, U16 AtimWnd)
4870 {
4871 void *reg = pObj->reg;
4872 U32 ul_PreTBTT;
4873
4874 //++
4875 // Make sure that Pre_TBTT > ATIMWnd >= 0
4876
4877 ul_PreTBTT = pObj->GetReg(reg, ZD_Pre_TBTT);
4878 if (AtimWnd >= ul_PreTBTT){
4879 AtimWnd = (U16)(ul_PreTBTT-1);
4880 }
4881 //--
4882
4883 pObj->SetReg(reg, ZD_ATIMWndPeriod, AtimWnd);
4884 }
4885
4886
4887 void HW_UpdatePreTBTT(zd_80211Obj_t *pObj, U32 pretbtt)
4888 {
4889 void *reg = pObj->reg;
4890 U32 ul_BcnItvl;
4891 U32 ul_AtimWnd;
4892
4893 //++
4894 // Make sure that BcnInterval > Pre_TBTT > ATIMWnd
4895 ul_BcnItvl = pObj->GetReg(reg, ZD_BCNInterval);
4896 ul_BcnItvl &= 0xff;
4897 if (pretbtt >= ul_BcnItvl){
4898 pretbtt = ul_BcnItvl-1;
4899 }
4900
4901 ul_AtimWnd = pObj->GetReg(reg, ZD_ATIMWndPeriod);
4902 if (pretbtt <= ul_AtimWnd){
4903 pretbtt = ul_AtimWnd+1;
4904 }
4905 //--
4906
4907 pObj->SetReg(reg, ZD_Pre_TBTT, pretbtt);
4908 }
4909
4910 // for AMAC CAM operation
4911 void HW_CAM_Avail(zd_80211Obj_t *pObj)
4912 {
4913 void *reg = pObj->reg;
4914 U32 tmpValue;
4915 U16 loopCheck = 0;
4916
4917 tmpValue = pObj->GetReg(reg, ZD_CAM_MODE);
4918 while(tmpValue & HOST_PEND){
4919 // To WAIT HW Ready when set encryption key
4920 // Wait too long is abnormal.
4921 if(loopCheck++ > 100)
4922 {
4923 printk("infinite loop occurs in %s\n", __FUNCTION__);
4924 loopCheck = 0;
4925 break;
4926 }
4927
4928 pObj->DelayUs(10);
4929 tmpValue = pObj->GetReg(reg, ZD_CAM_MODE);
4930 }
4931 }
4932
4933 void HW_CAM_Write(zd_80211Obj_t *pObj, U32 address, U32 data)
4934 {
4935 void *reg = pObj->reg;
4936
4937 HW_CAM_Avail(pObj);
4938 pObj->SetReg(reg, ZD_CAM_DATA, data);
4939 pObj->SetReg(reg, ZD_CAM_ADDRESS, (address | CAM_WRITE));
4940 }
4941
4942 U32 HW_CAM_Read(zd_80211Obj_t *pObj, U32 address)
4943 {
4944 void *reg = pObj->reg;
4945 U32 result;
4946
4947 HW_CAM_Avail(pObj);
4948 pObj->SetReg(reg, ZD_CAM_ADDRESS, address);
4949 HW_CAM_Avail(pObj);
4950 result = pObj->GetReg(reg, ZD_CAM_DATA);
4951
4952 return result;
4953 }
4954
4955 void HW_CAM_SetMAC(zd_80211Obj_t *pObj, U16 aid, U8 *pMAC)
4956 {
4957 U32 userWordAddr;
4958 U32 userByteOffset;
4959 U32 tmpValue;
4960 int i;
4961
4962 userWordAddr = (aid/4)*6;
4963 userByteOffset = aid % 4;
4964
4965 for (i=0; i<MAC_LENGTH; i++) {
4966 tmpValue = HW_CAM_Read(pObj, (userWordAddr+i));
4967 tmpValue &= ~(0xff << (userByteOffset*8));
4968 tmpValue |= pMAC[i]<<(userByteOffset*8);
4969 HW_CAM_Write(pObj, (userWordAddr+i), tmpValue);
4970 }
4971 }
4972
4973
4974 void HW_CAM_GetMAC(zd_80211Obj_t *pObj, U16 aid, U8 *pMac)
4975 {
4976 U32 userWordAddr;
4977 U32 userByteOffset;
4978 U32 tmpValue;
4979 U8 mac[6];
4980 int i;
4981
4982 userWordAddr = (aid/4)*6;
4983 userByteOffset = aid % 4;
4984
4985 for (i=0; i<MAC_LENGTH; i++) {
4986 tmpValue = HW_CAM_Read(pObj, (userWordAddr+i));
4987 mac[i] = (U8)(tmpValue >> (userByteOffset*8)) & 0xFF;
4988 }
4989
4990 if (memcmp(mac, pMac, 6) != 0){
4991 FPRINT("*****Where is my MAC ????");
4992 }
4993 else
4994 FPRINT("*****Verify MAC OK!!!");
4995 }
4996
4997
4998 void HW_CAM_SetEncryType(zd_80211Obj_t *pObj, U16 aid, U8 encryType)
4999 {
5000 U32 encryWordAddr;
5001 U32 encryByteOffset;
5002 U32 tmpValue;
5003
5004 U8 targetByte;
5005
5006 encryWordAddr = ENCRY_TYPE_START_ADDR + (aid/8);
5007 encryByteOffset = (aid/2) % 4;
5008
5009 tmpValue = HW_CAM_Read(pObj, encryWordAddr);
5010 targetByte = (U8)(tmpValue >> (encryByteOffset*8));
5011 tmpValue &= ~(0xff << (encryByteOffset*8)); //clear target byte
5012 if (aid % 2)
5013 targetByte = (encryType<<4) | (targetByte & 0xf); //set hignt part
5014 else //low nibble
5015 targetByte = encryType | (targetByte & 0xf0); //set low part
5016
5017 tmpValue |= targetByte << (encryByteOffset*8);
5018
5019
5020 HW_CAM_Write(pObj, encryWordAddr, tmpValue);
5021 }
5022
5023
5024 U8 HW_CAM_GetEncryType(zd_80211Obj_t *pObj, U16 aid)
5025 {
5026 U32 encryWordAddr;
5027 U32 encryByteOffset;
5028
5029 U32 tmpValue;
5030 U8 keyLength = 0;
5031 U8 targetByte;
5032
5033 encryWordAddr = ENCRY_TYPE_START_ADDR + (aid/8);
5034 encryByteOffset = (aid/2) % 4;
5035
5036 tmpValue = HW_CAM_Read(pObj, encryWordAddr);
5037 targetByte = (U8)(tmpValue >> (encryByteOffset*8));
5038 if (aid % 2)
5039 targetByte >>= 4; //get hignt part
5040 else
5041 targetByte &= 0x0f; //get low part
5042
5043 switch(targetByte){
5044 case NO_WEP: //0
5045 FPRINT("***No Encryption");
5046 break;
5047
5048 case WEP64: //1
5049 FPRINT("***WEP 64");
5050 keyLength = 5;
5051 break;
5052
5053 case TKIP: //2
5054 FPRINT("**TKIP");
5055 keyLength = 16;
5056 break;
5057
5058 case AES: //4
5059
5060 FPRINT("***CCM");
5061 keyLength = 16;
5062 break;
5063
5064
5065 case WEP128: //5
5066 FPRINT("***WEP 128");
5067 keyLength = 13;
5068 break;
5069
5070 default:
5071 FPRINT("***Not Supported Encry");
5072 break;
5073 }
5074
5075 return keyLength;
5076
5077 }
5078
5079
5080 void HW_CAM_SetKey(zd_80211Obj_t *pObj, U16 aid, U8 keyLength, U8 *pKey)
5081 {
5082 U32 keyWordAddr;
5083 U8 offset;
5084 U32 tmpValue;
5085 int i, j, k;
5086
5087 keyWordAddr = KEY_START_ADDR + (aid*8);
5088
5089 offset = 0;
5090 for (i=0; i<8; i++){
5091 tmpValue = HW_CAM_Read(pObj, (keyWordAddr+i));
5092 for (j=offset, k=0; k<4; j++, k++) {
5093 tmpValue &= ~(0xff << (k*8));
5094 if (offset < keyLength){
5095 tmpValue |= pKey[j] << (k*8);
5096 }
5097 offset++;
5098 }
5099 HW_CAM_Write(pObj, (keyWordAddr+i), tmpValue);
5100 }
5101
5102 }
5103
5104
5105 void HW_CAM_GetKey(zd_80211Obj_t *pObj, U16 aid, U8 keyLength, U8 *pKey)
5106 {
5107 U32 keyWordAddr;
5108 U8 key[32];
5109 int i, j;
5110 U32 tmpValue;
5111
5112 keyWordAddr = KEY_START_ADDR + (aid*8);
5113 j = 0;
5114 for (i=0; i<8; i++){
5115 tmpValue = HW_CAM_Read(pObj, (keyWordAddr+i));
5116 key[j] = (U8)(tmpValue);
5117 j++;
5118 key[j] = (U8)(tmpValue >> 8);
5119 j++;
5120 key[j] = (U8)(tmpValue >> 16);
5121 j++;
5122 key[j] = (U8)(tmpValue >> 24);
5123 j++;
5124 }
5125
5126 if (memcmp(&key[0], pKey, keyLength) != 0){
5127 FPRINT("*****Where is my Key ????");
5128 }
5129 else
5130 FPRINT("*****Verify KEY OK!!!");
5131 }
5132
5133
5134 void HW_CAM_UpdateRollTbl(zd_80211Obj_t *pObj, U16 aid)
5135 {
5136 void *reg = pObj->reg;
5137 U32 tmpValue;
5138
5139 if (aid >= 32){
5140 tmpValue = pObj->GetReg(reg, ZD_CAM_ROLL_TB_HIGH);
5141 tmpValue |= BIT_0 << (aid-32);
5142 pObj->SetReg(reg, ZD_CAM_ROLL_TB_HIGH, tmpValue);
5143 }
5144 else {
5145 tmpValue = pObj->GetReg(reg, ZD_CAM_ROLL_TB_LOW);
5146 tmpValue |= (BIT_0 << aid);
5147 pObj->SetReg(reg, ZD_CAM_ROLL_TB_LOW, tmpValue);
5148 }
5149 }
5150
5151
5152 void HW_CAM_ResetRollTbl(zd_80211Obj_t *pObj)
5153 {
5154 void *reg = pObj->reg;
5155
5156 pObj->SetReg(reg, ZD_CAM_ROLL_TB_LOW, 0);
5157 pObj->SetReg(reg, ZD_CAM_ROLL_TB_HIGH, 0);
5158 }
5159
5160
5161 void HW_CAM_ClearRollTbl(zd_80211Obj_t *pObj, U16 aid)
5162 {
5163 void *reg = pObj->reg;
5164 U32 tmpValue;
5165
5166
5167 //update roll table
5168 if (aid > 32) {
5169 tmpValue = pObj->GetReg(reg, ZD_CAM_ROLL_TB_HIGH);
5170 tmpValue &= ~(BIT_0 << (aid-32)); //set user invalid
5171 pObj->SetReg(reg, ZD_CAM_ROLL_TB_HIGH, tmpValue);
5172 }
5173 else {
5174 tmpValue = pObj->GetReg(reg, ZD_CAM_ROLL_TB_LOW);
5175 tmpValue &= ~(BIT_0 << aid); //set user invalid
5176 pObj->SetReg(reg, ZD_CAM_ROLL_TB_LOW, tmpValue);
5177 }
5178 }
5179 #if 0
5180 void HW_ConfigDynaKey(zd_80211Obj_t *pObj, U16 aid, U8 *pMac, U8 *pKey, U8 keyLength, U8 encryType)
5181 {
5182 //void *reg = pObj->reg;
5183
5184 //set MAC address
5185 HW_CAM_SetMAC(pObj, aid, pMac);
5186 HW_CAM_SetEncryType(pObj, aid, encryType);
5187 HW_CAM_SetKey(pObj, aid, keyLength, pKey);
5188 HW_CAM_UpdateRollTbl(pObj, aid);
5189 }
5190 #endif
5191 void HW_ConfigDynaKey(zd_80211Obj_t *pObj, U16 aid, U8 *pMac, U8 *pKey, U8 keyLength, U8 encryType, U8 change_enc)
5192 {
5193 //set MAC address
5194 // int flags;
5195 //flags = pObj->EnterCS();
5196 HW_CAM_ClearRollTbl(pObj, aid);
5197 if (change_enc)
5198 //if (1)
5199 {
5200 HW_CAM_SetMAC(pObj, aid, pMac);
5201 HW_CAM_SetEncryType(pObj, aid, encryType);
5202 }
5203 HW_CAM_SetKey(pObj, aid, keyLength, pKey);
5204 HW_CAM_UpdateRollTbl(pObj, aid);
5205 //pObj->ExitCS(flags);
5206 }
5207
5208 void HW_ConfigStatKey(zd_80211Obj_t *pObj, U8 *pKey, U8 keyLen, U32 startAddr)
5209 {
5210 int i, j, k, offset;
5211 U32 tmpKey = 0;
5212 U16 loopCheck = 0;
5213
5214 j = 0;
5215 offset = 0;
5216
5217 while(offset < keyLen){
5218 // Just a loop check even if it is impossible occur.
5219 if(loopCheck++ > 100)
5220 {
5221 printk("infinite loop occurs in %s\n", __FUNCTION__);
5222 loopCheck = 0;
5223 break;
5224 }
5225
5226 for (i=offset, k=0; k<4; i++, k++){
5227 tmpKey |= pKey[i] << ((k%4)*8);
5228 offset++;
5229 if (offset == keyLen)
5230 goto last_part;
5231 }
5232 HW_CAM_Write(pObj, startAddr+j, tmpKey);
5233 j++;
5234 tmpKey = 0;
5235 }
5236
5237 last_part:
5238 HW_CAM_Write(pObj, startAddr+j, tmpKey);
5239 }
5240
5241
5242 void HW_GetStatKey(zd_80211Obj_t *pObj)
5243 {
5244 //void *reg = pObj->reg;
5245 int i, j;
5246 U8 key[128];
5247 U32 tmpValue;
5248 U32 encryType;
5249 U8 keyLength;
5250
5251 encryType = HW_CAM_Read(pObj, DEFAULT_ENCRY_TYPE);
5252 switch(encryType){
5253 case WEP64:
5254 FPRINT("WEP64 Mode");
5255
5256 keyLength = 5;
5257 break;
5258
5259 case WEP128:
5260 FPRINT("WEP128 Mode");
5261 keyLength = 13;
5262 break;
5263
5264 case WEP256:
5265 FPRINT("WEP256 Mode");
5266 keyLength = 29;
5267 break;
5268
5269 default:
5270 FPRINT("Not supported Mode");
5271 return;
5272
5273 }
5274
5275 for (i=0, j=0; i<32; i++){
5276 tmpValue = HW_CAM_Read(pObj, (STA_KEY_START_ADDR+i));
5277
5278 key[j] = (U8)(tmpValue);
5279 j++;
5280 key[j] = (U8)(tmpValue >> 8);
5281 j++;
5282 key[j] = (U8)(tmpValue >> 16);
5283 j++;
5284 key[j] = (U8)(tmpValue >> 24);
5285 j++;
5286 }
5287
5288 zd1205_dump_data("Key 1 = ", (U8 *)&key[0], keyLength);
5289 zd1205_dump_data("Key 2 = ", (U8 *)&key[32], keyLength);
5290 zd1205_dump_data("Key 3 = ", (U8 *)&key[2*32], keyLength);
5291 zd1205_dump_data("Key 4 = ", (U8 *)&key[3*32], keyLength);
5292 return;
5293 }
5294
5295 /*
5296 void HW_EEPROM_ACCESS(zd_80211Obj_t *pObj, U8 RamAddr, U32 RomAddr, U32 length, U8 bWrite)
5297 {
5298 void *reg = pObj->reg;
5299 U32 status;
5300 U32 access = 0;
5301 U32 startTime;
5302 U32 endTime;
5303 U32 diffTime;
5304 int count = 0;
5305
5306 if (bWrite){
5307 FPRINT("Write Access");
5308 }
5309 else
5310 FPRINT("Read Access");
5311
5312
5313 FPRINT_V("RomAddr", RomAddr);
5314 FPRINT_V("RamAddr", RamAddr);
5315 FPRINT_V("Length", length);
5316
5317 if (bWrite){
5318 access = EEPROM_WRITE_ACCESS;
5319 //unlock write access
5320 pObj->SetReg(reg, ZD_EPP_KEY_PROT, 0x55aa);
5321 pObj->SetReg(reg, ZD_EPP_KEY_PROT, 0x44bb);
5322 pObj->SetReg(reg, ZD_EPP_KEY_PROT, 0x33cc);
5323 pObj->SetReg(reg, ZD_EPP_KEY_PROT, 0x22dd);
5324 }
5325
5326 pObj->SetReg(reg, ZD_EPP_ROM_ADDRESS, RomAddr);
5327 pObj->SetReg(reg, ZD_EPP_SRAM_ADDRESS, RamAddr);
5328 pObj->SetReg(reg, ZD_EPP_LENG_DIR, access | length);
5329
5330 startTime = pObj->GetReg(reg, ZD_TSF_LowPart);
5331
5332 pObj->DelayUs(2000);
5333 status = pObj->GetReg(reg, ZD_EPP_CLOCK_DIV);
5334 while(status & EEPROM_BUSY_FLAG){
5335 pObj->DelayUs(1000);
5336 //FPRINT("EEPROM programming !!!");
5337 status = pObj->GetReg(reg, ZD_EPP_CLOCK_DIV);
5338
5339 if (count > 500) {
5340 FPRINT("EEPROM Timeout !!!");
5341 if (bWrite)
5342 pObj->SetReg(reg, ZD_EPP_KEY_PROT, 0x00);
5343 return;
5344 }
5345 //len = pObj->GetReg(reg, ZD_EPP_LENG_DIR);
5346 //FPRINT_V("len", len);
5347 count++;
5348 }
5349
5350 endTime = pObj->GetReg(reg, ZD_TSF_LowPart);
5351 if (endTime > startTime){
5352 diffTime = endTime - startTime;
5353 }
5354 else {
5355 diffTime = 0xffffffff + startTime - endTime;
5356 }
5357
5358 //FPRINT_V("Processing Time", diffTime);
5359
5360 printk("\nProcessing Time = %u ms\n", (u32)diffTime/1000);
5361
5362
5363 //lock write access
5364 if (bWrite)
5365 pObj->SetReg(reg, ZD_EPP_KEY_PROT, 0x00);
5366 }
5367 */
5368 void HW_EEPROM_ACCESS(zd_80211Obj_t *pObj, U16 RamAddr, U16 RomAddr, U32 length,
5369 U8 bWrite)
5370 {
5371 void *reg = pObj->reg;
5372 U32 tmp;
5373 U32 access = 0;
5374 tmp = pObj->GetReg(reg, ZD1211_CLOCK_CTRL);
5375 pObj->SetReg(reg, ZD1211_CLOCK_CTRL, tmp | BIT_0);
5376
5377 if(bWrite)
5378 access = BIT_15;
5379
5380 #ifdef ZD1211B
5381 if(bWrite)
5382 {
5383 pObj->SetReg(reg, 0x863a, 0x55aa);
5384 pObj->SetReg(reg, 0x8685, 0x44bb);
5385 pObj->SetReg(reg, 0x861b, 0x33cc);
5386 pObj->SetReg(reg, 0x8666, 0x22dd);
5387 pObj->DelayUs(5000);
5388 }
5389 #endif
5390
5391
5392
5393 pObj->SetReg(reg, 0x862a, RomAddr);
5394 pObj->SetReg(reg, 0x862b, RamAddr);
5395 pObj->SetReg(reg, 0x862c, length | access);
5396
5397 pObj->DelayUs(5000);
5398 pObj->SetReg(reg, ZD1211_CLOCK_CTRL, tmp & ~BIT_0);
5399
5400
5401 }
5402 /*
5403 void ZD1205_WriteE2P(zd_80211Obj_t *pObj)
5404 {
5405
5406 u32 tmpvalue;
5407 int i;
5408 void *reg = pObj->reg;
5409
5410 //0x00000000 means the first 2K
5411 pObj->SetReg(reg,E2P_ADDR_COUNTER,0x00000000);
5412 //0x8100 -> 8 means write to eeprom
5413 // -> 0x100 means 2K
5414 tmpvalue = pObj->GetReg(reg,E2P_DMA_LENGTH);
5415 tmpvalue &= 0xFFFF0000;
5416 tmpvalue |= 0x00008100;
5417 pObj->SetReg(reg,E2P_DMA_LENGTH,tmpvalue);
5418 //0x0 means 78.125KHz, 0x1 means 312.5KHz
5419 pObj->SetReg(reg,E2P_CLOCK,0x00000000);
5420 //0x55aa->0x44bb->0x33cc->0x22dd means unlock the key
5421 tmpvalue = pObj->GetReg(reg,E2P_WRITE_PROTECT);
5422 tmpvalue &= 0xFFFF0000;
5423 tmpvalue |= 0x000055aa;
5424 pObj->SetReg(reg,E2P_WRITE_PROTECT,tmpvalue);
5425 tmpvalue = pObj->GetReg(reg,E2P_WRITE_PROTECT);
5426 tmpvalue &= 0xFFFF0000;
5427 tmpvalue |= 0x000044bb;
5428 pObj->SetReg(reg,E2P_WRITE_PROTECT,tmpvalue);
5429 tmpvalue = pObj->GetReg(reg,E2P_WRITE_PROTECT);
5430 tmpvalue &= 0xFFFF0000;
5431 tmpvalue |= 0x000033cc;
5432 pObj->SetReg(reg,E2P_WRITE_PROTECT,tmpvalue);
5433 tmpvalue = pObj->GetReg(reg,E2P_WRITE_PROTECT);
5434 tmpvalue &= 0xFFFF0000;
5435 tmpvalue |= 0x000022dd;
5436 pObj->SetReg(reg,E2P_WRITE_PROTECT,tmpvalue);
5437
5438 //wait until the DMA busy flag is clear
5439 tmpvalue = pObj->GetReg(reg,E2P_CLOCK);
5440 i=0;
5441 while ( (tmpvalue&0x8000) != 0) {
5442 pObj->DelayUs(10);
5443 i++;
5444 tmpvalue = pObj->GetReg(reg,E2P_CLOCK);
5445 }
5446 //lock the key to provide write protection
5447 //if not lock the key , EEPROM will hang when read it again
5448 pObj->SetReg(reg,E2P_WRITE_PROTECT,0x0);
5449
5450 }
5451 */
5452
5453
5454 #endif
5455
MOXA 2.6.9 from sdlinux-moxaart.tgz