include/asm-arm/arch-epxa10db/timer00.h

   1 /*
   2  *
   3  *  This file contains the register definitions for the Excalibur
   4  *  Timer TIMER00.
   5  *
   6  *  Copyright (C) 2001 Altera Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22 #ifndef __TIMER00_H
  23 #define __TIMER00_H
  24
  25 /*
  26  * Register definitions for the timers
  27  */
  28
  29
  30 #define TIMER0_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x00 ))
  31 #define TIMER0_CR_B_MSK (0x20)
  32 #define TIMER0_CR_B_OFST (0x5)
  33 #define TIMER0_CR_S_MSK  (0x10)
  34 #define TIMER0_CR_S_OFST (0x4)
  35 #define TIMER0_CR_CI_MSK (0x08)
  36 #define TIMER0_CR_CI_OFST (0x3)
  37 #define TIMER0_CR_IE_MSK (0x04)
  38 #define TIMER0_CR_IE_OFST (0x2)
  39 #define TIMER0_CR_MODE_MSK (0x3)
  40 #define TIMER0_CR_MODE_OFST (0)
  41 #define TIMER0_CR_MODE_FREE (0)
  42 #define TIMER0_CR_MODE_ONE  (1)
  43 #define TIMER0_CR_MODE_INTVL (2)
  44
  45 #define TIMER0_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x00 ))
  46 #define TIMER0_SR_B_MSK (0x20)
  47 #define TIMER0_SR_B_OFST (0x5)
  48 #define TIMER0_SR_S_MSK  (0x10)
  49 #define TIMER0_SR_S_OFST (0x4)
  50 #define TIMER0_SR_CI_MSK (0x08)
  51 #define TIMER0_SR_CI_OFST (0x3)
  52 #define TIMER0_SR_IE_MSK (0x04)
  53 #define TIMER0_SR_IE_OFST (0x2)
  54 #define TIMER0_SR_MODE_MSK (0x3)
  55 #define TIMER0_SR_MODE_OFST (0)
  56 #define TIMER0_SR_MODE_FREE (0)
  57 #define TIMER0_SR_MODE_ONE  (1)
  58 #define TIMER0_SR_MODE_INTVL (2)
  59
  60 #define TIMER0_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x010 ))
  61 #define TIMER0_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x020 ))
  62 #define TIMER0_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x030 ))
  63
  64 #define TIMER1_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x40 ))
  65 #define TIMER1_CR_B_MSK (0x20)
  66 #define TIMER1_CR_B_OFST (0x5)
  67 #define TIMER1_CR_S_MSK  (0x10)
  68 #define TIMER1_CR_S_OFST (0x4)
  69 #define TIMER1_CR_CI_MSK (0x08)
  70 #define TIMER1_CR_CI_OFST (0x3)
  71 #define TIMER1_CR_IE_MSK (0x04)
  72 #define TIMER1_CR_IE_OFST (0x2)
  73 #define TIMER1_CR_MODE_MSK (0x3)
  74 #define TIMER1_CR_MODE_OFST (0)
  75 #define TIMER1_CR_MODE_FREE (0)
  76 #define TIMER1_CR_MODE_ONE  (1)
  77 #define TIMER1_CR_MODE_INTVL (2)
  78
  79 #define TIMER1_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x40 ))
  80 #define TIMER1_SR_B_MSK (0x20)
  81 #define TIMER1_SR_B_OFST (0x5)
  82 #define TIMER1_SR_S_MSK  (0x10)
  83 #define TIMER1_SR_S_OFST (0x4)
  84 #define TIMER1_SR_CI_MSK (0x08)
  85 #define TIMER1_SR_CI_OFST (0x3)
  86 #define TIMER1_SR_IE_MSK (0x04)
  87 #define TIMER1_SR_IE_OFST (0x2)
  88 #define TIMER1_SR_MODE_MSK (0x3)
  89 #define TIMER1_SR_MODE_OFST (0)
  90 #define TIMER1_SR_MODE_FREE (0)
  91 #define TIMER1_SR_MODE_ONE  (1)
  92 #define TIMER1_SR_MODE_INTVL (2)
  93
  94 #define TIMER1_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x050 ))
  95 #define TIMER1_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x060 ))
  96 #define TIMER1_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x070 ))
  97
  98 #endif /* __TIMER00_H */