drivers/net/moxacpu_mac.h

   1
   2 /*
   3  * This file is the define for Moxa CPU MAC controller.
   4  *
   5  * History:
   6  * Date         Author                  Comment
   7  * 06-15-2005   Victor Yu.              Create it.
   8  */
   9 #ifndef _MOXACPU_MAC_H
  10 #define _MOXACPU_MAC_H
  11
  12 typedef struct tx_desc_struct {
  13         // TXDES0
  14         union {
  15                 unsigned int    ui;
  16 #define TXDMA_OWN               (1<<31)
  17 #define TXPKT_EXSCOL            (1<<1)
  18 #define TXPKT_LATECOL           (1<<0)
  19                 struct {
  20                         unsigned int    TxPktLateCol:1; // is aborted due to late collision
  21                         unsigned int    TxPktExsCol:1;  // is aborted after 16 collisions
  22                         unsigned int    Reserved1:29;
  23                         unsigned int    TxDMAOwn:1;     // is owned by the MAC controller
  24                 } ubit;
  25         } txdes0;
  26
  27         // TXDES1
  28         union {
  29                 unsigned int    ui;
  30 #define EDOTR                   (1<<31)
  31 #define TXIC                    (1<<30)
  32 #define TX2FIC                  (1<<29)
  33 #define FTS                     (1<<28)
  34 #define LTS                     (1<<27)
  35 #define TXBUF_SIZE_MASK         0x7ff
  36 #define TXBUF_SIZE_MAX          (TXBUF_SIZE_MASK+1)
  37                 struct {
  38                         unsigned int    TxBufSize:11;   // transmit buffer size in byte
  39                         unsigned int    Reserved2:16;
  40                         unsigned int    Lts:1;          // is the last descriptor of a Tx
  41                                                         // packet
  42                         unsigned int    Fts:1;          // is the first descriptor of a Tx
  43                                                         // packet
  44                         unsigned int    Tx2fic:1;       // transmit to FIFO interrupt on
  45                                                         // completion
  46                         unsigned int    Txic:1;         // transmit interrupt on completion
  47                         unsigned int    Edotr:1;        // end descriptor of transmit ring
  48                 } ubit;
  49         } txdes1;
  50
  51         // TXDES2
  52         struct {
  53                 unsigned int    phyTxBufBaseAddr;// transmit buffer physical base address
  54                 unsigned char   *virtTxBufBaseAddr;// transmit buffer virtual base address
  55         } txdes2;
  56 } tx_desc_t;
  57
  58 typedef struct rx_desc_struct {
  59         // RXDES0
  60         union {
  61                 unsigned int    ui;
  62 #define RXDMA_OWN               (1<<31)
  63 #define FRS                     (1<<29)
  64 #define LRS                     (1<<28)
  65 #define RX_ODD_NB               (1<<22)
  66 #define RUNT                    (1<<21)
  67 #define FTL                     (1<<20)
  68 #define CRC_ERR                 (1<<19)
  69 #define RX_ERR                  (1<<18)
  70 #define BROADCAST_RXDES0        (1<<17)
  71 #define MULTICAST_RXDES0        (1<<16)
  72 #define RFL_MASK                0x7ff
  73 #define RFL_MAX                 (RFL_MASK+1)
  74                 struct {
  75                         unsigned int    RecvFrameLen:11;        // receive frame length
  76                         unsigned int    Reserved1:5;
  77                         unsigned int    Multicast:1;    // multicast frame
  78                         unsigned int    Broadcast:1;    // broadcast frame
  79                         unsigned int    RxErr:1;        // receive error
  80                         unsigned int    CRCErr:1;       // CRC error
  81                         unsigned int    Ftl:1;          // frame too long
  82                         unsigned int    Runt:1;         // runt packet, less than 64 bytes
  83                         unsigned int    RxOddNb:1;      // receive odd nibbles
  84                         unsigned int    Reserved2:5;
  85                         unsigned int    Lrs:1;          // last receive segment descriptor
  86                         unsigned int    Frs:1;          // first receive segment descriptor
  87                         unsigned int    Reserved3:1;
  88                         unsigned int    RxDMAOwn:1;     // RXDMA onwership
  89                 } ubit;
  90         } rxdes0;
  91
  92         // RXDES1
  93         union {
  94                 unsigned int    ui;
  95 #define EDORR                   (1<<31)
  96 #define RXBUF_SIZE_MASK         0x7ff
  97 #define RXBUF_SIZE_MAX          (RXBUF_SIZE_MASK+1)
  98                 struct {
  99                         unsigned int    RxBufSize:11;   // receive buffer size
 100                         unsigned int    Reserved4:20;
 101                         unsigned int    Edorr:1;        // end descriptor of receive ring
 102                 } ubit;
 103         } rxdes1;
 104
 105         // RXDES2
 106         struct {
 107                 unsigned int    phyRxBufBaseAddr;// receive buffer physical base address
 108                 unsigned char   *virtRxBufBaseAddr;// receive buffer virtual base address
 109         } rxdes2;
 110 } rx_desc_t;
 111
 112 typedef struct mac_control_reg_struct {
 113         unsigned int    isr;    // interrupt status, 0x0
 114 #define RPKT_FINISH             (1<<0)  // RXDMA has received packets into RX buffer
 115                                         // successfully
 116 #define NORXBUF                 (1<<1)  // receive buffer unavailable
 117 #define XPKT_FINISH             (1<<2)  // TXDMA has moved data into the TX FIFO
 118 #define NOTXBUF                 (1<<3)  // transmit buffer unavailable
 119 #define XPKT_OK_INT_STS         (1<<4)  // packets transmitted to ethernet successfully
 120 #define XPKT_LOST_INT_STS       (1<<5)  // packets transmitted to ethernet lost due to late
 121                                         // collision or excessive collision
 122 #define RPKT_SAV                (1<<6)  // packets received into RX FIFO successfully
 123 #define RPKT_LOST_INT_STS       (1<<7)  // received packet lost due to RX FIFO full
 124 #define AHB_ERR                 (1<<8)  // AHB error
 125 #define PHYSTS_CHG              (1<<9)  // PHY link status change
 126         unsigned int    imr;    // interrupt mask, 0x4
 127 #define RPKT_FINISH_M           (1<<0)  // interrupt mask of ISR[0]
 128 #define NORXBUF_M               (1<<1)  // interrupt mask of ISR[1]
 129 #define XPKT_FINISH_M           (1<<2)  // interrupt mask of ISR[2]
 130 #define NOTXBUF_M               (1<<3)  // interrupt mask of ISR[3]
 131 #define XPKT_OK_M               (1<<4)  // interrupt mask of ISR[4]
 132 #define XPKT_LOST_M             (1<<5)  // interrupt mask of ISR[5]
 133 #define RPKT_SAV_M              (1<<6)  // interrupt mask of ISR[6]
 134 #define RPKT_LOST_M             (1<<7)  // interrupt mask of ISR[7]
 135 #define AHB_ERR_M               (1<<8)  // interrupt mask of ISR[8]
 136 #define PHYSTS_CHG_M            (1<<9)  // interrupt mask of ISR[9]
 137         unsigned int    mac_madr;       // MAC most significant address, 0x8
 138 #define MAC_MADR_MASK           0xffff  // the most significant 2 bytes of MAC address
 139         unsigned int    mac_ldar;       // MAC least significant address, 0xc
 140         unsigned int    matht0;         // multicast address hash table 0, 0x10
 141         unsigned int    matht1;         // multicast address hash table 1, 0x14
 142         unsigned int    txpd;           // transmit poll demand, 0x18
 143         unsigned int    rxpd;           // receive poll demand, 0x1c
 144         unsigned int    txr_badr;       // transmit ring base address, 0x20
 145         unsigned int    rxr_badr;       // receive ring base address, 0x24
 146         unsigned int    itc;            // interrupt timer control, 0x28
 147 #define TXINT_TIME_SEL          (1<<15) // defines the period of TX cycle time
 148 #define TXINT_THR_MASK          (1<<14|1<13|1<12)
 149 #define TXINT_CNT_MASK          (1<<11|1<<10|1<<9|1<<8)
 150 #define RXINT_TIME_SEL          (1<<7)  // defines the period of RX cycle time
 151 #define RXINT_THR_MASK          (1<<6|1<<5|1<<4)
 152 #define RXINT_CNT_MASK          (1<<3|1<<2|1<<1|1<<0)
 153         unsigned int    aptc;           // automatic polling timer control, 0x2c
 154 #define TXPOLL_TIME_SEL         (1<<12) // defines the period of TX poll time
 155 #define TXPOLL_CNT_MASK         (1<<11|1<<10|1<<9|1<<8)
 156 #define TXPOLL_CNT_SHIFT_BIT    8
 157 #define RXPOLL_TIME_SEL         (1<<4)  // defines the period of RX poll time
 158 #define RXPOLL_CNT_MASK         (1<<3|1<<2|1<<1|1<<0)
 159 #define RXPOLL_CNT_SHIFT_BIT    0
 160         unsigned int    dblac;          // DMA burst length and arbitration control, 0x30
 161 #define RX_THR_EN               (1<<9)  // enable RX FIFO threshold arbitration
 162 #define RXFIFO_HTHR_MASK        (1<<8|1<<7|1<<6)
 163 #define RXFIFO_LTHR_MASK        (1<<5|1<<4|1<<3)
 164 #define INCR16_EN               (1<<2)  // use INCR16 burst command in AHB bus
 165 #define INCR8_EN                (1<<1)  // use INCR8 burst command in AHB bus
 166 #define INCR4_EN                (1<<0)  // use INCR4 burst command in AHB bus
 167         unsigned int    reserved1[21];  // 0x34 - 0x84
 168         unsigned int    maccr;          // MAC control, 0x88
 169 #define RX_BROADPKT             (1<<17) // receive boradcast packet
 170 #define RX_MULTIPKT             (1<<16) // receive all multicast packet
 171 #define FULLDUP                 (1<<15) // full duplex
 172 #define CRC_APD                 (1<<14) // append CRC to transmitted packet
 173 #define RCV_ALL                 (1<<12) // not check incoming packet's dest. address
 174 #define RX_FTL                  (1<<11) // store incoming packet even if its length is
 175                                         // great than 1518 bytes
 176 #define RX_RUNT                 (1<<10) // store incoming packet even if its length is
 177                                         // less than 64 bytes
 178 #define HT_MULTI_EN             (1<<9)  // enable storing incoming packet if the packet
 179                                         // passes hash table address filtering and is a
 180                                         // multicast packet
 181 #define RCV_EN                  (1<<8)  // receiver enable
 182 #define ENRX_IN_HALFTX          (1<<6)  // enable packet reception when transmitting
 183                                         // packet in half duplex mode
 184 #define XMT_EN                  (1<<5)  // transmitter enable
 185 #define CRC_DIS                 (1<<4)  // disable CRC check when receiving packets
 186 #define LOOP_EN                 (1<<3)  // internal loop-back
 187 #define SW_RST                  (1<<2)  // software reset, last 64 AHB bus clocks
 188 #define RDMA_EN                 (1<<1)  // enable receive DMA channel
 189 #define XDMA_EN                 (1<<0)  // enable transmit DMA channel
 190         unsigned int    macsr;          // MAC status, 0x8c
 191 #define COL_EXCEED              (1<<11) // collision amount exceeds 16
 192 #define LATE_COL                (1<<10) // transmitter detects late collision
 193 #define XPKT_LOST               (1<<9)  // packet transmitted to ethernet lost due to late
 194                                         // collision or excessive collision
 195 #define XPKT_OK                 (1<<8)  // packets transmitted to ethernet successfully
 196 #define RUNT_MAC_STS            (1<<7)  // receiver detects a runt packet
 197 #define FTL_MAC_STS             (1<<6)  // receiver detects a frame that is too long
 198 #define CRC_ERR_MAC_STS         (1<<5)
 199 #define RPKT_LOST               (1<<4)  // received packets list due to RX FIFO full
 200 #define RPKT_SAVE               (1<<3)  // packets received into RX FIFO successfully
 201 #define COL                     (1<<2)  // incoming packet dropped due to collision
 202 #define MCPU_BROADCAST          (1<<1)
 203 #define MCPU_MULTICAST          (1<<0)
 204         unsigned int    phycr;          // PHY control, 0x90
 205 #define MIIWR                   (1<<27) // initialize a write sequence to PHY by setting
 206                                         // this bit to 1. This bit would be auto cleared
 207                                         // after the write operation is finished.
 208 #define MIIRD                   (1<<26)
 209 #define REGAD_MASK              (1<<25|1<<24|1<<23|1<<22|1<<21)
 210 #define PHYAD_MASK              (1<<20|1<<19|1<<18|1<<17|1<<16)
 211 #define MIIRDATA_MASK           0xffff
 212         unsigned int    phywdata;       // PHY write data, 0x94
 213 #define MIIWDATA_MASK           0xffff
 214         unsigned int    fcr;            // flow control, 0x98
 215 #define PAUSE_TIME_MASK         0xffff0000
 216 #define FC_HIGH_MASK            (1<<15|1<<14|1<<13|1<<12)
 217 #define FC_LOW_MASK             (1<<11|1<<10|1<<9|1<<8)
 218 #define RX_PAUSE                (1<<4)  // receive pause frame
 219 #define TXPAUSED                (1<<3)  // packet transmission is paused due to receive
 220                                         // pause frame
 221 #define FCTHR_EN                (1<<2)  // enable flow control threshold mode.
 222 #define TX_PAUSE                (1<<1)  // transmit pause frame
 223 #define FC_EN                   (1<<0)  // flow control mode enable
 224         unsigned int    bpr;            // back pressure, 0x9c
 225 #define BK_LOW_MASK             (1<<11|1<<10|1<<9|1<<8)
 226 #define BKJAM_LEN_MASK          (1<<7|1<<6|1<<5|1<<4)
 227 #define BK_MODE                 (1<<1)  // back pressure address mode
 228 #define BK_EN                   (1<<0)  // back pressure mode enable
 229         unsigned int    reserved2[9];   // 0xa0 - 0xc0
 230         unsigned int    ts;             // test seed, 0xc4
 231 #define TEST_SEED_MASK          0x3fff
 232         unsigned int    dmafifos;       // DMA/FIFO state, 0xc8
 233 #define TXD_REQ                 (1<<31) // TXDMA request
 234 #define RXD_REQ                 (1<<30) // RXDMA request
 235 #define DARB_TXGNT              (1<<29) // TXDMA grant
 236 #define DARB_RXGNT              (1<<28) // RXDMA grant
 237 #define TXFIFO_EMPTY            (1<<27) // TX FIFO is empty
 238 #define RXFIFO_EMPTY            (1<<26) // RX FIFO is empty
 239 #define TXDMA2_SM_MASK          (1<<14|1<<13|1<<12)
 240 #define TXDMA1_SM_MASK          (1<<11|1<<10|1<<9|1<<8)
 241 #define RXDMA2_SM_MASK          (1<<6|1<<5|1<<4)
 242 #define RXDMA1_SM_MASK          (1<<3|1<<2|1<<1|1<<0)
 243         unsigned int    tm;             // test mode, 0xcc
 244 #define SINGLE_PKT              (1<<26) // single packet mode
 245 #define PTIMER_TEST             (1<<25) // automatic polling timer test mode
 246 #define ITIMER_TEST             (1<<24) // interrupt timer test mode
 247 #define TEST_SEED_SEL           (1<<22) // test seed select
 248 #define SEED_SEL                (1<<21) // seed select
 249 #define TEST_MODE               (1<<20) // transmission test mode
 250 #define TEST_TIME_MASK          (1<<19|1<<18|1<<17|1<<16|1<<15|1<<14|1<<13|1<<12|1<<11|1<<10)
 251 #define TEST_EXCEL_MASK         (1<<9|1<<8|1<<7|1<<6|1<<5)
 252         unsigned int    reserved3;      // 0xd0
 253         unsigned int    txmcol_xscol;   // TX_MCOL and TX_SCOL counter, 0xd4
 254 #define TX_MCOL_MASK            0xffff0000
 255 #define TX_MCOL_SHIFT_BIT       16
 256 #define TX_SCOL_MASK            0xffff
 257 #define TX_SCOL_SHIFT_BIT       0
 258         unsigned int    rpf_aep;        // RPF and AEP counter, 0xd8
 259 #define RPF_MASK                0xffff0000
 260 #define RPF_SHIFT_BIT           16
 261 #define AEP_MASK                0xffff
 262 #define AEP_SHIFT_BIT           0
 263         unsigned int    xm_pg;          // XM and PG counter, 0xdc
 264 #define XM_MASK                 0xffff0000
 265 #define XM_SHIFT_BIT            16
 266 #define PG_MASK                 0xffff
 267 #define PG_SHIFT_BIT            0
 268         unsigned int    runtcnt_tlcc;   // RUNT_CNT and TLCC counter, 0xe0
 269 #define RUNT_CNT_MASK           0xffff0000
 270 #define RUNT_CNT_SHIFT_BIT      16
 271 #define TLCC_MASK               0xffff
 272 #define TLCC_SHIFT_BIT          0
 273         unsigned int    crcercnt_ftlcnt;        // CRCER_CNT and FTL_CNT counter, 0xe4
 274 #define CRCER_CNT_MASK          0xffff0000
 275 #define CRCER_CNT_SHIFT_BIT     16
 276 #define FTL_CNT_MASK            0xffff
 277 #define FTL_CNT_SHIFT_BIT       0
 278         unsigned int    rlc_rcc;        // RLC and RCC counter, 0xe8
 279 #define RLC_MASK                0xffff0000
 280 #define RLC_SHIFT_BIT           16
 281 #define RCC_MASK                0xffff
 282 #define RCC_SHIFT_BIT           0
 283         unsigned int    broc;           // BROC counter, 0xec
 284         unsigned int    mulca;          // MULCA counter, 0xf0
 285         unsigned int    rp;             // RP counter, 0xf4
 286         unsigned int    xp;             // XP counter, 0xf8
 287 } mac_control_reg_t;
 288
 289 #define ISR_REG_OFFSET                  0x00
 290 #define IMR_REG_OFFSET                  0x04
 291 #define MAC_MADR_REG_OFFSET             0x08
 292 #define MAC_LADR_REG_OFFSET             0x0C
 293 #define MATH0_REG_OFFSET                0x10
 294 #define MATH1_REG_OFFSET                0x14
 295 #define TXPD_REG_OFFSET                 0x18
 296 #define RXPD_REG_OFFSET                 0x1C
 297 #define TXR_BADR_REG_OFFSET             0x20
 298 #define RXR_BADR_REG_OFFSET             0x24
 299 #define ITC_REG_OFFSET                  0x28
 300 #define APTC_REG_OFFSET                 0x2C
 301 #define DBLAC_REG_OFFSET                0x30
 302 #define MACCR_REG_OFFSET                0x88
 303 #define MACSR_REG_OFFSET                0x8C
 304 #define PHYCR_REG_OFFSET                0x90
 305 #define PHYWDATA_REG_OFFSET             0x94
 306 #define FCR_REG_OFFSET                  0x98
 307 #define BPR_REG_OFFSET                  0x9C
 308 #define TS_REG_OFFSET                   0xC4
 309 #define DMAFIFOS_REG_OFFSET             0xC8
 310 #define TM_REG_OFFSET                   0xCC
 311 #define TX_MCOL_TX_SCOL_REG_OFFSET      0xD4
 312 #define RPF_AEP_REG_OFFSET              0xD8
 313 #define XM_PG_REG_OFFSET                0xDC
 314 #define RUNT_CNT_TLCC_REG_OFFSET        0xE0
 315 #define CRCER_CNT_FTL_CNT_REG_OFFSET    0xE4
 316 #define RLC_RCC_REG_OFFSET              0xE8
 317 #define BROC_REG_OFFSET                 0xEC
 318 #define MULCA_REG_OFFSET                0xF0
 319 #define RP_REG_OFFSET                   0xF4
 320 #define XP_REG_OFFSET                   0xF8
 321
 322 typedef struct mcpu_mac_priv_struct {
 323         unsigned int    phyTxDescBaseAddr;      // Tx descriptor physical base address
 324         tx_desc_t       *virtTxDescBaseAddr;    // Tx descriptor virtual base address
 325         unsigned int    phyRxDescBaseAddr;      // Rx descriptor physical base address
 326         rx_desc_t       *virtRxDescBaseAddr;    // Rx descriptor virtual base address
 327         unsigned int    phyTxBufBaseAddr;       // Tx buffer physical base address
 328         unsigned char   *virtTxBufBaseAddr;     // Tx buffer virtual base address
 329         unsigned int    phyRxBufBaseAddr;       // Rx buffer physical base address
 330         unsigned char   *virtRxBufBaseAddr;     // Rx buffer virtual base address
 331         int             TxDescNow;      // Tx descriptor now first used index
 332         int             RxDescNow;      // Rx descriptor now first used index
 333         struct net_device_stats stats;  // OS about the ethernet statistics
 334         spinlock_t      txlock;
 335         spinlock_t      rxlock;
 336         unsigned int    maccr;          // store the maccr control register value
 337 #if 1   // add by Victor Yu. 07-04-2005
 338         struct work_struct      rqueue;
 339 #endif
 340 } mcpu_mac_priv_t;
 341
 342 #endif  // MOXACPU_MAC_H