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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / net / wireless / rtlink / Module / rtmp_init.c
blob4e0e5f72d61d8efd7116fee647e75faec1b98eb5
1 /*************************************************************************
2 * Ralink Tech Inc. *
3 * 4F, No. 2 Technology 5th Rd. *
4 * Science-based Industrial Park *
5 * Hsin-chu, Taiwan, R.O.C. *
6 * *
7 * (c) Copyright 2002, Ralink Technology, Inc. *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 * *
24 *************************************************************************
25
26 Module Name:
27 rtmp_init.c
28
29 Abstract:
30 Miniport generic portion header file
31
32 Revision History:
33 Who When What
34 -------- ---------- ----------------------------------------------
35 Paul Lin 08-01-2002 created
36
37 */
38 #include "rt_config.h"
39
40 //
41 // BBP register initialization set
42 //
43 ULONG BBPRegTable[] = {
44 0x00018302, // R03
45 0x00018419, // R04
46 0x00018E1C, // R14
47 0x00018F30, // R15
48 0x000190ac, // R16
49 0x00019148, // R17
50 0x00019218, // R18
51 0x000193ff, // R19
52 0x0001941E, // R20
53 0x00019508, // R21
54 0x00019608, // R22
55 0x00019708, // R23
56 0x00019870, // R24
57 0x00019940, // R25
58 0x00019A08, // R26
59 0x00019B23, // R27
60 0x00019E10, // R30
61 0x00019F2B, // R31
62 0x0001A0B9, // R32
63 0x0001A212, // R34
64 0x0001A350, // R35
65 0x0001A7c4, // R39
66 0x0001A802, // R40
67 0x0001A960, // R41
68 0x0001B510, // R53
69 0x0001B618, // R54
70 0x0001B808, // R56
71 0x0001B910, // R57
72 0x0001BA08, // R58
73 0x0001BD6d, // R61
74 0x0001BE10, // R62
75 };
76
77 //
78 // MAC register initialization sets
79 //
80 RTMP_REG_PAIR MACRegTable[] = {
81 {PSCSR0, 0x00020002}, // 0xc8
82 {PSCSR1, 0x00000002}, // 0xcc
83 // {PSCSR2, 0x00023f20}, // 0xd0
84 {PSCSR2, 0x00020002}, // 0xd0
85 {PSCSR3, 0x00000002}, // 0xd4
86 {TIMECSR, 0x00003f21}, // 0xDC, to slower down our 1-us tick
87 {CSR9, 0x00000780}, // 0x24
88 {CSR11, 0x07041483}, // 0x2C, lrc=7, src=4, slot=20us, CWmax=2^8, CWmax=2^3
89 {CSR18, 0x00140000}, // SIFS=10us - TR switch time, PIFS=SIFS+20us
90 {CSR19, 0x016C0028}, // DIFS=SIFS+2*20us, EIFS=364us
91 {CNT3, 0x00000000}, // Backoff_CCA_Th, RX_&_TX_CCA_Th
92
93 {TXCSR1, 0x07614562}, // 0x64, ACK as 1Mb time
94 {TXCSR8, 0x8c8d8b8a}, // 0x98, CCK TX BBP register ID
95 //{TXCSR9, 0x86870885}, // 0x94, OFDM TX BBP register ID
96
97 {ARCSR1, 0x0000000f}, // 0x9c, Basic rate set bitmap
98 {PLCP1MCSR, 0x00700400}, // 0x13c, ACK/CTS PLCP at 1 Mbps
99 {PLCP2MCSR, 0x00380401}, // 0x140, ACK/CTS PLCP at 2 Mbps
100 {PLCP5MCSR, 0x00150402}, // 0x144, ACK/CTS PLCP at 5.5 Mbps
101 {PLCP11MCSR,0x000b8403}, // 0x148, ACK/CTS PLCP at 11 Mbps
102
103 {ARTCSR0, 0x7038140a}, // 0x14c, ACK/CTS payload consumed time for 1/2/5.5/11 mbps
104 {ARTCSR1, 0x1d21252d}, // 0x150, alexsu : OFDM ACK/CTS payload consumed time for 18/12/9/6 mbps
105 {ARTCSR2, 0x1919191d}, // 0x154, alexsu : OFDM ACK/CTS payload consumed time for 54/48/36/24 mbps
106
107 {RXCSR0, 0xffffffff}, // 0x80
108 {RXCSR3, 0xb3aab3af}, // 0x90. RT2530 BBP 51:RSSI, R42:OFDM rate, R47:CCK SIGNAL
109 {PCICSR, 0x000003b8}, // 0x8c, alexsu : PCI control register
110 {PWRCSR0, 0x3f3b3100}, // 0xC4
111 {GPIOCSR, 0x0000ff00}, // 0x120, GPIO default value
112 {TESTCSR, 0x000000f0}, // 0x138, Test CSR, make sure it's running at normal mode
113 {PWRCSR1, 0x000001ff}, // 0xd8
114 {MACCSR0, 0x00213223}, // 0xE0, Enable Tx dribble mode - 2003/10/22:Gary
115 {MACCSR1, 0x00235518}, // 0xE4, Disable Rx Reset, tx dribble count, 2x30x16 = 960n,
116 {MACCSR2, 0x00000040}, // 0x0134, 64*33ns = 2us
117 {RALINKCSR, 0x9a009a11}, // 0xE8
118 {CSR7, 0xffffffff}, // 0x1C, Clear all pending interrupt source
119 {LEDCSR, 0x00001E46}, // default both LEDs off
120 {BBPCSR1, 0x82188200}, // for 2560+2522
121 {TXACKCSR0, 0x00000020}, // 0x110, TX ACK timeout in usec
122 {SECCSR3, 0x0000e78f}, // AES, mask off more data bit for MIC calculation
123 };
124
125 #define NUM_BBP_REG_PARMS (sizeof(BBPRegTable) / sizeof(ULONG))
126 #define NUM_MAC_REG_PARMS (sizeof(MACRegTable) / sizeof(RTMP_REG_PAIR))
127
128 /*
129 ========================================================================
130
131 Routine Description:
132 Allocate all DMA releated resources
133
134 Arguments:
135 Adapter Pointer to our adapter
136
137 Return Value:
138 None
139
140 Note:
141
142 ========================================================================
143 */
144 NDIS_STATUS RTMPAllocDMAMemory(
145 IN PRTMP_ADAPTER pAd)
146 {
147 INT index;
148 VOID *ring; // VA of ring descriptor
149 VOID *ring_data; // VA of DMA data buffer
150 dma_addr_t ring_dma; // PA of ring descriptor
151 dma_addr_t ring_data_dma; // PA of DMA data buffer
152 PTXD_STRUC pTxD; // Tx type ring descriptor
153 PRXD_STRUC pRxD; // Rx type ring descriptor
154
155 DBGPRINT(RT_DEBUG_INFO, "--> RTMPAllocDMAMemory\n");
156
157 // 1. Allocate Tx Ring DMA descriptor and buffer memory
158 // Allocate Ring descriptors DMA block
159 ring = pci_alloc_consistent(pAd->pPci_Dev, (TX_RING_SIZE * RING_DESCRIPTOR_SIZE), &ring_dma);
160 if (!ring) {
161 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring descriptor memory.\n");
162 goto err_out_allocate_txring;
163 }
164
165 // Zero init ring descriptors
166 memset(ring, 0, (TX_RING_SIZE * RING_DESCRIPTOR_SIZE));
167
168 // Allocate Ring data DMA blocks
169 ring_data = pci_alloc_consistent(pAd->pPci_Dev, (TX_RING_SIZE * TX_BUFFER_SIZE), &ring_data_dma);
170
171 // If failed, release ring descriptors DMA block & exit
172 if (!ring_data) {
173 pci_free_consistent(pAd->pPci_Dev, (TX_RING_SIZE * RING_DESCRIPTOR_SIZE), ring, ring_dma);
174 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring buffer memory.\n");
175 goto err_out_allocate_txring;
176 }
177
178 // Start with Tx ring & DMA buffer
179 for (index = 0; index < TX_RING_SIZE; index++)
180 {
181 // Init Tx Ring Size, Va, Pa variables
182 pAd->TxRing[index].size = RING_DESCRIPTOR_SIZE;
183 pAd->TxRing[index].va_addr = ring;
184 pAd->TxRing[index].pa_addr = ring_dma;
185 ring += RING_DESCRIPTOR_SIZE;
186 ring_dma += RING_DESCRIPTOR_SIZE;
187
188 // Init Tx DMA buffer
189 pAd->TxRing[index].data_size = TX_BUFFER_SIZE;
190 pAd->TxRing[index].va_data_addr = ring_data;
191 pAd->TxRing[index].pa_data_addr = ring_data_dma;
192 ring_data += TX_BUFFER_SIZE;
193 ring_data_dma += TX_BUFFER_SIZE;
194
195 // Write TxD buffer address & allocated buffer length
196 pTxD = (PTXD_STRUC) pAd->TxRing[index].va_addr;
197 #ifndef BIG_ENDIAN
198 pTxD->BufferAddressPa = pAd->TxRing[index].pa_data_addr;
199 #else
200 pTxD->BufferAddressPa = SWAP32(pAd->TxRing[index].pa_data_addr);
201 #endif
202
203 DBGPRINT(RT_DEBUG_INFO, "TxRing[%d] va = 0x%lu, pa = 0x%x, size = 0x%x\n",
204 index, (unsigned long)pAd->TxRing[index].va_addr, (UINT)pAd->TxRing[index].pa_addr, pAd->TxRing[index].size);
205 DBGPRINT(RT_DEBUG_INFO, "TxRing[%d] va_data = 0x%lu, pa_data = 0x%x, size = 0x%x\n",
206 index, (unsigned long)pAd->TxRing[index].va_data_addr, (UINT)pAd->TxRing[index].pa_data_addr, pAd->TxRing[index].data_size);
207 }
208
209 // 2. Allocate Prio Ring DMA descriptor and buffer memory
210 // Allocate Ring descriptors DMA block
211 ring = pci_alloc_consistent(pAd->pPci_Dev, (PRIO_RING_SIZE * RING_DESCRIPTOR_SIZE), &ring_dma);
212 if (!ring) {
213 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring descriptor memory.\n");
214 goto err_out_allocate_prioring;
215 }
216
217 // Zero init ring descriptors
218 memset(ring, 0, (PRIO_RING_SIZE * RING_DESCRIPTOR_SIZE));
219
220 // Allocate Ring data DMA blocks
221 ring_data = pci_alloc_consistent(pAd->pPci_Dev, (PRIO_RING_SIZE * PRIO_BUFFER_SIZE), &ring_data_dma);
222
223 // If failed, release ring descriptors DMA block & exit
224 if (!ring_data) {
225 pci_free_consistent(pAd->pPci_Dev, (PRIO_RING_SIZE * RING_DESCRIPTOR_SIZE), ring, ring_dma);
226 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring buffer memory.\n");
227 goto err_out_allocate_prioring;
228 }
229
230 // Second with Prio ring & DMA buffer
231 for (index = 0; index < PRIO_RING_SIZE; index++)
232 {
233 // Init Prio Ring Size, Va, Pa variables
234 pAd->PrioRing[index].size = RING_DESCRIPTOR_SIZE;
235 pAd->PrioRing[index].va_addr = ring;
236 pAd->PrioRing[index].pa_addr = ring_dma;
237 ring += RING_DESCRIPTOR_SIZE;
238 ring_dma += RING_DESCRIPTOR_SIZE;
239
240 // Init Prio DMA buffer
241 pAd->PrioRing[index].data_size = PRIO_BUFFER_SIZE;
242 pAd->PrioRing[index].va_data_addr = ring_data;
243 pAd->PrioRing[index].pa_data_addr = ring_data_dma;
244 ring_data += PRIO_BUFFER_SIZE;
245 ring_data_dma += PRIO_BUFFER_SIZE;
246
247 // Write TxD buffer address & allocated buffer length for priority ring
248 pTxD = (PTXD_STRUC) pAd->PrioRing[index].va_addr;
249 #ifndef BIG_ENDIAN
250 pTxD->BufferAddressPa = pAd->PrioRing[index].pa_data_addr;
251 #else
252 pTxD->BufferAddressPa = SWAP32(pAd->PrioRing[index].pa_data_addr);
253 #endif
254
255 DBGPRINT(RT_DEBUG_INFO, "PrioRing[%d] va = 0x%lu, pa = 0x%x, size = 0x%x\n",
256 index, (unsigned long)pAd->PrioRing[index].va_addr, (UINT)pAd->PrioRing[index].pa_addr, pAd->PrioRing[index].size);
257 DBGPRINT(RT_DEBUG_INFO, "PrioRing[%d] va_data = 0x%lu, pa_data = 0x%x, size = 0x%x\n",
258 index, (unsigned long)pAd->PrioRing[index].va_data_addr, (UINT)pAd->PrioRing[index].pa_data_addr, pAd->PrioRing[index].data_size);
259 }
260
261 // 3. Allocate Atim Ring DMA descriptor and buffer memory
262 // Allocate Ring descriptors DMA block
263 ring = pci_alloc_consistent(pAd->pPci_Dev, (ATIM_RING_SIZE * RING_DESCRIPTOR_SIZE), &ring_dma);
264 if (!ring) {
265 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring descriptor memory.\n");
266 goto err_out_allocate_atimring;
267 }
268
269 // Zero init ring descriptors
270 memset(ring, 0, (ATIM_RING_SIZE * RING_DESCRIPTOR_SIZE));
271
272 // Allocate Ring data DMA blocks
273 ring_data = pci_alloc_consistent(pAd->pPci_Dev, (ATIM_RING_SIZE * ATIM_BUFFER_SIZE), &ring_data_dma);
274
275 // If failed, release ring descriptors DMA block & exit
276 if (!ring_data) {
277 pci_free_consistent(pAd->pPci_Dev, (ATIM_RING_SIZE * RING_DESCRIPTOR_SIZE), ring, ring_dma);
278 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring buffer memory.\n");
279 goto err_out_allocate_atimring;
280 }
281
282 // Atim ring & DMA buffer
283 for (index = 0; index < ATIM_RING_SIZE; index++)
284 {
285 // Init Atim Ring Size, Va, Pa variables
286 pAd->AtimRing[index].size = RING_DESCRIPTOR_SIZE;
287 pAd->AtimRing[index].va_addr = ring;
288 pAd->AtimRing[index].pa_addr = ring_dma;
289 ring += RING_DESCRIPTOR_SIZE;
290 ring_dma += RING_DESCRIPTOR_SIZE;
291
292 // Init Atim DMA buffer
293 pAd->AtimRing[index].data_size = ATIM_BUFFER_SIZE;
294 pAd->AtimRing[index].va_data_addr = ring_data;
295 pAd->AtimRing[index].pa_data_addr = ring_data_dma;
296 ring_data += ATIM_BUFFER_SIZE;
297 ring_data_dma += ATIM_BUFFER_SIZE;
298
299 // Write TxD buffer address & allocated buffer length
300 pTxD = (PTXD_STRUC) pAd->AtimRing[index].va_addr;
301 #ifndef BIG_ENDIAN
302 pTxD->BufferAddressPa = pAd->AtimRing[index].pa_data_addr;
303 #else
304 pTxD->BufferAddressPa = SWAP32(pAd->AtimRing[index].pa_data_addr);
305 #endif
306
307 DBGPRINT(RT_DEBUG_INFO, "AtimRing[%d] va = 0x%lu, pa = 0x%x, size = 0x%x\n",
308 index, (unsigned long)pAd->AtimRing[index].va_addr, (UINT)pAd->AtimRing[index].pa_addr, pAd->AtimRing[index].size);
309 DBGPRINT(RT_DEBUG_INFO, "AtimRing[%d] va_data = 0x%lu, pa_data = 0x%x, size = 0x%x\n",
310 index, (unsigned long)pAd->AtimRing[index].va_data_addr, (UINT)pAd->AtimRing[index].pa_data_addr, pAd->AtimRing[index].data_size);
311 }
312
313 // 4. Allocate Rx Ring DMA descriptor and buffer memory
314 // Allocate Ring descriptors DMA block
315 ring = pci_alloc_consistent(pAd->pPci_Dev, (RX_RING_SIZE * RING_DESCRIPTOR_SIZE), &ring_dma);
316 if (!ring) {
317 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring descriptor memory.\n");
318 goto err_out_allocate_rxring;
319 }
320
321 // Zero init ring descriptors
322 memset(ring, 0, (RX_RING_SIZE * RING_DESCRIPTOR_SIZE));
323
324 // Allocate Ring data DMA blocks
325 ring_data = pci_alloc_consistent(pAd->pPci_Dev, (RX_RING_SIZE * RX_BUFFER_SIZE), &ring_data_dma);
326
327 // If failed, release ring descriptors DMA block & exit
328 if (!ring_data) {
329 pci_free_consistent(pAd->pPci_Dev, (RX_RING_SIZE * RING_DESCRIPTOR_SIZE), ring, ring_dma);
330 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring buffer memory.\n");
331 goto err_out_allocate_rxring;
332 }
333
334 // Rx ring & DMA buffer
335 for (index = 0; index < RX_RING_SIZE; index++)
336 {
337 // Init Rx Ring Size, Va, Pa variables
338 pAd->RxRing[index].size = RING_DESCRIPTOR_SIZE;
339 pAd->RxRing[index].va_addr = ring;
340 pAd->RxRing[index].pa_addr = ring_dma;
341 ring += RING_DESCRIPTOR_SIZE;
342 ring_dma += RING_DESCRIPTOR_SIZE;
343
344 // Init Rx DMA buffer
345 pAd->RxRing[index].data_size = RX_BUFFER_SIZE;
346 pAd->RxRing[index].va_data_addr = ring_data;
347 pAd->RxRing[index].pa_data_addr = ring_data_dma;
348 ring_data += RX_BUFFER_SIZE;
349 ring_data_dma += RX_BUFFER_SIZE;
350
351 // Write RxD buffer address & allocated buffer length
352 pRxD = (PRXD_STRUC) pAd->RxRing[index].va_addr;
353 #ifndef BIG_ENDIAN
354 pRxD->BufferAddressPa = pAd->RxRing[index].pa_data_addr;
355 #else
356 pRxD->BufferAddressPa = SWAP32(pAd->RxRing[index].pa_data_addr);
357 #endif
358 // Rx owner bit assign to NIC immediately
359 pRxD->Owner = DESC_OWN_NIC;
360
361 #ifdef BIG_ENDIAN
362 RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
363 #endif
364
365 DBGPRINT(RT_DEBUG_INFO, "RxRing[%d] va = 0x%lu, pa = 0x%x, size = 0x%x\n",
366 index, (unsigned long)pAd->RxRing[index].va_addr, (UINT)pAd->RxRing[index].pa_addr, pAd->RxRing[index].size);
367 DBGPRINT(RT_DEBUG_INFO, "RxRing[%d] va_data = 0x%lu, pa_data = 0x%x, size = 0x%x\n",
368 index, (unsigned long)pAd->RxRing[index].va_data_addr, (UINT)pAd->RxRing[index].pa_data_addr, pAd->RxRing[index].data_size);
369 }
370
371 // 5. Allocate Beacon Ring DMA descriptor and buffer memory
372 // Init Beacon Ring Size, Va, Pa variables
373 ring = pci_alloc_consistent(pAd->pPci_Dev, RING_DESCRIPTOR_SIZE, &ring_dma);
374 if (!ring) {
375 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring descriptor memory.\n");
376 goto err_out_allocate_beaconring;
377 }
378
379 // Zero init ring descriptors
380 memset(ring, 0, (RING_DESCRIPTOR_SIZE));
381
382 // Allocate Ring data DMA blocks
383 ring_data = pci_alloc_consistent(pAd->pPci_Dev, BEACON_BUFFER_SIZE, &ring_data_dma);
384
385 // If failed, release ring descriptors DMA block & exit
386 if (!ring_data) {
387 pci_free_consistent(pAd->pPci_Dev, RING_DESCRIPTOR_SIZE, ring, ring_dma);
388 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring buffer memory.\n");
389 goto err_out_allocate_beaconring;
390 }
391
392 pAd->BeaconRing.size = RING_DESCRIPTOR_SIZE;
393 pAd->BeaconRing.va_addr = ring;
394 pAd->BeaconRing.pa_addr = ring_dma;
395
396 // Init Beacon DMA buffer
397 pAd->BeaconRing.data_size = BEACON_BUFFER_SIZE;
398 pAd->BeaconRing.va_data_addr = ring_data;
399 pAd->BeaconRing.pa_data_addr = ring_data_dma;
400
401 // Write RxD buffer address & allocated buffer length
402 pTxD = (PTXD_STRUC) pAd->BeaconRing.va_addr;
403 #ifndef BIG_ENDIAN
404 pTxD->BufferAddressPa = pAd->BeaconRing.pa_data_addr;
405 #else
406 pTxD->BufferAddressPa = SWAP32(pAd->BeaconRing.pa_data_addr);
407 #endif
408
409 DBGPRINT(RT_DEBUG_INFO, "BeaconRing va = 0x%lu, pa = 0x%x, size = 0x%x\n",
410 (unsigned long)pAd->BeaconRing.va_addr, (UINT)pAd->BeaconRing.pa_addr, pAd->BeaconRing.size);
411 DBGPRINT(RT_DEBUG_INFO, "BeaconRing va_data = 0x%lu, pa_data = 0x%x, size = 0x%x\n",
412 (unsigned long)pAd->BeaconRing.va_data_addr, (UINT)pAd->BeaconRing.pa_data_addr, pAd->BeaconRing.data_size);
413
414 DBGPRINT(RT_DEBUG_INFO, "<-- RTMPAllocDMAMemory\n");
415 return NDIS_STATUS_SUCCESS;
416
417
418 err_out_allocate_beaconring:
419 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
420 pci_free_consistent(pAd->pPci_Dev, (RX_RING_SIZE * RX_BUFFER_SIZE),
421 pAd->RxRing[0].va_data_addr, pAd->RxRing[0].pa_data_addr);
422 // Free ring descriptor second, the start address is the same as TxRing first elment
423 pci_free_consistent(pAd->pPci_Dev, (RX_RING_SIZE * RING_DESCRIPTOR_SIZE),
424 pAd->RxRing[0].va_addr, pAd->RxRing[0].pa_addr);
425 err_out_allocate_rxring:
426 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
427 pci_free_consistent(pAd->pPci_Dev, (ATIM_RING_SIZE * ATIM_BUFFER_SIZE),
428 pAd->AtimRing[0].va_data_addr, pAd->AtimRing[0].pa_data_addr);
429 // Free ring descriptor second, the start address is the same as TxRing first elment
430 pci_free_consistent(pAd->pPci_Dev, (ATIM_RING_SIZE * RING_DESCRIPTOR_SIZE),
431 pAd->AtimRing[0].va_addr, pAd->AtimRing[0].pa_addr);
432 err_out_allocate_atimring:
433 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
434 pci_free_consistent(pAd->pPci_Dev, (PRIO_RING_SIZE * PRIO_BUFFER_SIZE),
435 pAd->PrioRing[0].va_data_addr, pAd->PrioRing[0].pa_data_addr);
436 // Free ring descriptor second, the start address is the same as TxRing first elment
437 pci_free_consistent(pAd->pPci_Dev, (PRIO_RING_SIZE * RING_DESCRIPTOR_SIZE),
438 pAd->PrioRing[0].va_addr, pAd->PrioRing[0].pa_addr);
439 err_out_allocate_prioring:
440 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
441 pci_free_consistent(pAd->pPci_Dev, (TX_RING_SIZE * TX_BUFFER_SIZE),
442 pAd->TxRing[0].va_data_addr, pAd->TxRing[0].pa_data_addr);
443 // Free ring descriptor second, the start address is the same as TxRing first elment
444 pci_free_consistent(pAd->pPci_Dev, (TX_RING_SIZE * RING_DESCRIPTOR_SIZE),
445 pAd->TxRing[0].va_addr, pAd->TxRing[0].pa_addr);
446 err_out_allocate_txring:
447 DBGPRINT(RT_DEBUG_ERROR, "<-- RTMPAllocDMAMemory (memory not allocate successfully!)\n");
448
449 return -ENOMEM;
450 }
451
452 /*
453 ========================================================================
454
455 Routine Description:
456 Free all DMA memory.
457
458 Arguments:
459 Adapter Pointer to our adapter
460
461 Return Value:
462 None
463
464 Note:
465
466 ========================================================================
467 */
468 VOID RTMPFreeDMAMemory(
469 IN PRTMP_ADAPTER pAd)
470 {
471 DBGPRINT(RT_DEBUG_INFO, "--> RTMPFreeDMAMemory\n");
472
473 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
474 pci_free_consistent(pAd->pPci_Dev, (TX_RING_SIZE * TX_BUFFER_SIZE),
475 pAd->TxRing[0].va_data_addr, pAd->TxRing[0].pa_data_addr);
476 // Free ring descriptor second, the start address is the same as TxRing first elment
477 pci_free_consistent(pAd->pPci_Dev, (TX_RING_SIZE * RING_DESCRIPTOR_SIZE),
478 pAd->TxRing[0].va_addr, pAd->TxRing[0].pa_addr);
479
480 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
481 pci_free_consistent(pAd->pPci_Dev, (PRIO_RING_SIZE * PRIO_BUFFER_SIZE),
482 pAd->PrioRing[0].va_data_addr, pAd->PrioRing[0].pa_data_addr);
483 // Free ring descriptor second, the start address is the same as TxRing first elment
484 pci_free_consistent(pAd->pPci_Dev, (PRIO_RING_SIZE * RING_DESCRIPTOR_SIZE),
485 pAd->PrioRing[0].va_addr, pAd->PrioRing[0].pa_addr);
486
487 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
488 pci_free_consistent(pAd->pPci_Dev, (ATIM_RING_SIZE * ATIM_BUFFER_SIZE),
489 pAd->AtimRing[0].va_data_addr, pAd->AtimRing[0].pa_data_addr);
490 // Free ring descriptor second, the start address is the same as TxRing first elment
491 pci_free_consistent(pAd->pPci_Dev, (ATIM_RING_SIZE * RING_DESCRIPTOR_SIZE),
492 pAd->AtimRing[0].va_addr, pAd->AtimRing[0].pa_addr);
493
494 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
495 pci_free_consistent(pAd->pPci_Dev, (RX_RING_SIZE * RX_BUFFER_SIZE),
496 pAd->RxRing[0].va_data_addr, pAd->RxRing[0].pa_data_addr);
497 // Free ring descriptor second, the start address is the same as TxRing first elment
498 pci_free_consistent(pAd->pPci_Dev, (RX_RING_SIZE * RING_DESCRIPTOR_SIZE),
499 pAd->RxRing[0].va_addr, pAd->RxRing[0].pa_addr);
500
501 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
502 pci_free_consistent(pAd->pPci_Dev, (BEACON_RING_SIZE * BEACON_BUFFER_SIZE),
503 pAd->BeaconRing.va_data_addr, pAd->BeaconRing.pa_data_addr);
504 // Free ring descriptor second, the start address is the same as TxRing first elment
505 pci_free_consistent(pAd->pPci_Dev, (BEACON_RING_SIZE * RING_DESCRIPTOR_SIZE),
506 pAd->BeaconRing.va_addr, pAd->BeaconRing.pa_addr);
507
508 }
509
510 /*
511 ========================================================================
512
513 Routine Description:
514 Initialize transmit data structures
515
516 Arguments:
517 Adapter Pointer to our adapter
518
519 Return Value:
520 None
521
522 Note:
523 Initialize all transmit releated private buffer, include those define
524 in RTMP_ADAPTER structure and all private data structures.
525
526 ========================================================================
527 */
528 VOID NICInitTransmit(
529 IN PRTMP_ADAPTER pAdapter)
530 {
531 DBGPRINT(RT_DEBUG_TRACE, "--> NICInitTransmit\n");
532
533 // Initialize all Transmit releated queues
534 InitializeQueueHeader(&pAdapter->TxSwQueue0);
535 InitializeQueueHeader(&pAdapter->TxSwQueue1);
536 InitializeQueueHeader(&pAdapter->TxSwQueue2);
537 InitializeQueueHeader(&pAdapter->TxSwQueue3);
538
539 // Init Ring index pointer
540 pAdapter->CurRxIndex = 0;
541 pAdapter->CurDecryptIndex = 0;
542 pAdapter->CurTxIndex = 0;
543 pAdapter->CurEncryptIndex = 0;
544 pAdapter->CurAtimIndex = 0;
545 pAdapter->CurPrioIndex = 0;
546 pAdapter->NextEncryptDoneIndex = 0;
547 pAdapter->NextTxDoneIndex = 0;
548 pAdapter->NextAtimDoneIndex = 0;
549 pAdapter->NextPrioDoneIndex = 0;
550 pAdapter->NextDecryptDoneIndex = 0;
551 pAdapter->PushMgmtIndex = 0;
552 pAdapter->PopMgmtIndex = 0;
553 pAdapter->MgmtQueueSize = 0;
554
555 pAdapter->PrivateInfo.TxRingFullCnt = 0;
556
557 DBGPRINT(RT_DEBUG_TRACE, "<-- NICInitTransmit\n");
558 }
559
560 // By removing 'inline' directive from the function definitions.
561 // Then Driverloader is compiled and runs smooth after kernel 2.6.9
562 #ifdef BIG_ENDIAN
563 inline VOID
564 #else
565 VOID
566 #endif
567 NICDisableInterrupt(
568 IN PRTMP_ADAPTER pAd)
569 {
570 RTMP_IO_WRITE32(pAd, CSR8, 0xFFFF);
571 RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE);
572 }
573
574
575 #ifdef BIG_ENDIAN
576 inline VOID
577 #else
578 VOID
579 #endif
580 NICEnableInterrupt(
581 IN PRTMP_ADAPTER pAd)
582 {
583 // 0xFF37 : Txdone & Rxdone, 0xFF07: Txdonw, Rxdone, PrioDone, AtimDone,
584 RTMP_IO_WRITE32(pAd, CSR8, 0xFE14);
585 RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE);
586 }
587
588 /*
589 ========================================================================
590
591 Routine Description:
592 Read additional information from EEPROM, such as MAC address
593
594 Arguments:
595 Adapter Pointer to our adapter
596
597 Return Value:
598 NDIS_STATUS_SUCCESS
599 NDIS_STATUS_FAILURE
600
601 Note:
602
603 ========================================================================
604 */
605 NDIS_STATUS NICReadAdapterInfo(
606 IN PRTMP_ADAPTER pAd)
607 {
608 CSR3_STRUC StaMacReg0;
609 CSR4_STRUC StaMacReg1;
610 NDIS_STATUS Status = NDIS_STATUS_SUCCESS;
611
612 //
613 // Read MAC address from CSR3 & CSR4, these CSRs reflects real value
614 // stored with EEPROM.
615 //
616 RTMP_IO_READ32(pAd, CSR3, &StaMacReg0.word);
617 RTMP_IO_READ32(pAd, CSR4, &StaMacReg1.word);
618 // Set Current address
619 pAd->CurrentAddress[0] = StaMacReg0.field.Byte0;
620 pAd->CurrentAddress[1] = StaMacReg0.field.Byte1;
621 pAd->CurrentAddress[2] = StaMacReg0.field.Byte2;
622 pAd->CurrentAddress[3] = StaMacReg0.field.Byte3;
623 pAd->CurrentAddress[4] = StaMacReg1.field.Byte4;
624 pAd->CurrentAddress[5] = StaMacReg1.field.Byte5;
625 pAd->PermanentAddress[0] = StaMacReg0.field.Byte0;
626 pAd->PermanentAddress[1] = StaMacReg0.field.Byte1;
627 pAd->PermanentAddress[2] = StaMacReg0.field.Byte2;
628 pAd->PermanentAddress[3] = StaMacReg0.field.Byte3;
629 pAd->PermanentAddress[4] = StaMacReg1.field.Byte4;
630 pAd->PermanentAddress[5] = StaMacReg1.field.Byte5;
631
632 return Status;
633 }
634
635 /*
636 ========================================================================
637
638 Routine Description:
639 Read initial parameters from EEPROM
640
641 Arguments:
642 Adapter Pointer to our adapter
643
644 Return Value:
645 None
646
647 Note:
648
649 ========================================================================
650 */
651 VOID NICReadEEPROMParameters(
652 IN PRTMP_ADAPTER pAdapter)
653 {
654 ULONG data;
655 USHORT i, value;
656 UCHAR TmpPhy;
657 EEPROM_TX_PWR_STRUC Power;
658 EEPROM_VERSION_STRUC Version;
659 EEPROM_ANTENNA_STRUC Antenna;
660
661 DBGPRINT(RT_DEBUG_TRACE, "--> NICReadEEPROMParameters\n");
662
663 // Init EEPROM Address Number, before access EEPROM; if 93c46, EEPROMAddressNum=6, else if 93c66, EEPROMAddressNum=8
664 RTMP_IO_READ32(pAdapter, CSR21, &data);
665
666 if(data & 0x20)
667 pAdapter->EEPROMAddressNum = 6;
668 else
669 pAdapter->EEPROMAddressNum = 8;
670
671 // if E2PROM version mismatch with driver's expectation, then skip
672 // all subsequent E2RPOM retieval and set a system error bit to notify GUI
673 Version.word = RTMP_EEPROM_READ16(pAdapter, EEPROM_VERSION_OFFSET);
674 if (Version.field.Version != VALID_EEPROM_VERSION)
675 {
676 DBGPRINT(RT_DEBUG_ERROR, "WRONG E2PROM VERSION %d, should be %d\n",Version.field.Version, VALID_EEPROM_VERSION);
677 pAdapter->PortCfg.SystemErrorBitmap |= 0x00000001;
678 return;
679 }
680
681 // Read BBP default value from EEPROM and store to array(EEPROMDefaultValue) in pAdapter
682 for(i = 0; i < NUM_EEPROM_BBP_PARMS; i++)
683 {
684 value = RTMP_EEPROM_READ16(pAdapter, EEPROM_BBP_BASE_OFFSET + i*2);
685
686 pAdapter->EEPROMDefaultValue[i] = value;
687 }
688
689 #if 1
690 // We have to parse NIC configuration 0 at here.
691 // If TSSI did not have preloaded value, it should reset the TxAutoAgc to false
692 // Therefore, we have to read TxAutoAgc control beforehand.
693 // Read Tx AGC control bit
694 Antenna.word = pAdapter->EEPROMDefaultValue[0];
695 if (Antenna.field.DynamicTxAgcControl == 1)
696 pAdapter->PortCfg.bAutoTxAgc = TRUE;
697 else
698 pAdapter->PortCfg.bAutoTxAgc = FALSE;
699
700 // Read Tx power value for all 14 channels
701 // Value from 1 - 0x7f. Default value is 24.
702 for (i = 0; i < NUM_EEPROM_TX_PARMS; i++)
703 {
704 Power.word = RTMP_EEPROM_READ16(pAdapter, EEPROM_TX_PWR_OFFSET + i*2);
705 pAdapter->PortCfg.ChannelTxPower[i * 2] = ((Power.field.Byte0 > 32) ? 24 : Power.field.Byte0);
706 pAdapter->PortCfg.ChannelTxPower[i * 2 + 1] = ((Power.field.Byte1 > 32) ? 24 : Power.field.Byte1);
707 }
708
709 // Read Tx TSSI reference value, OK to reuse Power data structure
710 for (i = 0; i < NUM_EEPROM_TX_PARMS; i++)
711 {
712 Power.word = RTMP_EEPROM_READ16(pAdapter, EEPROM_TSSI_REF_OFFSET + i * 2);
713 pAdapter->PortCfg.ChannelTssiRef[i * 2] = Power.field.Byte0;
714 pAdapter->PortCfg.ChannelTssiRef[i * 2 + 1] = Power.field.Byte1;
715 // Disable TxAgc if the value is not right
716 if ((pAdapter->PortCfg.ChannelTssiRef[i * 2] == 0xff) ||
717 (pAdapter->PortCfg.ChannelTssiRef[i * 2 + 1] == 0xff))
718 pAdapter->PortCfg.bAutoTxAgc = FALSE;
719 }
720
721 // Tx Tssi delta offset 0x24
722 Power.word = RTMP_EEPROM_READ16(pAdapter, EEPROM_TSSI_DELTA_OFFSET);
723 pAdapter->PortCfg.ChannelTssiDelta = Power.field.Byte0;
724
725 #endif
726
727 //CountryRegion byte offset = 0x35
728 value = pAdapter->EEPROMDefaultValue[2] >> 8;
729 if ((value <= 7))
730 {
731 pAdapter->PortCfg.CountryRegion = (UCHAR) value;
732 TmpPhy = pAdapter->PortCfg.PhyMode;
733 pAdapter->PortCfg.PhyMode = 0xff;
734 RTMPSetPhyMode(pAdapter, TmpPhy);
735 }
736 // Read new Calibrated CV value, reuse the power variable
737 Power.word = RTMP_EEPROM_READ16(pAdapter, EEPROM_CALIBRATE_OFFSET);
738 if (Power.field.Byte0 == 0xff)
739 {
740 //pAdapter->PortCfg.R17Dec = 0;
741 pAdapter->PortCfg.RssiToDbm = 0x79;
742 }
743 else
744 {
745 //pAdapter->PortCfg.R17Dec = 0x79 - Power.field.Byte0;
746 pAdapter->PortCfg.RssiToDbm = Power.field.Byte0;
747 }
748
749 DBGPRINT(RT_DEBUG_TRACE, "<-- NICReadEEPROMParameters, pAdapter->PortCfg.RssiToDbm = %d\n", pAdapter->PortCfg.RssiToDbm);
750 }
751
752 /*
753 ========================================================================
754
755 Routine Description:
756 Set default value from EEPROM
757
758 Arguments:
759 Adapter Pointer to our adapter
760
761 Return Value:
762 None
763
764 Note:
765
766 ========================================================================
767 */
768 VOID NICInitAsicFromEEPROM(
769 IN PRTMP_ADAPTER pAdapter)
770 {
771 ULONG data, BbpCsr1;
772 USHORT i, value;
773 UCHAR TxValue,RxValue;
774 EEPROM_ANTENNA_STRUC Antenna;
775 EEPROM_NIC_CONFIG2_STRUC NicConfig2;
776
777 DBGPRINT(RT_DEBUG_TRACE, "--> NICInitAsicFromEEPROM\n");
778
779 for(i = 3; i < NUM_EEPROM_BBP_PARMS; i++)
780 {
781 value = pAdapter->EEPROMDefaultValue[i];
782
783 if((value != 0xFFFF) && (value != 0))
784 {
785 data = value | 0x18000;
786 RTMP_BBP_IO_WRITE32(pAdapter, data);
787 }
788 }
789
790 Antenna.word = pAdapter->EEPROMDefaultValue[0];
791
792 if ((Antenna.word == 0xFFFF) || (Antenna.field.TxDefaultAntenna > 2) || (Antenna.field.RxDefaultAntenna > 2))
793 {
794 DBGPRINT(RT_DEBUG_TRACE, "E2PROM error(=0x%04x), hard code as 0x0002\n", Antenna.word);
795 Antenna.word = 0x0002;
796 }
797
798 pAdapter->PortCfg.NumberOfAntenna = 2; // (UCHAR)Antenna.field.NumOfAntenna;
799 pAdapter->PortCfg.CurrentTxAntenna = (UCHAR)Antenna.field.TxDefaultAntenna;
800 pAdapter->PortCfg.CurrentRxAntenna = (UCHAR)Antenna.field.RxDefaultAntenna;
801 pAdapter->PortCfg.RfType = (UCHAR) Antenna.field.RfType;
802
803 RTMP_BBP_IO_READ32_BY_REG_ID(pAdapter, BBP_Tx_Configure, &TxValue);
804 RTMP_BBP_IO_READ32_BY_REG_ID(pAdapter, BBP_Rx_Configure, &RxValue);
805 RTMP_IO_READ32(pAdapter, BBPCSR1, &BbpCsr1);
806
807 // Tx antenna select
808 if(Antenna.field.TxDefaultAntenna == 1) // Antenna A
809 {
810 TxValue = (TxValue & 0xFC) | 0x00;
811 BbpCsr1 = (BbpCsr1 & 0xFFFCFFFC) | 0x00000000;
812 }
813 else if(Antenna.field.TxDefaultAntenna == 2) // Antenna B
814 {
815 TxValue = (TxValue & 0xFC) | 0x02;
816 BbpCsr1 = (BbpCsr1 & 0xFFFCFFFC) | 0x00020002;
817 }
818 else // diverity - start from Antenna B
819 {
820 TxValue = (TxValue & 0xFC) | 0x02;
821 BbpCsr1 = (BbpCsr1 & 0xFFFCFFFC) | 0x00020002;
822 }
823
824 // Rx antenna select
825 if(Antenna.field.RxDefaultAntenna == 1) // Antenna A
826 RxValue = (RxValue & 0xFC) | 0x00;
827 else if(Antenna.field.RxDefaultAntenna == 2) // Antenna B
828 RxValue = (RxValue & 0xFC) | 0x02;
829 else // Antenna Diversity
830 RxValue = (RxValue & 0xFC) | 0x02;
831
832 // RT5222 needs special treatment to swap TX I/Q
833 if (pAdapter->PortCfg.RfType == RFIC_5222)
834 {
835 BbpCsr1 |= 0x00040004;
836 TxValue |= 0x04; // TX I/Q flip
837 }
838 // RT2525E need to flip TX I/Q but not RX I/Q
839 else if (pAdapter->PortCfg.RfType == RFIC_2525E)
840 {
841 BbpCsr1 |= 0x00040004;
842 TxValue |= 0x04; // TX I/Q flip
843 RxValue &= 0xfb; // RX I/Q no flip
844 }
845
846 // Change to match microsoft definition, 0xff: diversity, 0: A, 1: B
847 pAdapter->PortCfg.CurrentTxAntenna--;
848 pAdapter->PortCfg.CurrentRxAntenna--;
849
850 RTMP_IO_WRITE32(pAdapter, BBPCSR1, BbpCsr1);
851 RTMP_BBP_IO_WRITE32_BY_REG_ID(pAdapter, BBP_Tx_Configure, TxValue);
852 RTMP_BBP_IO_WRITE32_BY_REG_ID(pAdapter, BBP_Rx_Configure, RxValue);
853
854 // 2003-12-16 software-based RX antenna diversity
855 // pAdapter->PortCfg.CurrentRxAntenna = 0xff; // Diversity ON
856 AsicSetRxAnt(pAdapter);
857
858 if (Antenna.field.LedMode == LED_MODE_TXRX_ACTIVITY)
859 pAdapter->PortCfg.LedMode = LED_MODE_TXRX_ACTIVITY;
860 else if (Antenna.field.LedMode == LED_MODE_SINGLE)
861 {
862 pAdapter->PortCfg.LedMode = LED_MODE_SINGLE;
863 ASIC_LED_ACT_ON(pAdapter);
864 }
865 else if (Antenna.field.LedMode == LED_MODE_ASUS)
866 {
867 pAdapter->PortCfg.LedMode = LED_MODE_ASUS;
868 RTMP_IO_WRITE32(pAdapter, LEDCSR, 0x0002461E);
869 }
870 else
871 pAdapter->PortCfg.LedMode = LED_MODE_DEFAULT;
872
873 // Read Hardware controlled Radio state enable bit
874 if (Antenna.field.HardwareRadioControl == 1)
875 {
876 pAdapter->PortCfg.bHardwareRadio = TRUE;
877
878 // Read GPIO pin0 as Hardware controlled radio state
879 RTMP_IO_READ32(pAdapter, GPIOCSR, &data);
880 if ((data & 0x01) == 0)
881 {
882 pAdapter->PortCfg.bHwRadio = FALSE;
883 pAdapter->PortCfg.bRadio = FALSE;
884 RTMP_IO_WRITE32(pAdapter, PWRCSR0, 0x00000000);
885 RTMP_SET_FLAG(pAdapter, fRTMP_ADAPTER_RADIO_OFF);
886 if (pAdapter->PortCfg.LedMode == LED_MODE_ASUS)
887 {
888 // Turn bit 17 for Radio OFF
889 RTMP_IO_WRITE32(pAdapter, LEDCSR, 0x0000461E);
890 }
891 }
892 }
893 else
894 pAdapter->PortCfg.bHardwareRadio = FALSE;
895
896 NicConfig2.word = pAdapter->EEPROMDefaultValue[1];
897 if (NicConfig2.word == 0xffff)
898 NicConfig2.word = 0; // empty E2PROM, use default
899
900 // for dynamic BBP R17:RX sensibility tuning
901 {
902 UCHAR r17;
903 RTMP_BBP_IO_READ32_BY_REG_ID(pAdapter, 17, &r17);
904 pAdapter->PortCfg.BbpTuningEnable = (NicConfig2.field.DynamicBbpTuning==0)? 1:0;
905 pAdapter->PortCfg.VgcLowerBound = r17;
906
907 // 2004-3-4 per David's request, R7 starts at upper bound
908 pAdapter->PortCfg.BbpTuning.VgcUpperBound = BBP_R17_DYNAMIC_UP_BOUND;
909 r17 = pAdapter->PortCfg.BbpTuning.VgcUpperBound;
910 pAdapter->PortCfg.LastR17Value = r17;
911 RTMP_BBP_IO_WRITE32_BY_REG_ID(pAdapter, 17, r17);
912
913 // 2004-2-2 per David's request, lower R17 low-bound for very good quality NIC
914 pAdapter->PortCfg.VgcLowerBound -= 6;
915 DBGPRINT(RT_DEBUG_TRACE,"R17 tuning enable=%d, R17=0x%02x, range=<0x%02x, 0x%02x>\n",
916 pAdapter->PortCfg.BbpTuningEnable, r17, pAdapter->PortCfg.VgcLowerBound, pAdapter->PortCfg.BbpTuning.VgcUpperBound);
917 }
918
919 DBGPRINT(RT_DEBUG_TRACE, "RF IC=%d, LED mode=%d\n", pAdapter->PortCfg.RfType, pAdapter->PortCfg.LedMode);
920
921 DBGPRINT(RT_DEBUG_TRACE, "<-- NICInitAsicFromEEPROM\n");
922 }
923
924 void NICInitializeAdapter(IN PRTMP_ADAPTER pAdapter)
925 {
926 TXCSR2_STRUC TxCSR2;
927 RXCSR1_STRUC RxCSR1;
928 ULONG Value;
929
930 DBGPRINT(RT_DEBUG_TRACE, "--> NICInitializeAdapter\n");
931
932 // Init spin locks
933 NdisAllocateSpinLock(&pAdapter->TxRingLock);
934 NdisAllocateSpinLock(&pAdapter->PrioRingLock);
935 NdisAllocateSpinLock(&pAdapter->AtimRingLock);
936 NdisAllocateSpinLock(&pAdapter->RxRingLock);
937 NdisAllocateSpinLock(&pAdapter->TxSwQueueLock);
938 NdisAllocateSpinLock(&pAdapter->MemLock);
939
940 // Write TXCSR2 register
941 TxCSR2.field.TxDSize = RING_DESCRIPTOR_SIZE;
942 TxCSR2.field.NumTxD = TX_RING_SIZE;
943 TxCSR2.field.NumAtimD = ATIM_RING_SIZE;
944 TxCSR2.field.NumPrioD = PRIO_RING_SIZE;
945 RTMP_IO_WRITE32(pAdapter, TXCSR2, TxCSR2.word);
946
947 // Write TXCSR3 register
948 Value = pAdapter->TxRing[0].pa_addr;
949 RTMP_IO_WRITE32(pAdapter, TX_RING_BASE_REG, Value);
950
951 // Write TXCSR4 register
952 Value = pAdapter->PrioRing[0].pa_addr;
953 RTMP_IO_WRITE32(pAdapter, PRIO_RING_BASE_REG, Value);
954
955 // Write TXCSR5 register
956 Value = pAdapter->AtimRing[0].pa_addr;
957 RTMP_IO_WRITE32(pAdapter, ATIM_RING_BASE_REG, Value);
958
959 // Write TXCSR6 register
960 Value = pAdapter->BeaconRing.pa_addr;
961 RTMP_IO_WRITE32(pAdapter, BEACON_BASE_REG, Value);
962
963 // Write RXCSR1 register
964 RxCSR1.field.RxDSize = RING_DESCRIPTOR_SIZE;
965 RxCSR1.field.NumRxD = RX_RING_SIZE;
966 RTMP_IO_WRITE32(pAdapter, RXCSR1, RxCSR1.word);
967
968 // Write RXCSR2 register
969 Value = pAdapter->RxRing[0].pa_addr;
970 RTMP_IO_WRITE32(pAdapter, RX_RING_BASE_REG, Value);
971
972 // Write CSR1 for host ready
973 // Move Host reay to end of ASIC initialization
974 // to ensure no Rx will perform before ASIC init
975 // RTMP_IO_WRITE32(pAdapter, CSR1, 0x4);
976
977 // Initialze ASIC for TX & Rx operation
978 NICInitializeAsic(pAdapter);
979
980 DBGPRINT(RT_DEBUG_TRACE, "<-- NICInitializeAdapter\n");
981 }
982
983 void NICInitializeAsic(IN PRTMP_ADAPTER pAdapter)
984 {
985 ULONG Index;
986 UCHAR Value = 0xff;
987
988 DBGPRINT(RT_DEBUG_TRACE, "--> NICInitializeAsic\n");
989
990 // Initialize MAC register to default value
991 for (Index = 0; Index < NUM_MAC_REG_PARMS; Index++)
992 {
993 RTMP_IO_WRITE32(pAdapter, MACRegTable[Index].Register, MACRegTable[Index].Value);
994 }
995
996 // Set Host ready before kicking Rx
997 RTMP_IO_WRITE32(pAdapter, CSR1, 0x1); // reset MAC state machine, requested by Kevin 2003-2-11
998 RTMP_IO_WRITE32(pAdapter, CSR1, 0x4);
999
1000 // Read BBP register, make sure BBP is up and running before write new data
1001 while ((Value == 0xff) || (Value == 0x00))
1002 {
1003 RTMP_BBP_IO_READ32_BY_REG_ID(pAdapter, BBP_Version, &Value);
1004 DBGPRINT(RT_DEBUG_TRACE, "Value = %d\n", Value);
1005 }
1006
1007 // Initialize BBP register to default value
1008 for (Index = 0; Index < NUM_BBP_REG_PARMS; Index++)
1009 {
1010 RTMP_BBP_IO_WRITE32(pAdapter, BBPRegTable[Index]);
1011 }
1012
1013 // Initialize RF register to default value
1014 AsicSwitchChannel(pAdapter, pAdapter->PortCfg.Channel);
1015 AsicLockChannel(pAdapter, pAdapter->PortCfg.Channel);
1016
1017 // Add radio off control
1018 if (pAdapter->PortCfg.bRadio == FALSE)
1019 {
1020 RTMP_IO_WRITE32(pAdapter, PWRCSR0, 0x00000000);
1021 RTMP_SET_FLAG(pAdapter, fRTMP_ADAPTER_RADIO_OFF);
1022 }
1023
1024 // Kick Rx
1025 RTMP_IO_WRITE32(pAdapter, RXCSR0, 0x7e);
1026 // Clear old FCS jitter before init ASIC
1027 RTMP_IO_READ32(pAdapter, CNT0, &Index);
1028 // Clear old Rx FIFO error jitter before init ASIC
1029 RTMP_IO_READ32(pAdapter, CNT4, &Index);
1030
1031 DBGPRINT(RT_DEBUG_TRACE, "<-- NICInitializeAsic\n");
1032 }
1033
1034 /*
1035 ========================================================================
1036
1037 Routine Description:
1038 Reset NIC Asics
1039
1040 Arguments:
1041 Adapter Pointer to our adapter
1042
1043 Return Value:
1044 None
1045
1046 Note:
1047 Reset NIC to initial state AS IS system boot up time.
1048
1049 ========================================================================
1050 */
1051 VOID NICIssueReset(
1052 IN PRTMP_ADAPTER pAdapter)
1053 {
1054 CSR3_STRUC StaMacReg0;
1055 CSR4_STRUC StaMacReg1;
1056
1057 DBGPRINT(RT_DEBUG_TRACE, "--> NICIssueReset\n");
1058
1059 // Abort Tx, prevent ASIC from writing to Host memory
1060 RTMP_IO_WRITE32(pAdapter, TXCSR0, 0x08);
1061
1062 // Disable Rx, register value supposed will remain after reset
1063 RTMP_IO_WRITE32(pAdapter, RXCSR0, 0x01);
1064
1065 if (pAdapter->PortCfg.bLocalAdminMAC)
1066 {
1067 // Write Back Permanent MAC address to CSR3 & CSR4
1068 StaMacReg0.field.Byte0 = pAdapter->PermanentAddress[0];
1069 StaMacReg0.field.Byte1 = pAdapter->PermanentAddress[1];
1070 StaMacReg0.field.Byte2 = pAdapter->PermanentAddress[2];
1071 StaMacReg0.field.Byte3 = pAdapter->PermanentAddress[3];
1072 StaMacReg1.field.Byte4 = pAdapter->PermanentAddress[4];
1073 StaMacReg1.field.Byte5 = pAdapter->PermanentAddress[5];
1074 RTMP_IO_WRITE32(pAdapter, CSR3, StaMacReg0.word);
1075 RTMP_IO_WRITE32(pAdapter, CSR4, StaMacReg1.word);
1076 }
1077
1078 // Issue reset and clear from reset state
1079 RTMP_IO_WRITE32(pAdapter, CSR1, 0x01);
1080 RTMP_IO_WRITE32(pAdapter, CSR1, 0x00);
1081
1082 DBGPRINT(RT_DEBUG_TRACE, "<-- NICIssueReset\n");
1083 }
1084
1085 /*
1086 ========================================================================
1087
1088 Routine Description:
1089 Check ASIC registers and find any reason the system might hang
1090
1091 Arguments:
1092 Adapter Pointer to our adapter
1093
1094 Return Value:
1095 None
1096
1097 Note:
1098
1099
1100 ========================================================================
1101 */
1102 BOOLEAN NICCheckForHang(
1103 IN PRTMP_ADAPTER pAd)
1104 {
1105 // garbage collection
1106 // if ((pAd->RalinkCounters.EncryptCount - pAd->RalinkCounters.TxDoneCount) == TX_RING_SIZE)
1107 // {
1108 // DBGPRINT(RT_DEBUG_WARNING,"\nNICCheckForHang --- Garbage Collection!!!\n\n");
1109 // }
1110
1111 {
1112 RTMPHandleTxRingTxDoneInterrupt(pAd);
1113 RTMPHandleEncryptionDoneInterrupt(pAd);
1114 }
1115
1116 return (FALSE);
1117 }
1118
1119 /*
1120 ========================================================================
1121
1122 Routine Description:
1123 Reset NIC from error
1124
1125 Arguments:
1126 Adapter Pointer to our adapter
1127
1128 Return Value:
1129 None
1130
1131 Note:
1132 Reset NIC from error state
1133
1134 ========================================================================
1135 */
1136 VOID NICResetFromError(
1137 IN PRTMP_ADAPTER pAdapter)
1138 {
1139 // Reset BBP (according to alex, reset ASIC will force reset BBP
1140 // Therefore, skip the reset BBP
1141 // RTMP_IO_WRITE32(pAdapter, CSR1, 0x2);
1142 // Release BBP reset
1143 // RTMP_IO_WRITE32(pAdapter, CSR1, 0x0);
1144
1145 RTMP_IO_WRITE32(pAdapter, CSR1, 0x1);
1146 // Remove ASIC from reset state
1147 RTMP_IO_WRITE32(pAdapter, CSR1, 0x0);
1148
1149 // Init send data structures and related parameters
1150 NICInitTransmit(pAdapter);
1151
1152 NICInitializeAdapter(pAdapter);
1153 NICInitAsicFromEEPROM(pAdapter);
1154
1155 // Switch to current channel, since during reset process, the connection should remains on.
1156 AsicSwitchChannel(pAdapter, pAdapter->PortCfg.Channel);
1157 AsicLockChannel(pAdapter, pAdapter->PortCfg.Channel);
1158 }
1159 /*
1160 ========================================================================
1161
1162 Routine Description:
1163 Verify section is valid for Get key parameter.
1164
1165 Arguments:
1166 buffer Pointer to the buffer to start find the key section
1167 ptr pointer to section
1168
1169 Return Value:
1170 TRUE Success
1171 FALSE Fail
1172 ========================================================================
1173 */
1174 INT RTMPIsFindSection(
1175 IN PUCHAR ptr,
1176 IN PUCHAR buffer)
1177 {
1178 if(ptr == buffer)
1179 return TRUE;
1180 else if (ptr > buffer)
1181 {
1182 while (ptr > buffer)
1183 {
1184 ptr--;
1185 if( *ptr == 0x0a)
1186 return TRUE;
1187 else if( (*ptr == ' ') || (*ptr == '\t'))
1188 continue;
1189 else
1190 return FALSE;
1191 }
1192 return TRUE;
1193 }
1194
1195 return FALSE;
1196 }
1197 /*
1198 ========================================================================
1199
1200 Routine Description:
1201 Find key section for Get key parameter.
1202
1203 Arguments:
1204 buffer Pointer to the buffer to start find the key section
1205 section the key of the secion to be find
1206
1207 Return Value:
1208 NULL Fail
1209 Others Success
1210 ========================================================================
1211 */
1212 PUCHAR RTMPFindSection(
1213 IN PCHAR buffer,
1214 IN PCHAR section)
1215 {
1216 CHAR temp_buf[255];
1217 PUCHAR ptr;
1218
1219 strcpy(temp_buf, "["); /* and the opening bracket [ */
1220 strcat(temp_buf, section);
1221 strcat(temp_buf, "]");
1222
1223 if((ptr = rtstrstr(buffer, temp_buf)) != NULL)
1224 {
1225 if(RTMPIsFindSection(ptr, buffer))
1226 return (ptr+strlen("\n"));
1227 else
1228 return NULL;
1229 }
1230 else
1231 return NULL;
1232 }
1233 /**
1234 * strstr - Find the first substring in a %NUL terminated string
1235 * @s1: The string to be searched
1236 * @s2: The string to search for
1237 */
1238 char * rtstrstr(const char * s1,const char * s2)
1239 {
1240 int l1, l2;
1241
1242 l2 = strlen(s2);
1243 if (!l2)
1244 return (char *) s1;
1245 l1 = strlen(s1);
1246 while (l1 >= l2) {
1247 l1--;
1248 if (!memcmp(s1,s2,l2))
1249 return (char *) s1;
1250 s1++;
1251 }
1252 return NULL;
1253 }
1254 /*
1255 ========================================================================
1256
1257 Routine Description:
1258 Get key parameter.
1259
1260 Arguments:
1261 section the key of the secion
1262 key Pointer to key string
1263 dest Pointer to destination
1264 destsize The datasize of the destination
1265 buffer Pointer to the buffer to start find the key
1266
1267 Return Value:
1268 TRUE Success
1269 FALSE Fail
1270
1271 Note:
1272 This routine get the value with the matched key (case case-sensitive)
1273 ========================================================================
1274 */
1275 INT RTMPGetKeyParameter(
1276 IN PUCHAR section,
1277 IN PCHAR key,
1278 OUT PCHAR dest,
1279 IN INT destsize,
1280 IN PCHAR buffer)
1281 {
1282 char temp_buf1[600];
1283 char temp_buf2[600];
1284 char *start_ptr;
1285 char *end_ptr;
1286 char *ptr;
1287 char *too_far_ptr;
1288 char *offset;
1289 int len;
1290
1291 //find section
1292 if((offset = RTMPFindSection(buffer, section)) == NULL)
1293 return (FALSE);
1294
1295 strcpy(temp_buf1, "\n");
1296 strcat(temp_buf1, key);
1297 strcat(temp_buf1, "=");
1298
1299 //search key
1300 if((start_ptr=rtstrstr(offset, temp_buf1))==NULL)
1301 return FALSE;
1302
1303 start_ptr+=strlen("\n");
1304 if((too_far_ptr=rtstrstr(offset+1, "["))==NULL)
1305 too_far_ptr=offset+strlen(offset);
1306
1307 if((end_ptr=rtstrstr(start_ptr, "\n"))==NULL)
1308 end_ptr=start_ptr+strlen(start_ptr);
1309
1310 if (too_far_ptr<start_ptr)
1311 return FALSE;
1312
1313 memcpy(temp_buf2, start_ptr, end_ptr-start_ptr);
1314 temp_buf2[end_ptr-start_ptr]='\0';
1315 len = strlen(temp_buf2);
1316 strcpy(temp_buf1, temp_buf2);
1317 if((start_ptr=rtstrstr(temp_buf1, "=")) == NULL)
1318 return FALSE;
1319
1320 strcpy(temp_buf2, start_ptr+1);
1321 ptr = temp_buf2;
1322 //trim space or tab
1323 while(*ptr != 0x00)
1324 {
1325 if( (*ptr == ' ') || (*ptr == '\t') )
1326 ptr++;
1327 else
1328 break;
1329 }
1330
1331 len = strlen(ptr);
1332 memset(dest, 0x00, destsize);
1333 strncpy(dest, ptr, len >= destsize ? destsize: len);
1334
1335 return TRUE;
1336 }
1337 /*
1338 ========================================================================
1339
1340 Routine Description:
1341 In kernel mode read parameters from file
1342
1343 Arguments:
1344 src the location of the file.
1345 dest put the parameters to the destination.
1346 Length size to read.
1347
1348 Return Value:
1349 None
1350
1351 Note:
1352
1353 ========================================================================
1354 */
1355
1356 VOID RTMPReadParametersFromFile(
1357 IN PRTMP_ADAPTER pAd)
1358 {
1359 PUCHAR src;
1360 struct file *srcf;
1361 INT retval, orgfsuid, orgfsgid;
1362 mm_segment_t orgfs;
1363 CHAR buffer[MAX_INI_BUFFER_SIZE];
1364 CHAR tmpbuf[255];
1365 UCHAR keyMaterial[40];
1366 UCHAR Channel;
1367 ULONG ulInfo;
1368 RT_802_11_PREAMBLE Preamble;
1369 int KeyLen;
1370 int i;
1371 BOOLEAN bIsHex = TRUE;
1372 ULONG rate_mapping[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54}; //according to README
1373
1374 src = PROFILE_PATH;
1375
1376 // Save uid and gid used for filesystem access.
1377 // Set user and group to 0 (root)
1378 orgfsuid = current->fsuid;
1379 orgfsgid = current->fsgid;
1380 current->fsuid=current->fsgid = 0;
1381 orgfs = get_fs();
1382 set_fs(KERNEL_DS);
1383
1384 if (src && *src)
1385 {
1386 srcf = filp_open(src, O_RDONLY, 0);
1387 if (IS_ERR(srcf))
1388 {
1389 DBGPRINT(RT_DEBUG_TRACE, "--> Error %ld opening %s\n", -PTR_ERR(srcf),src);
1390 }
1391 else
1392 {
1393 /* The object must have a read method */
1394 if (srcf->f_op && srcf->f_op->read)
1395 {
1396 memset(buffer, 0x00, MAX_INI_BUFFER_SIZE);
1397 retval=srcf->f_op->read(srcf, buffer, MAX_INI_BUFFER_SIZE, &srcf->f_pos);
1398 if (retval < 0)
1399 {
1400 DBGPRINT(RT_DEBUG_TRACE, "--> Read %s error %d\n", src, -retval);
1401 }
1402 else
1403 {
1404 // set file parameter to portcfg
1405 //CountryRegion
1406 if (RTMPGetKeyParameter("Default", "CountryRegion", tmpbuf, 255, buffer))
1407 {
1408 ulInfo = simple_strtol(tmpbuf, 0, 10);
1409 if ((ulInfo >= REGION_MIN) && (ulInfo <= REGION_MAX) )
1410 {
1411 pAd->PortCfg.CountryRegion = (UCHAR) ulInfo;
1412 DBGPRINT(RT_DEBUG_TRACE, "%s::(CountryRegion=%d)\n", __FUNCTION__, pAd->PortCfg.CountryRegion);
1413 }
1414 }
1415 //SSID
1416 memset(tmpbuf, 0x00, 255);
1417 if (RTMPGetKeyParameter("Default", "SSID", tmpbuf, 32, buffer))
1418 {
1419 pAd->PortCfg.SsidLen = (UCHAR) strlen(tmpbuf);
1420 memcpy(pAd->PortCfg.Ssid, tmpbuf, pAd->PortCfg.SsidLen);
1421
1422 pAd->Mlme.CntlAux.SsidLen = pAd->PortCfg.SsidLen;
1423 memcpy(pAd->Mlme.CntlAux.Ssid, tmpbuf, pAd->Mlme.CntlAux.SsidLen);
1424
1425 DBGPRINT(RT_DEBUG_TRACE, "%s::(SSID=%s Len=%d)\n", __FUNCTION__, tmpbuf, pAd->PortCfg.SsidLen);
1426 }
1427 //NetworkType
1428 if (RTMPGetKeyParameter("Default", "NetworkType", tmpbuf, 255, buffer))
1429 {
1430 pAd->bConfigChanged = TRUE;
1431 if (strcmp(tmpbuf, "Adhoc") == 0)
1432 pAd->PortCfg.BssType = BSS_INDEP;
1433 else //Default Infrastructure mode
1434 pAd->PortCfg.BssType = BSS_INFRA;
1435 // Reset Ralink supplicant to not use, it will be set to start when UI set PMK key
1436 pAd->PortCfg.WpaState = SS_NOTUSE;
1437 DBGPRINT(RT_DEBUG_TRACE, "%s::(NetworkType=%d)\n", __FUNCTION__, pAd->PortCfg.BssType);
1438 }
1439 //WirelessMode
1440 if (RTMPGetKeyParameter("Default", "WirelessMode", tmpbuf, 10, buffer))
1441 {
1442 ulInfo = simple_strtol(tmpbuf, 0, 10);
1443 if ((ulInfo == PHY_11BG_MIXED) || (ulInfo == PHY_11B) ||
1444 (ulInfo == PHY_11A) || (ulInfo == PHY_11ABG_MIXED))
1445 {
1446 RTMPSetPhyMode(pAd, ulInfo);
1447 DBGPRINT(RT_DEBUG_TRACE, "%s::(WirelessMode=%d)\n", __FUNCTION__, ulInfo);
1448 }
1449 }
1450 //TxRate
1451 if (RTMPGetKeyParameter("Default", "TxRate", tmpbuf, 10, buffer))
1452 {
1453 ulInfo = simple_strtol(tmpbuf, 0, 10);
1454 {
1455 if (ulInfo == 0)
1456 RTMPSetDesiredRates(pAd, -1);
1457 else
1458 RTMPSetDesiredRates(pAd, (LONG) (rate_mapping[ulInfo-1] * 1000000));
1459
1460 DBGPRINT(RT_DEBUG_TRACE, "%s::(TxRate=%d)\n", __FUNCTION__, ulInfo);
1461 }
1462 }
1463 //Channel
1464 if (RTMPGetKeyParameter("Default", "Channel", tmpbuf, 10, buffer))
1465 {
1466 Channel = (UCHAR) simple_strtol(tmpbuf, 0, 10);
1467 if (ChannelSanity(pAd, Channel) == TRUE)
1468 {
1469 pAd->PortCfg.Channel = Channel;
1470 // If default profile in Registry is an ADHOC network, driver should use the specified channel
1471 // number when starting IBSS the first time, because RaConfig is passive and will not set this
1472 // via OID_802_11_CONFIGURATION upon driver bootup.
1473 pAd->PortCfg.IbssConfig.Channel = pAd->PortCfg.Channel;
1474 DBGPRINT(RT_DEBUG_TRACE, "%s::(Channel=%d)\n", __FUNCTION__, Channel);
1475 }
1476 }
1477 //BGProtection
1478 if (RTMPGetKeyParameter("Default", "BGProtection", tmpbuf, 10, buffer))
1479 {
1480 switch (simple_strtol(tmpbuf, 0, 10))
1481 {
1482 case 1: //Always On
1483 pAd->PortCfg.UseBGProtection = 1;
1484 break;
1485 case 2: //Always OFF
1486 pAd->PortCfg.UseBGProtection = 2;
1487 break;
1488 case 0: //AUTO
1489 default:
1490 pAd->PortCfg.UseBGProtection = 0;
1491 break;
1492 }
1493 DBGPRINT(RT_DEBUG_TRACE, "%s::(BGProtection=%d)\n", __FUNCTION__, pAd->PortCfg.UseBGProtection);
1494 }
1495 //StaWithEtherBridge
1496 if (RTMPGetKeyParameter("Default", "StaWithEtherBridge", tmpbuf, 10, buffer))
1497 {
1498 switch (simple_strtol(tmpbuf, 0, 10))
1499 {
1500 case 0: //Off
1501 pAd->PortCfg.StaWithEtherBridge.Enable = FALSE;
1502 break;
1503 case 1: //On
1504 pAd->PortCfg.StaWithEtherBridge.Enable = TRUE;
1505 break;
1506 default:
1507 pAd->PortCfg.StaWithEtherBridge.Enable = FALSE;
1508 break;
1509 }
1510 DBGPRINT(RT_DEBUG_TRACE, "%s::(StaWithEtherBridge=%d)\n", __FUNCTION__, pAd->PortCfg.StaWithEtherBridge.Enable);
1511 }
1512 //TxPreamble
1513 if (RTMPGetKeyParameter("Default", "TxPreamble", tmpbuf, 10, buffer))
1514 {
1515 Preamble = simple_strtol(tmpbuf, 0, 10);
1516 switch (Preamble)
1517 {
1518 case Rt802_11PreambleShort:
1519 pAd->PortCfg.WindowsTxPreamble = Preamble;
1520 MlmeSetTxPreamble(pAd, Rt802_11PreambleShort);
1521 break;
1522 case Rt802_11PreambleLong:
1523 case Rt802_11PreambleAuto:
1524 default:
1525 // if user wants AUTO, initialize to LONG here, then change according to AP's
1526 // capability upon association.
1527 pAd->PortCfg.WindowsTxPreamble = Preamble;
1528 MlmeSetTxPreamble(pAd, Rt802_11PreambleLong);
1529 }
1530 DBGPRINT(RT_DEBUG_TRACE, "%s::(TxPreamble=%d)\n", __FUNCTION__, Preamble);
1531 }
1532 //RTSThreshold
1533 if (RTMPGetKeyParameter("Default", "RTSThreshold", tmpbuf, 10, buffer))
1534 {
1535 ulInfo = simple_strtol(tmpbuf, 0, 10);
1536
1537 if((ulInfo > 0) && (ulInfo <= MAX_RTS_THRESHOLD))
1538 pAd->PortCfg.RtsThreshold = (USHORT)ulInfo;
1539 else
1540 pAd->PortCfg.RtsThreshold = MAX_RTS_THRESHOLD;
1541
1542 DBGPRINT(RT_DEBUG_TRACE, "%s::(RTSThreshold=%d)\n", __FUNCTION__, pAd->PortCfg.RtsThreshold);
1543 }
1544 //FragThreshold
1545 if (RTMPGetKeyParameter("Default", "FragThreshold", tmpbuf, 10, buffer))
1546 {
1547 ulInfo = simple_strtol(tmpbuf, 0, 10);
1548
1549 if ( (ulInfo >= MIN_FRAG_THRESHOLD) && (ulInfo <= MAX_FRAG_THRESHOLD))
1550 pAd->PortCfg.FragmentThreshold = (USHORT)ulInfo;
1551 else
1552 pAd->PortCfg.FragmentThreshold = MAX_FRAG_THRESHOLD;
1553
1554 if (pAd->PortCfg.FragmentThreshold == MAX_FRAG_THRESHOLD)
1555 pAd->PortCfg.bFragmentZeroDisable = TRUE;
1556 else
1557 pAd->PortCfg.bFragmentZeroDisable = FALSE;
1558
1559 DBGPRINT(RT_DEBUG_TRACE, "%s::(FragThreshold=%d)\n", __FUNCTION__, ulInfo);
1560 }
1561 //AdhocOfdm
1562 if (RTMPGetKeyParameter("Default", "AdhocOfdm", tmpbuf, 10, buffer))
1563 {
1564 ulInfo = simple_strtol(tmpbuf, 0, 10);
1565
1566 if (ulInfo == 1)
1567 pAd->PortCfg.AdhocMode = 1;
1568 else
1569 pAd->PortCfg.AdhocMode = 0;
1570
1571 DBGPRINT(RT_DEBUG_TRACE, "%s::(AdhocOfdm=%d)\n", __FUNCTION__, pAd->PortCfg.AdhocMode);
1572 }
1573 //TxBurst
1574 if (RTMPGetKeyParameter("Default", "TxBurst", tmpbuf, 10, buffer))
1575 {
1576 ulInfo = simple_strtol(tmpbuf, 0, 10);
1577
1578 if (ulInfo == 1)
1579 pAd->PortCfg.EnableTxBurst = TRUE;
1580 else
1581 pAd->PortCfg.EnableTxBurst = FALSE;
1582
1583 DBGPRINT(RT_DEBUG_TRACE, "%s::(TxBurst=%d)\n", __FUNCTION__, pAd->PortCfg.EnableTxBurst);
1584 }
1585 //TurboRate
1586 if (RTMPGetKeyParameter("Default", "TurboRate", tmpbuf, 10, buffer))
1587 {
1588 ulInfo = simple_strtol(tmpbuf, 0, 10);
1589
1590 if (ulInfo == 1)
1591 pAd->PortCfg.EnableTurboRate = TRUE;
1592 else
1593 pAd->PortCfg.EnableTurboRate = FALSE;
1594
1595 DBGPRINT(RT_DEBUG_TRACE, "%s::(TurboRate=%d)\n", __FUNCTION__, pAd->PortCfg.EnableTurboRate);
1596 }
1597 //ShortSlot
1598 if (RTMPGetKeyParameter("Default", "ShortSlot", tmpbuf, 10, buffer))
1599 {
1600 ulInfo = simple_strtol(tmpbuf, 0, 10);
1601
1602 if (ulInfo == 1)
1603 pAd->PortCfg.UseShortSlotTime = TRUE;
1604 else
1605 pAd->PortCfg.UseShortSlotTime = FALSE;
1606
1607 DBGPRINT(RT_DEBUG_TRACE, "%s::(ShortSlot=%d)\n", __FUNCTION__, pAd->PortCfg.UseShortSlotTime);
1608 }
1609 //POWER_MODE
1610 if (RTMPGetKeyParameter("Default", "PSMode", tmpbuf, 10, buffer))
1611 {
1612 if (pAd->PortCfg.BssType == BSS_INFRA)
1613 {
1614 if ((strcmp(tmpbuf, "MAX_PSP") == 0) || (strcmp(tmpbuf, "max_psp") == 0))
1615 {
1616 // do NOT turn on PSM bit here, wait until MlmeCheckForPsmChange()
1617 // to exclude certain situations.
1618 // MlmeSetPsmBit(pAdapter, PWR_SAVE);
1619 if (pAd->PortCfg.WindowsACCAMEnable == FALSE)
1620 pAd->PortCfg.WindowsPowerMode = Ndis802_11PowerModeMAX_PSP;
1621 pAd->PortCfg.WindowsBatteryPowerMode = Ndis802_11PowerModeMAX_PSP;
1622 pAd->PortCfg.RecvDtim = TRUE; // FALSE;
1623 pAd->PortCfg.DefaultListenCount = 5;
1624 }
1625 else if ((strcmp(tmpbuf, "Fast_PSP") == 0) || (strcmp(tmpbuf, "fast_psp") == 0)
1626 || (strcmp(tmpbuf, "FAST_PSP") == 0))
1627 {
1628 // do NOT turn on PSM bit here, wait until MlmeCheckForPsmChange()
1629 // to exclude certain situations.
1630 // MlmeSetPsmBit(pAdapter, PWR_SAVE);
1631 pAd->PortCfg.RecvDtim = TRUE;
1632 if (pAd->PortCfg.WindowsACCAMEnable == FALSE)
1633 pAd->PortCfg.WindowsPowerMode = Ndis802_11PowerModeFast_PSP;
1634 pAd->PortCfg.WindowsBatteryPowerMode = Ndis802_11PowerModeFast_PSP;
1635 pAd->PortCfg.DefaultListenCount = 3;
1636 }
1637 else
1638 { //Default Ndis802_11PowerModeCAM
1639 // clear PSM bit immediately
1640 MlmeSetPsmBit(pAd, PWR_ACTIVE);
1641 pAd->PortCfg.RecvDtim = TRUE;
1642 if (pAd->PortCfg.WindowsACCAMEnable == FALSE)
1643 pAd->PortCfg.WindowsPowerMode = Ndis802_11PowerModeCAM;
1644 pAd->PortCfg.WindowsBatteryPowerMode = Ndis802_11PowerModeCAM;
1645 }
1646 DBGPRINT(RT_DEBUG_TRACE, "%s::(PSMode=%d)\n", __FUNCTION__, pAd->PortCfg.WindowsPowerMode);
1647 }
1648 }
1649 //AuthMode
1650 if (RTMPGetKeyParameter("Default", "AuthMode", tmpbuf, 10, buffer))
1651 {
1652 if ((strcmp(tmpbuf, "SHARED") == 0) || (strcmp(tmpbuf, "shared") == 0))
1653 pAd->PortCfg.AuthMode = Ndis802_11AuthModeShared;
1654 else if ((strcmp(tmpbuf, "WPAPSK") == 0) || (strcmp(tmpbuf, "wpapsk") == 0))
1655 pAd->PortCfg.AuthMode = Ndis802_11AuthModeWPAPSK;
1656 else if ((strcmp(tmpbuf, "AUTO") == 0) || (strcmp(tmpbuf, "auto") == 0))
1657 pAd->PortCfg.AuthMode = Ndis802_11AuthModeAutoSwitch;
1658 else if ((strcmp(tmpbuf, "WPANONE") == 0) || (strcmp(tmpbuf, "wpanone") == 0))
1659 pAd->PortCfg.AuthMode = Ndis802_11AuthModeWPANone;
1660 else
1661 pAd->PortCfg.AuthMode = Ndis802_11AuthModeOpen;
1662
1663 pAd->PortCfg.PortSecured = WPA_802_1X_PORT_NOT_SECURED;
1664 DBGPRINT(RT_DEBUG_TRACE, "%s::(AuthMode=%d)\n", __FUNCTION__, pAd->PortCfg.AuthMode);
1665 }
1666 //EncrypType
1667 if (RTMPGetKeyParameter("Default", "EncrypType", tmpbuf, 10, buffer))
1668 {
1669 if ((strcmp(tmpbuf, "WEP") == 0) || (strcmp(tmpbuf, "wep") == 0))
1670 pAd->PortCfg.WepStatus = Ndis802_11WEPEnabled;
1671 else if ((strcmp(tmpbuf, "TKIP") == 0) || (strcmp(tmpbuf, "tkip") == 0))
1672 pAd->PortCfg.WepStatus = Ndis802_11Encryption2Enabled;
1673 else if ((strcmp(tmpbuf, "AES") == 0) || (strcmp(tmpbuf, "aes") == 0))
1674 pAd->PortCfg.WepStatus = Ndis802_11Encryption3Enabled;
1675 else
1676 pAd->PortCfg.WepStatus = Ndis802_11WEPDisabled;
1677
1678 DBGPRINT(RT_DEBUG_TRACE, "%s::(EncrypType=%d)\n", __FUNCTION__, pAd->PortCfg.WepStatus);
1679 }
1680 //WPAPSK_KEY
1681 if (RTMPGetKeyParameter("Default", "WPAPSK", tmpbuf, 255, buffer))
1682 {
1683 if ((strlen(tmpbuf) >= 8) && (strlen(tmpbuf) < 64))
1684 {
1685 PasswordHash((char *)tmpbuf, pAd->PortCfg.Ssid, pAd->PortCfg.SsidLen, keyMaterial);
1686 NdisMoveMemory(pAd->PortCfg.PskKey.Key, keyMaterial, 32);
1687 // Use RaConfig as PSK agent.
1688 // Start STA supplicant state machine
1689 pAd->PortCfg.WpaState = SS_START;
1690 #if 0
1691 DBGPRINT(RT_DEBUG_TRACE, "%s WPAPSK Key => \n", __FUNCTION__);
1692 for (i = 0; i < 32; i++)
1693 {
1694 DBGPRINT(RT_DEBUG_TRACE, "%02x:", pAd->PortCfg.PskKey.Key[i]);
1695 if (i%16 == 15)
1696 DBGPRINT(RT_DEBUG_TRACE, "\n");
1697 }
1698 DBGPRINT(RT_DEBUG_TRACE, "\n");
1699 #endif
1700 }
1701 else if (strlen(tmpbuf) == 64)
1702 {
1703 AtoH(tmpbuf, pAd->PortCfg.PskKey.Key, 32);
1704 pAd->PortCfg.WpaState = SS_START;
1705 }
1706 }
1707 //DefaultKeyID
1708 if (RTMPGetKeyParameter("Default", "DefaultKeyID", tmpbuf, 10, buffer))
1709 {
1710 ulInfo = simple_strtol(tmpbuf, 0, 10);
1711 if((ulInfo >= 1 ) && (ulInfo <= 4))
1712 pAd->PortCfg.DefaultKeyId = (UCHAR) (ulInfo - 1 );
1713 else
1714 pAd->PortCfg.DefaultKeyId = 0;
1715
1716 DBGPRINT(RT_DEBUG_TRACE, "%s::(DefaultKeyID=%d)\n", __FUNCTION__, pAd->PortCfg.DefaultKeyId);
1717 }
1718 //Key1Str
1719 if (RTMPGetKeyParameter("Default", "Key1Str", tmpbuf, 26, buffer))
1720 {
1721 KeyLen = strlen(tmpbuf);
1722 switch (KeyLen)
1723 {
1724 case 0:
1725 pAd->PortCfg.SharedKey[0].KeyLen = 0;
1726 break;
1727 case 5: //wep 40 Ascii type
1728 pAd->PortCfg.SharedKey[0].KeyLen = KeyLen;
1729 memcpy(pAd->PortCfg.SharedKey[0].Key, tmpbuf, KeyLen);
1730 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key1=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Ascii");
1731 case 10: //wep 40 Hex type
1732 for(i=0; i < KeyLen; i++)
1733 {
1734 if( !isxdigit(*(tmpbuf+i)) )
1735 {
1736 bIsHex = FALSE;
1737 break;
1738 }
1739 }
1740
1741 if (bIsHex)
1742 {
1743 pAd->PortCfg.SharedKey[0].KeyLen = KeyLen / 2 ;
1744 AtoH(tmpbuf, pAd->PortCfg.SharedKey[0].Key, KeyLen / 2);
1745 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key1=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Hex");
1746 }
1747 break;
1748 case 13: //wep 104 Ascii type
1749 pAd->PortCfg.SharedKey[0].KeyLen = KeyLen;
1750 memcpy(pAd->PortCfg.SharedKey[0].Key, tmpbuf, KeyLen);
1751 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key1=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Ascii");
1752 break;
1753 case 26: //wep 104 Hex type
1754 for(i=0; i < KeyLen; i++)
1755 {
1756 if( !isxdigit(*(tmpbuf+i)) )
1757 {
1758 bIsHex = FALSE;
1759 break;
1760 }
1761 }
1762
1763 if (bIsHex)
1764 {
1765 pAd->PortCfg.SharedKey[0].KeyLen = KeyLen / 2 ;
1766 AtoH(tmpbuf, pAd->PortCfg.SharedKey[0].Key, KeyLen / 2);
1767 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key1=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Hex");
1768 }
1769 break;
1770 default:
1771 pAd->PortCfg.SharedKey[0].KeyLen = 0;
1772 DBGPRINT(RT_DEBUG_TRACE, "%s::Invalid Key (=%s)\n", __FUNCTION__, tmpbuf);
1773 }
1774 }
1775 //Key2Str
1776 if (RTMPGetKeyParameter("Default", "Key2Str", tmpbuf, 26, buffer))
1777 {
1778 KeyLen = strlen(tmpbuf);
1779 switch (KeyLen)
1780 {
1781 case 0:
1782 pAd->PortCfg.SharedKey[1].KeyLen = 0;
1783 break;
1784 case 5: //wep 40 Ascii type
1785 pAd->PortCfg.SharedKey[1].KeyLen = KeyLen;
1786 memcpy(pAd->PortCfg.SharedKey[1].Key, tmpbuf, KeyLen);
1787 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key2=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Ascii");
1788 case 10: //wep 40 Hex type
1789 for(i=0; i < KeyLen; i++)
1790 {
1791 if( !isxdigit(*(tmpbuf+i)) )
1792 {
1793 bIsHex = FALSE;
1794 break;
1795 }
1796 }
1797
1798 if (bIsHex)
1799 {
1800 pAd->PortCfg.SharedKey[1].KeyLen = KeyLen / 2 ;
1801 AtoH(tmpbuf, pAd->PortCfg.SharedKey[1].Key, KeyLen / 2);
1802 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key2=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Hex");
1803 }
1804 break;
1805 case 13: //wep 104 Ascii type
1806 pAd->PortCfg.SharedKey[1].KeyLen = KeyLen;
1807 memcpy(pAd->PortCfg.SharedKey[1].Key, tmpbuf, KeyLen);
1808 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key2=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Ascii");
1809 break;
1810 case 26: //wep 104 Hex type
1811 for(i=0; i < KeyLen; i++)
1812 {
1813 if( !isxdigit(*(tmpbuf+i)) )
1814 {
1815 bIsHex = FALSE;
1816 break;
1817 }
1818 }
1819
1820 if (bIsHex)
1821 {
1822 pAd->PortCfg.SharedKey[1].KeyLen = KeyLen / 2 ;
1823 AtoH(tmpbuf, pAd->PortCfg.SharedKey[1].Key, KeyLen / 2);
1824 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key2=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Hex");
1825 }
1826 break;
1827 default:
1828 pAd->PortCfg.SharedKey[1].KeyLen = 0;
1829 DBGPRINT(RT_DEBUG_TRACE, "%s::Invalid argument (=%s)\n", __FUNCTION__, tmpbuf);
1830 }
1831 }
1832 //Key3Str
1833 if (RTMPGetKeyParameter("Default", "Key3Str", tmpbuf, 26, buffer))
1834 {
1835 KeyLen = strlen(tmpbuf);
1836 switch (KeyLen)
1837 {
1838 case 0:
1839 pAd->PortCfg.SharedKey[2].KeyLen = 0;
1840 break;
1841 case 5: //wep 40 Ascii type
1842 pAd->PortCfg.SharedKey[2].KeyLen = KeyLen;
1843 memcpy(pAd->PortCfg.SharedKey[2].Key, tmpbuf, KeyLen);
1844 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key3=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Ascii");
1845 case 10: //wep 40 Hex type
1846 for(i=0; i < KeyLen; i++)
1847 {
1848 if( !isxdigit(*(tmpbuf+i)) )
1849 {
1850 bIsHex = FALSE;
1851 break;
1852 }
1853 }
1854
1855 if (bIsHex)
1856 {
1857 pAd->PortCfg.SharedKey[2].KeyLen = KeyLen / 2 ;
1858 AtoH(tmpbuf, pAd->PortCfg.SharedKey[2].Key, KeyLen / 2);
1859 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key3=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Hex");
1860 }
1861 break;
1862 case 13: //wep 104 Ascii type
1863 pAd->PortCfg.SharedKey[2].KeyLen = KeyLen;
1864 memcpy(pAd->PortCfg.SharedKey[2].Key, tmpbuf, KeyLen);
1865 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key3=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Ascii");
1866 break;
1867 case 26: //wep 104 Hex type
1868 for(i=0; i < KeyLen; i++)
1869 {
1870 if( !isxdigit(*(tmpbuf+i)) )
1871 {
1872 bIsHex = FALSE;
1873 break;
1874 }
1875 }
1876
1877 if (bIsHex)
1878 {
1879 pAd->PortCfg.SharedKey[2].KeyLen = KeyLen / 2 ;
1880 AtoH(tmpbuf, pAd->PortCfg.SharedKey[2].Key, KeyLen / 2);
1881 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key3=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Hex");
1882 }
1883 break;
1884 default:
1885 pAd->PortCfg.SharedKey[2].KeyLen = 0;
1886 DBGPRINT(RT_DEBUG_TRACE, "%s::Invalid argument (=%s)\n", __FUNCTION__, tmpbuf);
1887 }
1888 }
1889 //Key4Str
1890 if (RTMPGetKeyParameter("Default", "Key4Str", tmpbuf, 26, buffer))
1891 {
1892 KeyLen = strlen(tmpbuf);
1893 switch (KeyLen)
1894 {
1895 case 0:
1896 pAd->PortCfg.SharedKey[3].KeyLen = 0;
1897 break;
1898 case 5: //wep 40 Ascii type
1899 pAd->PortCfg.SharedKey[3].KeyLen = KeyLen;
1900 memcpy(pAd->PortCfg.SharedKey[3].Key, tmpbuf, KeyLen);
1901 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key4=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Ascii");
1902 case 10: //wep 40 Hex type
1903 for(i=0; i < KeyLen; i++)
1904 {
1905 if( !isxdigit(*(tmpbuf+i)) )
1906 {
1907 bIsHex = FALSE;
1908 break;
1909 }
1910 }
1911
1912 if (bIsHex)
1913 {
1914 pAd->PortCfg.SharedKey[3].KeyLen = KeyLen / 2 ;
1915 AtoH(tmpbuf, pAd->PortCfg.SharedKey[3].Key, KeyLen / 2);
1916 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key4=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Hex");
1917 }
1918 break;
1919 case 13: //wep 104 Ascii type
1920 pAd->PortCfg.SharedKey[3].KeyLen = KeyLen;
1921 memcpy(pAd->PortCfg.SharedKey[3].Key, tmpbuf, KeyLen);
1922 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key4=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Ascii");
1923 break;
1924 case 26: //wep 104 Hex type
1925 for(i=0; i < KeyLen; i++)
1926 {
1927 if( !isxdigit(*(tmpbuf+i)) )
1928 {
1929 bIsHex = FALSE;
1930 break;
1931 }
1932 }
1933
1934 if (bIsHex)
1935 {
1936 pAd->PortCfg.SharedKey[3].KeyLen = KeyLen / 2 ;
1937 AtoH(tmpbuf, pAd->PortCfg.SharedKey[3].Key, KeyLen / 2);
1938 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key4=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Hex");
1939 }
1940 break;
1941 default:
1942 pAd->PortCfg.SharedKey[3].KeyLen = 0;
1943 DBGPRINT(RT_DEBUG_TRACE, "%s::Invalid argument (=%s)\n", __FUNCTION__, tmpbuf);
1944 }
1945 }
1946 }
1947 }
1948 else
1949 {
1950 DBGPRINT(RT_DEBUG_TRACE, "--> %s does not have a write method\n", src);
1951 }
1952
1953 retval=filp_close(srcf,NULL);
1954 if (retval)
1955 {
1956 DBGPRINT(RT_DEBUG_TRACE, "--> Error %d closing %s\n", -retval, src);
1957 }
1958 }
1959 } //if (src && *src)
1960
1961 set_fs(orgfs);
1962 current->fsuid = orgfsuid;
1963 current->fsgid = orgfsgid;
1964 }
1965 /*
1966 ========================================================================
1967
1968 Routine Description:
1969 Reset NIC Asics
1970
1971 Arguments:
1972 Adapter Pointer to our adapter
1973
1974 Return Value:
1975 None
1976
1977 Note:
1978 Reset NIC to initial state AS IS system boot up time.
1979
1980 ========================================================================
1981 */
1982 VOID RTMPRingCleanUp(
1983 IN PRTMP_ADAPTER pAdapter,
1984 IN UCHAR RingType)
1985 {
1986 ULONG Count;
1987 PTXD_STRUC pTxD;
1988 PRXD_STRUC pRxD;
1989 PMGMT_STRUC pMgmt;
1990 struct sk_buff *skb;
1991
1992 Count = 0;
1993 switch (RingType)
1994 {
1995 case TX_RING:
1996 // We have to clean all descriptos in case some error happened with reset
1997 do
1998 {
1999 pTxD = (PTXD_STRUC) pAdapter->TxRing[pAdapter->NextTxDoneIndex].va_addr;
2000
2001 pTxD->Owner = DESC_OWN_HOST;
2002 pTxD->Valid = FALSE;
2003
2004 pAdapter->NextTxDoneIndex++;
2005 Count++;
2006 if (pAdapter->NextTxDoneIndex >= TX_RING_SIZE)
2007 {
2008 pAdapter->NextTxDoneIndex = 0;
2009 }
2010
2011 } while (Count < TX_RING_SIZE); // We have to scan all TX ring
2012
2013 // Check for packet in send tx wait waiting queue
2014 while (pAdapter->TxSwQueue0.Head != NULL)
2015 {
2016 // Packets queued, Remove all and return to upper layer
2017 skb = (struct sk_buff *)RemoveHeadQueue(&pAdapter->TxSwQueue0);
2018 // Release packet by calling send failure
2019 RTMPFreeSkbBuffer(skb);
2020 }
2021 while (pAdapter->TxSwQueue1.Head != NULL)
2022 {
2023 // Packets queued, Remove all and return to upper layer
2024 skb = (struct sk_buff *)RemoveHeadQueue(&pAdapter->TxSwQueue1);
2025 // Release packet by calling send failure
2026 RTMPFreeSkbBuffer(skb);
2027 }
2028 while (pAdapter->TxSwQueue2.Head != NULL)
2029 {
2030 // Packets queued, Remove all and return to upper layer
2031 skb = (struct sk_buff *)RemoveHeadQueue(&pAdapter->TxSwQueue2);
2032 // Release packet by calling send failure
2033 RTMPFreeSkbBuffer(skb);
2034 }
2035 while (pAdapter->TxSwQueue3.Head != NULL)
2036 {
2037 // Packets queued, Remove all and return to upper layer
2038 skb = (struct sk_buff *)RemoveHeadQueue(&pAdapter->TxSwQueue3);
2039 // Release packet by calling send failure
2040 RTMPFreeSkbBuffer(skb);
2041 }
2042 break;
2043
2044 case PRIO_RING:
2045 // We have to clean all descriptos in case some error happened with reset
2046 do
2047 {
2048 pTxD = (PTXD_STRUC) pAdapter->PrioRing[pAdapter->NextPrioDoneIndex].va_addr;
2049
2050 // We just re-claim these ring spaces.
2051 pTxD->Owner = DESC_OWN_HOST;
2052 pTxD->Valid = FALSE;
2053
2054 pAdapter->NextPrioDoneIndex++;
2055 Count++;
2056 if (pAdapter->NextPrioDoneIndex >= PRIO_RING_SIZE)
2057 {
2058 pAdapter->NextPrioDoneIndex = 0;
2059 }
2060
2061 } while (Count < PRIO_RING_SIZE); // We have to scan all Priority Ring
2062
2063 // Clear managemt buffer ring
2064 while ((pAdapter->PushMgmtIndex != pAdapter->PopMgmtIndex) || (pAdapter->MgmtQueueSize != 0))
2065 {
2066 pMgmt = (PMGMT_STRUC) &pAdapter->MgmtRing[pAdapter->PopMgmtIndex];
2067 if (pMgmt->Valid == TRUE)
2068 {
2069 MlmeFreeMemory(pAdapter, pMgmt->pBuffer);
2070 pMgmt->Valid = FALSE;
2071 pAdapter->PopMgmtIndex++;
2072 pAdapter->MgmtQueueSize--;
2073 if (pAdapter->PopMgmtIndex >= MGMT_RING_SIZE)
2074 {
2075 pAdapter->PopMgmtIndex = 0;
2076 }
2077 }
2078 }
2079 pAdapter->RalinkCounters.MgmtRingFullCount = 0;
2080 break;
2081
2082 case RX_RING:
2083 // We have to clean all descriptos in case some error happened with reset
2084 do
2085 {
2086 pRxD = (PRXD_STRUC) pAdapter->RxRing[pAdapter->CurRxIndex].va_addr;
2087
2088 // Re-initial Rx ring cell to owned by NIC.
2089 pRxD->Owner = DESC_OWN_NIC;
2090
2091 pAdapter->CurRxIndex++;
2092 Count++;
2093 if (pAdapter->CurRxIndex >= RX_RING_SIZE)
2094 {
2095 pAdapter->CurRxIndex = 0;
2096 }
2097
2098 } while (Count < RX_RING_SIZE); // We have to scan all Rx Ring
2099 break;
2100
2101 default:
2102 break;
2103
2104 }
2105 }
2106
2107 /*
2108 ========================================================================
2109
2110 Routine Description:
2111 Compare two memory block
2112
2113 Arguments:
2114 Adapter Pointer to our adapter
2115
2116 Return Value:
2117 1: memory are equal
2118 0: memory are not equal
2119
2120 Note:
2121
2122 ========================================================================
2123 */
2124 ULONG RTMPEqualMemory(
2125 IN PVOID pSrc1,
2126 IN PVOID pSrc2,
2127 IN ULONG Length)
2128 {
2129 PUCHAR pMem1;
2130 PUCHAR pMem2;
2131 ULONG Index = 0;
2132
2133 pMem1 = (PUCHAR) pSrc1;
2134 pMem2 = (PUCHAR) pSrc2;
2135
2136 for (Index = 0; Index < Length; Index++)
2137 {
2138 if (pMem1[Index] != pMem2[Index])
2139 {
2140 break;
2141 }
2142 }
2143
2144 if (Index == Length)
2145 {
2146 return (1);
2147 }
2148 else
2149 {
2150 return (0);
2151 }
2152 }
2153
2154 /*
2155 ========================================================================
2156
2157 Routine Description:
2158 Compare two memory block
2159
2160 Arguments:
2161 pSrc1 Pointer to first memory address
2162 pSrc2 Pointer to second memory addres
2163
2164 Return Value:
2165 0: memory is equal
2166 1: pSrc1 memory is larger
2167 2: pSrc2 memory is larger
2168
2169 Note:
2170
2171 ========================================================================
2172 */
2173 ULONG RTMPCompareMemory(
2174 IN PVOID pSrc1,
2175 IN PVOID pSrc2,
2176 IN ULONG Length)
2177 {
2178 PUCHAR pMem1;
2179 PUCHAR pMem2;
2180 ULONG Index = 0;
2181
2182 pMem1 = (PUCHAR) pSrc1;
2183 pMem2 = (PUCHAR) pSrc2;
2184
2185 for (Index = 0; Index < Length; Index++)
2186 {
2187 if (pMem1[Index] > pMem2[Index])
2188 return (1);
2189 else if (pMem1[Index] < pMem2[Index])
2190 return (2);
2191 }
2192
2193 // Equal
2194 return (0);
2195 }
2196
2197 /*
2198 ========================================================================
2199
2200 Routine Description:
2201 Zero out memory block
2202
2203 Arguments:
2204 pSrc1 Pointer to memory address
2205 Length Size
2206
2207 Return Value:
2208 None
2209
2210 Note:
2211
2212 ========================================================================
2213 */
2214 VOID NdisZeroMemory(
2215 IN PVOID pSrc,
2216 IN ULONG Length)
2217 {
2218 #if 0
2219 PUCHAR pMem;
2220 ULONG Index = 0;
2221
2222 pMem = (PUCHAR) pSrc;
2223
2224 for (Index = 0; Index < Length; Index++)
2225 {
2226 pMem[Index] = 0x00;
2227 }
2228 #else
2229 memset(pSrc, 0, Length);
2230 #endif
2231 }
2232
2233 VOID NdisFillMemory(
2234 IN PVOID pSrc,
2235 IN ULONG Length,
2236 IN UCHAR Fill)
2237 {
2238 #if 0
2239 PUCHAR pMem;
2240 ULONG Index = 0;
2241
2242 pMem = (PUCHAR) pSrc;
2243
2244 for (Index = 0; Index < Length; Index++)
2245 {
2246 pMem[Index] = Fill;
2247 }
2248 #else
2249 memset(pSrc, Fill, Length);
2250 #endif
2251 }
2252
2253 /*
2254 ========================================================================
2255
2256 Routine Description:
2257 Copy data from memory block 1 to memory block 2
2258
2259 Arguments:
2260 pDest Pointer to destination memory address
2261 pSrc Pointer to source memory address
2262 Length Copy size
2263
2264 Return Value:
2265 None
2266
2267 Note:
2268
2269 ========================================================================
2270 */
2271 VOID NdisMoveMemory(
2272 OUT PVOID pDest,
2273 IN PVOID pSrc,
2274 IN ULONG Length)
2275 {
2276 memcpy(pDest, pSrc, Length);
2277 }
2278
2279 /*
2280 ========================================================================
2281
2282 Routine Description:
2283 Initialize port configuration structure
2284
2285 Arguments:
2286 Adapter Pointer to our adapter
2287
2288 Return Value:
2289 None
2290
2291 Note:
2292
2293 ========================================================================
2294 */
2295 VOID PortCfgInit(
2296 IN PRTMP_ADAPTER pAdapter)
2297 {
2298 UINT i;
2299
2300 DBGPRINT(RT_DEBUG_TRACE, "--> PortCfgInit\n");
2301
2302 pAdapter->PortCfg.UseBGProtection = 0; // 0: AUTO
2303
2304 pAdapter->PortCfg.CapabilityInfo = 0x0000;
2305 pAdapter->PortCfg.Psm = PWR_ACTIVE;
2306 pAdapter->PortCfg.BeaconPeriod = 100; // in mSec
2307
2308 pAdapter->PortCfg.CfpMaxDuration = 0; // never mind, decided by AP later
2309 pAdapter->PortCfg.CfpDurRemain = 0; // never mind, decided by AP later
2310 pAdapter->PortCfg.CfpCount = 0; // never mind, decided by AP later
2311 pAdapter->PortCfg.CfpPeriod = 0; // never mind, decided by AP later
2312 pAdapter->PortCfg.AuthMode = Ndis802_11AuthModeOpen;
2313
2314 for(i = 0; i < SHARE_KEY_NO; i++) {
2315 pAdapter->PortCfg.SharedKey[i].KeyLen = 0;
2316 }
2317
2318 for(i = 0; i < PAIRWISE_KEY_NO; i++) {
2319 pAdapter->PortCfg.PairwiseKey[i].KeyLen = 0;
2320 }
2321
2322 for(i = 0; i < GROUP_KEY_NO; i++) {
2323 pAdapter->PortCfg.GroupKey[i].KeyLen = 0;
2324 }
2325
2326 pAdapter->PortCfg.WepStatus = Ndis802_11EncryptionDisabled;
2327 pAdapter->PortCfg.DefaultKeyId = 0;
2328 pAdapter->PortCfg.PrivacyFilter = Ndis802_11PrivFilterAcceptAll;
2329
2330 // 802.1x port control
2331 pAdapter->PortCfg.PortSecured = WPA_802_1X_PORT_NOT_SECURED;
2332 pAdapter->PortCfg.LastMicErrorTime = 0;
2333 pAdapter->PortCfg.MicErrCnt = 0;
2334 pAdapter->PortCfg.bBlockAssoc = FALSE;
2335 pAdapter->PortCfg.WpaState = SS_NOTUSE;
2336
2337 pAdapter->PortCfg.RtsThreshold = 2347;
2338 pAdapter->PortCfg.FragmentThreshold = 2346;
2339 pAdapter->PortCfg.bFragmentZeroDisable = FALSE;
2340
2341 pAdapter->PortCfg.CurrentTxAntenna = 0xff; // diversity
2342 pAdapter->PortCfg.CurrentRxAntenna = 0xff; // diversity
2343 pAdapter->PortCfg.NumberOfAntenna = 2;
2344
2345 // pAdapter->PortCfg.TxPowerLevel[0] = 100;
2346 // pAdapter->PortCfg.NumOfTxPowerLevel = 1;
2347 pAdapter->PortCfg.TxPower = 100; //mW
2348 pAdapter->PortCfg.TxPowerPercentage = 0xffffffff; // AUTO
2349
2350 pAdapter->PortCfg.AntennaSupportTx = TRUE;
2351 pAdapter->PortCfg.AntennaSupportRx = TRUE;
2352 pAdapter->PortCfg.AntennaSupportDiversityRx = TRUE;
2353
2354 pAdapter->PortCfg.RecvDtim = TRUE;
2355 NdisZeroMemory(&pAdapter->PortCfg.Bssid, MAC_ADDR_LEN);
2356 NdisFillMemory(&pAdapter->PortCfg.Broadcast, MAC_ADDR_LEN, 0xff);
2357 pAdapter->PortCfg.Pss = PWR_ACTIVE;
2358 pAdapter->PortCfg.RssiTrigger = 0;
2359 pAdapter->PortCfg.LastRssi = 0;
2360 pAdapter->PortCfg.LastAvgRssi = -95 + RSSI_TO_DBM_OFFSET;// default -95dm
2361 pAdapter->PortCfg.AvgRssi = 0;
2362 pAdapter->PortCfg.RssiTriggerMode = RSSI_TRIGGERED_UPON_BELOW_THRESHOLD;
2363 pAdapter->PortCfg.AtimWin = 0;
2364 pAdapter->PortCfg.Channel = 1;
2365
2366 pAdapter->PortCfg.Aid = 1;
2367
2368 pAdapter->PortCfg.DefaultListenCount = 3;//default listen count;
2369 pAdapter->PortCfg.BssType = BSS_INFRA; // BSS_INFRA or BSS_INDEP
2370
2371 pAdapter->PortCfg.AdhocMode = 0;
2372
2373 pAdapter->PortCfg.SsidLen = 0;
2374 NdisZeroMemory(pAdapter->PortCfg.Ssid, MAX_LEN_OF_SSID); // NOT NULL-terminated
2375
2376 // global variables mXXXX used in MAC protocol state machines
2377 pAdapter->PortCfg.Mibss = FALSE;
2378 pAdapter->PortCfg.Massoc = FALSE;
2379 pAdapter->PortCfg.Mauth = FALSE;
2380
2381 // PHY specification
2382 pAdapter->PortCfg.PhyMode = 0xff;
2383 // RTMPSetPhyMode(pAdapter, PHY_11BG_MIXED); // default in 11BG mixed mode
2384 // pAdapter->PortCfg.Channel = FirstChannel(pAdapter);
2385 pAdapter->PortCfg.Dsifs = 10; // in units of usec
2386 pAdapter->PortCfg.TxPreambleInUsed = Rt802_11PreambleLong; // use Long preamble on TX by defaut
2387
2388 // user desired power mode
2389 pAdapter->PortCfg.WindowsPowerMode = Ndis802_11PowerModeCAM; // Ndis802_11PowerModeFast_PSP;
2390 pAdapter->PortCfg.WindowsBatteryPowerMode = Ndis802_11PowerModeCAM; // Ndis802_11PowerModeFast_PSP;
2391 pAdapter->PortCfg.WindowsTxPreamble = Rt802_11PreambleAuto; // use Long preamble on TX by defaut
2392 pAdapter->PortCfg.WindowsACCAMEnable = FALSE;
2393 // pAdapter->PortCfg.PacketFilter = NDIS_PACKET_TYPE_ALL_MULTICAST | NDIS_PACKET_TYPE_DIRECTED | NDIS_PACKET_TYPE_BROADCAST;
2394 pAdapter->bAcceptDirect = TRUE;
2395 pAdapter->bAcceptMulticast = FALSE;
2396 pAdapter->bAcceptBroadcast = TRUE;
2397 pAdapter->bAcceptAllMulticast = TRUE;
2398
2399 // parameters to be used when this STA starts a new ADHOC network
2400 pAdapter->PortCfg.IbssConfig.BeaconPeriod = 100;
2401 pAdapter->PortCfg.IbssConfig.AtimWin = 0;
2402 pAdapter->PortCfg.IbssConfig.Channel = 1;
2403 pAdapter->PortCfg.RfType = RFIC_2525;
2404 pAdapter->PortCfg.LedMode = LED_MODE_DEFAULT;
2405 RTMPInitTimer(pAdapter, &pAdapter->PortCfg.RfTuningTimer, AsicRfTuningExec);
2406
2407 pAdapter->PortCfg.IgnoredScanNumber = 0;
2408 pAdapter->bTxBusy = FALSE;
2409
2410 pAdapter->PortCfg.bHwRadio = TRUE;
2411 pAdapter->PortCfg.bSwRadio = TRUE;
2412 pAdapter->PortCfg.bRadio = TRUE;
2413 pAdapter->PortCfg.bHardwareRadio = FALSE; // Default is OFF
2414 pAdapter->PortCfg.bAutoTxAgc = FALSE; // Default is OFF
2415 pAdapter->PortCfg.bShowHiddenSSID = FALSE;
2416
2417 // Nitro mode control
2418 pAdapter->PortCfg.EnableTxBurst = 0;
2419 pAdapter->PortCfg.AutoReconnect = TRUE;
2420
2421 // Save the init time as last scan time, the system should do scan after 2 seconds.
2422 pAdapter->PortCfg.LastScanTime = 0;
2423
2424 // Default Config change flag
2425 pAdapter->bConfigChanged = FALSE;
2426
2427 pAdapter->PortCfg.bLocalAdminMAC = TRUE;
2428
2429 pAdapter->NeedSwapToLittleEndian = TRUE;
2430
2431 // dynamic BBP R17:sensibity tuning to overcome background noise
2432 pAdapter->PortCfg.BbpTuningEnable = TRUE; // overwritten by E2PROM setting
2433 pAdapter->PortCfg.VgcLowerBound = 0x38; // overwritten by E2PROM setting
2434 pAdapter->PortCfg.BbpTuning.FalseCcaLowerThreshold = 100;
2435 pAdapter->PortCfg.BbpTuning.FalseCcaUpperThreshold = 4; // unit 128, 4*128 = 512
2436 pAdapter->PortCfg.BbpTuning.VgcDelta = 1;
2437 pAdapter->PortCfg.BbpTuning.VgcUpperBound = BBP_R17_DYNAMIC_UP_BOUND;
2438
2439 pAdapter->PortCfg.StaWithEtherBridge.Enable = FALSE;
2440 NdisFillMemory(&pAdapter->PortCfg.StaWithEtherBridge.EtherMacAddr, MAC_ADDR_LEN, 0xff);
2441
2442 #ifdef RALINK_ATE
2443 memset(&pAdapter->ate, 0, sizeof(ATE_INFO));
2444 pAdapter->ate.Mode = ATE_STASTART;
2445 pAdapter->ate.TxCount = TX_RING_SIZE;
2446 pAdapter->ate.TxLength = PRIO_BUFFER_SIZE;
2447 pAdapter->ate.TxRate = RATE_11;
2448 pAdapter->ate.Channel = 1;
2449 memcpy(&pAdapter->ate.Addr1,"001122334455", ETH_LENGTH_OF_ADDRESS);
2450 memcpy(&pAdapter->ate.Addr2,"001122334455", ETH_LENGTH_OF_ADDRESS);
2451 memcpy(&pAdapter->ate.Addr3,"001122334455", ETH_LENGTH_OF_ADDRESS);
2452 #endif //#ifdef RALINK_ATE
2453
2454 RTMP_IO_READ32(pAdapter, 0, &pAdapter->PortCfg.Rt2560Version);
2455
2456 DBGPRINT(RT_DEBUG_TRACE, "<-- PortCfgInit\n");
2457 }
2458
2459 UCHAR BtoH(char ch)
2460 {
2461 if (ch >= '0' && ch <= '9') return (ch - '0'); // Handle numerals
2462 if (ch >= 'A' && ch <= 'F') return (ch - 'A' + 0xA); // Handle capitol hex digits
2463 if (ch >= 'a' && ch <= 'f') return (ch - 'a' + 0xA); // Handle small hex digits
2464 return(255);
2465 }
2466
2467 //
2468 // FUNCTION: AtoH(char *, UCHAR *, int)
2469 //
2470 // PURPOSE: Converts ascii string to network order hex
2471 //
2472 // PARAMETERS:
2473 // src - pointer to input ascii string
2474 // dest - pointer to output hex
2475 // destlen - size of dest
2476 //
2477 // COMMENTS:
2478 //
2479 // 2 ascii bytes make a hex byte so must put 1st ascii byte of pair
2480 // into upper nibble and 2nd ascii byte of pair into lower nibble.
2481 //
2482
2483 void AtoH(char * src, UCHAR * dest, int destlen)
2484 {
2485 char *srcptr;
2486 PUCHAR destTemp;
2487
2488 srcptr = src;
2489 destTemp = (PUCHAR) dest;
2490
2491 while(destlen--)
2492 {
2493 *destTemp = BtoH(*srcptr++) << 4; // Put 1st ascii byte in upper nibble.
2494 *destTemp += BtoH(*srcptr++); // Add 2nd ascii byte to above.
2495 destTemp++;
2496 }
2497 }
2498
2499 /*
2500 ========================================================================
2501
2502 Routine Description:
2503 Init timer objects
2504
2505 Arguments:
2506 pAdapter Pointer to our adapter
2507 pTimer Timer structure
2508 pTimerFunc Function to execute when timer expired
2509 Repeat Ture for period timer
2510
2511 Return Value:
2512 None
2513
2514 Note:
2515
2516 ========================================================================
2517 */
2518 VOID RTMPInitTimer(
2519 IN PRTMP_ADAPTER pAdapter,
2520 IN PRALINK_TIMER_STRUCT pTimer,
2521 IN PVOID pTimerFunc)
2522 {
2523 pTimer->State = FALSE;
2524 init_timer(&pTimer->TimerObj);
2525 pTimer->TimerObj.data = (unsigned long)pAdapter;
2526 pTimer->TimerObj.function = pTimerFunc;
2527 }
2528
2529 /*
2530 ========================================================================
2531
2532 Routine Description:
2533 Init timer objects
2534
2535 Arguments:
2536 pTimer Timer structure
2537 Value Timer value in milliseconds
2538
2539 Return Value:
2540 None
2541
2542 Note:
2543
2544 ========================================================================
2545 */
2546 VOID RTMPSetTimer(
2547 IN PRTMP_ADAPTER pAdapter,
2548 IN PRALINK_TIMER_STRUCT pTimer,
2549 IN ULONG Value)
2550 {
2551 pTimer->TimerValue = Value;
2552 pTimer->State = FALSE;
2553 pTimer->TimerObj.expires = jiffies + (Value * HZ)/1000;
2554 add_timer(&pTimer->TimerObj);
2555 }
2556
2557 /*
2558 ========================================================================
2559
2560 Routine Description:
2561 Cancel timer objects
2562
2563 Arguments:
2564 Adapter Pointer to our adapter
2565
2566 Return Value:
2567 None
2568
2569 Note:
2570 Reset NIC to initial state AS IS system boot up time.
2571
2572 ========================================================================
2573 */
2574 VOID RTMPCancelTimer(
2575 IN PRALINK_TIMER_STRUCT pTimer)
2576 {
2577 del_timer_sync(&pTimer->TimerObj);
2578 }
2579
MOXA 2.6.9 from sdlinux-moxaart.tgz