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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / net / wireless / rtlink / rtmp_init.c
blobec2f7b1ec2ee51a3c55dcc062e0926740ab12d05
1 /*************************************************************************
2 * Ralink Tech Inc. *
3 * 4F, No. 2 Technology 5th Rd. *
4 * Science-based Industrial Park *
5 * Hsin-chu, Taiwan, R.O.C. *
6 * *
7 * (c) Copyright 2002, Ralink Technology, Inc. *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 * *
24 *************************************************************************
25
26 Module Name:
27 rtmp_init.c
28
29 Abstract:
30 Miniport generic portion header file
31
32 Revision History:
33 Who When What
34 -------- ---------- ----------------------------------------------
35 Paul Lin 08-01-2002 created
36
37 */
38 #include "rt_config.h"
39
40 //
41 // BBP register initialization set
42 //
43 ULONG BBPRegTable[] = {
44 0x00018302, // R03
45 0x00018419, // R04
46 0x00018E1C, // R14
47 0x00018F30, // R15
48 0x000190ac, // R16
49 0x00019148, // R17
50 0x00019218, // R18
51 0x000193ff, // R19
52 0x0001941E, // R20
53 0x00019508, // R21
54 0x00019608, // R22
55 0x00019708, // R23
56 0x00019870, // R24
57 0x00019940, // R25
58 0x00019A08, // R26
59 0x00019B23, // R27
60 0x00019E10, // R30
61 0x00019F2B, // R31
62 0x0001A0B9, // R32
63 0x0001A212, // R34
64 0x0001A350, // R35
65 0x0001A7c4, // R39
66 0x0001A802, // R40
67 0x0001A960, // R41
68 0x0001B510, // R53
69 0x0001B618, // R54
70 0x0001B808, // R56
71 0x0001B910, // R57
72 0x0001BA08, // R58
73 0x0001BD6d, // R61
74 0x0001BE10, // R62
75 };
76
77 //
78 // MAC register initialization sets
79 //
80 RTMP_REG_PAIR MACRegTable[] = {
81 {PSCSR0, 0x00020002}, // 0xc8
82 {PSCSR1, 0x00000002}, // 0xcc
83 // {PSCSR2, 0x00023f20}, // 0xd0
84 {PSCSR2, 0x00020002}, // 0xd0
85 {PSCSR3, 0x00000002}, // 0xd4
86 {TIMECSR, 0x00003f21}, // 0xDC, to slower down our 1-us tick
87 {CSR9, 0x00000780}, // 0x24
88 {CSR11, 0x07041483}, // 0x2C, lrc=7, src=4, slot=20us, CWmax=2^8, CWmax=2^3
89 {CSR18, 0x00140000}, // SIFS=10us - TR switch time, PIFS=SIFS+20us
90 {CSR19, 0x016C0028}, // DIFS=SIFS+2*20us, EIFS=364us
91 {CNT3, 0x00000000}, // Backoff_CCA_Th, RX_&_TX_CCA_Th
92
93 {TXCSR1, 0x07614562}, // 0x64, ACK as 1Mb time
94 {TXCSR8, 0x8c8d8b8a}, // 0x98, CCK TX BBP register ID
95 //{TXCSR9, 0x86870885}, // 0x94, OFDM TX BBP register ID
96
97 {ARCSR1, 0x0000000f}, // 0x9c, Basic rate set bitmap
98 {PLCP1MCSR, 0x00700400}, // 0x13c, ACK/CTS PLCP at 1 Mbps
99 {PLCP2MCSR, 0x00380401}, // 0x140, ACK/CTS PLCP at 2 Mbps
100 {PLCP5MCSR, 0x00150402}, // 0x144, ACK/CTS PLCP at 5.5 Mbps
101 {PLCP11MCSR,0x000b8403}, // 0x148, ACK/CTS PLCP at 11 Mbps
102
103 {ARTCSR0, 0x7038140a}, // 0x14c, ACK/CTS payload consumed time for 1/2/5.5/11 mbps
104 {ARTCSR1, 0x1d21252d}, // 0x150, alexsu : OFDM ACK/CTS payload consumed time for 18/12/9/6 mbps
105 {ARTCSR2, 0x1919191d}, // 0x154, alexsu : OFDM ACK/CTS payload consumed time for 54/48/36/24 mbps
106
107 {RXCSR0, 0xffffffff}, // 0x80
108 {RXCSR3, 0xb3aab3af}, // 0x90. RT2530 BBP 51:RSSI, R42:OFDM rate, R47:CCK SIGNAL
109 {PCICSR, 0x000003b8}, // 0x8c, alexsu : PCI control register
110 {PWRCSR0, 0x3f3b3100}, // 0xC4
111 {GPIOCSR, 0x0000ff00}, // 0x120, GPIO default value
112 {TESTCSR, 0x000000f0}, // 0x138, Test CSR, make sure it's running at normal mode
113 {PWRCSR1, 0x000001ff}, // 0xd8
114 {MACCSR0, 0x00213223}, // 0xE0, Enable Tx dribble mode - 2003/10/22:Gary
115 {MACCSR1, 0x00235518}, // 0xE4, Disable Rx Reset, tx dribble count, 2x30x16 = 960n,
116 {MACCSR2, 0x00000040}, // 0x0134, 64*33ns = 2us
117 {RALINKCSR, 0x9a009a11}, // 0xE8
118 {CSR7, 0xffffffff}, // 0x1C, Clear all pending interrupt source
119 {LEDCSR, 0x00001E46}, // default both LEDs off
120 {BBPCSR1, 0x82188200}, // for 2560+2522
121 {TXACKCSR0, 0x00000020}, // 0x110, TX ACK timeout in usec
122 {SECCSR3, 0x0000e78f}, // AES, mask off more data bit for MIC calculation
123 };
124
125 #define NUM_BBP_REG_PARMS (sizeof(BBPRegTable) / sizeof(ULONG))
126 #define NUM_MAC_REG_PARMS (sizeof(MACRegTable) / sizeof(RTMP_REG_PAIR))
127
128 /*
129 ========================================================================
130
131 Routine Description:
132 Allocate all DMA releated resources
133
134 Arguments:
135 Adapter Pointer to our adapter
136
137 Return Value:
138 None
139
140 Note:
141
142 ========================================================================
143 */
144 NDIS_STATUS RTMPAllocDMAMemory(
145 IN PRTMP_ADAPTER pAd)
146 {
147 INT index;
148 VOID *ring; // VA of ring descriptor
149 VOID *ring_data; // VA of DMA data buffer
150 dma_addr_t ring_dma; // PA of ring descriptor
151 dma_addr_t ring_data_dma; // PA of DMA data buffer
152 PTXD_STRUC pTxD; // Tx type ring descriptor
153 PRXD_STRUC pRxD; // Rx type ring descriptor
154
155 DBGPRINT(RT_DEBUG_INFO, "--> RTMPAllocDMAMemory\n");
156
157 // 1. Allocate Tx Ring DMA descriptor and buffer memory
158 // Allocate Ring descriptors DMA block
159 #if 0 // mask by Victor Yu. 05-18-2006
160 ring = pci_alloc_consistent(pAd->pPci_Dev, (TX_RING_SIZE * RING_DESCRIPTOR_SIZE), &ring_dma);
161 #else // add by Victor Yu. 05-18-2006
162 ring = (VOID *)dma_alloc_coherent(NULL, TX_RING_SIZE*RING_DESCRIPTOR_SIZE, &ring_dma, GFP_DMA|GFP_KERNEL);
163 #endif
164 if (!ring) {
165 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring descriptor memory.\n");
166 goto err_out_allocate_txring;
167 }
168
169 // Zero init ring descriptors
170 memset(ring, 0, (TX_RING_SIZE * RING_DESCRIPTOR_SIZE));
171
172 // Allocate Ring data DMA blocks
173 #if 0 // maks by Victor Yu. 05-18-2006
174 ring_data = pci_alloc_consistent(pAd->pPci_Dev, (TX_RING_SIZE * TX_BUFFER_SIZE), &ring_data_dma);
175 #else // add by Victor Yu. 05-18-2006
176 ring_data = (VOID *)dma_alloc_coherent(NULL, TX_RING_SIZE*TX_BUFFER_SIZE, &ring_data_dma, GFP_DMA|GFP_KERNEL);
177 #endif
178
179 // If failed, release ring descriptors DMA block & exit
180 if (!ring_data) {
181 #if 0 // mask by Victor Yu, 05-18-2006
182 pci_free_consistent(pAd->pPci_Dev, (TX_RING_SIZE * RING_DESCRIPTOR_SIZE), ring, ring_dma);
183 #else // add by Victor Yu. 05-18-2006
184 dma_free_coherent(NULL, TX_RING_SIZE*RING_DESCRIPTOR_SIZE, ring, ring_dma);
185 #endif
186
187 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring buffer memory.\n");
188 goto err_out_allocate_txring;
189 }
190
191 // Start with Tx ring & DMA buffer
192 for (index = 0; index < TX_RING_SIZE; index++)
193 {
194 // Init Tx Ring Size, Va, Pa variables
195 pAd->TxRing[index].size = RING_DESCRIPTOR_SIZE;
196 pAd->TxRing[index].va_addr = ring;
197 pAd->TxRing[index].pa_addr = ring_dma;
198 ring += RING_DESCRIPTOR_SIZE;
199 ring_dma += RING_DESCRIPTOR_SIZE;
200
201 // Init Tx DMA buffer
202 pAd->TxRing[index].data_size = TX_BUFFER_SIZE;
203 pAd->TxRing[index].va_data_addr = ring_data;
204 pAd->TxRing[index].pa_data_addr = ring_data_dma;
205 ring_data += TX_BUFFER_SIZE;
206 ring_data_dma += TX_BUFFER_SIZE;
207
208 // Write TxD buffer address & allocated buffer length
209 pTxD = (PTXD_STRUC) pAd->TxRing[index].va_addr;
210 #ifndef BIG_ENDIAN
211 pTxD->BufferAddressPa = pAd->TxRing[index].pa_data_addr;
212 #else
213 pTxD->BufferAddressPa = SWAP32(pAd->TxRing[index].pa_data_addr);
214 #endif
215
216 DBGPRINT(RT_DEBUG_INFO, "TxRing[%d] va = 0x%lu, pa = 0x%x, size = 0x%x\n",
217 index, (unsigned long)pAd->TxRing[index].va_addr, (UINT)pAd->TxRing[index].pa_addr, pAd->TxRing[index].size);
218 DBGPRINT(RT_DEBUG_INFO, "TxRing[%d] va_data = 0x%lu, pa_data = 0x%x, size = 0x%x\n",
219 index, (unsigned long)pAd->TxRing[index].va_data_addr, (UINT)pAd->TxRing[index].pa_data_addr, pAd->TxRing[index].data_size);
220 }
221
222 // 2. Allocate Prio Ring DMA descriptor and buffer memory
223 // Allocate Ring descriptors DMA block
224 #if 0 // mask by Victor Yu. 05-18-2006
225 ring = pci_alloc_consistent(pAd->pPci_Dev, (PRIO_RING_SIZE * RING_DESCRIPTOR_SIZE), &ring_dma);
226 #else // add by Victor Yu. 05-18-2006
227 ring = (VOID *)dma_alloc_coherent(NULL, PRIO_RING_SIZE*RING_DESCRIPTOR_SIZE, &ring_dma, GFP_DMA|GFP_KERNEL);
228 #endif
229
230 if (!ring) {
231 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring descriptor memory.\n");
232 goto err_out_allocate_prioring;
233 }
234
235 // Zero init ring descriptors
236 memset(ring, 0, (PRIO_RING_SIZE * RING_DESCRIPTOR_SIZE));
237
238 // Allocate Ring data DMA blocks
239 #if 0 // mask by Victor Yu. 05-18-2006
240 ring_data = pci_alloc_consistent(pAd->pPci_Dev, (PRIO_RING_SIZE * PRIO_BUFFER_SIZE), &ring_data_dma);
241 #else // add by Victor Yu. 05-18-2006
242 ring_data = (VOID *)dma_alloc_coherent(NULL, PRIO_RING_SIZE*PRIO_BUFFER_SIZE, &ring_data_dma, GFP_DMA|GFP_KERNEL);
243 #endif
244
245 // If failed, release ring descriptors DMA block & exit
246 if (!ring_data) {
247 pci_free_consistent(pAd->pPci_Dev, (PRIO_RING_SIZE * RING_DESCRIPTOR_SIZE), ring, ring_dma);
248 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring buffer memory.\n");
249 goto err_out_allocate_prioring;
250 }
251
252 // Second with Prio ring & DMA buffer
253 for (index = 0; index < PRIO_RING_SIZE; index++)
254 {
255 // Init Prio Ring Size, Va, Pa variables
256 pAd->PrioRing[index].size = RING_DESCRIPTOR_SIZE;
257 pAd->PrioRing[index].va_addr = ring;
258 pAd->PrioRing[index].pa_addr = ring_dma;
259 ring += RING_DESCRIPTOR_SIZE;
260 ring_dma += RING_DESCRIPTOR_SIZE;
261
262 // Init Prio DMA buffer
263 pAd->PrioRing[index].data_size = PRIO_BUFFER_SIZE;
264 pAd->PrioRing[index].va_data_addr = ring_data;
265 pAd->PrioRing[index].pa_data_addr = ring_data_dma;
266 ring_data += PRIO_BUFFER_SIZE;
267 ring_data_dma += PRIO_BUFFER_SIZE;
268
269 // Write TxD buffer address & allocated buffer length for priority ring
270 pTxD = (PTXD_STRUC) pAd->PrioRing[index].va_addr;
271 #ifndef BIG_ENDIAN
272 pTxD->BufferAddressPa = pAd->PrioRing[index].pa_data_addr;
273 #else
274 pTxD->BufferAddressPa = SWAP32(pAd->PrioRing[index].pa_data_addr);
275 #endif
276
277 DBGPRINT(RT_DEBUG_INFO, "PrioRing[%d] va = 0x%lu, pa = 0x%x, size = 0x%x\n",
278 index, (unsigned long)pAd->PrioRing[index].va_addr, (UINT)pAd->PrioRing[index].pa_addr, pAd->PrioRing[index].size);
279 DBGPRINT(RT_DEBUG_INFO, "PrioRing[%d] va_data = 0x%lu, pa_data = 0x%x, size = 0x%x\n",
280 index, (unsigned long)pAd->PrioRing[index].va_data_addr, (UINT)pAd->PrioRing[index].pa_data_addr, pAd->PrioRing[index].data_size);
281 }
282
283 // 3. Allocate Atim Ring DMA descriptor and buffer memory
284 // Allocate Ring descriptors DMA block
285 #if 0 // mask by Victor Yu. 05-18-2006
286 ring = pci_alloc_consistent(pAd->pPci_Dev, (ATIM_RING_SIZE * RING_DESCRIPTOR_SIZE), &ring_dma);
287 #else // add by Victor Yu. 05-18-2006
288 ring = (VOID *)dma_alloc_coherent(NULL, ATIM_RING_SIZE*RING_DESCRIPTOR_SIZE, &ring_dma, GFP_DMA|GFP_KERNEL);
289 #endif
290 if (!ring) {
291 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring descriptor memory.\n");
292 goto err_out_allocate_atimring;
293 }
294
295 // Zero init ring descriptors
296 memset(ring, 0, (ATIM_RING_SIZE * RING_DESCRIPTOR_SIZE));
297
298 // Allocate Ring data DMA blocks
299 #if 0 // mask by Victor Yu. 05-18-2006
300 ring_data = pci_alloc_consistent(pAd->pPci_Dev, (ATIM_RING_SIZE * ATIM_BUFFER_SIZE), &ring_data_dma);
301 #else // add by Victor Yu. 05-18-2006
302 ring_data = (VOID *)dma_alloc_coherent(NULL, ATIM_RING_SIZE*ATIM_BUFFER_SIZE, &ring_data_dma, GFP_DMA|GFP_KERNEL);
303 #endif
304
305 // If failed, release ring descriptors DMA block & exit
306 if (!ring_data) {
307 pci_free_consistent(pAd->pPci_Dev, (ATIM_RING_SIZE * RING_DESCRIPTOR_SIZE), ring, ring_dma);
308 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring buffer memory.\n");
309 goto err_out_allocate_atimring;
310 }
311
312 // Atim ring & DMA buffer
313 for (index = 0; index < ATIM_RING_SIZE; index++)
314 {
315 // Init Atim Ring Size, Va, Pa variables
316 pAd->AtimRing[index].size = RING_DESCRIPTOR_SIZE;
317 pAd->AtimRing[index].va_addr = ring;
318 pAd->AtimRing[index].pa_addr = ring_dma;
319 ring += RING_DESCRIPTOR_SIZE;
320 ring_dma += RING_DESCRIPTOR_SIZE;
321
322 // Init Atim DMA buffer
323 pAd->AtimRing[index].data_size = ATIM_BUFFER_SIZE;
324 pAd->AtimRing[index].va_data_addr = ring_data;
325 pAd->AtimRing[index].pa_data_addr = ring_data_dma;
326 ring_data += ATIM_BUFFER_SIZE;
327 ring_data_dma += ATIM_BUFFER_SIZE;
328
329 // Write TxD buffer address & allocated buffer length
330 pTxD = (PTXD_STRUC) pAd->AtimRing[index].va_addr;
331 #ifndef BIG_ENDIAN
332 pTxD->BufferAddressPa = pAd->AtimRing[index].pa_data_addr;
333 #else
334 pTxD->BufferAddressPa = SWAP32(pAd->AtimRing[index].pa_data_addr);
335 #endif
336
337 DBGPRINT(RT_DEBUG_INFO, "AtimRing[%d] va = 0x%lu, pa = 0x%x, size = 0x%x\n",
338 index, (unsigned long)pAd->AtimRing[index].va_addr, (UINT)pAd->AtimRing[index].pa_addr, pAd->AtimRing[index].size);
339 DBGPRINT(RT_DEBUG_INFO, "AtimRing[%d] va_data = 0x%lu, pa_data = 0x%x, size = 0x%x\n",
340 index, (unsigned long)pAd->AtimRing[index].va_data_addr, (UINT)pAd->AtimRing[index].pa_data_addr, pAd->AtimRing[index].data_size);
341 }
342
343 // 4. Allocate Rx Ring DMA descriptor and buffer memory
344 // Allocate Ring descriptors DMA block
345 #if 0 // mask by Victor Yu. 05-18-2006
346 ring = pci_alloc_consistent(pAd->pPci_Dev, (RX_RING_SIZE * RING_DESCRIPTOR_SIZE), &ring_dma);
347 #else // add by Victor Yu. 05-18-2006
348 ring = (VOID *)dma_alloc_coherent(NULL, RX_RING_SIZE*RING_DESCRIPTOR_SIZE, &ring_dma, GFP_DMA|GFP_KERNEL);
349 #endif
350 if (!ring) {
351 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring descriptor memory.\n");
352 goto err_out_allocate_rxring;
353 }
354
355 // Zero init ring descriptors
356 memset(ring, 0, (RX_RING_SIZE * RING_DESCRIPTOR_SIZE));
357
358 // Allocate Ring data DMA blocks
359 #if 0 // mask by Victor Yu. 05-18-2006
360 ring_data = pci_alloc_consistent(pAd->pPci_Dev, (RX_RING_SIZE * RX_BUFFER_SIZE), &ring_data_dma);
361 #else // add by Victor Yu. 05-18-2006
362 ring_data = (VOID *)dma_alloc_coherent(NULL, RX_RING_SIZE*RX_BUFFER_SIZE, &ring_data_dma, GFP_DMA|GFP_KERNEL);
363 #endif
364
365 // If failed, release ring descriptors DMA block & exit
366 if (!ring_data) {
367 pci_free_consistent(pAd->pPci_Dev, (RX_RING_SIZE * RING_DESCRIPTOR_SIZE), ring, ring_dma);
368 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring buffer memory.\n");
369 goto err_out_allocate_rxring;
370 }
371
372 // Rx ring & DMA buffer
373 for (index = 0; index < RX_RING_SIZE; index++)
374 {
375 // Init Rx Ring Size, Va, Pa variables
376 pAd->RxRing[index].size = RING_DESCRIPTOR_SIZE;
377 pAd->RxRing[index].va_addr = ring;
378 pAd->RxRing[index].pa_addr = ring_dma;
379 ring += RING_DESCRIPTOR_SIZE;
380 ring_dma += RING_DESCRIPTOR_SIZE;
381
382 // Init Rx DMA buffer
383 pAd->RxRing[index].data_size = RX_BUFFER_SIZE;
384 pAd->RxRing[index].va_data_addr = ring_data;
385 pAd->RxRing[index].pa_data_addr = ring_data_dma;
386 ring_data += RX_BUFFER_SIZE;
387 ring_data_dma += RX_BUFFER_SIZE;
388
389 // Write RxD buffer address & allocated buffer length
390 pRxD = (PRXD_STRUC) pAd->RxRing[index].va_addr;
391 #ifndef BIG_ENDIAN
392 pRxD->BufferAddressPa = pAd->RxRing[index].pa_data_addr;
393 #else
394 pRxD->BufferAddressPa = SWAP32(pAd->RxRing[index].pa_data_addr);
395 #endif
396 // Rx owner bit assign to NIC immediately
397 pRxD->Owner = DESC_OWN_NIC;
398
399 #ifdef BIG_ENDIAN
400 RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
401 #endif
402
403 DBGPRINT(RT_DEBUG_INFO, "RxRing[%d] va = 0x%lu, pa = 0x%x, size = 0x%x\n",
404 index, (unsigned long)pAd->RxRing[index].va_addr, (UINT)pAd->RxRing[index].pa_addr, pAd->RxRing[index].size);
405 DBGPRINT(RT_DEBUG_INFO, "RxRing[%d] va_data = 0x%lu, pa_data = 0x%x, size = 0x%x\n",
406 index, (unsigned long)pAd->RxRing[index].va_data_addr, (UINT)pAd->RxRing[index].pa_data_addr, pAd->RxRing[index].data_size);
407 }
408
409 // 5. Allocate Beacon Ring DMA descriptor and buffer memory
410 // Init Beacon Ring Size, Va, Pa variables
411 #if 0 // mask by Victor Yu. 05-18-2006
412 ring = pci_alloc_consistent(pAd->pPci_Dev, RING_DESCRIPTOR_SIZE, &ring_dma);
413 #else // add by Victor Yu. 05-18-2006
414 ring = (VOID *)dma_alloc_coherent(NULL, RING_DESCRIPTOR_SIZE, &ring_dma, GFP_DMA|GFP_KERNEL);
415 #endif
416
417 if (!ring) {
418 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring descriptor memory.\n");
419 goto err_out_allocate_beaconring;
420 }
421
422 // Zero init ring descriptors
423 memset(ring, 0, (RING_DESCRIPTOR_SIZE));
424
425 // Allocate Ring data DMA blocks
426 #if 0 // mask by Victor Yu. 05-18-2006
427 ring_data = pci_alloc_consistent(pAd->pPci_Dev, BEACON_BUFFER_SIZE, &ring_data_dma);
428 #else // add by Victor Yu. 05-18-2006
429 ring_data = (VOID *)dma_alloc_coherent(NULL, BEACON_BUFFER_SIZE, &ring_data_dma, GFP_DMA|GFP_KERNEL);
430 #endif
431
432 // If failed, release ring descriptors DMA block & exit
433 if (!ring_data) {
434 pci_free_consistent(pAd->pPci_Dev, RING_DESCRIPTOR_SIZE, ring, ring_dma);
435 DBGPRINT(RT_DEBUG_ERROR, "Could not allocate DMA ring buffer memory.\n");
436 goto err_out_allocate_beaconring;
437 }
438
439 pAd->BeaconRing.size = RING_DESCRIPTOR_SIZE;
440 pAd->BeaconRing.va_addr = ring;
441 pAd->BeaconRing.pa_addr = ring_dma;
442
443 // Init Beacon DMA buffer
444 pAd->BeaconRing.data_size = BEACON_BUFFER_SIZE;
445 pAd->BeaconRing.va_data_addr = ring_data;
446 pAd->BeaconRing.pa_data_addr = ring_data_dma;
447
448 // Write RxD buffer address & allocated buffer length
449 pTxD = (PTXD_STRUC) pAd->BeaconRing.va_addr;
450 #ifndef BIG_ENDIAN
451 pTxD->BufferAddressPa = pAd->BeaconRing.pa_data_addr;
452 #else
453 pTxD->BufferAddressPa = SWAP32(pAd->BeaconRing.pa_data_addr);
454 #endif
455
456 DBGPRINT(RT_DEBUG_INFO, "BeaconRing va = 0x%lu, pa = 0x%x, size = 0x%x\n",
457 (unsigned long)pAd->BeaconRing.va_addr, (UINT)pAd->BeaconRing.pa_addr, pAd->BeaconRing.size);
458 DBGPRINT(RT_DEBUG_INFO, "BeaconRing va_data = 0x%lu, pa_data = 0x%x, size = 0x%x\n",
459 (unsigned long)pAd->BeaconRing.va_data_addr, (UINT)pAd->BeaconRing.pa_data_addr, pAd->BeaconRing.data_size);
460
461 DBGPRINT(RT_DEBUG_INFO, "<-- RTMPAllocDMAMemory\n");
462 return NDIS_STATUS_SUCCESS;
463
464
465 err_out_allocate_beaconring:
466 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
467 pci_free_consistent(pAd->pPci_Dev, (RX_RING_SIZE * RX_BUFFER_SIZE),
468 pAd->RxRing[0].va_data_addr, pAd->RxRing[0].pa_data_addr);
469 // Free ring descriptor second, the start address is the same as TxRing first elment
470 pci_free_consistent(pAd->pPci_Dev, (RX_RING_SIZE * RING_DESCRIPTOR_SIZE),
471 pAd->RxRing[0].va_addr, pAd->RxRing[0].pa_addr);
472 err_out_allocate_rxring:
473 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
474 pci_free_consistent(pAd->pPci_Dev, (ATIM_RING_SIZE * ATIM_BUFFER_SIZE),
475 pAd->AtimRing[0].va_data_addr, pAd->AtimRing[0].pa_data_addr);
476 // Free ring descriptor second, the start address is the same as TxRing first elment
477 pci_free_consistent(pAd->pPci_Dev, (ATIM_RING_SIZE * RING_DESCRIPTOR_SIZE),
478 pAd->AtimRing[0].va_addr, pAd->AtimRing[0].pa_addr);
479 err_out_allocate_atimring:
480 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
481 pci_free_consistent(pAd->pPci_Dev, (PRIO_RING_SIZE * PRIO_BUFFER_SIZE),
482 pAd->PrioRing[0].va_data_addr, pAd->PrioRing[0].pa_data_addr);
483 // Free ring descriptor second, the start address is the same as TxRing first elment
484 pci_free_consistent(pAd->pPci_Dev, (PRIO_RING_SIZE * RING_DESCRIPTOR_SIZE),
485 pAd->PrioRing[0].va_addr, pAd->PrioRing[0].pa_addr);
486 err_out_allocate_prioring:
487 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
488 pci_free_consistent(pAd->pPci_Dev, (TX_RING_SIZE * TX_BUFFER_SIZE),
489 pAd->TxRing[0].va_data_addr, pAd->TxRing[0].pa_data_addr);
490 // Free ring descriptor second, the start address is the same as TxRing first elment
491 pci_free_consistent(pAd->pPci_Dev, (TX_RING_SIZE * RING_DESCRIPTOR_SIZE),
492 pAd->TxRing[0].va_addr, pAd->TxRing[0].pa_addr);
493 err_out_allocate_txring:
494 DBGPRINT(RT_DEBUG_ERROR, "<-- RTMPAllocDMAMemory (memory not allocate successfully!)\n");
495
496 return -ENOMEM;
497 }
498
499 /*
500 ========================================================================
501
502 Routine Description:
503 Free all DMA memory.
504
505 Arguments:
506 Adapter Pointer to our adapter
507
508 Return Value:
509 None
510
511 Note:
512
513 ========================================================================
514 */
515 VOID RTMPFreeDMAMemory(
516 IN PRTMP_ADAPTER pAd)
517 {
518 DBGPRINT(RT_DEBUG_INFO, "--> RTMPFreeDMAMemory\n");
519
520 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
521 pci_free_consistent(pAd->pPci_Dev, (TX_RING_SIZE * TX_BUFFER_SIZE),
522 pAd->TxRing[0].va_data_addr, pAd->TxRing[0].pa_data_addr);
523 // Free ring descriptor second, the start address is the same as TxRing first elment
524 pci_free_consistent(pAd->pPci_Dev, (TX_RING_SIZE * RING_DESCRIPTOR_SIZE),
525 pAd->TxRing[0].va_addr, pAd->TxRing[0].pa_addr);
526
527 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
528 pci_free_consistent(pAd->pPci_Dev, (PRIO_RING_SIZE * PRIO_BUFFER_SIZE),
529 pAd->PrioRing[0].va_data_addr, pAd->PrioRing[0].pa_data_addr);
530 // Free ring descriptor second, the start address is the same as TxRing first elment
531 pci_free_consistent(pAd->pPci_Dev, (PRIO_RING_SIZE * RING_DESCRIPTOR_SIZE),
532 pAd->PrioRing[0].va_addr, pAd->PrioRing[0].pa_addr);
533
534 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
535 pci_free_consistent(pAd->pPci_Dev, (ATIM_RING_SIZE * ATIM_BUFFER_SIZE),
536 pAd->AtimRing[0].va_data_addr, pAd->AtimRing[0].pa_data_addr);
537 // Free ring descriptor second, the start address is the same as TxRing first elment
538 pci_free_consistent(pAd->pPci_Dev, (ATIM_RING_SIZE * RING_DESCRIPTOR_SIZE),
539 pAd->AtimRing[0].va_addr, pAd->AtimRing[0].pa_addr);
540
541 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
542 pci_free_consistent(pAd->pPci_Dev, (RX_RING_SIZE * RX_BUFFER_SIZE),
543 pAd->RxRing[0].va_data_addr, pAd->RxRing[0].pa_data_addr);
544 // Free ring descriptor second, the start address is the same as TxRing first elment
545 pci_free_consistent(pAd->pPci_Dev, (RX_RING_SIZE * RING_DESCRIPTOR_SIZE),
546 pAd->RxRing[0].va_addr, pAd->RxRing[0].pa_addr);
547
548 // Free data DMA blocks first, the start address is the same as TxRing first DMA data block
549 pci_free_consistent(pAd->pPci_Dev, (BEACON_RING_SIZE * BEACON_BUFFER_SIZE),
550 pAd->BeaconRing.va_data_addr, pAd->BeaconRing.pa_data_addr);
551 // Free ring descriptor second, the start address is the same as TxRing first elment
552 pci_free_consistent(pAd->pPci_Dev, (BEACON_RING_SIZE * RING_DESCRIPTOR_SIZE),
553 pAd->BeaconRing.va_addr, pAd->BeaconRing.pa_addr);
554
555 }
556
557 /*
558 ========================================================================
559
560 Routine Description:
561 Initialize transmit data structures
562
563 Arguments:
564 Adapter Pointer to our adapter
565
566 Return Value:
567 None
568
569 Note:
570 Initialize all transmit releated private buffer, include those define
571 in RTMP_ADAPTER structure and all private data structures.
572
573 ========================================================================
574 */
575 VOID NICInitTransmit(
576 IN PRTMP_ADAPTER pAdapter)
577 {
578 DBGPRINT(RT_DEBUG_TRACE, "--> NICInitTransmit\n");
579
580 // Initialize all Transmit releated queues
581 InitializeQueueHeader(&pAdapter->TxSwQueue0);
582 InitializeQueueHeader(&pAdapter->TxSwQueue1);
583 InitializeQueueHeader(&pAdapter->TxSwQueue2);
584 InitializeQueueHeader(&pAdapter->TxSwQueue3);
585
586 // Init Ring index pointer
587 pAdapter->CurRxIndex = 0;
588 pAdapter->CurDecryptIndex = 0;
589 pAdapter->CurTxIndex = 0;
590 pAdapter->CurEncryptIndex = 0;
591 pAdapter->CurAtimIndex = 0;
592 pAdapter->CurPrioIndex = 0;
593 pAdapter->NextEncryptDoneIndex = 0;
594 pAdapter->NextTxDoneIndex = 0;
595 pAdapter->NextAtimDoneIndex = 0;
596 pAdapter->NextPrioDoneIndex = 0;
597 pAdapter->NextDecryptDoneIndex = 0;
598 pAdapter->PushMgmtIndex = 0;
599 pAdapter->PopMgmtIndex = 0;
600 pAdapter->MgmtQueueSize = 0;
601
602 pAdapter->PrivateInfo.TxRingFullCnt = 0;
603
604 DBGPRINT(RT_DEBUG_TRACE, "<-- NICInitTransmit\n");
605 }
606
607 // By removing 'inline' directive from the function definitions.
608 // Then Driverloader is compiled and runs smooth after kernel 2.6.9
609 #ifdef BIG_ENDIAN
610 inline VOID
611 #else
612 VOID
613 #endif
614 NICDisableInterrupt(
615 IN PRTMP_ADAPTER pAd)
616 {
617 RTMP_IO_WRITE32(pAd, CSR8, 0xFFFF);
618 RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE);
619 }
620
621
622 #ifdef BIG_ENDIAN
623 inline VOID
624 #else
625 VOID
626 #endif
627 NICEnableInterrupt(
628 IN PRTMP_ADAPTER pAd)
629 {
630 // 0xFF37 : Txdone & Rxdone, 0xFF07: Txdonw, Rxdone, PrioDone, AtimDone,
631 RTMP_IO_WRITE32(pAd, CSR8, 0xFE14);
632 RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE);
633 }
634
635 /*
636 ========================================================================
637
638 Routine Description:
639 Read additional information from EEPROM, such as MAC address
640
641 Arguments:
642 Adapter Pointer to our adapter
643
644 Return Value:
645 NDIS_STATUS_SUCCESS
646 NDIS_STATUS_FAILURE
647
648 Note:
649
650 ========================================================================
651 */
652 NDIS_STATUS NICReadAdapterInfo(
653 IN PRTMP_ADAPTER pAd)
654 {
655 CSR3_STRUC StaMacReg0;
656 CSR4_STRUC StaMacReg1;
657 NDIS_STATUS Status = NDIS_STATUS_SUCCESS;
658
659 //
660 // Read MAC address from CSR3 & CSR4, these CSRs reflects real value
661 // stored with EEPROM.
662 //
663 RTMP_IO_READ32(pAd, CSR3, &StaMacReg0.word);
664 RTMP_IO_READ32(pAd, CSR4, &StaMacReg1.word);
665 // Set Current address
666 pAd->CurrentAddress[0] = StaMacReg0.field.Byte0;
667 pAd->CurrentAddress[1] = StaMacReg0.field.Byte1;
668 pAd->CurrentAddress[2] = StaMacReg0.field.Byte2;
669 pAd->CurrentAddress[3] = StaMacReg0.field.Byte3;
670 pAd->CurrentAddress[4] = StaMacReg1.field.Byte4;
671 pAd->CurrentAddress[5] = StaMacReg1.field.Byte5;
672 pAd->PermanentAddress[0] = StaMacReg0.field.Byte0;
673 pAd->PermanentAddress[1] = StaMacReg0.field.Byte1;
674 pAd->PermanentAddress[2] = StaMacReg0.field.Byte2;
675 pAd->PermanentAddress[3] = StaMacReg0.field.Byte3;
676 pAd->PermanentAddress[4] = StaMacReg1.field.Byte4;
677 pAd->PermanentAddress[5] = StaMacReg1.field.Byte5;
678
679 return Status;
680 }
681
682 /*
683 ========================================================================
684
685 Routine Description:
686 Read initial parameters from EEPROM
687
688 Arguments:
689 Adapter Pointer to our adapter
690
691 Return Value:
692 None
693
694 Note:
695
696 ========================================================================
697 */
698 VOID NICReadEEPROMParameters(
699 IN PRTMP_ADAPTER pAdapter)
700 {
701 ULONG data;
702 USHORT i, value;
703 UCHAR TmpPhy;
704 EEPROM_TX_PWR_STRUC Power;
705 EEPROM_VERSION_STRUC Version;
706 EEPROM_ANTENNA_STRUC Antenna;
707
708 DBGPRINT(RT_DEBUG_TRACE, "--> NICReadEEPROMParameters\n");
709
710 // Init EEPROM Address Number, before access EEPROM; if 93c46, EEPROMAddressNum=6, else if 93c66, EEPROMAddressNum=8
711 RTMP_IO_READ32(pAdapter, CSR21, &data);
712
713 if(data & 0x20)
714 pAdapter->EEPROMAddressNum = 6;
715 else
716 pAdapter->EEPROMAddressNum = 8;
717
718 // if E2PROM version mismatch with driver's expectation, then skip
719 // all subsequent E2RPOM retieval and set a system error bit to notify GUI
720 Version.word = RTMP_EEPROM_READ16(pAdapter, EEPROM_VERSION_OFFSET);
721 if (Version.field.Version != VALID_EEPROM_VERSION)
722 {
723 DBGPRINT(RT_DEBUG_ERROR, "WRONG E2PROM VERSION %d, should be %d\n",Version.field.Version, VALID_EEPROM_VERSION);
724 pAdapter->PortCfg.SystemErrorBitmap |= 0x00000001;
725 return;
726 }
727
728 // Read BBP default value from EEPROM and store to array(EEPROMDefaultValue) in pAdapter
729 for(i = 0; i < NUM_EEPROM_BBP_PARMS; i++)
730 {
731 value = RTMP_EEPROM_READ16(pAdapter, EEPROM_BBP_BASE_OFFSET + i*2);
732
733 pAdapter->EEPROMDefaultValue[i] = value;
734 }
735
736 #if 1
737 // We have to parse NIC configuration 0 at here.
738 // If TSSI did not have preloaded value, it should reset the TxAutoAgc to false
739 // Therefore, we have to read TxAutoAgc control beforehand.
740 // Read Tx AGC control bit
741 Antenna.word = pAdapter->EEPROMDefaultValue[0];
742 if (Antenna.field.DynamicTxAgcControl == 1)
743 pAdapter->PortCfg.bAutoTxAgc = TRUE;
744 else
745 pAdapter->PortCfg.bAutoTxAgc = FALSE;
746
747 // Read Tx power value for all 14 channels
748 // Value from 1 - 0x7f. Default value is 24.
749 for (i = 0; i < NUM_EEPROM_TX_PARMS; i++)
750 {
751 Power.word = RTMP_EEPROM_READ16(pAdapter, EEPROM_TX_PWR_OFFSET + i*2);
752 pAdapter->PortCfg.ChannelTxPower[i * 2] = ((Power.field.Byte0 > 32) ? 24 : Power.field.Byte0);
753 pAdapter->PortCfg.ChannelTxPower[i * 2 + 1] = ((Power.field.Byte1 > 32) ? 24 : Power.field.Byte1);
754 }
755
756 // Read Tx TSSI reference value, OK to reuse Power data structure
757 for (i = 0; i < NUM_EEPROM_TX_PARMS; i++)
758 {
759 Power.word = RTMP_EEPROM_READ16(pAdapter, EEPROM_TSSI_REF_OFFSET + i * 2);
760 pAdapter->PortCfg.ChannelTssiRef[i * 2] = Power.field.Byte0;
761 pAdapter->PortCfg.ChannelTssiRef[i * 2 + 1] = Power.field.Byte1;
762 // Disable TxAgc if the value is not right
763 if ((pAdapter->PortCfg.ChannelTssiRef[i * 2] == 0xff) ||
764 (pAdapter->PortCfg.ChannelTssiRef[i * 2 + 1] == 0xff))
765 pAdapter->PortCfg.bAutoTxAgc = FALSE;
766 }
767
768 // Tx Tssi delta offset 0x24
769 Power.word = RTMP_EEPROM_READ16(pAdapter, EEPROM_TSSI_DELTA_OFFSET);
770 pAdapter->PortCfg.ChannelTssiDelta = Power.field.Byte0;
771
772 #endif
773
774 //CountryRegion byte offset = 0x35
775 value = pAdapter->EEPROMDefaultValue[2] >> 8;
776 if ((value <= 7))
777 {
778 pAdapter->PortCfg.CountryRegion = (UCHAR) value;
779 TmpPhy = pAdapter->PortCfg.PhyMode;
780 pAdapter->PortCfg.PhyMode = 0xff;
781 RTMPSetPhyMode(pAdapter, TmpPhy);
782 }
783 // Read new Calibrated CV value, reuse the power variable
784 Power.word = RTMP_EEPROM_READ16(pAdapter, EEPROM_CALIBRATE_OFFSET);
785 if (Power.field.Byte0 == 0xff)
786 {
787 //pAdapter->PortCfg.R17Dec = 0;
788 pAdapter->PortCfg.RssiToDbm = 0x79;
789 }
790 else
791 {
792 //pAdapter->PortCfg.R17Dec = 0x79 - Power.field.Byte0;
793 pAdapter->PortCfg.RssiToDbm = Power.field.Byte0;
794 }
795
796 DBGPRINT(RT_DEBUG_TRACE, "<-- NICReadEEPROMParameters, pAdapter->PortCfg.RssiToDbm = %d\n", pAdapter->PortCfg.RssiToDbm);
797 }
798
799 /*
800 ========================================================================
801
802 Routine Description:
803 Set default value from EEPROM
804
805 Arguments:
806 Adapter Pointer to our adapter
807
808 Return Value:
809 None
810
811 Note:
812
813 ========================================================================
814 */
815 VOID NICInitAsicFromEEPROM(
816 IN PRTMP_ADAPTER pAdapter)
817 {
818 ULONG data, BbpCsr1;
819 USHORT i, value;
820 UCHAR TxValue,RxValue;
821 EEPROM_ANTENNA_STRUC Antenna;
822 EEPROM_NIC_CONFIG2_STRUC NicConfig2;
823
824 DBGPRINT(RT_DEBUG_TRACE, "--> NICInitAsicFromEEPROM\n");
825
826 for(i = 3; i < NUM_EEPROM_BBP_PARMS; i++)
827 {
828 value = pAdapter->EEPROMDefaultValue[i];
829
830 if((value != 0xFFFF) && (value != 0))
831 {
832 data = value | 0x18000;
833 RTMP_BBP_IO_WRITE32(pAdapter, data);
834 }
835 }
836
837 Antenna.word = pAdapter->EEPROMDefaultValue[0];
838
839 if ((Antenna.word == 0xFFFF) || (Antenna.field.TxDefaultAntenna > 2) || (Antenna.field.RxDefaultAntenna > 2))
840 {
841 DBGPRINT(RT_DEBUG_TRACE, "E2PROM error(=0x%04x), hard code as 0x0002\n", Antenna.word);
842 Antenna.word = 0x0002;
843 }
844
845 pAdapter->PortCfg.NumberOfAntenna = 2; // (UCHAR)Antenna.field.NumOfAntenna;
846 pAdapter->PortCfg.CurrentTxAntenna = (UCHAR)Antenna.field.TxDefaultAntenna;
847 pAdapter->PortCfg.CurrentRxAntenna = (UCHAR)Antenna.field.RxDefaultAntenna;
848 pAdapter->PortCfg.RfType = (UCHAR) Antenna.field.RfType;
849
850 RTMP_BBP_IO_READ32_BY_REG_ID(pAdapter, BBP_Tx_Configure, &TxValue);
851 RTMP_BBP_IO_READ32_BY_REG_ID(pAdapter, BBP_Rx_Configure, &RxValue);
852 RTMP_IO_READ32(pAdapter, BBPCSR1, &BbpCsr1);
853
854 // Tx antenna select
855 if(Antenna.field.TxDefaultAntenna == 1) // Antenna A
856 {
857 TxValue = (TxValue & 0xFC) | 0x00;
858 BbpCsr1 = (BbpCsr1 & 0xFFFCFFFC) | 0x00000000;
859 }
860 else if(Antenna.field.TxDefaultAntenna == 2) // Antenna B
861 {
862 TxValue = (TxValue & 0xFC) | 0x02;
863 BbpCsr1 = (BbpCsr1 & 0xFFFCFFFC) | 0x00020002;
864 }
865 else // diverity - start from Antenna B
866 {
867 TxValue = (TxValue & 0xFC) | 0x02;
868 BbpCsr1 = (BbpCsr1 & 0xFFFCFFFC) | 0x00020002;
869 }
870
871 // Rx antenna select
872 if(Antenna.field.RxDefaultAntenna == 1) // Antenna A
873 RxValue = (RxValue & 0xFC) | 0x00;
874 else if(Antenna.field.RxDefaultAntenna == 2) // Antenna B
875 RxValue = (RxValue & 0xFC) | 0x02;
876 else // Antenna Diversity
877 RxValue = (RxValue & 0xFC) | 0x02;
878
879 // RT5222 needs special treatment to swap TX I/Q
880 if (pAdapter->PortCfg.RfType == RFIC_5222)
881 {
882 BbpCsr1 |= 0x00040004;
883 TxValue |= 0x04; // TX I/Q flip
884 }
885 // RT2525E need to flip TX I/Q but not RX I/Q
886 else if (pAdapter->PortCfg.RfType == RFIC_2525E)
887 {
888 BbpCsr1 |= 0x00040004;
889 TxValue |= 0x04; // TX I/Q flip
890 RxValue &= 0xfb; // RX I/Q no flip
891 }
892
893 // Change to match microsoft definition, 0xff: diversity, 0: A, 1: B
894 pAdapter->PortCfg.CurrentTxAntenna--;
895 pAdapter->PortCfg.CurrentRxAntenna--;
896
897 RTMP_IO_WRITE32(pAdapter, BBPCSR1, BbpCsr1);
898 RTMP_BBP_IO_WRITE32_BY_REG_ID(pAdapter, BBP_Tx_Configure, TxValue);
899 RTMP_BBP_IO_WRITE32_BY_REG_ID(pAdapter, BBP_Rx_Configure, RxValue);
900
901 // 2003-12-16 software-based RX antenna diversity
902 // pAdapter->PortCfg.CurrentRxAntenna = 0xff; // Diversity ON
903 AsicSetRxAnt(pAdapter);
904
905 if (Antenna.field.LedMode == LED_MODE_TXRX_ACTIVITY)
906 pAdapter->PortCfg.LedMode = LED_MODE_TXRX_ACTIVITY;
907 else if (Antenna.field.LedMode == LED_MODE_SINGLE)
908 {
909 pAdapter->PortCfg.LedMode = LED_MODE_SINGLE;
910 ASIC_LED_ACT_ON(pAdapter);
911 }
912 else if (Antenna.field.LedMode == LED_MODE_ASUS)
913 {
914 pAdapter->PortCfg.LedMode = LED_MODE_ASUS;
915 RTMP_IO_WRITE32(pAdapter, LEDCSR, 0x0002461E);
916 }
917 else
918 pAdapter->PortCfg.LedMode = LED_MODE_DEFAULT;
919
920 // Read Hardware controlled Radio state enable bit
921 if (Antenna.field.HardwareRadioControl == 1)
922 {
923 pAdapter->PortCfg.bHardwareRadio = TRUE;
924
925 // Read GPIO pin0 as Hardware controlled radio state
926 RTMP_IO_READ32(pAdapter, GPIOCSR, &data);
927 if ((data & 0x01) == 0)
928 {
929 pAdapter->PortCfg.bHwRadio = FALSE;
930 pAdapter->PortCfg.bRadio = FALSE;
931 RTMP_IO_WRITE32(pAdapter, PWRCSR0, 0x00000000);
932 RTMP_SET_FLAG(pAdapter, fRTMP_ADAPTER_RADIO_OFF);
933 if (pAdapter->PortCfg.LedMode == LED_MODE_ASUS)
934 {
935 // Turn bit 17 for Radio OFF
936 RTMP_IO_WRITE32(pAdapter, LEDCSR, 0x0000461E);
937 }
938 }
939 }
940 else
941 pAdapter->PortCfg.bHardwareRadio = FALSE;
942
943 NicConfig2.word = pAdapter->EEPROMDefaultValue[1];
944 if (NicConfig2.word == 0xffff)
945 NicConfig2.word = 0; // empty E2PROM, use default
946
947 // for dynamic BBP R17:RX sensibility tuning
948 {
949 UCHAR r17;
950 RTMP_BBP_IO_READ32_BY_REG_ID(pAdapter, 17, &r17);
951 pAdapter->PortCfg.BbpTuningEnable = (NicConfig2.field.DynamicBbpTuning==0)? 1:0;
952 pAdapter->PortCfg.VgcLowerBound = r17;
953
954 // 2004-3-4 per David's request, R7 starts at upper bound
955 pAdapter->PortCfg.BbpTuning.VgcUpperBound = BBP_R17_DYNAMIC_UP_BOUND;
956 r17 = pAdapter->PortCfg.BbpTuning.VgcUpperBound;
957 pAdapter->PortCfg.LastR17Value = r17;
958 RTMP_BBP_IO_WRITE32_BY_REG_ID(pAdapter, 17, r17);
959
960 // 2004-2-2 per David's request, lower R17 low-bound for very good quality NIC
961 pAdapter->PortCfg.VgcLowerBound -= 6;
962 DBGPRINT(RT_DEBUG_TRACE,"R17 tuning enable=%d, R17=0x%02x, range=<0x%02x, 0x%02x>\n",
963 pAdapter->PortCfg.BbpTuningEnable, r17, pAdapter->PortCfg.VgcLowerBound, pAdapter->PortCfg.BbpTuning.VgcUpperBound);
964 }
965
966 DBGPRINT(RT_DEBUG_TRACE, "RF IC=%d, LED mode=%d\n", pAdapter->PortCfg.RfType, pAdapter->PortCfg.LedMode);
967
968 DBGPRINT(RT_DEBUG_TRACE, "<-- NICInitAsicFromEEPROM\n");
969 }
970
971 void NICInitializeAdapter(IN PRTMP_ADAPTER pAdapter)
972 {
973 TXCSR2_STRUC TxCSR2;
974 RXCSR1_STRUC RxCSR1;
975 ULONG Value;
976
977 DBGPRINT(RT_DEBUG_TRACE, "--> NICInitializeAdapter\n");
978
979 // Init spin locks
980 NdisAllocateSpinLock(&pAdapter->TxRingLock);
981 NdisAllocateSpinLock(&pAdapter->PrioRingLock);
982 NdisAllocateSpinLock(&pAdapter->AtimRingLock);
983 NdisAllocateSpinLock(&pAdapter->RxRingLock);
984 NdisAllocateSpinLock(&pAdapter->TxSwQueueLock);
985 NdisAllocateSpinLock(&pAdapter->MemLock);
986
987 // Write TXCSR2 register
988 TxCSR2.field.TxDSize = RING_DESCRIPTOR_SIZE;
989 TxCSR2.field.NumTxD = TX_RING_SIZE;
990 TxCSR2.field.NumAtimD = ATIM_RING_SIZE;
991 TxCSR2.field.NumPrioD = PRIO_RING_SIZE;
992 RTMP_IO_WRITE32(pAdapter, TXCSR2, TxCSR2.word);
993
994 // Write TXCSR3 register
995 Value = pAdapter->TxRing[0].pa_addr;
996 RTMP_IO_WRITE32(pAdapter, TX_RING_BASE_REG, Value);
997
998 // Write TXCSR4 register
999 Value = pAdapter->PrioRing[0].pa_addr;
1000 RTMP_IO_WRITE32(pAdapter, PRIO_RING_BASE_REG, Value);
1001
1002 // Write TXCSR5 register
1003 Value = pAdapter->AtimRing[0].pa_addr;
1004 RTMP_IO_WRITE32(pAdapter, ATIM_RING_BASE_REG, Value);
1005
1006 // Write TXCSR6 register
1007 Value = pAdapter->BeaconRing.pa_addr;
1008 RTMP_IO_WRITE32(pAdapter, BEACON_BASE_REG, Value);
1009
1010 // Write RXCSR1 register
1011 RxCSR1.field.RxDSize = RING_DESCRIPTOR_SIZE;
1012 RxCSR1.field.NumRxD = RX_RING_SIZE;
1013 RTMP_IO_WRITE32(pAdapter, RXCSR1, RxCSR1.word);
1014
1015 // Write RXCSR2 register
1016 Value = pAdapter->RxRing[0].pa_addr;
1017 RTMP_IO_WRITE32(pAdapter, RX_RING_BASE_REG, Value);
1018
1019 // Write CSR1 for host ready
1020 // Move Host reay to end of ASIC initialization
1021 // to ensure no Rx will perform before ASIC init
1022 // RTMP_IO_WRITE32(pAdapter, CSR1, 0x4);
1023
1024 // Initialze ASIC for TX & Rx operation
1025 NICInitializeAsic(pAdapter);
1026
1027 DBGPRINT(RT_DEBUG_TRACE, "<-- NICInitializeAdapter\n");
1028 }
1029
1030 void NICInitializeAsic(IN PRTMP_ADAPTER pAdapter)
1031 {
1032 ULONG Index;
1033 UCHAR Value = 0xff;
1034
1035 DBGPRINT(RT_DEBUG_TRACE, "--> NICInitializeAsic\n");
1036
1037 // Initialize MAC register to default value
1038 for (Index = 0; Index < NUM_MAC_REG_PARMS; Index++)
1039 {
1040 RTMP_IO_WRITE32(pAdapter, MACRegTable[Index].Register, MACRegTable[Index].Value);
1041 }
1042
1043 // Set Host ready before kicking Rx
1044 RTMP_IO_WRITE32(pAdapter, CSR1, 0x1); // reset MAC state machine, requested by Kevin 2003-2-11
1045 RTMP_IO_WRITE32(pAdapter, CSR1, 0x4);
1046
1047 // Read BBP register, make sure BBP is up and running before write new data
1048 while ((Value == 0xff) || (Value == 0x00))
1049 {
1050 RTMP_BBP_IO_READ32_BY_REG_ID(pAdapter, BBP_Version, &Value);
1051 DBGPRINT(RT_DEBUG_TRACE, "Value = %d\n", Value);
1052 }
1053
1054 // Initialize BBP register to default value
1055 for (Index = 0; Index < NUM_BBP_REG_PARMS; Index++)
1056 {
1057 RTMP_BBP_IO_WRITE32(pAdapter, BBPRegTable[Index]);
1058 }
1059
1060 // Initialize RF register to default value
1061 AsicSwitchChannel(pAdapter, pAdapter->PortCfg.Channel);
1062 AsicLockChannel(pAdapter, pAdapter->PortCfg.Channel);
1063
1064 // Add radio off control
1065 if (pAdapter->PortCfg.bRadio == FALSE)
1066 {
1067 RTMP_IO_WRITE32(pAdapter, PWRCSR0, 0x00000000);
1068 RTMP_SET_FLAG(pAdapter, fRTMP_ADAPTER_RADIO_OFF);
1069 }
1070
1071 // Kick Rx
1072 RTMP_IO_WRITE32(pAdapter, RXCSR0, 0x7e);
1073 // Clear old FCS jitter before init ASIC
1074 RTMP_IO_READ32(pAdapter, CNT0, &Index);
1075 // Clear old Rx FIFO error jitter before init ASIC
1076 RTMP_IO_READ32(pAdapter, CNT4, &Index);
1077
1078 DBGPRINT(RT_DEBUG_TRACE, "<-- NICInitializeAsic\n");
1079 }
1080
1081 /*
1082 ========================================================================
1083
1084 Routine Description:
1085 Reset NIC Asics
1086
1087 Arguments:
1088 Adapter Pointer to our adapter
1089
1090 Return Value:
1091 None
1092
1093 Note:
1094 Reset NIC to initial state AS IS system boot up time.
1095
1096 ========================================================================
1097 */
1098 VOID NICIssueReset(
1099 IN PRTMP_ADAPTER pAdapter)
1100 {
1101 CSR3_STRUC StaMacReg0;
1102 CSR4_STRUC StaMacReg1;
1103
1104 DBGPRINT(RT_DEBUG_TRACE, "--> NICIssueReset\n");
1105
1106 // Abort Tx, prevent ASIC from writing to Host memory
1107 RTMP_IO_WRITE32(pAdapter, TXCSR0, 0x08);
1108
1109 // Disable Rx, register value supposed will remain after reset
1110 RTMP_IO_WRITE32(pAdapter, RXCSR0, 0x01);
1111
1112 if (pAdapter->PortCfg.bLocalAdminMAC)
1113 {
1114 // Write Back Permanent MAC address to CSR3 & CSR4
1115 StaMacReg0.field.Byte0 = pAdapter->PermanentAddress[0];
1116 StaMacReg0.field.Byte1 = pAdapter->PermanentAddress[1];
1117 StaMacReg0.field.Byte2 = pAdapter->PermanentAddress[2];
1118 StaMacReg0.field.Byte3 = pAdapter->PermanentAddress[3];
1119 StaMacReg1.field.Byte4 = pAdapter->PermanentAddress[4];
1120 StaMacReg1.field.Byte5 = pAdapter->PermanentAddress[5];
1121 RTMP_IO_WRITE32(pAdapter, CSR3, StaMacReg0.word);
1122 RTMP_IO_WRITE32(pAdapter, CSR4, StaMacReg1.word);
1123 }
1124
1125 // Issue reset and clear from reset state
1126 RTMP_IO_WRITE32(pAdapter, CSR1, 0x01);
1127 RTMP_IO_WRITE32(pAdapter, CSR1, 0x00);
1128
1129 DBGPRINT(RT_DEBUG_TRACE, "<-- NICIssueReset\n");
1130 }
1131
1132 /*
1133 ========================================================================
1134
1135 Routine Description:
1136 Check ASIC registers and find any reason the system might hang
1137
1138 Arguments:
1139 Adapter Pointer to our adapter
1140
1141 Return Value:
1142 None
1143
1144 Note:
1145
1146
1147 ========================================================================
1148 */
1149 BOOLEAN NICCheckForHang(
1150 IN PRTMP_ADAPTER pAd)
1151 {
1152 // garbage collection
1153 // if ((pAd->RalinkCounters.EncryptCount - pAd->RalinkCounters.TxDoneCount) == TX_RING_SIZE)
1154 // {
1155 // DBGPRINT(RT_DEBUG_WARNING,"\nNICCheckForHang --- Garbage Collection!!!\n\n");
1156 // }
1157
1158 {
1159 RTMPHandleTxRingTxDoneInterrupt(pAd);
1160 RTMPHandleEncryptionDoneInterrupt(pAd);
1161 }
1162
1163 return (FALSE);
1164 }
1165
1166 /*
1167 ========================================================================
1168
1169 Routine Description:
1170 Reset NIC from error
1171
1172 Arguments:
1173 Adapter Pointer to our adapter
1174
1175 Return Value:
1176 None
1177
1178 Note:
1179 Reset NIC from error state
1180
1181 ========================================================================
1182 */
1183 VOID NICResetFromError(
1184 IN PRTMP_ADAPTER pAdapter)
1185 {
1186 // Reset BBP (according to alex, reset ASIC will force reset BBP
1187 // Therefore, skip the reset BBP
1188 // RTMP_IO_WRITE32(pAdapter, CSR1, 0x2);
1189 // Release BBP reset
1190 // RTMP_IO_WRITE32(pAdapter, CSR1, 0x0);
1191
1192 RTMP_IO_WRITE32(pAdapter, CSR1, 0x1);
1193 // Remove ASIC from reset state
1194 RTMP_IO_WRITE32(pAdapter, CSR1, 0x0);
1195
1196 // Init send data structures and related parameters
1197 NICInitTransmit(pAdapter);
1198
1199 NICInitializeAdapter(pAdapter);
1200 NICInitAsicFromEEPROM(pAdapter);
1201
1202 // Switch to current channel, since during reset process, the connection should remains on.
1203 AsicSwitchChannel(pAdapter, pAdapter->PortCfg.Channel);
1204 AsicLockChannel(pAdapter, pAdapter->PortCfg.Channel);
1205 }
1206 /*
1207 ========================================================================
1208
1209 Routine Description:
1210 Verify section is valid for Get key parameter.
1211
1212 Arguments:
1213 buffer Pointer to the buffer to start find the key section
1214 ptr pointer to section
1215
1216 Return Value:
1217 TRUE Success
1218 FALSE Fail
1219 ========================================================================
1220 */
1221 INT RTMPIsFindSection(
1222 IN PUCHAR ptr,
1223 IN PUCHAR buffer)
1224 {
1225 if(ptr == buffer)
1226 return TRUE;
1227 else if (ptr > buffer)
1228 {
1229 while (ptr > buffer)
1230 {
1231 ptr--;
1232 if( *ptr == 0x0a)
1233 return TRUE;
1234 else if( (*ptr == ' ') || (*ptr == '\t'))
1235 continue;
1236 else
1237 return FALSE;
1238 }
1239 return TRUE;
1240 }
1241
1242 return FALSE;
1243 }
1244 /*
1245 ========================================================================
1246
1247 Routine Description:
1248 Find key section for Get key parameter.
1249
1250 Arguments:
1251 buffer Pointer to the buffer to start find the key section
1252 section the key of the secion to be find
1253
1254 Return Value:
1255 NULL Fail
1256 Others Success
1257 ========================================================================
1258 */
1259 PUCHAR RTMPFindSection(
1260 IN PCHAR buffer,
1261 IN PCHAR section)
1262 {
1263 CHAR temp_buf[255];
1264 PUCHAR ptr;
1265
1266 strcpy(temp_buf, "["); /* and the opening bracket [ */
1267 strcat(temp_buf, section);
1268 strcat(temp_buf, "]");
1269
1270 if((ptr = rtstrstr(buffer, temp_buf)) != NULL)
1271 {
1272 if(RTMPIsFindSection(ptr, buffer))
1273 return (ptr+strlen("\n"));
1274 else
1275 return NULL;
1276 }
1277 else
1278 return NULL;
1279 }
1280 /**
1281 * strstr - Find the first substring in a %NUL terminated string
1282 * @s1: The string to be searched
1283 * @s2: The string to search for
1284 */
1285 char * rtstrstr(const char * s1,const char * s2)
1286 {
1287 int l1, l2;
1288
1289 l2 = strlen(s2);
1290 if (!l2)
1291 return (char *) s1;
1292 l1 = strlen(s1);
1293 while (l1 >= l2) {
1294 l1--;
1295 if (!memcmp(s1,s2,l2))
1296 return (char *) s1;
1297 s1++;
1298 }
1299 return NULL;
1300 }
1301 /*
1302 ========================================================================
1303
1304 Routine Description:
1305 Get key parameter.
1306
1307 Arguments:
1308 section the key of the secion
1309 key Pointer to key string
1310 dest Pointer to destination
1311 destsize The datasize of the destination
1312 buffer Pointer to the buffer to start find the key
1313
1314 Return Value:
1315 TRUE Success
1316 FALSE Fail
1317
1318 Note:
1319 This routine get the value with the matched key (case case-sensitive)
1320 ========================================================================
1321 */
1322 INT RTMPGetKeyParameter(
1323 IN PUCHAR section,
1324 IN PCHAR key,
1325 OUT PCHAR dest,
1326 IN INT destsize,
1327 IN PCHAR buffer)
1328 {
1329 char temp_buf1[600];
1330 char temp_buf2[600];
1331 char *start_ptr;
1332 char *end_ptr;
1333 char *ptr;
1334 char *too_far_ptr;
1335 char *offset;
1336 int len;
1337
1338 //find section
1339 if((offset = RTMPFindSection(buffer, section)) == NULL)
1340 return (FALSE);
1341
1342 strcpy(temp_buf1, "\n");
1343 strcat(temp_buf1, key);
1344 strcat(temp_buf1, "=");
1345
1346 //search key
1347 if((start_ptr=rtstrstr(offset, temp_buf1))==NULL)
1348 return FALSE;
1349
1350 start_ptr+=strlen("\n");
1351 if((too_far_ptr=rtstrstr(offset+1, "["))==NULL)
1352 too_far_ptr=offset+strlen(offset);
1353
1354 if((end_ptr=rtstrstr(start_ptr, "\n"))==NULL)
1355 end_ptr=start_ptr+strlen(start_ptr);
1356
1357 if (too_far_ptr<start_ptr)
1358 return FALSE;
1359
1360 memcpy(temp_buf2, start_ptr, end_ptr-start_ptr);
1361 temp_buf2[end_ptr-start_ptr]='\0';
1362 len = strlen(temp_buf2);
1363 strcpy(temp_buf1, temp_buf2);
1364 if((start_ptr=rtstrstr(temp_buf1, "=")) == NULL)
1365 return FALSE;
1366
1367 strcpy(temp_buf2, start_ptr+1);
1368 ptr = temp_buf2;
1369 //trim space or tab
1370 while(*ptr != 0x00)
1371 {
1372 if( (*ptr == ' ') || (*ptr == '\t') )
1373 ptr++;
1374 else
1375 break;
1376 }
1377
1378 len = strlen(ptr);
1379 memset(dest, 0x00, destsize);
1380 strncpy(dest, ptr, len >= destsize ? destsize: len);
1381
1382 return TRUE;
1383 }
1384 /*
1385 ========================================================================
1386
1387 Routine Description:
1388 In kernel mode read parameters from file
1389
1390 Arguments:
1391 src the location of the file.
1392 dest put the parameters to the destination.
1393 Length size to read.
1394
1395 Return Value:
1396 None
1397
1398 Note:
1399
1400 ========================================================================
1401 */
1402
1403 VOID RTMPReadParametersFromFile(
1404 IN PRTMP_ADAPTER pAd)
1405 {
1406 PUCHAR src;
1407 struct file *srcf;
1408 INT retval, orgfsuid, orgfsgid;
1409 mm_segment_t orgfs;
1410 CHAR buffer[MAX_INI_BUFFER_SIZE];
1411 CHAR tmpbuf[255];
1412 UCHAR keyMaterial[40];
1413 UCHAR Channel;
1414 ULONG ulInfo;
1415 RT_802_11_PREAMBLE Preamble;
1416 int KeyLen;
1417 int i;
1418 BOOLEAN bIsHex = TRUE;
1419 ULONG rate_mapping[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54}; //according to README
1420
1421 src = PROFILE_PATH;
1422
1423 // Save uid and gid used for filesystem access.
1424 // Set user and group to 0 (root)
1425 orgfsuid = current->fsuid;
1426 orgfsgid = current->fsgid;
1427 current->fsuid=current->fsgid = 0;
1428 orgfs = get_fs();
1429 set_fs(KERNEL_DS);
1430
1431 if (src && *src)
1432 {
1433 srcf = filp_open(src, O_RDONLY, 0);
1434 if (IS_ERR(srcf))
1435 {
1436 DBGPRINT(RT_DEBUG_TRACE, "--> Error %ld opening %s\n", -PTR_ERR(srcf),src);
1437 }
1438 else
1439 {
1440 /* The object must have a read method */
1441 if (srcf->f_op && srcf->f_op->read)
1442 {
1443 memset(buffer, 0x00, MAX_INI_BUFFER_SIZE);
1444 retval=srcf->f_op->read(srcf, buffer, MAX_INI_BUFFER_SIZE, &srcf->f_pos);
1445 if (retval < 0)
1446 {
1447 DBGPRINT(RT_DEBUG_TRACE, "--> Read %s error %d\n", src, -retval);
1448 }
1449 else
1450 {
1451 // set file parameter to portcfg
1452 //CountryRegion
1453 if (RTMPGetKeyParameter("Default", "CountryRegion", tmpbuf, 255, buffer))
1454 {
1455 ulInfo = simple_strtol(tmpbuf, 0, 10);
1456 if ((ulInfo >= REGION_MIN) && (ulInfo <= REGION_MAX) )
1457 {
1458 pAd->PortCfg.CountryRegion = (UCHAR) ulInfo;
1459 DBGPRINT(RT_DEBUG_TRACE, "%s::(CountryRegion=%d)\n", __FUNCTION__, pAd->PortCfg.CountryRegion);
1460 }
1461 }
1462 //SSID
1463 memset(tmpbuf, 0x00, 255);
1464 if (RTMPGetKeyParameter("Default", "SSID", tmpbuf, 32, buffer))
1465 {
1466 pAd->PortCfg.SsidLen = (UCHAR) strlen(tmpbuf);
1467 memcpy(pAd->PortCfg.Ssid, tmpbuf, pAd->PortCfg.SsidLen);
1468
1469 pAd->Mlme.CntlAux.SsidLen = pAd->PortCfg.SsidLen;
1470 memcpy(pAd->Mlme.CntlAux.Ssid, tmpbuf, pAd->Mlme.CntlAux.SsidLen);
1471
1472 DBGPRINT(RT_DEBUG_TRACE, "%s::(SSID=%s Len=%d)\n", __FUNCTION__, tmpbuf, pAd->PortCfg.SsidLen);
1473 }
1474 //NetworkType
1475 if (RTMPGetKeyParameter("Default", "NetworkType", tmpbuf, 255, buffer))
1476 {
1477 pAd->bConfigChanged = TRUE;
1478 if (strcmp(tmpbuf, "Adhoc") == 0)
1479 pAd->PortCfg.BssType = BSS_INDEP;
1480 else //Default Infrastructure mode
1481 pAd->PortCfg.BssType = BSS_INFRA;
1482 // Reset Ralink supplicant to not use, it will be set to start when UI set PMK key
1483 pAd->PortCfg.WpaState = SS_NOTUSE;
1484 DBGPRINT(RT_DEBUG_TRACE, "%s::(NetworkType=%d)\n", __FUNCTION__, pAd->PortCfg.BssType);
1485 }
1486 //WirelessMode
1487 if (RTMPGetKeyParameter("Default", "WirelessMode", tmpbuf, 10, buffer))
1488 {
1489 ulInfo = simple_strtol(tmpbuf, 0, 10);
1490 if ((ulInfo == PHY_11BG_MIXED) || (ulInfo == PHY_11B) ||
1491 (ulInfo == PHY_11A) || (ulInfo == PHY_11ABG_MIXED))
1492 {
1493 RTMPSetPhyMode(pAd, ulInfo);
1494 DBGPRINT(RT_DEBUG_TRACE, "%s::(WirelessMode=%d)\n", __FUNCTION__, ulInfo);
1495 }
1496 }
1497 //TxRate
1498 if (RTMPGetKeyParameter("Default", "TxRate", tmpbuf, 10, buffer))
1499 {
1500 ulInfo = simple_strtol(tmpbuf, 0, 10);
1501 {
1502 if (ulInfo == 0)
1503 RTMPSetDesiredRates(pAd, -1);
1504 else
1505 RTMPSetDesiredRates(pAd, (LONG) (rate_mapping[ulInfo-1] * 1000000));
1506
1507 DBGPRINT(RT_DEBUG_TRACE, "%s::(TxRate=%d)\n", __FUNCTION__, ulInfo);
1508 }
1509 }
1510 //Channel
1511 if (RTMPGetKeyParameter("Default", "Channel", tmpbuf, 10, buffer))
1512 {
1513 Channel = (UCHAR) simple_strtol(tmpbuf, 0, 10);
1514 if (ChannelSanity(pAd, Channel) == TRUE)
1515 {
1516 pAd->PortCfg.Channel = Channel;
1517 // If default profile in Registry is an ADHOC network, driver should use the specified channel
1518 // number when starting IBSS the first time, because RaConfig is passive and will not set this
1519 // via OID_802_11_CONFIGURATION upon driver bootup.
1520 pAd->PortCfg.IbssConfig.Channel = pAd->PortCfg.Channel;
1521 DBGPRINT(RT_DEBUG_TRACE, "%s::(Channel=%d)\n", __FUNCTION__, Channel);
1522 }
1523 }
1524 //BGProtection
1525 if (RTMPGetKeyParameter("Default", "BGProtection", tmpbuf, 10, buffer))
1526 {
1527 switch (simple_strtol(tmpbuf, 0, 10))
1528 {
1529 case 1: //Always On
1530 pAd->PortCfg.UseBGProtection = 1;
1531 break;
1532 case 2: //Always OFF
1533 pAd->PortCfg.UseBGProtection = 2;
1534 break;
1535 case 0: //AUTO
1536 default:
1537 pAd->PortCfg.UseBGProtection = 0;
1538 break;
1539 }
1540 DBGPRINT(RT_DEBUG_TRACE, "%s::(BGProtection=%d)\n", __FUNCTION__, pAd->PortCfg.UseBGProtection);
1541 }
1542 //StaWithEtherBridge
1543 if (RTMPGetKeyParameter("Default", "StaWithEtherBridge", tmpbuf, 10, buffer))
1544 {
1545 switch (simple_strtol(tmpbuf, 0, 10))
1546 {
1547 case 0: //Off
1548 pAd->PortCfg.StaWithEtherBridge.Enable = FALSE;
1549 break;
1550 case 1: //On
1551 pAd->PortCfg.StaWithEtherBridge.Enable = TRUE;
1552 break;
1553 default:
1554 pAd->PortCfg.StaWithEtherBridge.Enable = FALSE;
1555 break;
1556 }
1557 DBGPRINT(RT_DEBUG_TRACE, "%s::(StaWithEtherBridge=%d)\n", __FUNCTION__, pAd->PortCfg.StaWithEtherBridge.Enable);
1558 }
1559 //TxPreamble
1560 if (RTMPGetKeyParameter("Default", "TxPreamble", tmpbuf, 10, buffer))
1561 {
1562 Preamble = simple_strtol(tmpbuf, 0, 10);
1563 switch (Preamble)
1564 {
1565 case Rt802_11PreambleShort:
1566 pAd->PortCfg.WindowsTxPreamble = Preamble;
1567 MlmeSetTxPreamble(pAd, Rt802_11PreambleShort);
1568 break;
1569 case Rt802_11PreambleLong:
1570 case Rt802_11PreambleAuto:
1571 default:
1572 // if user wants AUTO, initialize to LONG here, then change according to AP's
1573 // capability upon association.
1574 pAd->PortCfg.WindowsTxPreamble = Preamble;
1575 MlmeSetTxPreamble(pAd, Rt802_11PreambleLong);
1576 }
1577 DBGPRINT(RT_DEBUG_TRACE, "%s::(TxPreamble=%d)\n", __FUNCTION__, Preamble);
1578 }
1579 //RTSThreshold
1580 if (RTMPGetKeyParameter("Default", "RTSThreshold", tmpbuf, 10, buffer))
1581 {
1582 ulInfo = simple_strtol(tmpbuf, 0, 10);
1583
1584 if((ulInfo > 0) && (ulInfo <= MAX_RTS_THRESHOLD))
1585 pAd->PortCfg.RtsThreshold = (USHORT)ulInfo;
1586 else
1587 pAd->PortCfg.RtsThreshold = MAX_RTS_THRESHOLD;
1588
1589 DBGPRINT(RT_DEBUG_TRACE, "%s::(RTSThreshold=%d)\n", __FUNCTION__, pAd->PortCfg.RtsThreshold);
1590 }
1591 //FragThreshold
1592 if (RTMPGetKeyParameter("Default", "FragThreshold", tmpbuf, 10, buffer))
1593 {
1594 ulInfo = simple_strtol(tmpbuf, 0, 10);
1595
1596 if ( (ulInfo >= MIN_FRAG_THRESHOLD) && (ulInfo <= MAX_FRAG_THRESHOLD))
1597 pAd->PortCfg.FragmentThreshold = (USHORT)ulInfo;
1598 else
1599 pAd->PortCfg.FragmentThreshold = MAX_FRAG_THRESHOLD;
1600
1601 if (pAd->PortCfg.FragmentThreshold == MAX_FRAG_THRESHOLD)
1602 pAd->PortCfg.bFragmentZeroDisable = TRUE;
1603 else
1604 pAd->PortCfg.bFragmentZeroDisable = FALSE;
1605
1606 DBGPRINT(RT_DEBUG_TRACE, "%s::(FragThreshold=%d)\n", __FUNCTION__, ulInfo);
1607 }
1608 //AdhocOfdm
1609 if (RTMPGetKeyParameter("Default", "AdhocOfdm", tmpbuf, 10, buffer))
1610 {
1611 ulInfo = simple_strtol(tmpbuf, 0, 10);
1612
1613 if (ulInfo == 1)
1614 pAd->PortCfg.AdhocMode = 1;
1615 else
1616 pAd->PortCfg.AdhocMode = 0;
1617
1618 DBGPRINT(RT_DEBUG_TRACE, "%s::(AdhocOfdm=%d)\n", __FUNCTION__, pAd->PortCfg.AdhocMode);
1619 }
1620 //TxBurst
1621 if (RTMPGetKeyParameter("Default", "TxBurst", tmpbuf, 10, buffer))
1622 {
1623 ulInfo = simple_strtol(tmpbuf, 0, 10);
1624
1625 if (ulInfo == 1)
1626 pAd->PortCfg.EnableTxBurst = TRUE;
1627 else
1628 pAd->PortCfg.EnableTxBurst = FALSE;
1629
1630 DBGPRINT(RT_DEBUG_TRACE, "%s::(TxBurst=%d)\n", __FUNCTION__, pAd->PortCfg.EnableTxBurst);
1631 }
1632 //TurboRate
1633 if (RTMPGetKeyParameter("Default", "TurboRate", tmpbuf, 10, buffer))
1634 {
1635 ulInfo = simple_strtol(tmpbuf, 0, 10);
1636
1637 if (ulInfo == 1)
1638 pAd->PortCfg.EnableTurboRate = TRUE;
1639 else
1640 pAd->PortCfg.EnableTurboRate = FALSE;
1641
1642 DBGPRINT(RT_DEBUG_TRACE, "%s::(TurboRate=%d)\n", __FUNCTION__, pAd->PortCfg.EnableTurboRate);
1643 }
1644 //ShortSlot
1645 if (RTMPGetKeyParameter("Default", "ShortSlot", tmpbuf, 10, buffer))
1646 {
1647 ulInfo = simple_strtol(tmpbuf, 0, 10);
1648
1649 if (ulInfo == 1)
1650 pAd->PortCfg.UseShortSlotTime = TRUE;
1651 else
1652 pAd->PortCfg.UseShortSlotTime = FALSE;
1653
1654 DBGPRINT(RT_DEBUG_TRACE, "%s::(ShortSlot=%d)\n", __FUNCTION__, pAd->PortCfg.UseShortSlotTime);
1655 }
1656 //POWER_MODE
1657 if (RTMPGetKeyParameter("Default", "PSMode", tmpbuf, 10, buffer))
1658 {
1659 if (pAd->PortCfg.BssType == BSS_INFRA)
1660 {
1661 if ((strcmp(tmpbuf, "MAX_PSP") == 0) || (strcmp(tmpbuf, "max_psp") == 0))
1662 {
1663 // do NOT turn on PSM bit here, wait until MlmeCheckForPsmChange()
1664 // to exclude certain situations.
1665 // MlmeSetPsmBit(pAdapter, PWR_SAVE);
1666 if (pAd->PortCfg.WindowsACCAMEnable == FALSE)
1667 pAd->PortCfg.WindowsPowerMode = Ndis802_11PowerModeMAX_PSP;
1668 pAd->PortCfg.WindowsBatteryPowerMode = Ndis802_11PowerModeMAX_PSP;
1669 pAd->PortCfg.RecvDtim = TRUE; // FALSE;
1670 pAd->PortCfg.DefaultListenCount = 5;
1671 }
1672 else if ((strcmp(tmpbuf, "Fast_PSP") == 0) || (strcmp(tmpbuf, "fast_psp") == 0)
1673 || (strcmp(tmpbuf, "FAST_PSP") == 0))
1674 {
1675 // do NOT turn on PSM bit here, wait until MlmeCheckForPsmChange()
1676 // to exclude certain situations.
1677 // MlmeSetPsmBit(pAdapter, PWR_SAVE);
1678 pAd->PortCfg.RecvDtim = TRUE;
1679 if (pAd->PortCfg.WindowsACCAMEnable == FALSE)
1680 pAd->PortCfg.WindowsPowerMode = Ndis802_11PowerModeFast_PSP;
1681 pAd->PortCfg.WindowsBatteryPowerMode = Ndis802_11PowerModeFast_PSP;
1682 pAd->PortCfg.DefaultListenCount = 3;
1683 }
1684 else
1685 { //Default Ndis802_11PowerModeCAM
1686 // clear PSM bit immediately
1687 MlmeSetPsmBit(pAd, PWR_ACTIVE);
1688 pAd->PortCfg.RecvDtim = TRUE;
1689 if (pAd->PortCfg.WindowsACCAMEnable == FALSE)
1690 pAd->PortCfg.WindowsPowerMode = Ndis802_11PowerModeCAM;
1691 pAd->PortCfg.WindowsBatteryPowerMode = Ndis802_11PowerModeCAM;
1692 }
1693 DBGPRINT(RT_DEBUG_TRACE, "%s::(PSMode=%d)\n", __FUNCTION__, pAd->PortCfg.WindowsPowerMode);
1694 }
1695 }
1696 //AuthMode
1697 if (RTMPGetKeyParameter("Default", "AuthMode", tmpbuf, 10, buffer))
1698 {
1699 if ((strcmp(tmpbuf, "SHARED") == 0) || (strcmp(tmpbuf, "shared") == 0))
1700 pAd->PortCfg.AuthMode = Ndis802_11AuthModeShared;
1701 else if ((strcmp(tmpbuf, "WPAPSK") == 0) || (strcmp(tmpbuf, "wpapsk") == 0))
1702 pAd->PortCfg.AuthMode = Ndis802_11AuthModeWPAPSK;
1703 else if ((strcmp(tmpbuf, "AUTO") == 0) || (strcmp(tmpbuf, "auto") == 0))
1704 pAd->PortCfg.AuthMode = Ndis802_11AuthModeAutoSwitch;
1705 else if ((strcmp(tmpbuf, "WPANONE") == 0) || (strcmp(tmpbuf, "wpanone") == 0))
1706 pAd->PortCfg.AuthMode = Ndis802_11AuthModeWPANone;
1707 else
1708 pAd->PortCfg.AuthMode = Ndis802_11AuthModeOpen;
1709
1710 pAd->PortCfg.PortSecured = WPA_802_1X_PORT_NOT_SECURED;
1711 DBGPRINT(RT_DEBUG_TRACE, "%s::(AuthMode=%d)\n", __FUNCTION__, pAd->PortCfg.AuthMode);
1712 }
1713 //EncrypType
1714 if (RTMPGetKeyParameter("Default", "EncrypType", tmpbuf, 10, buffer))
1715 {
1716 if ((strcmp(tmpbuf, "WEP") == 0) || (strcmp(tmpbuf, "wep") == 0))
1717 pAd->PortCfg.WepStatus = Ndis802_11WEPEnabled;
1718 else if ((strcmp(tmpbuf, "TKIP") == 0) || (strcmp(tmpbuf, "tkip") == 0))
1719 pAd->PortCfg.WepStatus = Ndis802_11Encryption2Enabled;
1720 else if ((strcmp(tmpbuf, "AES") == 0) || (strcmp(tmpbuf, "aes") == 0))
1721 pAd->PortCfg.WepStatus = Ndis802_11Encryption3Enabled;
1722 else
1723 pAd->PortCfg.WepStatus = Ndis802_11WEPDisabled;
1724
1725 DBGPRINT(RT_DEBUG_TRACE, "%s::(EncrypType=%d)\n", __FUNCTION__, pAd->PortCfg.WepStatus);
1726 }
1727 //WPAPSK_KEY
1728 if (RTMPGetKeyParameter("Default", "WPAPSK", tmpbuf, 255, buffer))
1729 {
1730 if ((strlen(tmpbuf) >= 8) && (strlen(tmpbuf) < 64))
1731 {
1732 PasswordHash((char *)tmpbuf, pAd->PortCfg.Ssid, pAd->PortCfg.SsidLen, keyMaterial);
1733 NdisMoveMemory(pAd->PortCfg.PskKey.Key, keyMaterial, 32);
1734 // Use RaConfig as PSK agent.
1735 // Start STA supplicant state machine
1736 pAd->PortCfg.WpaState = SS_START;
1737 #if 0
1738 DBGPRINT(RT_DEBUG_TRACE, "%s WPAPSK Key => \n", __FUNCTION__);
1739 for (i = 0; i < 32; i++)
1740 {
1741 DBGPRINT(RT_DEBUG_TRACE, "%02x:", pAd->PortCfg.PskKey.Key[i]);
1742 if (i%16 == 15)
1743 DBGPRINT(RT_DEBUG_TRACE, "\n");
1744 }
1745 DBGPRINT(RT_DEBUG_TRACE, "\n");
1746 #endif
1747 }
1748 else if (strlen(tmpbuf) == 64)
1749 {
1750 AtoH(tmpbuf, pAd->PortCfg.PskKey.Key, 32);
1751 pAd->PortCfg.WpaState = SS_START;
1752 }
1753 }
1754 //DefaultKeyID
1755 if (RTMPGetKeyParameter("Default", "DefaultKeyID", tmpbuf, 10, buffer))
1756 {
1757 ulInfo = simple_strtol(tmpbuf, 0, 10);
1758 if((ulInfo >= 1 ) && (ulInfo <= 4))
1759 pAd->PortCfg.DefaultKeyId = (UCHAR) (ulInfo - 1 );
1760 else
1761 pAd->PortCfg.DefaultKeyId = 0;
1762
1763 DBGPRINT(RT_DEBUG_TRACE, "%s::(DefaultKeyID=%d)\n", __FUNCTION__, pAd->PortCfg.DefaultKeyId);
1764 }
1765 //Key1Str
1766 if (RTMPGetKeyParameter("Default", "Key1Str", tmpbuf, 26, buffer))
1767 {
1768 KeyLen = strlen(tmpbuf);
1769 switch (KeyLen)
1770 {
1771 case 0:
1772 pAd->PortCfg.SharedKey[0].KeyLen = 0;
1773 break;
1774 case 5: //wep 40 Ascii type
1775 pAd->PortCfg.SharedKey[0].KeyLen = KeyLen;
1776 memcpy(pAd->PortCfg.SharedKey[0].Key, tmpbuf, KeyLen);
1777 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key1=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Ascii");
1778 case 10: //wep 40 Hex type
1779 for(i=0; i < KeyLen; i++)
1780 {
1781 if( !isxdigit(*(tmpbuf+i)) )
1782 {
1783 bIsHex = FALSE;
1784 break;
1785 }
1786 }
1787
1788 if (bIsHex)
1789 {
1790 pAd->PortCfg.SharedKey[0].KeyLen = KeyLen / 2 ;
1791 AtoH(tmpbuf, pAd->PortCfg.SharedKey[0].Key, KeyLen / 2);
1792 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key1=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Hex");
1793 }
1794 break;
1795 case 13: //wep 104 Ascii type
1796 pAd->PortCfg.SharedKey[0].KeyLen = KeyLen;
1797 memcpy(pAd->PortCfg.SharedKey[0].Key, tmpbuf, KeyLen);
1798 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key1=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Ascii");
1799 break;
1800 case 26: //wep 104 Hex type
1801 for(i=0; i < KeyLen; i++)
1802 {
1803 if( !isxdigit(*(tmpbuf+i)) )
1804 {
1805 bIsHex = FALSE;
1806 break;
1807 }
1808 }
1809
1810 if (bIsHex)
1811 {
1812 pAd->PortCfg.SharedKey[0].KeyLen = KeyLen / 2 ;
1813 AtoH(tmpbuf, pAd->PortCfg.SharedKey[0].Key, KeyLen / 2);
1814 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key1=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Hex");
1815 }
1816 break;
1817 default:
1818 pAd->PortCfg.SharedKey[0].KeyLen = 0;
1819 DBGPRINT(RT_DEBUG_TRACE, "%s::Invalid Key (=%s)\n", __FUNCTION__, tmpbuf);
1820 }
1821 }
1822 //Key2Str
1823 if (RTMPGetKeyParameter("Default", "Key2Str", tmpbuf, 26, buffer))
1824 {
1825 KeyLen = strlen(tmpbuf);
1826 switch (KeyLen)
1827 {
1828 case 0:
1829 pAd->PortCfg.SharedKey[1].KeyLen = 0;
1830 break;
1831 case 5: //wep 40 Ascii type
1832 pAd->PortCfg.SharedKey[1].KeyLen = KeyLen;
1833 memcpy(pAd->PortCfg.SharedKey[1].Key, tmpbuf, KeyLen);
1834 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key2=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Ascii");
1835 case 10: //wep 40 Hex type
1836 for(i=0; i < KeyLen; i++)
1837 {
1838 if( !isxdigit(*(tmpbuf+i)) )
1839 {
1840 bIsHex = FALSE;
1841 break;
1842 }
1843 }
1844
1845 if (bIsHex)
1846 {
1847 pAd->PortCfg.SharedKey[1].KeyLen = KeyLen / 2 ;
1848 AtoH(tmpbuf, pAd->PortCfg.SharedKey[1].Key, KeyLen / 2);
1849 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key2=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Hex");
1850 }
1851 break;
1852 case 13: //wep 104 Ascii type
1853 pAd->PortCfg.SharedKey[1].KeyLen = KeyLen;
1854 memcpy(pAd->PortCfg.SharedKey[1].Key, tmpbuf, KeyLen);
1855 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key2=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Ascii");
1856 break;
1857 case 26: //wep 104 Hex type
1858 for(i=0; i < KeyLen; i++)
1859 {
1860 if( !isxdigit(*(tmpbuf+i)) )
1861 {
1862 bIsHex = FALSE;
1863 break;
1864 }
1865 }
1866
1867 if (bIsHex)
1868 {
1869 pAd->PortCfg.SharedKey[1].KeyLen = KeyLen / 2 ;
1870 AtoH(tmpbuf, pAd->PortCfg.SharedKey[1].Key, KeyLen / 2);
1871 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key2=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Hex");
1872 }
1873 break;
1874 default:
1875 pAd->PortCfg.SharedKey[1].KeyLen = 0;
1876 DBGPRINT(RT_DEBUG_TRACE, "%s::Invalid argument (=%s)\n", __FUNCTION__, tmpbuf);
1877 }
1878 }
1879 //Key3Str
1880 if (RTMPGetKeyParameter("Default", "Key3Str", tmpbuf, 26, buffer))
1881 {
1882 KeyLen = strlen(tmpbuf);
1883 switch (KeyLen)
1884 {
1885 case 0:
1886 pAd->PortCfg.SharedKey[2].KeyLen = 0;
1887 break;
1888 case 5: //wep 40 Ascii type
1889 pAd->PortCfg.SharedKey[2].KeyLen = KeyLen;
1890 memcpy(pAd->PortCfg.SharedKey[2].Key, tmpbuf, KeyLen);
1891 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key3=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Ascii");
1892 case 10: //wep 40 Hex type
1893 for(i=0; i < KeyLen; i++)
1894 {
1895 if( !isxdigit(*(tmpbuf+i)) )
1896 {
1897 bIsHex = FALSE;
1898 break;
1899 }
1900 }
1901
1902 if (bIsHex)
1903 {
1904 pAd->PortCfg.SharedKey[2].KeyLen = KeyLen / 2 ;
1905 AtoH(tmpbuf, pAd->PortCfg.SharedKey[2].Key, KeyLen / 2);
1906 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key3=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Hex");
1907 }
1908 break;
1909 case 13: //wep 104 Ascii type
1910 pAd->PortCfg.SharedKey[2].KeyLen = KeyLen;
1911 memcpy(pAd->PortCfg.SharedKey[2].Key, tmpbuf, KeyLen);
1912 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key3=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Ascii");
1913 break;
1914 case 26: //wep 104 Hex type
1915 for(i=0; i < KeyLen; i++)
1916 {
1917 if( !isxdigit(*(tmpbuf+i)) )
1918 {
1919 bIsHex = FALSE;
1920 break;
1921 }
1922 }
1923
1924 if (bIsHex)
1925 {
1926 pAd->PortCfg.SharedKey[2].KeyLen = KeyLen / 2 ;
1927 AtoH(tmpbuf, pAd->PortCfg.SharedKey[2].Key, KeyLen / 2);
1928 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key3=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Hex");
1929 }
1930 break;
1931 default:
1932 pAd->PortCfg.SharedKey[2].KeyLen = 0;
1933 DBGPRINT(RT_DEBUG_TRACE, "%s::Invalid argument (=%s)\n", __FUNCTION__, tmpbuf);
1934 }
1935 }
1936 //Key4Str
1937 if (RTMPGetKeyParameter("Default", "Key4Str", tmpbuf, 26, buffer))
1938 {
1939 KeyLen = strlen(tmpbuf);
1940 switch (KeyLen)
1941 {
1942 case 0:
1943 pAd->PortCfg.SharedKey[3].KeyLen = 0;
1944 break;
1945 case 5: //wep 40 Ascii type
1946 pAd->PortCfg.SharedKey[3].KeyLen = KeyLen;
1947 memcpy(pAd->PortCfg.SharedKey[3].Key, tmpbuf, KeyLen);
1948 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key4=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Ascii");
1949 case 10: //wep 40 Hex type
1950 for(i=0; i < KeyLen; i++)
1951 {
1952 if( !isxdigit(*(tmpbuf+i)) )
1953 {
1954 bIsHex = FALSE;
1955 break;
1956 }
1957 }
1958
1959 if (bIsHex)
1960 {
1961 pAd->PortCfg.SharedKey[3].KeyLen = KeyLen / 2 ;
1962 AtoH(tmpbuf, pAd->PortCfg.SharedKey[3].Key, KeyLen / 2);
1963 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key4=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Hex");
1964 }
1965 break;
1966 case 13: //wep 104 Ascii type
1967 pAd->PortCfg.SharedKey[3].KeyLen = KeyLen;
1968 memcpy(pAd->PortCfg.SharedKey[3].Key, tmpbuf, KeyLen);
1969 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key4=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Ascii");
1970 break;
1971 case 26: //wep 104 Hex type
1972 for(i=0; i < KeyLen; i++)
1973 {
1974 if( !isxdigit(*(tmpbuf+i)) )
1975 {
1976 bIsHex = FALSE;
1977 break;
1978 }
1979 }
1980
1981 if (bIsHex)
1982 {
1983 pAd->PortCfg.SharedKey[3].KeyLen = KeyLen / 2 ;
1984 AtoH(tmpbuf, pAd->PortCfg.SharedKey[3].Key, KeyLen / 2);
1985 DBGPRINT(RT_DEBUG_TRACE, "%s::(Key4=%s and type=%s)\n", __FUNCTION__, tmpbuf, "Hex");
1986 }
1987 break;
1988 default:
1989 pAd->PortCfg.SharedKey[3].KeyLen = 0;
1990 DBGPRINT(RT_DEBUG_TRACE, "%s::Invalid argument (=%s)\n", __FUNCTION__, tmpbuf);
1991 }
1992 }
1993 }
1994 }
1995 else
1996 {
1997 DBGPRINT(RT_DEBUG_TRACE, "--> %s does not have a write method\n", src);
1998 }
1999
2000 retval=filp_close(srcf,NULL);
2001 if (retval)
2002 {
2003 DBGPRINT(RT_DEBUG_TRACE, "--> Error %d closing %s\n", -retval, src);
2004 }
2005 }
2006 } //if (src && *src)
2007
2008 set_fs(orgfs);
2009 current->fsuid = orgfsuid;
2010 current->fsgid = orgfsgid;
2011 }
2012 /*
2013 ========================================================================
2014
2015 Routine Description:
2016 Reset NIC Asics
2017
2018 Arguments:
2019 Adapter Pointer to our adapter
2020
2021 Return Value:
2022 None
2023
2024 Note:
2025 Reset NIC to initial state AS IS system boot up time.
2026
2027 ========================================================================
2028 */
2029 VOID RTMPRingCleanUp(
2030 IN PRTMP_ADAPTER pAdapter,
2031 IN UCHAR RingType)
2032 {
2033 ULONG Count;
2034 PTXD_STRUC pTxD;
2035 PRXD_STRUC pRxD;
2036 PMGMT_STRUC pMgmt;
2037 struct sk_buff *skb;
2038
2039 Count = 0;
2040 switch (RingType)
2041 {
2042 case TX_RING:
2043 // We have to clean all descriptos in case some error happened with reset
2044 do
2045 {
2046 pTxD = (PTXD_STRUC) pAdapter->TxRing[pAdapter->NextTxDoneIndex].va_addr;
2047
2048 pTxD->Owner = DESC_OWN_HOST;
2049 pTxD->Valid = FALSE;
2050
2051 pAdapter->NextTxDoneIndex++;
2052 Count++;
2053 if (pAdapter->NextTxDoneIndex >= TX_RING_SIZE)
2054 {
2055 pAdapter->NextTxDoneIndex = 0;
2056 }
2057
2058 } while (Count < TX_RING_SIZE); // We have to scan all TX ring
2059
2060 // Check for packet in send tx wait waiting queue
2061 while (pAdapter->TxSwQueue0.Head != NULL)
2062 {
2063 // Packets queued, Remove all and return to upper layer
2064 skb = (struct sk_buff *)RemoveHeadQueue(&pAdapter->TxSwQueue0);
2065 // Release packet by calling send failure
2066 RTMPFreeSkbBuffer(skb);
2067 }
2068 while (pAdapter->TxSwQueue1.Head != NULL)
2069 {
2070 // Packets queued, Remove all and return to upper layer
2071 skb = (struct sk_buff *)RemoveHeadQueue(&pAdapter->TxSwQueue1);
2072 // Release packet by calling send failure
2073 RTMPFreeSkbBuffer(skb);
2074 }
2075 while (pAdapter->TxSwQueue2.Head != NULL)
2076 {
2077 // Packets queued, Remove all and return to upper layer
2078 skb = (struct sk_buff *)RemoveHeadQueue(&pAdapter->TxSwQueue2);
2079 // Release packet by calling send failure
2080 RTMPFreeSkbBuffer(skb);
2081 }
2082 while (pAdapter->TxSwQueue3.Head != NULL)
2083 {
2084 // Packets queued, Remove all and return to upper layer
2085 skb = (struct sk_buff *)RemoveHeadQueue(&pAdapter->TxSwQueue3);
2086 // Release packet by calling send failure
2087 RTMPFreeSkbBuffer(skb);
2088 }
2089 break;
2090
2091 case PRIO_RING:
2092 // We have to clean all descriptos in case some error happened with reset
2093 do
2094 {
2095 pTxD = (PTXD_STRUC) pAdapter->PrioRing[pAdapter->NextPrioDoneIndex].va_addr;
2096
2097 // We just re-claim these ring spaces.
2098 pTxD->Owner = DESC_OWN_HOST;
2099 pTxD->Valid = FALSE;
2100
2101 pAdapter->NextPrioDoneIndex++;
2102 Count++;
2103 if (pAdapter->NextPrioDoneIndex >= PRIO_RING_SIZE)
2104 {
2105 pAdapter->NextPrioDoneIndex = 0;
2106 }
2107
2108 } while (Count < PRIO_RING_SIZE); // We have to scan all Priority Ring
2109
2110 // Clear managemt buffer ring
2111 while ((pAdapter->PushMgmtIndex != pAdapter->PopMgmtIndex) || (pAdapter->MgmtQueueSize != 0))
2112 {
2113 pMgmt = (PMGMT_STRUC) &pAdapter->MgmtRing[pAdapter->PopMgmtIndex];
2114 if (pMgmt->Valid == TRUE)
2115 {
2116 MlmeFreeMemory(pAdapter, pMgmt->pBuffer);
2117 pMgmt->Valid = FALSE;
2118 pAdapter->PopMgmtIndex++;
2119 pAdapter->MgmtQueueSize--;
2120 if (pAdapter->PopMgmtIndex >= MGMT_RING_SIZE)
2121 {
2122 pAdapter->PopMgmtIndex = 0;
2123 }
2124 }
2125 }
2126 pAdapter->RalinkCounters.MgmtRingFullCount = 0;
2127 break;
2128
2129 case RX_RING:
2130 // We have to clean all descriptos in case some error happened with reset
2131 do
2132 {
2133 pRxD = (PRXD_STRUC) pAdapter->RxRing[pAdapter->CurRxIndex].va_addr;
2134
2135 // Re-initial Rx ring cell to owned by NIC.
2136 pRxD->Owner = DESC_OWN_NIC;
2137
2138 pAdapter->CurRxIndex++;
2139 Count++;
2140 if (pAdapter->CurRxIndex >= RX_RING_SIZE)
2141 {
2142 pAdapter->CurRxIndex = 0;
2143 }
2144
2145 } while (Count < RX_RING_SIZE); // We have to scan all Rx Ring
2146 break;
2147
2148 default:
2149 break;
2150
2151 }
2152 }
2153
2154 /*
2155 ========================================================================
2156
2157 Routine Description:
2158 Compare two memory block
2159
2160 Arguments:
2161 Adapter Pointer to our adapter
2162
2163 Return Value:
2164 1: memory are equal
2165 0: memory are not equal
2166
2167 Note:
2168
2169 ========================================================================
2170 */
2171 ULONG RTMPEqualMemory(
2172 IN PVOID pSrc1,
2173 IN PVOID pSrc2,
2174 IN ULONG Length)
2175 {
2176 PUCHAR pMem1;
2177 PUCHAR pMem2;
2178 ULONG Index = 0;
2179
2180 pMem1 = (PUCHAR) pSrc1;
2181 pMem2 = (PUCHAR) pSrc2;
2182
2183 for (Index = 0; Index < Length; Index++)
2184 {
2185 if (pMem1[Index] != pMem2[Index])
2186 {
2187 break;
2188 }
2189 }
2190
2191 if (Index == Length)
2192 {
2193 return (1);
2194 }
2195 else
2196 {
2197 return (0);
2198 }
2199 }
2200
2201 /*
2202 ========================================================================
2203
2204 Routine Description:
2205 Compare two memory block
2206
2207 Arguments:
2208 pSrc1 Pointer to first memory address
2209 pSrc2 Pointer to second memory addres
2210
2211 Return Value:
2212 0: memory is equal
2213 1: pSrc1 memory is larger
2214 2: pSrc2 memory is larger
2215
2216 Note:
2217
2218 ========================================================================
2219 */
2220 ULONG RTMPCompareMemory(
2221 IN PVOID pSrc1,
2222 IN PVOID pSrc2,
2223 IN ULONG Length)
2224 {
2225 PUCHAR pMem1;
2226 PUCHAR pMem2;
2227 ULONG Index = 0;
2228
2229 pMem1 = (PUCHAR) pSrc1;
2230 pMem2 = (PUCHAR) pSrc2;
2231
2232 for (Index = 0; Index < Length; Index++)
2233 {
2234 if (pMem1[Index] > pMem2[Index])
2235 return (1);
2236 else if (pMem1[Index] < pMem2[Index])
2237 return (2);
2238 }
2239
2240 // Equal
2241 return (0);
2242 }
2243
2244 /*
2245 ========================================================================
2246
2247 Routine Description:
2248 Zero out memory block
2249
2250 Arguments:
2251 pSrc1 Pointer to memory address
2252 Length Size
2253
2254 Return Value:
2255 None
2256
2257 Note:
2258
2259 ========================================================================
2260 */
2261 VOID NdisZeroMemory(
2262 IN PVOID pSrc,
2263 IN ULONG Length)
2264 {
2265 #if 0
2266 PUCHAR pMem;
2267 ULONG Index = 0;
2268
2269 pMem = (PUCHAR) pSrc;
2270
2271 for (Index = 0; Index < Length; Index++)
2272 {
2273 pMem[Index] = 0x00;
2274 }
2275 #else
2276 memset(pSrc, 0, Length);
2277 #endif
2278 }
2279
2280 VOID NdisFillMemory(
2281 IN PVOID pSrc,
2282 IN ULONG Length,
2283 IN UCHAR Fill)
2284 {
2285 #if 0
2286 PUCHAR pMem;
2287 ULONG Index = 0;
2288
2289 pMem = (PUCHAR) pSrc;
2290
2291 for (Index = 0; Index < Length; Index++)
2292 {
2293 pMem[Index] = Fill;
2294 }
2295 #else
2296 memset(pSrc, Fill, Length);
2297 #endif
2298 }
2299
2300 /*
2301 ========================================================================
2302
2303 Routine Description:
2304 Copy data from memory block 1 to memory block 2
2305
2306 Arguments:
2307 pDest Pointer to destination memory address
2308 pSrc Pointer to source memory address
2309 Length Copy size
2310
2311 Return Value:
2312 None
2313
2314 Note:
2315
2316 ========================================================================
2317 */
2318 VOID NdisMoveMemory(
2319 OUT PVOID pDest,
2320 IN PVOID pSrc,
2321 IN ULONG Length)
2322 {
2323 memcpy(pDest, pSrc, Length);
2324 }
2325
2326 /*
2327 ========================================================================
2328
2329 Routine Description:
2330 Initialize port configuration structure
2331
2332 Arguments:
2333 Adapter Pointer to our adapter
2334
2335 Return Value:
2336 None
2337
2338 Note:
2339
2340 ========================================================================
2341 */
2342 VOID PortCfgInit(
2343 IN PRTMP_ADAPTER pAdapter)
2344 {
2345 UINT i;
2346
2347 DBGPRINT(RT_DEBUG_TRACE, "--> PortCfgInit\n");
2348
2349 pAdapter->PortCfg.UseBGProtection = 0; // 0: AUTO
2350
2351 pAdapter->PortCfg.CapabilityInfo = 0x0000;
2352 pAdapter->PortCfg.Psm = PWR_ACTIVE;
2353 pAdapter->PortCfg.BeaconPeriod = 100; // in mSec
2354
2355 pAdapter->PortCfg.CfpMaxDuration = 0; // never mind, decided by AP later
2356 pAdapter->PortCfg.CfpDurRemain = 0; // never mind, decided by AP later
2357 pAdapter->PortCfg.CfpCount = 0; // never mind, decided by AP later
2358 pAdapter->PortCfg.CfpPeriod = 0; // never mind, decided by AP later
2359 pAdapter->PortCfg.AuthMode = Ndis802_11AuthModeOpen;
2360
2361 for(i = 0; i < SHARE_KEY_NO; i++) {
2362 pAdapter->PortCfg.SharedKey[i].KeyLen = 0;
2363 }
2364
2365 for(i = 0; i < PAIRWISE_KEY_NO; i++) {
2366 pAdapter->PortCfg.PairwiseKey[i].KeyLen = 0;
2367 }
2368
2369 for(i = 0; i < GROUP_KEY_NO; i++) {
2370 pAdapter->PortCfg.GroupKey[i].KeyLen = 0;
2371 }
2372
2373 pAdapter->PortCfg.WepStatus = Ndis802_11EncryptionDisabled;
2374 pAdapter->PortCfg.DefaultKeyId = 0;
2375 pAdapter->PortCfg.PrivacyFilter = Ndis802_11PrivFilterAcceptAll;
2376
2377 // 802.1x port control
2378 pAdapter->PortCfg.PortSecured = WPA_802_1X_PORT_NOT_SECURED;
2379 pAdapter->PortCfg.LastMicErrorTime = 0;
2380 pAdapter->PortCfg.MicErrCnt = 0;
2381 pAdapter->PortCfg.bBlockAssoc = FALSE;
2382 pAdapter->PortCfg.WpaState = SS_NOTUSE;
2383
2384 pAdapter->PortCfg.RtsThreshold = 2347;
2385 pAdapter->PortCfg.FragmentThreshold = 2346;
2386 pAdapter->PortCfg.bFragmentZeroDisable = FALSE;
2387
2388 pAdapter->PortCfg.CurrentTxAntenna = 0xff; // diversity
2389 pAdapter->PortCfg.CurrentRxAntenna = 0xff; // diversity
2390 pAdapter->PortCfg.NumberOfAntenna = 2;
2391
2392 // pAdapter->PortCfg.TxPowerLevel[0] = 100;
2393 // pAdapter->PortCfg.NumOfTxPowerLevel = 1;
2394 pAdapter->PortCfg.TxPower = 100; //mW
2395 pAdapter->PortCfg.TxPowerPercentage = 0xffffffff; // AUTO
2396
2397 pAdapter->PortCfg.AntennaSupportTx = TRUE;
2398 pAdapter->PortCfg.AntennaSupportRx = TRUE;
2399 pAdapter->PortCfg.AntennaSupportDiversityRx = TRUE;
2400
2401 pAdapter->PortCfg.RecvDtim = TRUE;
2402 NdisZeroMemory(&pAdapter->PortCfg.Bssid, MAC_ADDR_LEN);
2403 NdisFillMemory(&pAdapter->PortCfg.Broadcast, MAC_ADDR_LEN, 0xff);
2404 pAdapter->PortCfg.Pss = PWR_ACTIVE;
2405 pAdapter->PortCfg.RssiTrigger = 0;
2406 pAdapter->PortCfg.LastRssi = 0;
2407 pAdapter->PortCfg.LastAvgRssi = -95 + RSSI_TO_DBM_OFFSET;// default -95dm
2408 pAdapter->PortCfg.AvgRssi = 0;
2409 pAdapter->PortCfg.RssiTriggerMode = RSSI_TRIGGERED_UPON_BELOW_THRESHOLD;
2410 pAdapter->PortCfg.AtimWin = 0;
2411 pAdapter->PortCfg.Channel = 1;
2412
2413 pAdapter->PortCfg.Aid = 1;
2414
2415 pAdapter->PortCfg.DefaultListenCount = 3;//default listen count;
2416 pAdapter->PortCfg.BssType = BSS_INFRA; // BSS_INFRA or BSS_INDEP
2417
2418 pAdapter->PortCfg.AdhocMode = 0;
2419
2420 pAdapter->PortCfg.SsidLen = 0;
2421 NdisZeroMemory(pAdapter->PortCfg.Ssid, MAX_LEN_OF_SSID); // NOT NULL-terminated
2422
2423 // global variables mXXXX used in MAC protocol state machines
2424 pAdapter->PortCfg.Mibss = FALSE;
2425 pAdapter->PortCfg.Massoc = FALSE;
2426 pAdapter->PortCfg.Mauth = FALSE;
2427
2428 // PHY specification
2429 pAdapter->PortCfg.PhyMode = 0xff;
2430 // RTMPSetPhyMode(pAdapter, PHY_11BG_MIXED); // default in 11BG mixed mode
2431 // pAdapter->PortCfg.Channel = FirstChannel(pAdapter);
2432 pAdapter->PortCfg.Dsifs = 10; // in units of usec
2433 pAdapter->PortCfg.TxPreambleInUsed = Rt802_11PreambleLong; // use Long preamble on TX by defaut
2434
2435 // user desired power mode
2436 pAdapter->PortCfg.WindowsPowerMode = Ndis802_11PowerModeCAM; // Ndis802_11PowerModeFast_PSP;
2437 pAdapter->PortCfg.WindowsBatteryPowerMode = Ndis802_11PowerModeCAM; // Ndis802_11PowerModeFast_PSP;
2438 pAdapter->PortCfg.WindowsTxPreamble = Rt802_11PreambleAuto; // use Long preamble on TX by defaut
2439 pAdapter->PortCfg.WindowsACCAMEnable = FALSE;
2440 // pAdapter->PortCfg.PacketFilter = NDIS_PACKET_TYPE_ALL_MULTICAST | NDIS_PACKET_TYPE_DIRECTED | NDIS_PACKET_TYPE_BROADCAST;
2441 pAdapter->bAcceptDirect = TRUE;
2442 pAdapter->bAcceptMulticast = FALSE;
2443 pAdapter->bAcceptBroadcast = TRUE;
2444 pAdapter->bAcceptAllMulticast = TRUE;
2445
2446 // parameters to be used when this STA starts a new ADHOC network
2447 pAdapter->PortCfg.IbssConfig.BeaconPeriod = 100;
2448 pAdapter->PortCfg.IbssConfig.AtimWin = 0;
2449 pAdapter->PortCfg.IbssConfig.Channel = 1;
2450 pAdapter->PortCfg.RfType = RFIC_2525;
2451 pAdapter->PortCfg.LedMode = LED_MODE_DEFAULT;
2452 RTMPInitTimer(pAdapter, &pAdapter->PortCfg.RfTuningTimer, AsicRfTuningExec);
2453
2454 pAdapter->PortCfg.IgnoredScanNumber = 0;
2455 pAdapter->bTxBusy = FALSE;
2456
2457 pAdapter->PortCfg.bHwRadio = TRUE;
2458 pAdapter->PortCfg.bSwRadio = TRUE;
2459 pAdapter->PortCfg.bRadio = TRUE;
2460 pAdapter->PortCfg.bHardwareRadio = FALSE; // Default is OFF
2461 pAdapter->PortCfg.bAutoTxAgc = FALSE; // Default is OFF
2462 pAdapter->PortCfg.bShowHiddenSSID = FALSE;
2463
2464 // Nitro mode control
2465 pAdapter->PortCfg.EnableTxBurst = 0;
2466 pAdapter->PortCfg.AutoReconnect = TRUE;
2467
2468 // Save the init time as last scan time, the system should do scan after 2 seconds.
2469 pAdapter->PortCfg.LastScanTime = 0;
2470
2471 // Default Config change flag
2472 pAdapter->bConfigChanged = FALSE;
2473
2474 pAdapter->PortCfg.bLocalAdminMAC = TRUE;
2475
2476 pAdapter->NeedSwapToLittleEndian = TRUE;
2477
2478 // dynamic BBP R17:sensibity tuning to overcome background noise
2479 pAdapter->PortCfg.BbpTuningEnable = TRUE; // overwritten by E2PROM setting
2480 pAdapter->PortCfg.VgcLowerBound = 0x38; // overwritten by E2PROM setting
2481 pAdapter->PortCfg.BbpTuning.FalseCcaLowerThreshold = 100;
2482 pAdapter->PortCfg.BbpTuning.FalseCcaUpperThreshold = 4; // unit 128, 4*128 = 512
2483 pAdapter->PortCfg.BbpTuning.VgcDelta = 1;
2484 pAdapter->PortCfg.BbpTuning.VgcUpperBound = BBP_R17_DYNAMIC_UP_BOUND;
2485
2486 pAdapter->PortCfg.StaWithEtherBridge.Enable = FALSE;
2487 NdisFillMemory(&pAdapter->PortCfg.StaWithEtherBridge.EtherMacAddr, MAC_ADDR_LEN, 0xff);
2488
2489 #ifdef RALINK_ATE
2490 memset(&pAdapter->ate, 0, sizeof(ATE_INFO));
2491 pAdapter->ate.Mode = ATE_STASTART;
2492 pAdapter->ate.TxCount = TX_RING_SIZE;
2493 pAdapter->ate.TxLength = PRIO_BUFFER_SIZE;
2494 pAdapter->ate.TxRate = RATE_11;
2495 pAdapter->ate.Channel = 1;
2496 memcpy(&pAdapter->ate.Addr1,"001122334455", ETH_LENGTH_OF_ADDRESS);
2497 memcpy(&pAdapter->ate.Addr2,"001122334455", ETH_LENGTH_OF_ADDRESS);
2498 memcpy(&pAdapter->ate.Addr3,"001122334455", ETH_LENGTH_OF_ADDRESS);
2499 #endif //#ifdef RALINK_ATE
2500
2501 RTMP_IO_READ32(pAdapter, 0, &pAdapter->PortCfg.Rt2560Version);
2502
2503 DBGPRINT(RT_DEBUG_TRACE, "<-- PortCfgInit\n");
2504 }
2505
2506 UCHAR BtoH(char ch)
2507 {
2508 if (ch >= '0' && ch <= '9') return (ch - '0'); // Handle numerals
2509 if (ch >= 'A' && ch <= 'F') return (ch - 'A' + 0xA); // Handle capitol hex digits
2510 if (ch >= 'a' && ch <= 'f') return (ch - 'a' + 0xA); // Handle small hex digits
2511 return(255);
2512 }
2513
2514 //
2515 // FUNCTION: AtoH(char *, UCHAR *, int)
2516 //
2517 // PURPOSE: Converts ascii string to network order hex
2518 //
2519 // PARAMETERS:
2520 // src - pointer to input ascii string
2521 // dest - pointer to output hex
2522 // destlen - size of dest
2523 //
2524 // COMMENTS:
2525 //
2526 // 2 ascii bytes make a hex byte so must put 1st ascii byte of pair
2527 // into upper nibble and 2nd ascii byte of pair into lower nibble.
2528 //
2529
2530 void AtoH(char * src, UCHAR * dest, int destlen)
2531 {
2532 char *srcptr;
2533 PUCHAR destTemp;
2534
2535 srcptr = src;
2536 destTemp = (PUCHAR) dest;
2537
2538 while(destlen--)
2539 {
2540 *destTemp = BtoH(*srcptr++) << 4; // Put 1st ascii byte in upper nibble.
2541 *destTemp += BtoH(*srcptr++); // Add 2nd ascii byte to above.
2542 destTemp++;
2543 }
2544 }
2545
2546 /*
2547 ========================================================================
2548
2549 Routine Description:
2550 Init timer objects
2551
2552 Arguments:
2553 pAdapter Pointer to our adapter
2554 pTimer Timer structure
2555 pTimerFunc Function to execute when timer expired
2556 Repeat Ture for period timer
2557
2558 Return Value:
2559 None
2560
2561 Note:
2562
2563 ========================================================================
2564 */
2565 VOID RTMPInitTimer(
2566 IN PRTMP_ADAPTER pAdapter,
2567 IN PRALINK_TIMER_STRUCT pTimer,
2568 IN PVOID pTimerFunc)
2569 {
2570 pTimer->State = FALSE;
2571 init_timer(&pTimer->TimerObj);
2572 pTimer->TimerObj.data = (unsigned long)pAdapter;
2573 pTimer->TimerObj.function = pTimerFunc;
2574 }
2575
2576 /*
2577 ========================================================================
2578
2579 Routine Description:
2580 Init timer objects
2581
2582 Arguments:
2583 pTimer Timer structure
2584 Value Timer value in milliseconds
2585
2586 Return Value:
2587 None
2588
2589 Note:
2590
2591 ========================================================================
2592 */
2593 VOID RTMPSetTimer(
2594 IN PRTMP_ADAPTER pAdapter,
2595 IN PRALINK_TIMER_STRUCT pTimer,
2596 IN ULONG Value)
2597 {
2598 pTimer->TimerValue = Value;
2599 pTimer->State = FALSE;
2600 pTimer->TimerObj.expires = jiffies + (Value * HZ)/1000;
2601 add_timer(&pTimer->TimerObj);
2602 }
2603
2604 /*
2605 ========================================================================
2606
2607 Routine Description:
2608 Cancel timer objects
2609
2610 Arguments:
2611 Adapter Pointer to our adapter
2612
2613 Return Value:
2614 None
2615
2616 Note:
2617 Reset NIC to initial state AS IS system boot up time.
2618
2619 ========================================================================
2620 */
2621 VOID RTMPCancelTimer(
2622 IN PRALINK_TIMER_STRUCT pTimer)
2623 {
2624 del_timer_sync(&pTimer->TimerObj);
2625 }
2626
MOXA 2.6.9 from sdlinux-moxaart.tgz