include/asm-arm/arch-lh7a40x/registers.h

   1 /* include/asm-arm/arch-lh7a40x/registers.h
   2  *
   3  *  Copyright (C) 2004 Coastal Environmental Systems
   4  *  Copyright (C) 2004 Logic Product Development
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  version 2 as published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include <linux/config.h>
  13 #include <asm/arch/constants.h>
  14
  15 #ifndef __ASM_ARCH_REGISTERS_H
  16 #define __ASM_ARCH_REGISTERS_H
  17
  18
  19         /* Physical register base addresses */
  20
  21 #define AC97_PHYS       (0x80000000)    /* AC97 Controller */
  22 #define MMC_PHYS        (0x80000100)    /* Multimedia Card Controller */
  23 #define USB_PHYS        (0x80000200)    /* USB Client */
  24 #define SCI_PHYS        (0x80000300)    /* Secure Card Interface */
  25 #define CSC_PHYS        (0x80000400)    /* Clock/State Controller  */
  26 #define INTC_PHYS       (0x80000500)    /* Interrupt Controller */
  27 #define UART1_PHYS      (0x80000600)    /* UART1 Controller */
  28 #define SIR_PHYS        (0x80000600)    /* IR Controller, same are UART1 */
  29 #define UART2_PHYS      (0x80000700)    /* UART2 Controller */
  30 #define UART3_PHYS      (0x80000800)    /* UART3 Controller */
  31 #define DCDC_PHYS       (0x80000900)    /* DC to DC Controller */
  32 #define ACI_PHYS        (0x80000a00)    /* Audio Codec Interface */
  33 #define SSP_PHYS        (0x80000b00)    /* Synchronous ... */
  34 #define TIMER_PHYS      (0x80000c00)    /* Timer Controller */
  35 #define RTC_PHYS        (0x80000d00)    /* Real-time Clock */
  36 #define GPIO_PHYS       (0x80000e00)    /* General Purpose IO */
  37 #define BMI_PHYS        (0x80000f00)    /* Battery Monitor Interface */
  38 #define WDT_PHYS        (0x80001400)    /* Watchdog Timer */
  39 #define SMC_PHYS        (0x80002000)    /* Static Memory Controller */
  40 #define SDRC_PHYS       (0x80002400)    /* SDRAM Controller */
  41 #define DMAC_PHYS       (0x80002800)    /* DMA Controller */
  42 #define CLCDC_PHYS      (0x80003000)    /* Color LCD Controller */
  43
  44         /* Physical registers of the LH7A404 */
  45
  46 #define VIC1_PHYS       (0x80008000)    /* Vectored Interrupt Controller 1 */
  47 #define USBH_PHYS       (0x80009000)    /* USB OHCI host controller */
  48 #define VIC2_PHYS       (0x8000a000)    /* Vectored Interrupt Controller 2 */
  49
  50 /*#define KBD_PHYS      (0x80000e00) */
  51 /*#define LCDICP_PHYS   (0x80001000) */
  52
  53
  54         /* Clock/State Controller register */
  55
  56 #define CSC_PWRCNT      __REG(CSC_PHYS + 0x04) /* Power control */
  57
  58 #define CSC_PWRCNT_USBH_EN      (1<<28) /* USB Host power enable */
  59
  60
  61         /* Interrupt Controller registers */
  62
  63 #define INTC_INTSR      __REG(INTC_PHYS + 0x00) /* Status */
  64 #define INTC_INTRSR     __REG(INTC_PHYS + 0x04) /* Raw Status */
  65 #define INTC_INTENS     __REG(INTC_PHYS + 0x08) /* Enable Set */
  66 #define INTC_INTENC     __REG(INTC_PHYS + 0x0c) /* Enable Clear */
  67
  68
  69         /* Vectored Interrupted Controller registers */
  70
  71 #define VIC1_IRQSTATUS  __REG(VIC1_PHYS + 0x00)
  72 #define VIC1_FIQSTATUS  __REG(VIC1_PHYS + 0x04)
  73 #define VIC1_RAWINTR    __REG(VIC1_PHYS + 0x08)
  74 #define VIC1_INTSEL     __REG(VIC1_PHYS + 0x0c)
  75 #define VIC1_INTEN      __REG(VIC1_PHYS + 0x10)
  76 #define VIC1_INTENCLR   __REG(VIC1_PHYS + 0x14)
  77 #define VIC1_SOFTINT    __REG(VIC1_PHYS + 0x18)
  78 #define VIC1_SOFTINTCLR __REG(VIC1_PHYS + 0x1c)
  79 #define VIC1_PROTECT    __REG(VIC1_PHYS + 0x20)
  80 #define VIC1_VECTADDR   __REG(VIC1_PHYS + 0x30)
  81 #define VIC1_NVADDR     __REG(VIC1_PHYS + 0x34)
  82 #define VIC1_VAD0       __REG(VIC1_PHYS + 0x100)
  83 #define VIC1_VECTCNTL0  __REG(VIC1_PHYS + 0x200)
  84 #define VIC2_IRQSTATUS  __REG(VIC2_PHYS + 0x00)
  85 #define VIC2_FIQSTATUS  __REG(VIC2_PHYS + 0x04)
  86 #define VIC2_RAWINTR    __REG(VIC2_PHYS + 0x08)
  87 #define VIC2_INTSEL     __REG(VIC2_PHYS + 0x0c)
  88 #define VIC2_INTEN      __REG(VIC2_PHYS + 0x10)
  89 #define VIC2_INTENCLR   __REG(VIC2_PHYS + 0x14)
  90 #define VIC2_SOFTINT    __REG(VIC2_PHYS + 0x18)
  91 #define VIC2_SOFTINTCLR __REG(VIC2_PHYS + 0x1c)
  92 #define VIC2_PROTECT    __REG(VIC2_PHYS + 0x20)
  93 #define VIC2_VECTADDR   __REG(VIC2_PHYS + 0x30)
  94 #define VIC2_NVADDR     __REG(VIC2_PHYS + 0x34)
  95 #define VIC2_VAD0       __REG(VIC2_PHYS + 0x100)
  96 #define VIC2_VECTCNTL0  __REG(VIC2_PHYS + 0x200)
  97
  98 #define VIC_CNTL_ENABLE (0x20)
  99
 100         /* USB Host registers (Open HCI compatible) */
 101
 102 #define USBH_CMDSTATUS  __REG(USBH_PHYS + 0x08)
 103
 104
 105         /* GPIO registers */
 106
 107 #define GPIO_INTTYPE1   __REG(GPIO_PHYS + 0x4c) /* Interrupt Type 1 (Edge) */
 108 #define GPIO_INTTYPE2   __REG(GPIO_PHYS + 0x50) /* Interrupt Type 2 */
 109 #define GPIO_GPIOFEOI   __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
 110 #define GPIO_GPIOINTEN  __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
 111 #define GPIO_INTSTATUS  __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
 112
 113
 114         /* Static Memory Controller registers */
 115
 116 #define SMC_BCR0        __REG(SMC_PHYS + 0x00)  /* Bank 0 Configuration */
 117 #define SMC_BCR1        __REG(SMC_PHYS + 0x04)  /* Bank 1 Configuration */
 118 #define SMC_BCR2        __REG(SMC_PHYS + 0x08)  /* Bank 2 Configuration */
 119 #define SMC_BCR3        __REG(SMC_PHYS + 0x0C)  /* Bank 3 Configuration */
 120 #define SMC_BCR6        __REG(SMC_PHYS + 0x18)  /* Bank 6 Configuration */
 121 #define SMC_BCR7        __REG(SMC_PHYS + 0x1c)  /* Bank 7 Configuration */
 122
 123
 124 #ifdef CONFIG_MACH_KEV7A400
 125 # define CPLD_RD_OPT_DIP_SW     __REG16(CPLD_PHYS + 0x00) /* Read Option SW */
 126 # define CPLD_WR_IO_BRD_CTL     __REG16(CPLD_PHYS + 0x00) /* Write Control */
 127 # define CPLD_RD_PB_KEYS        __REG16(CPLD_PHYS + 0x02) /* Read Btn Keys */
 128 # define CPLD_LATCHED_INTS      __REG16(CPLD_PHYS + 0x04) /* Read INTR stat. */
 129 # define CPLD_CL_INT            __REG16(CPLD_PHYS + 0x04) /* Clear INTR stat */
 130 # define CPLD_BOOT_MMC_STATUS   __REG16(CPLD_PHYS + 0x06) /* R/O */
 131 # define CPLD_RD_KPD_ROW_SENSE  __REG16(CPLD_PHYS + 0x08)
 132 # define CPLD_WR_PB_INT_MASK    __REG16(CPLD_PHYS + 0x08)
 133 # define CPLD_RD_BRD_DISP_SW    __REG16(CPLD_PHYS + 0x0a)
 134 # define CPLD_WR_EXT_INT_MASK   __REG16(CPLD_PHYS + 0x0a)
 135 # define CPLD_LCD_PWR_CNTL      __REG16(CPLD_PHYS + 0x0c)
 136 # define CPLD_SEVEN_SEG         __REG16(CPLD_PHYS + 0x0e) /* 7 seg. LED mask */
 137
 138 #endif
 139
 140 #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
 141 # define CPLD_CONTROL           __REG8(CPLD02_PHYS)
 142 # define CPLD_SPI_DATA          __REG8(CPLD06_PHYS)
 143 # define CPLD_SPI_CONTROL       __REG8(CPLD08_PHYS)
 144 # define CPLD_SPI_EEPROM        __REG8(CPLD0A_PHYS)
 145 # define CPLD_INTERRUPTS        __REG8(CPLD0C_PHYS) /* IRQ mask/status */
 146 # define CPLD_BOOT_MODE         __REG8(CPLD0E_PHYS)
 147 # define CPLD_FLASH             __REG8(CPLD10_PHYS)
 148 # define CPLD_POWER_MGMT        __REG8(CPLD12_PHYS)
 149 # define CPLD_REVISION          __REG8(CPLD14_PHYS)
 150 # define CPLD_GPIO_EXT          __REG8(CPLD16_PHYS)
 151 # define CPLD_GPIO_DATA         __REG8(CPLD18_PHYS)
 152 # define CPLD_GPIO_DIR          __REG8(CPLD1A_PHYS)
 153 #endif
 154
 155
 156         /* Timer registers */
 157
 158 #define TIMER_LOAD1     __REG(TIMER_PHYS + 0x00) /* Timer 1 initial value */
 159 #define TIMER_VALUE1    __REG(TIMER_PHYS + 0x04) /* Timer 1 current value */
 160 #define TIMER_CONTROL1  __REG(TIMER_PHYS + 0x08) /* Timer 1 control word */
 161 #define TIMER_EOI1      __REG(TIMER_PHYS + 0x0c) /* Timer 1 interrupt clear */
 162
 163 #define TIMER_LOAD2     __REG(TIMER_PHYS + 0x20) /* Timer 2 initial value */
 164 #define TIMER_VALUE2    __REG(TIMER_PHYS + 0x24) /* Timer 2 current value */
 165 #define TIMER_CONTROL2  __REG(TIMER_PHYS + 0x28) /* Timer 2 control word */
 166 #define TIMER_EOI2      __REG(TIMER_PHYS + 0x2c) /* Timer 2 interrupt clear */
 167
 168 #define TIMER_BUZZCON   __REG(TIMER_PHYS + 0x40) /* Buzzer configuration */
 169
 170 #define TIMER_LOAD3     __REG(TIMER_PHYS + 0x80) /* Timer 3 initial value */
 171 #define TIMER_VALUE3    __REG(TIMER_PHYS + 0x84) /* Timer 3 current value */
 172 #define TIMER_CONTROL3  __REG(TIMER_PHYS + 0x88) /* Timer 3 control word */
 173 #define TIMER_EOI3      __REG(TIMER_PHYS + 0x8c) /* Timer 3 interrupt clear */
 174
 175 #define TIMER_C_ENABLE          (1<<7)
 176 #define TIMER_C_PERIODIC        (1<<6)
 177 #define TIMER_C_FREERUNNING     (0)
 178 #define TIMER_C_2KHZ            (0x00)          /* 1.986 kHz */
 179 #define TIMER_C_508KHZ          (0x08)
 180
 181         /* GPIO registers */
 182
 183 #define GPIO_PFDD               __REG(GPIO_PHYS + 0x34) /* PF direction */
 184 #define GPIO_INTTYPE1           __REG(GPIO_PHYS + 0x4c) /* IRQ edge or lvl  */
 185 #define GPIO_INTTYPE2           __REG(GPIO_PHYS + 0x50) /* IRQ activ hi/lo */
 186 #define GPIO_GPIOFEOI           __REG(GPIO_PHYS + 0x54) /* GPIOF end of IRQ */
 187 #define GPIO_GPIOFINTEN         __REG(GPIO_PHYS + 0x58) /* GPIOF IRQ enable */
 188 #define GPIO_INTSTATUS          __REG(GPIO_PHYS + 0x5c) /* GPIOF IRQ latch */
 189 #define GPIO_RAWINTSTATUS       __REG(GPIO_PHYS + 0x60) /* GPIOF IRQ raw */
 190
 191
 192 #endif  /* _ASM_ARCH_REGISTERS_H */
 193