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Linux 2.6.36-rc5
[linux-2.6/get_maintainer.git] / drivers / usb / musb / musb_core.c
blob540c766c4f8608eec95df744fc015030ddc54ff1
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101
102 #ifdef CONFIG_ARM
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
106 #endif
107
108 #include "musb_core.h"
109
110
111 #ifdef CONFIG_ARCH_DAVINCI
112 #include "davinci.h"
113 #endif
114
115 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
116
117
118 unsigned musb_debug;
119 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
120 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
121
122 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
123 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
124
125 #define MUSB_VERSION "6.0"
126
127 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
128
129 #define MUSB_DRIVER_NAME "musb_hdrc"
130 const char musb_driver_name[] = MUSB_DRIVER_NAME;
131
132 MODULE_DESCRIPTION(DRIVER_INFO);
133 MODULE_AUTHOR(DRIVER_AUTHOR);
134 MODULE_LICENSE("GPL");
135 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
136
137
138 /*-------------------------------------------------------------------------*/
139
140 static inline struct musb *dev_to_musb(struct device *dev)
141 {
142 #ifdef CONFIG_USB_MUSB_HDRC_HCD
143 /* usbcore insists dev->driver_data is a "struct hcd *" */
144 return hcd_to_musb(dev_get_drvdata(dev));
145 #else
146 return dev_get_drvdata(dev);
147 #endif
148 }
149
150 /*-------------------------------------------------------------------------*/
151
152 #ifndef CONFIG_BLACKFIN
153 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
154 {
155 void __iomem *addr = otg->io_priv;
156 int i = 0;
157 u8 r;
158 u8 power;
159
160 /* Make sure the transceiver is not in low power mode */
161 power = musb_readb(addr, MUSB_POWER);
162 power &= ~MUSB_POWER_SUSPENDM;
163 musb_writeb(addr, MUSB_POWER, power);
164
165 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
166 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
167 */
168
169 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
170 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
171 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
172
173 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
174 & MUSB_ULPI_REG_CMPLT)) {
175 i++;
176 if (i == 10000) {
177 DBG(3, "ULPI read timed out\n");
178 return -ETIMEDOUT;
179 }
180
181 }
182 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
183 r &= ~MUSB_ULPI_REG_CMPLT;
184 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
185
186 return musb_readb(addr, MUSB_ULPI_REG_DATA);
187 }
188
189 static int musb_ulpi_write(struct otg_transceiver *otg,
190 u32 offset, u32 data)
191 {
192 void __iomem *addr = otg->io_priv;
193 int i = 0;
194 u8 r = 0;
195 u8 power;
196
197 /* Make sure the transceiver is not in low power mode */
198 power = musb_readb(addr, MUSB_POWER);
199 power &= ~MUSB_POWER_SUSPENDM;
200 musb_writeb(addr, MUSB_POWER, power);
201
202 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
203 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
204 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
205
206 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
207 & MUSB_ULPI_REG_CMPLT)) {
208 i++;
209 if (i == 10000) {
210 DBG(3, "ULPI write timed out\n");
211 return -ETIMEDOUT;
212 }
213 }
214
215 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
216 r &= ~MUSB_ULPI_REG_CMPLT;
217 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
218
219 return 0;
220 }
221 #else
222 #define musb_ulpi_read NULL
223 #define musb_ulpi_write NULL
224 #endif
225
226 static struct otg_io_access_ops musb_ulpi_access = {
227 .read = musb_ulpi_read,
228 .write = musb_ulpi_write,
229 };
230
231 /*-------------------------------------------------------------------------*/
232
233 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
234
235 /*
236 * Load an endpoint's FIFO
237 */
238 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
239 {
240 void __iomem *fifo = hw_ep->fifo;
241
242 prefetch((u8 *)src);
243
244 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
245 'T', hw_ep->epnum, fifo, len, src);
246
247 /* we can't assume unaligned reads work */
248 if (likely((0x01 & (unsigned long) src) == 0)) {
249 u16 index = 0;
250
251 /* best case is 32bit-aligned source address */
252 if ((0x02 & (unsigned long) src) == 0) {
253 if (len >= 4) {
254 writesl(fifo, src + index, len >> 2);
255 index += len & ~0x03;
256 }
257 if (len & 0x02) {
258 musb_writew(fifo, 0, *(u16 *)&src[index]);
259 index += 2;
260 }
261 } else {
262 if (len >= 2) {
263 writesw(fifo, src + index, len >> 1);
264 index += len & ~0x01;
265 }
266 }
267 if (len & 0x01)
268 musb_writeb(fifo, 0, src[index]);
269 } else {
270 /* byte aligned */
271 writesb(fifo, src, len);
272 }
273 }
274
275 /*
276 * Unload an endpoint's FIFO
277 */
278 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
279 {
280 void __iomem *fifo = hw_ep->fifo;
281
282 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
283 'R', hw_ep->epnum, fifo, len, dst);
284
285 /* we can't assume unaligned writes work */
286 if (likely((0x01 & (unsigned long) dst) == 0)) {
287 u16 index = 0;
288
289 /* best case is 32bit-aligned destination address */
290 if ((0x02 & (unsigned long) dst) == 0) {
291 if (len >= 4) {
292 readsl(fifo, dst, len >> 2);
293 index = len & ~0x03;
294 }
295 if (len & 0x02) {
296 *(u16 *)&dst[index] = musb_readw(fifo, 0);
297 index += 2;
298 }
299 } else {
300 if (len >= 2) {
301 readsw(fifo, dst, len >> 1);
302 index = len & ~0x01;
303 }
304 }
305 if (len & 0x01)
306 dst[index] = musb_readb(fifo, 0);
307 } else {
308 /* byte aligned */
309 readsb(fifo, dst, len);
310 }
311 }
312
313 #endif /* normal PIO */
314
315
316 /*-------------------------------------------------------------------------*/
317
318 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
319 static const u8 musb_test_packet[53] = {
320 /* implicit SYNC then DATA0 to start */
321
322 /* JKJKJKJK x9 */
323 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
324 /* JJKKJJKK x8 */
325 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
326 /* JJJJKKKK x8 */
327 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
328 /* JJJJJJJKKKKKKK x8 */
329 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
330 /* JJJJJJJK x8 */
331 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
332 /* JKKKKKKK x10, JK */
333 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
334
335 /* implicit CRC16 then EOP to end */
336 };
337
338 void musb_load_testpacket(struct musb *musb)
339 {
340 void __iomem *regs = musb->endpoints[0].regs;
341
342 musb_ep_select(musb->mregs, 0);
343 musb_write_fifo(musb->control_ep,
344 sizeof(musb_test_packet), musb_test_packet);
345 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
346 }
347
348 /*-------------------------------------------------------------------------*/
349
350 const char *otg_state_string(struct musb *musb)
351 {
352 switch (musb->xceiv->state) {
353 case OTG_STATE_A_IDLE: return "a_idle";
354 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
355 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
356 case OTG_STATE_A_HOST: return "a_host";
357 case OTG_STATE_A_SUSPEND: return "a_suspend";
358 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
359 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
360 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
361 case OTG_STATE_B_IDLE: return "b_idle";
362 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
363 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
364 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
365 case OTG_STATE_B_HOST: return "b_host";
366 default: return "UNDEFINED";
367 }
368 }
369
370 #ifdef CONFIG_USB_MUSB_OTG
371
372 /*
373 * Handles OTG hnp timeouts, such as b_ase0_brst
374 */
375 void musb_otg_timer_func(unsigned long data)
376 {
377 struct musb *musb = (struct musb *)data;
378 unsigned long flags;
379
380 spin_lock_irqsave(&musb->lock, flags);
381 switch (musb->xceiv->state) {
382 case OTG_STATE_B_WAIT_ACON:
383 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
384 musb_g_disconnect(musb);
385 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
386 musb->is_active = 0;
387 break;
388 case OTG_STATE_A_SUSPEND:
389 case OTG_STATE_A_WAIT_BCON:
390 DBG(1, "HNP: %s timeout\n", otg_state_string(musb));
391 musb_set_vbus(musb, 0);
392 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
393 break;
394 default:
395 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
396 }
397 musb->ignore_disconnect = 0;
398 spin_unlock_irqrestore(&musb->lock, flags);
399 }
400
401 /*
402 * Stops the HNP transition. Caller must take care of locking.
403 */
404 void musb_hnp_stop(struct musb *musb)
405 {
406 struct usb_hcd *hcd = musb_to_hcd(musb);
407 void __iomem *mbase = musb->mregs;
408 u8 reg;
409
410 DBG(1, "HNP: stop from %s\n", otg_state_string(musb));
411
412 switch (musb->xceiv->state) {
413 case OTG_STATE_A_PERIPHERAL:
414 musb_g_disconnect(musb);
415 DBG(1, "HNP: back to %s\n", otg_state_string(musb));
416 break;
417 case OTG_STATE_B_HOST:
418 DBG(1, "HNP: Disabling HR\n");
419 hcd->self.is_b_host = 0;
420 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
421 MUSB_DEV_MODE(musb);
422 reg = musb_readb(mbase, MUSB_POWER);
423 reg |= MUSB_POWER_SUSPENDM;
424 musb_writeb(mbase, MUSB_POWER, reg);
425 /* REVISIT: Start SESSION_REQUEST here? */
426 break;
427 default:
428 DBG(1, "HNP: Stopping in unknown state %s\n",
429 otg_state_string(musb));
430 }
431
432 /*
433 * When returning to A state after HNP, avoid hub_port_rebounce(),
434 * which cause occasional OPT A "Did not receive reset after connect"
435 * errors.
436 */
437 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
438 }
439
440 #endif
441
442 /*
443 * Interrupt Service Routine to record USB "global" interrupts.
444 * Since these do not happen often and signify things of
445 * paramount importance, it seems OK to check them individually;
446 * the order of the tests is specified in the manual
447 *
448 * @param musb instance pointer
449 * @param int_usb register contents
450 * @param devctl
451 * @param power
452 */
453
454 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
455 u8 devctl, u8 power)
456 {
457 irqreturn_t handled = IRQ_NONE;
458
459 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
460 int_usb);
461
462 /* in host mode, the peripheral may issue remote wakeup.
463 * in peripheral mode, the host may resume the link.
464 * spurious RESUME irqs happen too, paired with SUSPEND.
465 */
466 if (int_usb & MUSB_INTR_RESUME) {
467 handled = IRQ_HANDLED;
468 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
469
470 if (devctl & MUSB_DEVCTL_HM) {
471 #ifdef CONFIG_USB_MUSB_HDRC_HCD
472 void __iomem *mbase = musb->mregs;
473
474 switch (musb->xceiv->state) {
475 case OTG_STATE_A_SUSPEND:
476 /* remote wakeup? later, GetPortStatus
477 * will stop RESUME signaling
478 */
479
480 if (power & MUSB_POWER_SUSPENDM) {
481 /* spurious */
482 musb->int_usb &= ~MUSB_INTR_SUSPEND;
483 DBG(2, "Spurious SUSPENDM\n");
484 break;
485 }
486
487 power &= ~MUSB_POWER_SUSPENDM;
488 musb_writeb(mbase, MUSB_POWER,
489 power | MUSB_POWER_RESUME);
490
491 musb->port1_status |=
492 (USB_PORT_STAT_C_SUSPEND << 16)
493 | MUSB_PORT_STAT_RESUME;
494 musb->rh_timer = jiffies
495 + msecs_to_jiffies(20);
496
497 musb->xceiv->state = OTG_STATE_A_HOST;
498 musb->is_active = 1;
499 usb_hcd_resume_root_hub(musb_to_hcd(musb));
500 break;
501 case OTG_STATE_B_WAIT_ACON:
502 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
503 musb->is_active = 1;
504 MUSB_DEV_MODE(musb);
505 break;
506 default:
507 WARNING("bogus %s RESUME (%s)\n",
508 "host",
509 otg_state_string(musb));
510 }
511 #endif
512 } else {
513 switch (musb->xceiv->state) {
514 #ifdef CONFIG_USB_MUSB_HDRC_HCD
515 case OTG_STATE_A_SUSPEND:
516 /* possibly DISCONNECT is upcoming */
517 musb->xceiv->state = OTG_STATE_A_HOST;
518 usb_hcd_resume_root_hub(musb_to_hcd(musb));
519 break;
520 #endif
521 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
522 case OTG_STATE_B_WAIT_ACON:
523 case OTG_STATE_B_PERIPHERAL:
524 /* disconnect while suspended? we may
525 * not get a disconnect irq...
526 */
527 if ((devctl & MUSB_DEVCTL_VBUS)
528 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
529 ) {
530 musb->int_usb |= MUSB_INTR_DISCONNECT;
531 musb->int_usb &= ~MUSB_INTR_SUSPEND;
532 break;
533 }
534 musb_g_resume(musb);
535 break;
536 case OTG_STATE_B_IDLE:
537 musb->int_usb &= ~MUSB_INTR_SUSPEND;
538 break;
539 #endif
540 default:
541 WARNING("bogus %s RESUME (%s)\n",
542 "peripheral",
543 otg_state_string(musb));
544 }
545 }
546 }
547
548 #ifdef CONFIG_USB_MUSB_HDRC_HCD
549 /* see manual for the order of the tests */
550 if (int_usb & MUSB_INTR_SESSREQ) {
551 void __iomem *mbase = musb->mregs;
552
553 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
554
555 /* IRQ arrives from ID pin sense or (later, if VBUS power
556 * is removed) SRP. responses are time critical:
557 * - turn on VBUS (with silicon-specific mechanism)
558 * - go through A_WAIT_VRISE
559 * - ... to A_WAIT_BCON.
560 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
561 */
562 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
563 musb->ep0_stage = MUSB_EP0_START;
564 musb->xceiv->state = OTG_STATE_A_IDLE;
565 MUSB_HST_MODE(musb);
566 musb_set_vbus(musb, 1);
567
568 handled = IRQ_HANDLED;
569 }
570
571 if (int_usb & MUSB_INTR_VBUSERROR) {
572 int ignore = 0;
573
574 /* During connection as an A-Device, we may see a short
575 * current spikes causing voltage drop, because of cable
576 * and peripheral capacitance combined with vbus draw.
577 * (So: less common with truly self-powered devices, where
578 * vbus doesn't act like a power supply.)
579 *
580 * Such spikes are short; usually less than ~500 usec, max
581 * of ~2 msec. That is, they're not sustained overcurrent
582 * errors, though they're reported using VBUSERROR irqs.
583 *
584 * Workarounds: (a) hardware: use self powered devices.
585 * (b) software: ignore non-repeated VBUS errors.
586 *
587 * REVISIT: do delays from lots of DEBUG_KERNEL checks
588 * make trouble here, keeping VBUS < 4.4V ?
589 */
590 switch (musb->xceiv->state) {
591 case OTG_STATE_A_HOST:
592 /* recovery is dicey once we've gotten past the
593 * initial stages of enumeration, but if VBUS
594 * stayed ok at the other end of the link, and
595 * another reset is due (at least for high speed,
596 * to redo the chirp etc), it might work OK...
597 */
598 case OTG_STATE_A_WAIT_BCON:
599 case OTG_STATE_A_WAIT_VRISE:
600 if (musb->vbuserr_retry) {
601 void __iomem *mbase = musb->mregs;
602
603 musb->vbuserr_retry--;
604 ignore = 1;
605 devctl |= MUSB_DEVCTL_SESSION;
606 musb_writeb(mbase, MUSB_DEVCTL, devctl);
607 } else {
608 musb->port1_status |=
609 USB_PORT_STAT_OVERCURRENT
610 | (USB_PORT_STAT_C_OVERCURRENT << 16);
611 }
612 break;
613 default:
614 break;
615 }
616
617 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
618 otg_state_string(musb),
619 devctl,
620 ({ char *s;
621 switch (devctl & MUSB_DEVCTL_VBUS) {
622 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
623 s = "<SessEnd"; break;
624 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
625 s = "<AValid"; break;
626 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
627 s = "<VBusValid"; break;
628 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
629 default:
630 s = "VALID"; break;
631 }; s; }),
632 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
633 musb->port1_status);
634
635 /* go through A_WAIT_VFALL then start a new session */
636 if (!ignore)
637 musb_set_vbus(musb, 0);
638 handled = IRQ_HANDLED;
639 }
640
641 #endif
642 if (int_usb & MUSB_INTR_SUSPEND) {
643 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
644 otg_state_string(musb), devctl, power);
645 handled = IRQ_HANDLED;
646
647 switch (musb->xceiv->state) {
648 #ifdef CONFIG_USB_MUSB_OTG
649 case OTG_STATE_A_PERIPHERAL:
650 /* We also come here if the cable is removed, since
651 * this silicon doesn't report ID-no-longer-grounded.
652 *
653 * We depend on T(a_wait_bcon) to shut us down, and
654 * hope users don't do anything dicey during this
655 * undesired detour through A_WAIT_BCON.
656 */
657 musb_hnp_stop(musb);
658 usb_hcd_resume_root_hub(musb_to_hcd(musb));
659 musb_root_disconnect(musb);
660 musb_platform_try_idle(musb, jiffies
661 + msecs_to_jiffies(musb->a_wait_bcon
662 ? : OTG_TIME_A_WAIT_BCON));
663
664 break;
665 #endif
666 case OTG_STATE_B_IDLE:
667 if (!musb->is_active)
668 break;
669 case OTG_STATE_B_PERIPHERAL:
670 musb_g_suspend(musb);
671 musb->is_active = is_otg_enabled(musb)
672 && musb->xceiv->gadget->b_hnp_enable;
673 if (musb->is_active) {
674 #ifdef CONFIG_USB_MUSB_OTG
675 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
676 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
677 mod_timer(&musb->otg_timer, jiffies
678 + msecs_to_jiffies(
679 OTG_TIME_B_ASE0_BRST));
680 #endif
681 }
682 break;
683 case OTG_STATE_A_WAIT_BCON:
684 if (musb->a_wait_bcon != 0)
685 musb_platform_try_idle(musb, jiffies
686 + msecs_to_jiffies(musb->a_wait_bcon));
687 break;
688 case OTG_STATE_A_HOST:
689 musb->xceiv->state = OTG_STATE_A_SUSPEND;
690 musb->is_active = is_otg_enabled(musb)
691 && musb->xceiv->host->b_hnp_enable;
692 break;
693 case OTG_STATE_B_HOST:
694 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
695 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
696 break;
697 default:
698 /* "should not happen" */
699 musb->is_active = 0;
700 break;
701 }
702 }
703
704 #ifdef CONFIG_USB_MUSB_HDRC_HCD
705 if (int_usb & MUSB_INTR_CONNECT) {
706 struct usb_hcd *hcd = musb_to_hcd(musb);
707
708 handled = IRQ_HANDLED;
709 musb->is_active = 1;
710 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
711
712 musb->ep0_stage = MUSB_EP0_START;
713
714 #ifdef CONFIG_USB_MUSB_OTG
715 /* flush endpoints when transitioning from Device Mode */
716 if (is_peripheral_active(musb)) {
717 /* REVISIT HNP; just force disconnect */
718 }
719 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
720 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
721 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
722 #endif
723 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
724 |USB_PORT_STAT_HIGH_SPEED
725 |USB_PORT_STAT_ENABLE
726 );
727 musb->port1_status |= USB_PORT_STAT_CONNECTION
728 |(USB_PORT_STAT_C_CONNECTION << 16);
729
730 /* high vs full speed is just a guess until after reset */
731 if (devctl & MUSB_DEVCTL_LSDEV)
732 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
733
734 /* indicate new connection to OTG machine */
735 switch (musb->xceiv->state) {
736 case OTG_STATE_B_PERIPHERAL:
737 if (int_usb & MUSB_INTR_SUSPEND) {
738 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
739 int_usb &= ~MUSB_INTR_SUSPEND;
740 goto b_host;
741 } else
742 DBG(1, "CONNECT as b_peripheral???\n");
743 break;
744 case OTG_STATE_B_WAIT_ACON:
745 DBG(1, "HNP: CONNECT, now b_host\n");
746 b_host:
747 musb->xceiv->state = OTG_STATE_B_HOST;
748 hcd->self.is_b_host = 1;
749 musb->ignore_disconnect = 0;
750 del_timer(&musb->otg_timer);
751 break;
752 default:
753 if ((devctl & MUSB_DEVCTL_VBUS)
754 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
755 musb->xceiv->state = OTG_STATE_A_HOST;
756 hcd->self.is_b_host = 0;
757 }
758 break;
759 }
760
761 /* poke the root hub */
762 MUSB_HST_MODE(musb);
763 if (hcd->status_urb)
764 usb_hcd_poll_rh_status(hcd);
765 else
766 usb_hcd_resume_root_hub(hcd);
767
768 DBG(1, "CONNECT (%s) devctl %02x\n",
769 otg_state_string(musb), devctl);
770 }
771 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
772
773 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
774 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
775 otg_state_string(musb),
776 MUSB_MODE(musb), devctl);
777 handled = IRQ_HANDLED;
778
779 switch (musb->xceiv->state) {
780 #ifdef CONFIG_USB_MUSB_HDRC_HCD
781 case OTG_STATE_A_HOST:
782 case OTG_STATE_A_SUSPEND:
783 usb_hcd_resume_root_hub(musb_to_hcd(musb));
784 musb_root_disconnect(musb);
785 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
786 musb_platform_try_idle(musb, jiffies
787 + msecs_to_jiffies(musb->a_wait_bcon));
788 break;
789 #endif /* HOST */
790 #ifdef CONFIG_USB_MUSB_OTG
791 case OTG_STATE_B_HOST:
792 /* REVISIT this behaves for "real disconnect"
793 * cases; make sure the other transitions from
794 * from B_HOST act right too. The B_HOST code
795 * in hnp_stop() is currently not used...
796 */
797 musb_root_disconnect(musb);
798 musb_to_hcd(musb)->self.is_b_host = 0;
799 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
800 MUSB_DEV_MODE(musb);
801 musb_g_disconnect(musb);
802 break;
803 case OTG_STATE_A_PERIPHERAL:
804 musb_hnp_stop(musb);
805 musb_root_disconnect(musb);
806 /* FALLTHROUGH */
807 case OTG_STATE_B_WAIT_ACON:
808 /* FALLTHROUGH */
809 #endif /* OTG */
810 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
811 case OTG_STATE_B_PERIPHERAL:
812 case OTG_STATE_B_IDLE:
813 musb_g_disconnect(musb);
814 break;
815 #endif /* GADGET */
816 default:
817 WARNING("unhandled DISCONNECT transition (%s)\n",
818 otg_state_string(musb));
819 break;
820 }
821 }
822
823 /* mentor saves a bit: bus reset and babble share the same irq.
824 * only host sees babble; only peripheral sees bus reset.
825 */
826 if (int_usb & MUSB_INTR_RESET) {
827 handled = IRQ_HANDLED;
828 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
829 /*
830 * Looks like non-HS BABBLE can be ignored, but
831 * HS BABBLE is an error condition. For HS the solution
832 * is to avoid babble in the first place and fix what
833 * caused BABBLE. When HS BABBLE happens we can only
834 * stop the session.
835 */
836 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
837 DBG(1, "BABBLE devctl: %02x\n", devctl);
838 else {
839 ERR("Stopping host session -- babble\n");
840 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
841 }
842 } else if (is_peripheral_capable()) {
843 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
844 switch (musb->xceiv->state) {
845 #ifdef CONFIG_USB_OTG
846 case OTG_STATE_A_SUSPEND:
847 /* We need to ignore disconnect on suspend
848 * otherwise tusb 2.0 won't reconnect after a
849 * power cycle, which breaks otg compliance.
850 */
851 musb->ignore_disconnect = 1;
852 musb_g_reset(musb);
853 /* FALLTHROUGH */
854 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
855 /* never use invalid T(a_wait_bcon) */
856 DBG(1, "HNP: in %s, %d msec timeout\n",
857 otg_state_string(musb),
858 TA_WAIT_BCON(musb));
859 mod_timer(&musb->otg_timer, jiffies
860 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
861 break;
862 case OTG_STATE_A_PERIPHERAL:
863 musb->ignore_disconnect = 0;
864 del_timer(&musb->otg_timer);
865 musb_g_reset(musb);
866 break;
867 case OTG_STATE_B_WAIT_ACON:
868 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
869 otg_state_string(musb));
870 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
871 musb_g_reset(musb);
872 break;
873 #endif
874 case OTG_STATE_B_IDLE:
875 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
876 /* FALLTHROUGH */
877 case OTG_STATE_B_PERIPHERAL:
878 musb_g_reset(musb);
879 break;
880 default:
881 DBG(1, "Unhandled BUS RESET as %s\n",
882 otg_state_string(musb));
883 }
884 }
885 }
886
887 #if 0
888 /* REVISIT ... this would be for multiplexing periodic endpoints, or
889 * supporting transfer phasing to prevent exceeding ISO bandwidth
890 * limits of a given frame or microframe.
891 *
892 * It's not needed for peripheral side, which dedicates endpoints;
893 * though it _might_ use SOF irqs for other purposes.
894 *
895 * And it's not currently needed for host side, which also dedicates
896 * endpoints, relies on TX/RX interval registers, and isn't claimed
897 * to support ISO transfers yet.
898 */
899 if (int_usb & MUSB_INTR_SOF) {
900 void __iomem *mbase = musb->mregs;
901 struct musb_hw_ep *ep;
902 u8 epnum;
903 u16 frame;
904
905 DBG(6, "START_OF_FRAME\n");
906 handled = IRQ_HANDLED;
907
908 /* start any periodic Tx transfers waiting for current frame */
909 frame = musb_readw(mbase, MUSB_FRAME);
910 ep = musb->endpoints;
911 for (epnum = 1; (epnum < musb->nr_endpoints)
912 && (musb->epmask >= (1 << epnum));
913 epnum++, ep++) {
914 /*
915 * FIXME handle framecounter wraps (12 bits)
916 * eliminate duplicated StartUrb logic
917 */
918 if (ep->dwWaitFrame >= frame) {
919 ep->dwWaitFrame = 0;
920 pr_debug("SOF --> periodic TX%s on %d\n",
921 ep->tx_channel ? " DMA" : "",
922 epnum);
923 if (!ep->tx_channel)
924 musb_h_tx_start(musb, epnum);
925 else
926 cppi_hostdma_start(musb, epnum);
927 }
928 } /* end of for loop */
929 }
930 #endif
931
932 schedule_work(&musb->irq_work);
933
934 return handled;
935 }
936
937 /*-------------------------------------------------------------------------*/
938
939 /*
940 * Program the HDRC to start (enable interrupts, dma, etc.).
941 */
942 void musb_start(struct musb *musb)
943 {
944 void __iomem *regs = musb->mregs;
945 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
946
947 DBG(2, "<== devctl %02x\n", devctl);
948
949 /* Set INT enable registers, enable interrupts */
950 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
951 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
952 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
953
954 musb_writeb(regs, MUSB_TESTMODE, 0);
955
956 /* put into basic highspeed mode and start session */
957 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
958 | MUSB_POWER_SOFTCONN
959 | MUSB_POWER_HSENAB
960 /* ENSUSPEND wedges tusb */
961 /* | MUSB_POWER_ENSUSPEND */
962 );
963
964 musb->is_active = 0;
965 devctl = musb_readb(regs, MUSB_DEVCTL);
966 devctl &= ~MUSB_DEVCTL_SESSION;
967
968 if (is_otg_enabled(musb)) {
969 /* session started after:
970 * (a) ID-grounded irq, host mode;
971 * (b) vbus present/connect IRQ, peripheral mode;
972 * (c) peripheral initiates, using SRP
973 */
974 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
975 musb->is_active = 1;
976 else
977 devctl |= MUSB_DEVCTL_SESSION;
978
979 } else if (is_host_enabled(musb)) {
980 /* assume ID pin is hard-wired to ground */
981 devctl |= MUSB_DEVCTL_SESSION;
982
983 } else /* peripheral is enabled */ {
984 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
985 musb->is_active = 1;
986 }
987 musb_platform_enable(musb);
988 musb_writeb(regs, MUSB_DEVCTL, devctl);
989 }
990
991
992 static void musb_generic_disable(struct musb *musb)
993 {
994 void __iomem *mbase = musb->mregs;
995 u16 temp;
996
997 /* disable interrupts */
998 musb_writeb(mbase, MUSB_INTRUSBE, 0);
999 musb_writew(mbase, MUSB_INTRTXE, 0);
1000 musb_writew(mbase, MUSB_INTRRXE, 0);
1001
1002 /* off */
1003 musb_writeb(mbase, MUSB_DEVCTL, 0);
1004
1005 /* flush pending interrupts */
1006 temp = musb_readb(mbase, MUSB_INTRUSB);
1007 temp = musb_readw(mbase, MUSB_INTRTX);
1008 temp = musb_readw(mbase, MUSB_INTRRX);
1009
1010 }
1011
1012 /*
1013 * Make the HDRC stop (disable interrupts, etc.);
1014 * reversible by musb_start
1015 * called on gadget driver unregister
1016 * with controller locked, irqs blocked
1017 * acts as a NOP unless some role activated the hardware
1018 */
1019 void musb_stop(struct musb *musb)
1020 {
1021 /* stop IRQs, timers, ... */
1022 musb_platform_disable(musb);
1023 musb_generic_disable(musb);
1024 DBG(3, "HDRC disabled\n");
1025
1026 /* FIXME
1027 * - mark host and/or peripheral drivers unusable/inactive
1028 * - disable DMA (and enable it in HdrcStart)
1029 * - make sure we can musb_start() after musb_stop(); with
1030 * OTG mode, gadget driver module rmmod/modprobe cycles that
1031 * - ...
1032 */
1033 musb_platform_try_idle(musb, 0);
1034 }
1035
1036 static void musb_shutdown(struct platform_device *pdev)
1037 {
1038 struct musb *musb = dev_to_musb(&pdev->dev);
1039 unsigned long flags;
1040
1041 spin_lock_irqsave(&musb->lock, flags);
1042 musb_platform_disable(musb);
1043 musb_generic_disable(musb);
1044 if (musb->clock)
1045 clk_put(musb->clock);
1046 spin_unlock_irqrestore(&musb->lock, flags);
1047
1048 /* FIXME power down */
1049 }
1050
1051
1052 /*-------------------------------------------------------------------------*/
1053
1054 /*
1055 * The silicon either has hard-wired endpoint configurations, or else
1056 * "dynamic fifo" sizing. The driver has support for both, though at this
1057 * writing only the dynamic sizing is very well tested. Since we switched
1058 * away from compile-time hardware parameters, we can no longer rely on
1059 * dead code elimination to leave only the relevant one in the object file.
1060 *
1061 * We don't currently use dynamic fifo setup capability to do anything
1062 * more than selecting one of a bunch of predefined configurations.
1063 */
1064 #if defined(CONFIG_USB_TUSB6010) || \
1065 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1066 || defined(CONFIG_ARCH_OMAP4)
1067 static ushort __initdata fifo_mode = 4;
1068 #else
1069 static ushort __initdata fifo_mode = 2;
1070 #endif
1071
1072 /* "modprobe ... fifo_mode=1" etc */
1073 module_param(fifo_mode, ushort, 0);
1074 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1075
1076 /*
1077 * tables defining fifo_mode values. define more if you like.
1078 * for host side, make sure both halves of ep1 are set up.
1079 */
1080
1081 /* mode 0 - fits in 2KB */
1082 static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1083 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1084 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1085 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1086 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1087 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1088 };
1089
1090 /* mode 1 - fits in 4KB */
1091 static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1092 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1093 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1094 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1095 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1096 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1097 };
1098
1099 /* mode 2 - fits in 4KB */
1100 static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1101 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1102 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1103 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1104 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1105 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1106 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1107 };
1108
1109 /* mode 3 - fits in 4KB */
1110 static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1111 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1112 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1113 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1114 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1115 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1116 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1117 };
1118
1119 /* mode 4 - fits in 16KB */
1120 static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1121 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1122 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1123 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1124 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1125 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1126 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1127 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1128 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1129 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1130 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1131 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1132 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1133 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1134 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1135 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1136 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1137 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1138 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1139 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1140 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1141 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1142 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1143 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1144 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1145 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1146 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1147 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1148 };
1149
1150 /* mode 5 - fits in 8KB */
1151 static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1152 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1153 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1154 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1155 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1156 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1157 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1158 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1159 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1160 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1161 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1162 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1163 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1164 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1165 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1166 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1167 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1168 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1169 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1170 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1171 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1172 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1173 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1174 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1175 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1176 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1177 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1178 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1179 };
1180
1181 /*
1182 * configure a fifo; for non-shared endpoints, this may be called
1183 * once for a tx fifo and once for an rx fifo.
1184 *
1185 * returns negative errno or offset for next fifo.
1186 */
1187 static int __init
1188 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1189 const struct musb_fifo_cfg *cfg, u16 offset)
1190 {
1191 void __iomem *mbase = musb->mregs;
1192 int size = 0;
1193 u16 maxpacket = cfg->maxpacket;
1194 u16 c_off = offset >> 3;
1195 u8 c_size;
1196
1197 /* expect hw_ep has already been zero-initialized */
1198
1199 size = ffs(max(maxpacket, (u16) 8)) - 1;
1200 maxpacket = 1 << size;
1201
1202 c_size = size - 3;
1203 if (cfg->mode == BUF_DOUBLE) {
1204 if ((offset + (maxpacket << 1)) >
1205 (1 << (musb->config->ram_bits + 2)))
1206 return -EMSGSIZE;
1207 c_size |= MUSB_FIFOSZ_DPB;
1208 } else {
1209 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1210 return -EMSGSIZE;
1211 }
1212
1213 /* configure the FIFO */
1214 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1215
1216 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1217 /* EP0 reserved endpoint for control, bidirectional;
1218 * EP1 reserved for bulk, two unidirection halves.
1219 */
1220 if (hw_ep->epnum == 1)
1221 musb->bulk_ep = hw_ep;
1222 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1223 #endif
1224 switch (cfg->style) {
1225 case FIFO_TX:
1226 musb_write_txfifosz(mbase, c_size);
1227 musb_write_txfifoadd(mbase, c_off);
1228 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1229 hw_ep->max_packet_sz_tx = maxpacket;
1230 break;
1231 case FIFO_RX:
1232 musb_write_rxfifosz(mbase, c_size);
1233 musb_write_rxfifoadd(mbase, c_off);
1234 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1235 hw_ep->max_packet_sz_rx = maxpacket;
1236 break;
1237 case FIFO_RXTX:
1238 musb_write_txfifosz(mbase, c_size);
1239 musb_write_txfifoadd(mbase, c_off);
1240 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1241 hw_ep->max_packet_sz_rx = maxpacket;
1242
1243 musb_write_rxfifosz(mbase, c_size);
1244 musb_write_rxfifoadd(mbase, c_off);
1245 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1246 hw_ep->max_packet_sz_tx = maxpacket;
1247
1248 hw_ep->is_shared_fifo = true;
1249 break;
1250 }
1251
1252 /* NOTE rx and tx endpoint irqs aren't managed separately,
1253 * which happens to be ok
1254 */
1255 musb->epmask |= (1 << hw_ep->epnum);
1256
1257 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1258 }
1259
1260 static struct musb_fifo_cfg __initdata ep0_cfg = {
1261 .style = FIFO_RXTX, .maxpacket = 64,
1262 };
1263
1264 static int __init ep_config_from_table(struct musb *musb)
1265 {
1266 const struct musb_fifo_cfg *cfg;
1267 unsigned i, n;
1268 int offset;
1269 struct musb_hw_ep *hw_ep = musb->endpoints;
1270
1271 if (musb->config->fifo_cfg) {
1272 cfg = musb->config->fifo_cfg;
1273 n = musb->config->fifo_cfg_size;
1274 goto done;
1275 }
1276
1277 switch (fifo_mode) {
1278 default:
1279 fifo_mode = 0;
1280 /* FALLTHROUGH */
1281 case 0:
1282 cfg = mode_0_cfg;
1283 n = ARRAY_SIZE(mode_0_cfg);
1284 break;
1285 case 1:
1286 cfg = mode_1_cfg;
1287 n = ARRAY_SIZE(mode_1_cfg);
1288 break;
1289 case 2:
1290 cfg = mode_2_cfg;
1291 n = ARRAY_SIZE(mode_2_cfg);
1292 break;
1293 case 3:
1294 cfg = mode_3_cfg;
1295 n = ARRAY_SIZE(mode_3_cfg);
1296 break;
1297 case 4:
1298 cfg = mode_4_cfg;
1299 n = ARRAY_SIZE(mode_4_cfg);
1300 break;
1301 case 5:
1302 cfg = mode_5_cfg;
1303 n = ARRAY_SIZE(mode_5_cfg);
1304 break;
1305 }
1306
1307 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1308 musb_driver_name, fifo_mode);
1309
1310
1311 done:
1312 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1313 /* assert(offset > 0) */
1314
1315 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1316 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1317 */
1318
1319 for (i = 0; i < n; i++) {
1320 u8 epn = cfg->hw_ep_num;
1321
1322 if (epn >= musb->config->num_eps) {
1323 pr_debug("%s: invalid ep %d\n",
1324 musb_driver_name, epn);
1325 return -EINVAL;
1326 }
1327 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1328 if (offset < 0) {
1329 pr_debug("%s: mem overrun, ep %d\n",
1330 musb_driver_name, epn);
1331 return -EINVAL;
1332 }
1333 epn++;
1334 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1335 }
1336
1337 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1338 musb_driver_name,
1339 n + 1, musb->config->num_eps * 2 - 1,
1340 offset, (1 << (musb->config->ram_bits + 2)));
1341
1342 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1343 if (!musb->bulk_ep) {
1344 pr_debug("%s: missing bulk\n", musb_driver_name);
1345 return -EINVAL;
1346 }
1347 #endif
1348
1349 return 0;
1350 }
1351
1352
1353 /*
1354 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1355 * @param musb the controller
1356 */
1357 static int __init ep_config_from_hw(struct musb *musb)
1358 {
1359 u8 epnum = 0;
1360 struct musb_hw_ep *hw_ep;
1361 void *mbase = musb->mregs;
1362 int ret = 0;
1363
1364 DBG(2, "<== static silicon ep config\n");
1365
1366 /* FIXME pick up ep0 maxpacket size */
1367
1368 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1369 musb_ep_select(mbase, epnum);
1370 hw_ep = musb->endpoints + epnum;
1371
1372 ret = musb_read_fifosize(musb, hw_ep, epnum);
1373 if (ret < 0)
1374 break;
1375
1376 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1377
1378 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1379 /* pick an RX/TX endpoint for bulk */
1380 if (hw_ep->max_packet_sz_tx < 512
1381 || hw_ep->max_packet_sz_rx < 512)
1382 continue;
1383
1384 /* REVISIT: this algorithm is lazy, we should at least
1385 * try to pick a double buffered endpoint.
1386 */
1387 if (musb->bulk_ep)
1388 continue;
1389 musb->bulk_ep = hw_ep;
1390 #endif
1391 }
1392
1393 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1394 if (!musb->bulk_ep) {
1395 pr_debug("%s: missing bulk\n", musb_driver_name);
1396 return -EINVAL;
1397 }
1398 #endif
1399
1400 return 0;
1401 }
1402
1403 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1404
1405 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1406 * configure endpoints, or take their config from silicon
1407 */
1408 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1409 {
1410 u8 reg;
1411 char *type;
1412 char aInfo[90], aRevision[32], aDate[12];
1413 void __iomem *mbase = musb->mregs;
1414 int status = 0;
1415 int i;
1416
1417 /* log core options (read using indexed model) */
1418 reg = musb_read_configdata(mbase);
1419
1420 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1421 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1422 strcat(aInfo, ", dyn FIFOs");
1423 musb->dyn_fifo = true;
1424 }
1425 if (reg & MUSB_CONFIGDATA_MPRXE) {
1426 strcat(aInfo, ", bulk combine");
1427 musb->bulk_combine = true;
1428 }
1429 if (reg & MUSB_CONFIGDATA_MPTXE) {
1430 strcat(aInfo, ", bulk split");
1431 musb->bulk_split = true;
1432 }
1433 if (reg & MUSB_CONFIGDATA_HBRXE) {
1434 strcat(aInfo, ", HB-ISO Rx");
1435 musb->hb_iso_rx = true;
1436 }
1437 if (reg & MUSB_CONFIGDATA_HBTXE) {
1438 strcat(aInfo, ", HB-ISO Tx");
1439 musb->hb_iso_tx = true;
1440 }
1441 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1442 strcat(aInfo, ", SoftConn");
1443
1444 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1445 musb_driver_name, reg, aInfo);
1446
1447 aDate[0] = 0;
1448 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1449 musb->is_multipoint = 1;
1450 type = "M";
1451 } else {
1452 musb->is_multipoint = 0;
1453 type = "";
1454 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1455 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1456 printk(KERN_ERR
1457 "%s: kernel must blacklist external hubs\n",
1458 musb_driver_name);
1459 #endif
1460 #endif
1461 }
1462
1463 /* log release info */
1464 musb->hwvers = musb_read_hwvers(mbase);
1465 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1466 MUSB_HWVERS_MINOR(musb->hwvers),
1467 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1468 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1469 musb_driver_name, type, aRevision, aDate);
1470
1471 /* configure ep0 */
1472 musb_configure_ep0(musb);
1473
1474 /* discover endpoint configuration */
1475 musb->nr_endpoints = 1;
1476 musb->epmask = 1;
1477
1478 if (musb->dyn_fifo)
1479 status = ep_config_from_table(musb);
1480 else
1481 status = ep_config_from_hw(musb);
1482
1483 if (status < 0)
1484 return status;
1485
1486 /* finish init, and print endpoint config */
1487 for (i = 0; i < musb->nr_endpoints; i++) {
1488 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1489
1490 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1491 #ifdef CONFIG_USB_TUSB6010
1492 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1493 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1494 hw_ep->fifo_sync_va =
1495 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1496
1497 if (i == 0)
1498 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1499 else
1500 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1501 #endif
1502
1503 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1504 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1505 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1506 hw_ep->rx_reinit = 1;
1507 hw_ep->tx_reinit = 1;
1508 #endif
1509
1510 if (hw_ep->max_packet_sz_tx) {
1511 DBG(1,
1512 "%s: hw_ep %d%s, %smax %d\n",
1513 musb_driver_name, i,
1514 hw_ep->is_shared_fifo ? "shared" : "tx",
1515 hw_ep->tx_double_buffered
1516 ? "doublebuffer, " : "",
1517 hw_ep->max_packet_sz_tx);
1518 }
1519 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1520 DBG(1,
1521 "%s: hw_ep %d%s, %smax %d\n",
1522 musb_driver_name, i,
1523 "rx",
1524 hw_ep->rx_double_buffered
1525 ? "doublebuffer, " : "",
1526 hw_ep->max_packet_sz_rx);
1527 }
1528 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1529 DBG(1, "hw_ep %d not configured\n", i);
1530 }
1531
1532 return 0;
1533 }
1534
1535 /*-------------------------------------------------------------------------*/
1536
1537 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) || \
1538 defined(CONFIG_ARCH_OMAP4)
1539
1540 static irqreturn_t generic_interrupt(int irq, void *__hci)
1541 {
1542 unsigned long flags;
1543 irqreturn_t retval = IRQ_NONE;
1544 struct musb *musb = __hci;
1545
1546 spin_lock_irqsave(&musb->lock, flags);
1547
1548 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1549 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1550 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1551
1552 if (musb->int_usb || musb->int_tx || musb->int_rx)
1553 retval = musb_interrupt(musb);
1554
1555 spin_unlock_irqrestore(&musb->lock, flags);
1556
1557 return retval;
1558 }
1559
1560 #else
1561 #define generic_interrupt NULL
1562 #endif
1563
1564 /*
1565 * handle all the irqs defined by the HDRC core. for now we expect: other
1566 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1567 * will be assigned, and the irq will already have been acked.
1568 *
1569 * called in irq context with spinlock held, irqs blocked
1570 */
1571 irqreturn_t musb_interrupt(struct musb *musb)
1572 {
1573 irqreturn_t retval = IRQ_NONE;
1574 u8 devctl, power;
1575 int ep_num;
1576 u32 reg;
1577
1578 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1579 power = musb_readb(musb->mregs, MUSB_POWER);
1580
1581 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1582 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1583 musb->int_usb, musb->int_tx, musb->int_rx);
1584
1585 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1586 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1587 if (!musb->gadget_driver) {
1588 DBG(5, "No gadget driver loaded\n");
1589 return IRQ_HANDLED;
1590 }
1591 #endif
1592
1593 /* the core can interrupt us for multiple reasons; docs have
1594 * a generic interrupt flowchart to follow
1595 */
1596 if (musb->int_usb)
1597 retval |= musb_stage0_irq(musb, musb->int_usb,
1598 devctl, power);
1599
1600 /* "stage 1" is handling endpoint irqs */
1601
1602 /* handle endpoint 0 first */
1603 if (musb->int_tx & 1) {
1604 if (devctl & MUSB_DEVCTL_HM)
1605 retval |= musb_h_ep0_irq(musb);
1606 else
1607 retval |= musb_g_ep0_irq(musb);
1608 }
1609
1610 /* RX on endpoints 1-15 */
1611 reg = musb->int_rx >> 1;
1612 ep_num = 1;
1613 while (reg) {
1614 if (reg & 1) {
1615 /* musb_ep_select(musb->mregs, ep_num); */
1616 /* REVISIT just retval = ep->rx_irq(...) */
1617 retval = IRQ_HANDLED;
1618 if (devctl & MUSB_DEVCTL_HM) {
1619 if (is_host_capable())
1620 musb_host_rx(musb, ep_num);
1621 } else {
1622 if (is_peripheral_capable())
1623 musb_g_rx(musb, ep_num);
1624 }
1625 }
1626
1627 reg >>= 1;
1628 ep_num++;
1629 }
1630
1631 /* TX on endpoints 1-15 */
1632 reg = musb->int_tx >> 1;
1633 ep_num = 1;
1634 while (reg) {
1635 if (reg & 1) {
1636 /* musb_ep_select(musb->mregs, ep_num); */
1637 /* REVISIT just retval |= ep->tx_irq(...) */
1638 retval = IRQ_HANDLED;
1639 if (devctl & MUSB_DEVCTL_HM) {
1640 if (is_host_capable())
1641 musb_host_tx(musb, ep_num);
1642 } else {
1643 if (is_peripheral_capable())
1644 musb_g_tx(musb, ep_num);
1645 }
1646 }
1647 reg >>= 1;
1648 ep_num++;
1649 }
1650
1651 return retval;
1652 }
1653
1654
1655 #ifndef CONFIG_MUSB_PIO_ONLY
1656 static int __initdata use_dma = 1;
1657
1658 /* "modprobe ... use_dma=0" etc */
1659 module_param(use_dma, bool, 0);
1660 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1661
1662 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1663 {
1664 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1665
1666 /* called with controller lock already held */
1667
1668 if (!epnum) {
1669 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1670 if (!is_cppi_enabled()) {
1671 /* endpoint 0 */
1672 if (devctl & MUSB_DEVCTL_HM)
1673 musb_h_ep0_irq(musb);
1674 else
1675 musb_g_ep0_irq(musb);
1676 }
1677 #endif
1678 } else {
1679 /* endpoints 1..15 */
1680 if (transmit) {
1681 if (devctl & MUSB_DEVCTL_HM) {
1682 if (is_host_capable())
1683 musb_host_tx(musb, epnum);
1684 } else {
1685 if (is_peripheral_capable())
1686 musb_g_tx(musb, epnum);
1687 }
1688 } else {
1689 /* receive */
1690 if (devctl & MUSB_DEVCTL_HM) {
1691 if (is_host_capable())
1692 musb_host_rx(musb, epnum);
1693 } else {
1694 if (is_peripheral_capable())
1695 musb_g_rx(musb, epnum);
1696 }
1697 }
1698 }
1699 }
1700
1701 #else
1702 #define use_dma 0
1703 #endif
1704
1705 /*-------------------------------------------------------------------------*/
1706
1707 #ifdef CONFIG_SYSFS
1708
1709 static ssize_t
1710 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1711 {
1712 struct musb *musb = dev_to_musb(dev);
1713 unsigned long flags;
1714 int ret = -EINVAL;
1715
1716 spin_lock_irqsave(&musb->lock, flags);
1717 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1718 spin_unlock_irqrestore(&musb->lock, flags);
1719
1720 return ret;
1721 }
1722
1723 static ssize_t
1724 musb_mode_store(struct device *dev, struct device_attribute *attr,
1725 const char *buf, size_t n)
1726 {
1727 struct musb *musb = dev_to_musb(dev);
1728 unsigned long flags;
1729 int status;
1730
1731 spin_lock_irqsave(&musb->lock, flags);
1732 if (sysfs_streq(buf, "host"))
1733 status = musb_platform_set_mode(musb, MUSB_HOST);
1734 else if (sysfs_streq(buf, "peripheral"))
1735 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1736 else if (sysfs_streq(buf, "otg"))
1737 status = musb_platform_set_mode(musb, MUSB_OTG);
1738 else
1739 status = -EINVAL;
1740 spin_unlock_irqrestore(&musb->lock, flags);
1741
1742 return (status == 0) ? n : status;
1743 }
1744 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1745
1746 static ssize_t
1747 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1748 const char *buf, size_t n)
1749 {
1750 struct musb *musb = dev_to_musb(dev);
1751 unsigned long flags;
1752 unsigned long val;
1753
1754 if (sscanf(buf, "%lu", &val) < 1) {
1755 dev_err(dev, "Invalid VBUS timeout ms value\n");
1756 return -EINVAL;
1757 }
1758
1759 spin_lock_irqsave(&musb->lock, flags);
1760 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1761 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1762 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1763 musb->is_active = 0;
1764 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1765 spin_unlock_irqrestore(&musb->lock, flags);
1766
1767 return n;
1768 }
1769
1770 static ssize_t
1771 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1772 {
1773 struct musb *musb = dev_to_musb(dev);
1774 unsigned long flags;
1775 unsigned long val;
1776 int vbus;
1777
1778 spin_lock_irqsave(&musb->lock, flags);
1779 val = musb->a_wait_bcon;
1780 /* FIXME get_vbus_status() is normally #defined as false...
1781 * and is effectively TUSB-specific.
1782 */
1783 vbus = musb_platform_get_vbus_status(musb);
1784 spin_unlock_irqrestore(&musb->lock, flags);
1785
1786 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1787 vbus ? "on" : "off", val);
1788 }
1789 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1790
1791 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1792
1793 /* Gadget drivers can't know that a host is connected so they might want
1794 * to start SRP, but users can. This allows userspace to trigger SRP.
1795 */
1796 static ssize_t
1797 musb_srp_store(struct device *dev, struct device_attribute *attr,
1798 const char *buf, size_t n)
1799 {
1800 struct musb *musb = dev_to_musb(dev);
1801 unsigned short srp;
1802
1803 if (sscanf(buf, "%hu", &srp) != 1
1804 || (srp != 1)) {
1805 dev_err(dev, "SRP: Value must be 1\n");
1806 return -EINVAL;
1807 }
1808
1809 if (srp == 1)
1810 musb_g_wakeup(musb);
1811
1812 return n;
1813 }
1814 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1815
1816 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1817
1818 static struct attribute *musb_attributes[] = {
1819 &dev_attr_mode.attr,
1820 &dev_attr_vbus.attr,
1821 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1822 &dev_attr_srp.attr,
1823 #endif
1824 NULL
1825 };
1826
1827 static const struct attribute_group musb_attr_group = {
1828 .attrs = musb_attributes,
1829 };
1830
1831 #endif /* sysfs */
1832
1833 /* Only used to provide driver mode change events */
1834 static void musb_irq_work(struct work_struct *data)
1835 {
1836 struct musb *musb = container_of(data, struct musb, irq_work);
1837 static int old_state;
1838
1839 if (musb->xceiv->state != old_state) {
1840 old_state = musb->xceiv->state;
1841 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1842 }
1843 }
1844
1845 /* --------------------------------------------------------------------------
1846 * Init support
1847 */
1848
1849 static struct musb *__init
1850 allocate_instance(struct device *dev,
1851 struct musb_hdrc_config *config, void __iomem *mbase)
1852 {
1853 struct musb *musb;
1854 struct musb_hw_ep *ep;
1855 int epnum;
1856 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1857 struct usb_hcd *hcd;
1858
1859 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1860 if (!hcd)
1861 return NULL;
1862 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1863
1864 musb = hcd_to_musb(hcd);
1865 INIT_LIST_HEAD(&musb->control);
1866 INIT_LIST_HEAD(&musb->in_bulk);
1867 INIT_LIST_HEAD(&musb->out_bulk);
1868
1869 hcd->uses_new_polling = 1;
1870
1871 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1872 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1873 #else
1874 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1875 if (!musb)
1876 return NULL;
1877 dev_set_drvdata(dev, musb);
1878
1879 #endif
1880
1881 musb->mregs = mbase;
1882 musb->ctrl_base = mbase;
1883 musb->nIrq = -ENODEV;
1884 musb->config = config;
1885 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1886 for (epnum = 0, ep = musb->endpoints;
1887 epnum < musb->config->num_eps;
1888 epnum++, ep++) {
1889 ep->musb = musb;
1890 ep->epnum = epnum;
1891 }
1892
1893 musb->controller = dev;
1894 return musb;
1895 }
1896
1897 static void musb_free(struct musb *musb)
1898 {
1899 /* this has multiple entry modes. it handles fault cleanup after
1900 * probe(), where things may be partially set up, as well as rmmod
1901 * cleanup after everything's been de-activated.
1902 */
1903
1904 #ifdef CONFIG_SYSFS
1905 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1906 #endif
1907
1908 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1909 musb_gadget_cleanup(musb);
1910 #endif
1911
1912 if (musb->nIrq >= 0) {
1913 if (musb->irq_wake)
1914 disable_irq_wake(musb->nIrq);
1915 free_irq(musb->nIrq, musb);
1916 }
1917 if (is_dma_capable() && musb->dma_controller) {
1918 struct dma_controller *c = musb->dma_controller;
1919
1920 (void) c->stop(c);
1921 dma_controller_destroy(c);
1922 }
1923
1924 #ifdef CONFIG_USB_MUSB_OTG
1925 put_device(musb->xceiv->dev);
1926 #endif
1927
1928 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1929 usb_put_hcd(musb_to_hcd(musb));
1930 #else
1931 kfree(musb);
1932 #endif
1933 }
1934
1935 /*
1936 * Perform generic per-controller initialization.
1937 *
1938 * @pDevice: the controller (already clocked, etc)
1939 * @nIrq: irq
1940 * @mregs: virtual address of controller registers,
1941 * not yet corrected for platform-specific offsets
1942 */
1943 static int __init
1944 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1945 {
1946 int status;
1947 struct musb *musb;
1948 struct musb_hdrc_platform_data *plat = dev->platform_data;
1949
1950 /* The driver might handle more features than the board; OK.
1951 * Fail when the board needs a feature that's not enabled.
1952 */
1953 if (!plat) {
1954 dev_dbg(dev, "no platform_data?\n");
1955 status = -ENODEV;
1956 goto fail0;
1957 }
1958
1959 switch (plat->mode) {
1960 case MUSB_HOST:
1961 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1962 break;
1963 #else
1964 goto bad_config;
1965 #endif
1966 case MUSB_PERIPHERAL:
1967 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1968 break;
1969 #else
1970 goto bad_config;
1971 #endif
1972 case MUSB_OTG:
1973 #ifdef CONFIG_USB_MUSB_OTG
1974 break;
1975 #else
1976 bad_config:
1977 #endif
1978 default:
1979 dev_err(dev, "incompatible Kconfig role setting\n");
1980 status = -EINVAL;
1981 goto fail0;
1982 }
1983
1984 /* allocate */
1985 musb = allocate_instance(dev, plat->config, ctrl);
1986 if (!musb) {
1987 status = -ENOMEM;
1988 goto fail0;
1989 }
1990
1991 spin_lock_init(&musb->lock);
1992 musb->board_mode = plat->mode;
1993 musb->board_set_power = plat->set_power;
1994 musb->set_clock = plat->set_clock;
1995 musb->min_power = plat->min_power;
1996
1997 /* Clock usage is chip-specific ... functional clock (DaVinci,
1998 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1999 * code does is make sure a clock handle is available; platform
2000 * code manages it during start/stop and suspend/resume.
2001 */
2002 if (plat->clock) {
2003 musb->clock = clk_get(dev, plat->clock);
2004 if (IS_ERR(musb->clock)) {
2005 status = PTR_ERR(musb->clock);
2006 musb->clock = NULL;
2007 goto fail1;
2008 }
2009 }
2010
2011 /* The musb_platform_init() call:
2012 * - adjusts musb->mregs and musb->isr if needed,
2013 * - may initialize an integrated tranceiver
2014 * - initializes musb->xceiv, usually by otg_get_transceiver()
2015 * - activates clocks.
2016 * - stops powering VBUS
2017 * - assigns musb->board_set_vbus if host mode is enabled
2018 *
2019 * There are various transciever configurations. Blackfin,
2020 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2021 * external/discrete ones in various flavors (twl4030 family,
2022 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2023 */
2024 musb->isr = generic_interrupt;
2025 status = musb_platform_init(musb, plat->board_data);
2026 if (status < 0)
2027 goto fail2;
2028
2029 if (!musb->isr) {
2030 status = -ENODEV;
2031 goto fail3;
2032 }
2033
2034 if (!musb->xceiv->io_ops) {
2035 musb->xceiv->io_priv = musb->mregs;
2036 musb->xceiv->io_ops = &musb_ulpi_access;
2037 }
2038
2039 #ifndef CONFIG_MUSB_PIO_ONLY
2040 if (use_dma && dev->dma_mask) {
2041 struct dma_controller *c;
2042
2043 c = dma_controller_create(musb, musb->mregs);
2044 musb->dma_controller = c;
2045 if (c)
2046 (void) c->start(c);
2047 }
2048 #endif
2049 /* ideally this would be abstracted in platform setup */
2050 if (!is_dma_capable() || !musb->dma_controller)
2051 dev->dma_mask = NULL;
2052
2053 /* be sure interrupts are disabled before connecting ISR */
2054 musb_platform_disable(musb);
2055 musb_generic_disable(musb);
2056
2057 /* setup musb parts of the core (especially endpoints) */
2058 status = musb_core_init(plat->config->multipoint
2059 ? MUSB_CONTROLLER_MHDRC
2060 : MUSB_CONTROLLER_HDRC, musb);
2061 if (status < 0)
2062 goto fail3;
2063
2064 #ifdef CONFIG_USB_MUSB_OTG
2065 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2066 #endif
2067
2068 /* Init IRQ workqueue before request_irq */
2069 INIT_WORK(&musb->irq_work, musb_irq_work);
2070
2071 /* attach to the IRQ */
2072 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2073 dev_err(dev, "request_irq %d failed!\n", nIrq);
2074 status = -ENODEV;
2075 goto fail3;
2076 }
2077 musb->nIrq = nIrq;
2078 /* FIXME this handles wakeup irqs wrong */
2079 if (enable_irq_wake(nIrq) == 0) {
2080 musb->irq_wake = 1;
2081 device_init_wakeup(dev, 1);
2082 } else {
2083 musb->irq_wake = 0;
2084 }
2085
2086 /* host side needs more setup */
2087 if (is_host_enabled(musb)) {
2088 struct usb_hcd *hcd = musb_to_hcd(musb);
2089
2090 otg_set_host(musb->xceiv, &hcd->self);
2091
2092 if (is_otg_enabled(musb))
2093 hcd->self.otg_port = 1;
2094 musb->xceiv->host = &hcd->self;
2095 hcd->power_budget = 2 * (plat->power ? : 250);
2096
2097 /* program PHY to use external vBus if required */
2098 if (plat->extvbus) {
2099 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2100 busctl |= MUSB_ULPI_USE_EXTVBUS;
2101 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2102 }
2103 }
2104
2105 /* For the host-only role, we can activate right away.
2106 * (We expect the ID pin to be forcibly grounded!!)
2107 * Otherwise, wait till the gadget driver hooks up.
2108 */
2109 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2110 MUSB_HST_MODE(musb);
2111 musb->xceiv->default_a = 1;
2112 musb->xceiv->state = OTG_STATE_A_IDLE;
2113
2114 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2115
2116 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2117 "HOST", status,
2118 musb_readb(musb->mregs, MUSB_DEVCTL),
2119 (musb_readb(musb->mregs, MUSB_DEVCTL)
2120 & MUSB_DEVCTL_BDEVICE
2121 ? 'B' : 'A'));
2122
2123 } else /* peripheral is enabled */ {
2124 MUSB_DEV_MODE(musb);
2125 musb->xceiv->default_a = 0;
2126 musb->xceiv->state = OTG_STATE_B_IDLE;
2127
2128 status = musb_gadget_setup(musb);
2129
2130 DBG(1, "%s mode, status %d, dev%02x\n",
2131 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2132 status,
2133 musb_readb(musb->mregs, MUSB_DEVCTL));
2134
2135 }
2136 if (status < 0)
2137 goto fail3;
2138
2139 status = musb_init_debugfs(musb);
2140 if (status < 0)
2141 goto fail4;
2142
2143 #ifdef CONFIG_SYSFS
2144 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2145 if (status)
2146 goto fail5;
2147 #endif
2148
2149 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2150 ({char *s;
2151 switch (musb->board_mode) {
2152 case MUSB_HOST: s = "Host"; break;
2153 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2154 default: s = "OTG"; break;
2155 }; s; }),
2156 ctrl,
2157 (is_dma_capable() && musb->dma_controller)
2158 ? "DMA" : "PIO",
2159 musb->nIrq);
2160
2161 return 0;
2162
2163 fail5:
2164 musb_exit_debugfs(musb);
2165
2166 fail4:
2167 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2168 usb_remove_hcd(musb_to_hcd(musb));
2169 else
2170 musb_gadget_cleanup(musb);
2171
2172 fail3:
2173 if (musb->irq_wake)
2174 device_init_wakeup(dev, 0);
2175 musb_platform_exit(musb);
2176
2177 fail2:
2178 if (musb->clock)
2179 clk_put(musb->clock);
2180
2181 fail1:
2182 dev_err(musb->controller,
2183 "musb_init_controller failed with status %d\n", status);
2184
2185 musb_free(musb);
2186
2187 fail0:
2188
2189 return status;
2190
2191 }
2192
2193 /*-------------------------------------------------------------------------*/
2194
2195 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2196 * bridge to a platform device; this driver then suffices.
2197 */
2198
2199 #ifndef CONFIG_MUSB_PIO_ONLY
2200 static u64 *orig_dma_mask;
2201 #endif
2202
2203 static int __init musb_probe(struct platform_device *pdev)
2204 {
2205 struct device *dev = &pdev->dev;
2206 int irq = platform_get_irq(pdev, 0);
2207 int status;
2208 struct resource *iomem;
2209 void __iomem *base;
2210
2211 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2212 if (!iomem || irq == 0)
2213 return -ENODEV;
2214
2215 base = ioremap(iomem->start, resource_size(iomem));
2216 if (!base) {
2217 dev_err(dev, "ioremap failed\n");
2218 return -ENOMEM;
2219 }
2220
2221 #ifndef CONFIG_MUSB_PIO_ONLY
2222 /* clobbered by use_dma=n */
2223 orig_dma_mask = dev->dma_mask;
2224 #endif
2225 status = musb_init_controller(dev, irq, base);
2226 if (status < 0)
2227 iounmap(base);
2228
2229 return status;
2230 }
2231
2232 static int __exit musb_remove(struct platform_device *pdev)
2233 {
2234 struct musb *musb = dev_to_musb(&pdev->dev);
2235 void __iomem *ctrl_base = musb->ctrl_base;
2236
2237 /* this gets called on rmmod.
2238 * - Host mode: host may still be active
2239 * - Peripheral mode: peripheral is deactivated (or never-activated)
2240 * - OTG mode: both roles are deactivated (or never-activated)
2241 */
2242 musb_exit_debugfs(musb);
2243 musb_shutdown(pdev);
2244 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2245 if (musb->board_mode == MUSB_HOST)
2246 usb_remove_hcd(musb_to_hcd(musb));
2247 #endif
2248 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2249 musb_platform_exit(musb);
2250 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2251
2252 musb_free(musb);
2253 iounmap(ctrl_base);
2254 device_init_wakeup(&pdev->dev, 0);
2255 #ifndef CONFIG_MUSB_PIO_ONLY
2256 pdev->dev.dma_mask = orig_dma_mask;
2257 #endif
2258 return 0;
2259 }
2260
2261 #ifdef CONFIG_PM
2262
2263 static struct musb_context_registers musb_context;
2264
2265 void musb_save_context(struct musb *musb)
2266 {
2267 int i;
2268 void __iomem *musb_base = musb->mregs;
2269
2270 if (is_host_enabled(musb)) {
2271 musb_context.frame = musb_readw(musb_base, MUSB_FRAME);
2272 musb_context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2273 musb_context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2274 }
2275 musb_context.power = musb_readb(musb_base, MUSB_POWER);
2276 musb_context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2277 musb_context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2278 musb_context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2279 musb_context.index = musb_readb(musb_base, MUSB_INDEX);
2280 musb_context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2281
2282 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2283 musb_writeb(musb_base, MUSB_INDEX, i);
2284 musb_context.index_regs[i].txmaxp =
2285 musb_readw(musb_base, 0x10 + MUSB_TXMAXP);
2286 musb_context.index_regs[i].txcsr =
2287 musb_readw(musb_base, 0x10 + MUSB_TXCSR);
2288 musb_context.index_regs[i].rxmaxp =
2289 musb_readw(musb_base, 0x10 + MUSB_RXMAXP);
2290 musb_context.index_regs[i].rxcsr =
2291 musb_readw(musb_base, 0x10 + MUSB_RXCSR);
2292
2293 if (musb->dyn_fifo) {
2294 musb_context.index_regs[i].txfifoadd =
2295 musb_read_txfifoadd(musb_base);
2296 musb_context.index_regs[i].rxfifoadd =
2297 musb_read_rxfifoadd(musb_base);
2298 musb_context.index_regs[i].txfifosz =
2299 musb_read_txfifosz(musb_base);
2300 musb_context.index_regs[i].rxfifosz =
2301 musb_read_rxfifosz(musb_base);
2302 }
2303 if (is_host_enabled(musb)) {
2304 musb_context.index_regs[i].txtype =
2305 musb_readb(musb_base, 0x10 + MUSB_TXTYPE);
2306 musb_context.index_regs[i].txinterval =
2307 musb_readb(musb_base, 0x10 + MUSB_TXINTERVAL);
2308 musb_context.index_regs[i].rxtype =
2309 musb_readb(musb_base, 0x10 + MUSB_RXTYPE);
2310 musb_context.index_regs[i].rxinterval =
2311 musb_readb(musb_base, 0x10 + MUSB_RXINTERVAL);
2312
2313 musb_context.index_regs[i].txfunaddr =
2314 musb_read_txfunaddr(musb_base, i);
2315 musb_context.index_regs[i].txhubaddr =
2316 musb_read_txhubaddr(musb_base, i);
2317 musb_context.index_regs[i].txhubport =
2318 musb_read_txhubport(musb_base, i);
2319
2320 musb_context.index_regs[i].rxfunaddr =
2321 musb_read_rxfunaddr(musb_base, i);
2322 musb_context.index_regs[i].rxhubaddr =
2323 musb_read_rxhubaddr(musb_base, i);
2324 musb_context.index_regs[i].rxhubport =
2325 musb_read_rxhubport(musb_base, i);
2326 }
2327 }
2328
2329 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2330
2331 musb_platform_save_context(musb, &musb_context);
2332 }
2333
2334 void musb_restore_context(struct musb *musb)
2335 {
2336 int i;
2337 void __iomem *musb_base = musb->mregs;
2338 void __iomem *ep_target_regs;
2339
2340 musb_platform_restore_context(musb, &musb_context);
2341
2342 if (is_host_enabled(musb)) {
2343 musb_writew(musb_base, MUSB_FRAME, musb_context.frame);
2344 musb_writeb(musb_base, MUSB_TESTMODE, musb_context.testmode);
2345 musb_write_ulpi_buscontrol(musb->mregs, musb_context.busctl);
2346 }
2347 musb_writeb(musb_base, MUSB_POWER, musb_context.power);
2348 musb_writew(musb_base, MUSB_INTRTXE, musb_context.intrtxe);
2349 musb_writew(musb_base, MUSB_INTRRXE, musb_context.intrrxe);
2350 musb_writeb(musb_base, MUSB_INTRUSBE, musb_context.intrusbe);
2351 musb_writeb(musb_base, MUSB_DEVCTL, musb_context.devctl);
2352
2353 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2354 musb_writeb(musb_base, MUSB_INDEX, i);
2355 musb_writew(musb_base, 0x10 + MUSB_TXMAXP,
2356 musb_context.index_regs[i].txmaxp);
2357 musb_writew(musb_base, 0x10 + MUSB_TXCSR,
2358 musb_context.index_regs[i].txcsr);
2359 musb_writew(musb_base, 0x10 + MUSB_RXMAXP,
2360 musb_context.index_regs[i].rxmaxp);
2361 musb_writew(musb_base, 0x10 + MUSB_RXCSR,
2362 musb_context.index_regs[i].rxcsr);
2363
2364 if (musb->dyn_fifo) {
2365 musb_write_txfifosz(musb_base,
2366 musb_context.index_regs[i].txfifosz);
2367 musb_write_rxfifosz(musb_base,
2368 musb_context.index_regs[i].rxfifosz);
2369 musb_write_txfifoadd(musb_base,
2370 musb_context.index_regs[i].txfifoadd);
2371 musb_write_rxfifoadd(musb_base,
2372 musb_context.index_regs[i].rxfifoadd);
2373 }
2374
2375 if (is_host_enabled(musb)) {
2376 musb_writeb(musb_base, 0x10 + MUSB_TXTYPE,
2377 musb_context.index_regs[i].txtype);
2378 musb_writeb(musb_base, 0x10 + MUSB_TXINTERVAL,
2379 musb_context.index_regs[i].txinterval);
2380 musb_writeb(musb_base, 0x10 + MUSB_RXTYPE,
2381 musb_context.index_regs[i].rxtype);
2382 musb_writeb(musb_base, 0x10 + MUSB_RXINTERVAL,
2383
2384 musb_context.index_regs[i].rxinterval);
2385 musb_write_txfunaddr(musb_base, i,
2386 musb_context.index_regs[i].txfunaddr);
2387 musb_write_txhubaddr(musb_base, i,
2388 musb_context.index_regs[i].txhubaddr);
2389 musb_write_txhubport(musb_base, i,
2390 musb_context.index_regs[i].txhubport);
2391
2392 ep_target_regs =
2393 musb_read_target_reg_base(i, musb_base);
2394
2395 musb_write_rxfunaddr(ep_target_regs,
2396 musb_context.index_regs[i].rxfunaddr);
2397 musb_write_rxhubaddr(ep_target_regs,
2398 musb_context.index_regs[i].rxhubaddr);
2399 musb_write_rxhubport(ep_target_regs,
2400 musb_context.index_regs[i].rxhubport);
2401 }
2402 }
2403
2404 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2405 }
2406
2407 static int musb_suspend(struct device *dev)
2408 {
2409 struct platform_device *pdev = to_platform_device(dev);
2410 unsigned long flags;
2411 struct musb *musb = dev_to_musb(&pdev->dev);
2412
2413 if (!musb->clock)
2414 return 0;
2415
2416 spin_lock_irqsave(&musb->lock, flags);
2417
2418 if (is_peripheral_active(musb)) {
2419 /* FIXME force disconnect unless we know USB will wake
2420 * the system up quickly enough to respond ...
2421 */
2422 } else if (is_host_active(musb)) {
2423 /* we know all the children are suspended; sometimes
2424 * they will even be wakeup-enabled.
2425 */
2426 }
2427
2428 musb_save_context(musb);
2429
2430 if (musb->set_clock)
2431 musb->set_clock(musb->clock, 0);
2432 else
2433 clk_disable(musb->clock);
2434 spin_unlock_irqrestore(&musb->lock, flags);
2435 return 0;
2436 }
2437
2438 static int musb_resume_noirq(struct device *dev)
2439 {
2440 struct platform_device *pdev = to_platform_device(dev);
2441 struct musb *musb = dev_to_musb(&pdev->dev);
2442
2443 if (!musb->clock)
2444 return 0;
2445
2446 if (musb->set_clock)
2447 musb->set_clock(musb->clock, 1);
2448 else
2449 clk_enable(musb->clock);
2450
2451 musb_restore_context(musb);
2452
2453 /* for static cmos like DaVinci, register values were preserved
2454 * unless for some reason the whole soc powered down or the USB
2455 * module got reset through the PSC (vs just being disabled).
2456 */
2457 return 0;
2458 }
2459
2460 static const struct dev_pm_ops musb_dev_pm_ops = {
2461 .suspend = musb_suspend,
2462 .resume_noirq = musb_resume_noirq,
2463 };
2464
2465 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2466 #else
2467 #define MUSB_DEV_PM_OPS NULL
2468 #endif
2469
2470 static struct platform_driver musb_driver = {
2471 .driver = {
2472 .name = (char *)musb_driver_name,
2473 .bus = &platform_bus_type,
2474 .owner = THIS_MODULE,
2475 .pm = MUSB_DEV_PM_OPS,
2476 },
2477 .remove = __exit_p(musb_remove),
2478 .shutdown = musb_shutdown,
2479 };
2480
2481 /*-------------------------------------------------------------------------*/
2482
2483 static int __init musb_init(void)
2484 {
2485 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2486 if (usb_disabled())
2487 return 0;
2488 #endif
2489
2490 pr_info("%s: version " MUSB_VERSION ", "
2491 #ifdef CONFIG_MUSB_PIO_ONLY
2492 "pio"
2493 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2494 "cppi-dma"
2495 #elif defined(CONFIG_USB_INVENTRA_DMA)
2496 "musb-dma"
2497 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2498 "tusb-omap-dma"
2499 #else
2500 "?dma?"
2501 #endif
2502 ", "
2503 #ifdef CONFIG_USB_MUSB_OTG
2504 "otg (peripheral+host)"
2505 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2506 "peripheral"
2507 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2508 "host"
2509 #endif
2510 ", debug=%d\n",
2511 musb_driver_name, musb_debug);
2512 return platform_driver_probe(&musb_driver, musb_probe);
2513 }
2514
2515 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2516 * and before usb gadget and host-side drivers start to register
2517 */
2518 fs_initcall(musb_init);
2519
2520 static void __exit musb_cleanup(void)
2521 {
2522 platform_driver_unregister(&musb_driver);
2523 }
2524 module_exit(musb_cleanup);
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