kmemtrace: SLOB hooks.
[linux-2.6/kmemtrace.git] / drivers / spi / atmel_spi.c
blobe81d59d789108041fee33e62b22b82d14e34fef3
1 /*
2 * Driver for Atmel AT32 and AT91 SPI Controllers
4 * Copyright (C) 2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/spi/spi.h>
22 #include <asm/io.h>
23 #include <asm/arch/board.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/cpu.h>
27 #include "atmel_spi.h"
30 * The core SPI transfer engine just talks to a register bank to set up
31 * DMA transfers; transfer queue progress is driven by IRQs. The clock
32 * framework provides the base clock, subdivided for each spi_device.
34 * Newer controllers, marked with "new_1" flag, have:
35 * - CR.LASTXFER
36 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
37 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
38 * - SPI_CSRx.CSAAT
39 * - SPI_CSRx.SBCR allows faster clocking
41 struct atmel_spi {
42 spinlock_t lock;
44 void __iomem *regs;
45 int irq;
46 struct clk *clk;
47 struct platform_device *pdev;
48 unsigned new_1:1;
49 struct spi_device *stay;
51 u8 stopping;
52 struct list_head queue;
53 struct spi_transfer *current_transfer;
54 unsigned long current_remaining_bytes;
55 struct spi_transfer *next_transfer;
56 unsigned long next_remaining_bytes;
58 void *buffer;
59 dma_addr_t buffer_dma;
62 #define BUFFER_SIZE PAGE_SIZE
63 #define INVALID_DMA_ADDRESS 0xffffffff
66 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
67 * they assume that spi slave device state will not change on deselect, so
68 * that automagic deselection is OK. ("NPCSx rises if no data is to be
69 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
70 * controllers have CSAAT and friends.
72 * Since the CSAAT functionality is a bit weird on newer controllers as
73 * well, we use GPIO to control nCSx pins on all controllers, updating
74 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
75 * support active-high chipselects despite the controller's belief that
76 * only active-low devices/systems exists.
78 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
79 * right when driven with GPIO. ("Mode Fault does not allow more than one
80 * Master on Chip Select 0.") No workaround exists for that ... so for
81 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
82 * and (c) will trigger that first erratum in some cases.
85 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
87 unsigned gpio = (unsigned) spi->controller_data;
88 unsigned active = spi->mode & SPI_CS_HIGH;
89 u32 mr;
90 int i;
91 u32 csr;
92 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
94 /* Make sure clock polarity is correct */
95 for (i = 0; i < spi->master->num_chipselect; i++) {
96 csr = spi_readl(as, CSR0 + 4 * i);
97 if ((csr ^ cpol) & SPI_BIT(CPOL))
98 spi_writel(as, CSR0 + 4 * i, csr ^ SPI_BIT(CPOL));
101 mr = spi_readl(as, MR);
102 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
104 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
105 gpio, active ? " (high)" : "",
106 mr);
108 if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
109 gpio_set_value(gpio, active);
110 spi_writel(as, MR, mr);
113 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
115 unsigned gpio = (unsigned) spi->controller_data;
116 unsigned active = spi->mode & SPI_CS_HIGH;
117 u32 mr;
119 /* only deactivate *this* device; sometimes transfers to
120 * another device may be active when this routine is called.
122 mr = spi_readl(as, MR);
123 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
124 mr = SPI_BFINS(PCS, 0xf, mr);
125 spi_writel(as, MR, mr);
128 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
129 gpio, active ? " (low)" : "",
130 mr);
132 if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
133 gpio_set_value(gpio, !active);
136 static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
137 struct spi_transfer *xfer)
139 return msg->transfers.prev == &xfer->transfer_list;
142 static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
144 return xfer->delay_usecs == 0 && !xfer->cs_change;
147 static void atmel_spi_next_xfer_data(struct spi_master *master,
148 struct spi_transfer *xfer,
149 dma_addr_t *tx_dma,
150 dma_addr_t *rx_dma,
151 u32 *plen)
153 struct atmel_spi *as = spi_master_get_devdata(master);
154 u32 len = *plen;
156 /* use scratch buffer only when rx or tx data is unspecified */
157 if (xfer->rx_buf)
158 *rx_dma = xfer->rx_dma + xfer->len - len;
159 else {
160 *rx_dma = as->buffer_dma;
161 if (len > BUFFER_SIZE)
162 len = BUFFER_SIZE;
164 if (xfer->tx_buf)
165 *tx_dma = xfer->tx_dma + xfer->len - len;
166 else {
167 *tx_dma = as->buffer_dma;
168 if (len > BUFFER_SIZE)
169 len = BUFFER_SIZE;
170 memset(as->buffer, 0, len);
171 dma_sync_single_for_device(&as->pdev->dev,
172 as->buffer_dma, len, DMA_TO_DEVICE);
175 *plen = len;
179 * Submit next transfer for DMA.
180 * lock is held, spi irq is blocked
182 static void atmel_spi_next_xfer(struct spi_master *master,
183 struct spi_message *msg)
185 struct atmel_spi *as = spi_master_get_devdata(master);
186 struct spi_transfer *xfer;
187 u32 len, remaining, total;
188 dma_addr_t tx_dma, rx_dma;
190 if (!as->current_transfer)
191 xfer = list_entry(msg->transfers.next,
192 struct spi_transfer, transfer_list);
193 else if (!as->next_transfer)
194 xfer = list_entry(as->current_transfer->transfer_list.next,
195 struct spi_transfer, transfer_list);
196 else
197 xfer = NULL;
199 if (xfer) {
200 len = xfer->len;
201 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
202 remaining = xfer->len - len;
204 spi_writel(as, RPR, rx_dma);
205 spi_writel(as, TPR, tx_dma);
207 if (msg->spi->bits_per_word > 8)
208 len >>= 1;
209 spi_writel(as, RCR, len);
210 spi_writel(as, TCR, len);
212 dev_dbg(&msg->spi->dev,
213 " start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
214 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
215 xfer->rx_buf, xfer->rx_dma);
216 } else {
217 xfer = as->next_transfer;
218 remaining = as->next_remaining_bytes;
221 as->current_transfer = xfer;
222 as->current_remaining_bytes = remaining;
224 if (remaining > 0)
225 len = remaining;
226 else if (!atmel_spi_xfer_is_last(msg, xfer)
227 && atmel_spi_xfer_can_be_chained(xfer)) {
228 xfer = list_entry(xfer->transfer_list.next,
229 struct spi_transfer, transfer_list);
230 len = xfer->len;
231 } else
232 xfer = NULL;
234 as->next_transfer = xfer;
236 if (xfer) {
237 total = len;
238 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
239 as->next_remaining_bytes = total - len;
241 spi_writel(as, RNPR, rx_dma);
242 spi_writel(as, TNPR, tx_dma);
244 if (msg->spi->bits_per_word > 8)
245 len >>= 1;
246 spi_writel(as, RNCR, len);
247 spi_writel(as, TNCR, len);
249 dev_dbg(&msg->spi->dev,
250 " next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
251 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
252 xfer->rx_buf, xfer->rx_dma);
253 } else {
254 spi_writel(as, RNCR, 0);
255 spi_writel(as, TNCR, 0);
258 /* REVISIT: We're waiting for ENDRX before we start the next
259 * transfer because we need to handle some difficult timing
260 * issues otherwise. If we wait for ENDTX in one transfer and
261 * then starts waiting for ENDRX in the next, it's difficult
262 * to tell the difference between the ENDRX interrupt we're
263 * actually waiting for and the ENDRX interrupt of the
264 * previous transfer.
266 * It should be doable, though. Just not now...
268 spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
269 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
272 static void atmel_spi_next_message(struct spi_master *master)
274 struct atmel_spi *as = spi_master_get_devdata(master);
275 struct spi_message *msg;
276 struct spi_device *spi;
278 BUG_ON(as->current_transfer);
280 msg = list_entry(as->queue.next, struct spi_message, queue);
281 spi = msg->spi;
283 dev_dbg(master->dev.parent, "start message %p for %s\n",
284 msg, spi->dev.bus_id);
286 /* select chip if it's not still active */
287 if (as->stay) {
288 if (as->stay != spi) {
289 cs_deactivate(as, as->stay);
290 cs_activate(as, spi);
292 as->stay = NULL;
293 } else
294 cs_activate(as, spi);
296 atmel_spi_next_xfer(master, msg);
300 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
301 * - The buffer is either valid for CPU access, else NULL
302 * - If the buffer is valid, so is its DMA addresss
304 * This driver manages the dma addresss unless message->is_dma_mapped.
306 static int
307 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
309 struct device *dev = &as->pdev->dev;
311 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
312 if (xfer->tx_buf) {
313 xfer->tx_dma = dma_map_single(dev,
314 (void *) xfer->tx_buf, xfer->len,
315 DMA_TO_DEVICE);
316 if (dma_mapping_error(xfer->tx_dma))
317 return -ENOMEM;
319 if (xfer->rx_buf) {
320 xfer->rx_dma = dma_map_single(dev,
321 xfer->rx_buf, xfer->len,
322 DMA_FROM_DEVICE);
323 if (dma_mapping_error(xfer->rx_dma)) {
324 if (xfer->tx_buf)
325 dma_unmap_single(dev,
326 xfer->tx_dma, xfer->len,
327 DMA_TO_DEVICE);
328 return -ENOMEM;
331 return 0;
334 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
335 struct spi_transfer *xfer)
337 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
338 dma_unmap_single(master->dev.parent, xfer->tx_dma,
339 xfer->len, DMA_TO_DEVICE);
340 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
341 dma_unmap_single(master->dev.parent, xfer->rx_dma,
342 xfer->len, DMA_FROM_DEVICE);
345 static void
346 atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
347 struct spi_message *msg, int status, int stay)
349 if (!stay || status < 0)
350 cs_deactivate(as, msg->spi);
351 else
352 as->stay = msg->spi;
354 list_del(&msg->queue);
355 msg->status = status;
357 dev_dbg(master->dev.parent,
358 "xfer complete: %u bytes transferred\n",
359 msg->actual_length);
361 spin_unlock(&as->lock);
362 msg->complete(msg->context);
363 spin_lock(&as->lock);
365 as->current_transfer = NULL;
366 as->next_transfer = NULL;
368 /* continue if needed */
369 if (list_empty(&as->queue) || as->stopping)
370 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
371 else
372 atmel_spi_next_message(master);
375 static irqreturn_t
376 atmel_spi_interrupt(int irq, void *dev_id)
378 struct spi_master *master = dev_id;
379 struct atmel_spi *as = spi_master_get_devdata(master);
380 struct spi_message *msg;
381 struct spi_transfer *xfer;
382 u32 status, pending, imr;
383 int ret = IRQ_NONE;
385 spin_lock(&as->lock);
387 xfer = as->current_transfer;
388 msg = list_entry(as->queue.next, struct spi_message, queue);
390 imr = spi_readl(as, IMR);
391 status = spi_readl(as, SR);
392 pending = status & imr;
394 if (pending & SPI_BIT(OVRES)) {
395 int timeout;
397 ret = IRQ_HANDLED;
399 spi_writel(as, IDR, (SPI_BIT(ENDTX) | SPI_BIT(ENDRX)
400 | SPI_BIT(OVRES)));
403 * When we get an overrun, we disregard the current
404 * transfer. Data will not be copied back from any
405 * bounce buffer and msg->actual_len will not be
406 * updated with the last xfer.
408 * We will also not process any remaning transfers in
409 * the message.
411 * First, stop the transfer and unmap the DMA buffers.
413 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
414 if (!msg->is_dma_mapped)
415 atmel_spi_dma_unmap_xfer(master, xfer);
417 /* REVISIT: udelay in irq is unfriendly */
418 if (xfer->delay_usecs)
419 udelay(xfer->delay_usecs);
421 dev_warn(master->dev.parent, "fifo overrun (%u/%u remaining)\n",
422 spi_readl(as, TCR), spi_readl(as, RCR));
425 * Clean up DMA registers and make sure the data
426 * registers are empty.
428 spi_writel(as, RNCR, 0);
429 spi_writel(as, TNCR, 0);
430 spi_writel(as, RCR, 0);
431 spi_writel(as, TCR, 0);
432 for (timeout = 1000; timeout; timeout--)
433 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
434 break;
435 if (!timeout)
436 dev_warn(master->dev.parent,
437 "timeout waiting for TXEMPTY");
438 while (spi_readl(as, SR) & SPI_BIT(RDRF))
439 spi_readl(as, RDR);
441 /* Clear any overrun happening while cleaning up */
442 spi_readl(as, SR);
444 atmel_spi_msg_done(master, as, msg, -EIO, 0);
445 } else if (pending & SPI_BIT(ENDRX)) {
446 ret = IRQ_HANDLED;
448 spi_writel(as, IDR, pending);
450 if (as->current_remaining_bytes == 0) {
451 msg->actual_length += xfer->len;
453 if (!msg->is_dma_mapped)
454 atmel_spi_dma_unmap_xfer(master, xfer);
456 /* REVISIT: udelay in irq is unfriendly */
457 if (xfer->delay_usecs)
458 udelay(xfer->delay_usecs);
460 if (atmel_spi_xfer_is_last(msg, xfer)) {
461 /* report completed message */
462 atmel_spi_msg_done(master, as, msg, 0,
463 xfer->cs_change);
464 } else {
465 if (xfer->cs_change) {
466 cs_deactivate(as, msg->spi);
467 udelay(1);
468 cs_activate(as, msg->spi);
472 * Not done yet. Submit the next transfer.
474 * FIXME handle protocol options for xfer
476 atmel_spi_next_xfer(master, msg);
478 } else {
480 * Keep going, we still have data to send in
481 * the current transfer.
483 atmel_spi_next_xfer(master, msg);
487 spin_unlock(&as->lock);
489 return ret;
492 /* the spi->mode bits understood by this driver: */
493 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
495 static int atmel_spi_setup(struct spi_device *spi)
497 struct atmel_spi *as;
498 u32 scbr, csr;
499 unsigned int bits = spi->bits_per_word;
500 unsigned long bus_hz;
501 unsigned int npcs_pin;
502 int ret;
504 as = spi_master_get_devdata(spi->master);
506 if (as->stopping)
507 return -ESHUTDOWN;
509 if (spi->chip_select > spi->master->num_chipselect) {
510 dev_dbg(&spi->dev,
511 "setup: invalid chipselect %u (%u defined)\n",
512 spi->chip_select, spi->master->num_chipselect);
513 return -EINVAL;
516 if (bits == 0)
517 bits = 8;
518 if (bits < 8 || bits > 16) {
519 dev_dbg(&spi->dev,
520 "setup: invalid bits_per_word %u (8 to 16)\n",
521 bits);
522 return -EINVAL;
525 if (spi->mode & ~MODEBITS) {
526 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
527 spi->mode & ~MODEBITS);
528 return -EINVAL;
531 /* see notes above re chipselect */
532 if (cpu_is_at91rm9200()
533 && spi->chip_select == 0
534 && (spi->mode & SPI_CS_HIGH)) {
535 dev_dbg(&spi->dev, "setup: can't be active-high\n");
536 return -EINVAL;
540 * Pre-new_1 chips start out at half the peripheral
541 * bus speed.
543 bus_hz = clk_get_rate(as->clk);
544 if (!as->new_1)
545 bus_hz /= 2;
547 if (spi->max_speed_hz) {
549 * Calculate the lowest divider that satisfies the
550 * constraint, assuming div32/fdiv/mbz == 0.
552 scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz);
555 * If the resulting divider doesn't fit into the
556 * register bitfield, we can't satisfy the constraint.
558 if (scbr >= (1 << SPI_SCBR_SIZE)) {
559 dev_dbg(&spi->dev,
560 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
561 spi->max_speed_hz, scbr, bus_hz/255);
562 return -EINVAL;
564 } else
565 /* speed zero means "as slow as possible" */
566 scbr = 0xff;
568 csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
569 if (spi->mode & SPI_CPOL)
570 csr |= SPI_BIT(CPOL);
571 if (!(spi->mode & SPI_CPHA))
572 csr |= SPI_BIT(NCPHA);
574 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
576 * DLYBCT would add delays between words, slowing down transfers.
577 * It could potentially be useful to cope with DMA bottlenecks, but
578 * in those cases it's probably best to just use a lower bitrate.
580 csr |= SPI_BF(DLYBS, 0);
581 csr |= SPI_BF(DLYBCT, 0);
583 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
584 npcs_pin = (unsigned int)spi->controller_data;
585 if (!spi->controller_state) {
586 ret = gpio_request(npcs_pin, spi->dev.bus_id);
587 if (ret)
588 return ret;
589 spi->controller_state = (void *)npcs_pin;
590 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
591 } else {
592 unsigned long flags;
594 spin_lock_irqsave(&as->lock, flags);
595 if (as->stay == spi)
596 as->stay = NULL;
597 cs_deactivate(as, spi);
598 spin_unlock_irqrestore(&as->lock, flags);
601 dev_dbg(&spi->dev,
602 "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
603 bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
605 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
607 return 0;
610 static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
612 struct atmel_spi *as;
613 struct spi_transfer *xfer;
614 unsigned long flags;
615 struct device *controller = spi->master->dev.parent;
617 as = spi_master_get_devdata(spi->master);
619 dev_dbg(controller, "new message %p submitted for %s\n",
620 msg, spi->dev.bus_id);
622 if (unlikely(list_empty(&msg->transfers)
623 || !spi->max_speed_hz))
624 return -EINVAL;
626 if (as->stopping)
627 return -ESHUTDOWN;
629 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
630 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
631 dev_dbg(&spi->dev, "missing rx or tx buf\n");
632 return -EINVAL;
635 /* FIXME implement these protocol options!! */
636 if (xfer->bits_per_word || xfer->speed_hz) {
637 dev_dbg(&spi->dev, "no protocol options yet\n");
638 return -ENOPROTOOPT;
642 * DMA map early, for performance (empties dcache ASAP) and
643 * better fault reporting. This is a DMA-only driver.
645 * NOTE that if dma_unmap_single() ever starts to do work on
646 * platforms supported by this driver, we would need to clean
647 * up mappings for previously-mapped transfers.
649 if (!msg->is_dma_mapped) {
650 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
651 return -ENOMEM;
655 #ifdef VERBOSE
656 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
657 dev_dbg(controller,
658 " xfer %p: len %u tx %p/%08x rx %p/%08x\n",
659 xfer, xfer->len,
660 xfer->tx_buf, xfer->tx_dma,
661 xfer->rx_buf, xfer->rx_dma);
663 #endif
665 msg->status = -EINPROGRESS;
666 msg->actual_length = 0;
668 spin_lock_irqsave(&as->lock, flags);
669 list_add_tail(&msg->queue, &as->queue);
670 if (!as->current_transfer)
671 atmel_spi_next_message(spi->master);
672 spin_unlock_irqrestore(&as->lock, flags);
674 return 0;
677 static void atmel_spi_cleanup(struct spi_device *spi)
679 struct atmel_spi *as = spi_master_get_devdata(spi->master);
680 unsigned gpio = (unsigned) spi->controller_data;
681 unsigned long flags;
683 if (!spi->controller_state)
684 return;
686 spin_lock_irqsave(&as->lock, flags);
687 if (as->stay == spi) {
688 as->stay = NULL;
689 cs_deactivate(as, spi);
691 spin_unlock_irqrestore(&as->lock, flags);
693 gpio_free(gpio);
696 /*-------------------------------------------------------------------------*/
698 static int __init atmel_spi_probe(struct platform_device *pdev)
700 struct resource *regs;
701 int irq;
702 struct clk *clk;
703 int ret;
704 struct spi_master *master;
705 struct atmel_spi *as;
707 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
708 if (!regs)
709 return -ENXIO;
711 irq = platform_get_irq(pdev, 0);
712 if (irq < 0)
713 return irq;
715 clk = clk_get(&pdev->dev, "spi_clk");
716 if (IS_ERR(clk))
717 return PTR_ERR(clk);
719 /* setup spi core then atmel-specific driver state */
720 ret = -ENOMEM;
721 master = spi_alloc_master(&pdev->dev, sizeof *as);
722 if (!master)
723 goto out_free;
725 master->bus_num = pdev->id;
726 master->num_chipselect = 4;
727 master->setup = atmel_spi_setup;
728 master->transfer = atmel_spi_transfer;
729 master->cleanup = atmel_spi_cleanup;
730 platform_set_drvdata(pdev, master);
732 as = spi_master_get_devdata(master);
735 * Scratch buffer is used for throwaway rx and tx data.
736 * It's coherent to minimize dcache pollution.
738 as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
739 &as->buffer_dma, GFP_KERNEL);
740 if (!as->buffer)
741 goto out_free;
743 spin_lock_init(&as->lock);
744 INIT_LIST_HEAD(&as->queue);
745 as->pdev = pdev;
746 as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
747 if (!as->regs)
748 goto out_free_buffer;
749 as->irq = irq;
750 as->clk = clk;
751 if (!cpu_is_at91rm9200())
752 as->new_1 = 1;
754 ret = request_irq(irq, atmel_spi_interrupt, 0,
755 pdev->dev.bus_id, master);
756 if (ret)
757 goto out_unmap_regs;
759 /* Initialize the hardware */
760 clk_enable(clk);
761 spi_writel(as, CR, SPI_BIT(SWRST));
762 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
763 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
764 spi_writel(as, CR, SPI_BIT(SPIEN));
766 /* go! */
767 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
768 (unsigned long)regs->start, irq);
770 ret = spi_register_master(master);
771 if (ret)
772 goto out_reset_hw;
774 return 0;
776 out_reset_hw:
777 spi_writel(as, CR, SPI_BIT(SWRST));
778 clk_disable(clk);
779 free_irq(irq, master);
780 out_unmap_regs:
781 iounmap(as->regs);
782 out_free_buffer:
783 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
784 as->buffer_dma);
785 out_free:
786 clk_put(clk);
787 spi_master_put(master);
788 return ret;
791 static int __exit atmel_spi_remove(struct platform_device *pdev)
793 struct spi_master *master = platform_get_drvdata(pdev);
794 struct atmel_spi *as = spi_master_get_devdata(master);
795 struct spi_message *msg;
797 /* reset the hardware and block queue progress */
798 spin_lock_irq(&as->lock);
799 as->stopping = 1;
800 spi_writel(as, CR, SPI_BIT(SWRST));
801 spi_readl(as, SR);
802 spin_unlock_irq(&as->lock);
804 /* Terminate remaining queued transfers */
805 list_for_each_entry(msg, &as->queue, queue) {
806 /* REVISIT unmapping the dma is a NOP on ARM and AVR32
807 * but we shouldn't depend on that...
809 msg->status = -ESHUTDOWN;
810 msg->complete(msg->context);
813 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
814 as->buffer_dma);
816 clk_disable(as->clk);
817 clk_put(as->clk);
818 free_irq(as->irq, master);
819 iounmap(as->regs);
821 spi_unregister_master(master);
823 return 0;
826 #ifdef CONFIG_PM
828 static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
830 struct spi_master *master = platform_get_drvdata(pdev);
831 struct atmel_spi *as = spi_master_get_devdata(master);
833 clk_disable(as->clk);
834 return 0;
837 static int atmel_spi_resume(struct platform_device *pdev)
839 struct spi_master *master = platform_get_drvdata(pdev);
840 struct atmel_spi *as = spi_master_get_devdata(master);
842 clk_enable(as->clk);
843 return 0;
846 #else
847 #define atmel_spi_suspend NULL
848 #define atmel_spi_resume NULL
849 #endif
852 static struct platform_driver atmel_spi_driver = {
853 .driver = {
854 .name = "atmel_spi",
855 .owner = THIS_MODULE,
857 .suspend = atmel_spi_suspend,
858 .resume = atmel_spi_resume,
859 .remove = __exit_p(atmel_spi_remove),
862 static int __init atmel_spi_init(void)
864 return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
866 module_init(atmel_spi_init);
868 static void __exit atmel_spi_exit(void)
870 platform_driver_unregister(&atmel_spi_driver);
872 module_exit(atmel_spi_exit);
874 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
875 MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
876 MODULE_LICENSE("GPL");
877 MODULE_ALIAS("platform:atmel_spi");