2 * This control block defines the PACA which defines the processor
3 * specific data for each logical processor on the system.
4 * There are some pointers defined that are utilized by PLIC.
6 * C 2001 PPC 64 Team, IBM Corp
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
13 #ifndef _ASM_POWERPC_PACA_H
14 #define _ASM_POWERPC_PACA_H
17 #include <asm/types.h>
18 #include <asm/lppaca.h>
21 register struct paca_struct
*local_paca
asm("r13");
23 #if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
24 extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
26 * Add standard checks that preemption cannot occur when using get_paca():
27 * otherwise the paca_struct it points to may be the wrong one just after.
29 #define get_paca() ((void) debug_smp_processor_id(), local_paca)
31 #define get_paca() local_paca
34 #define get_lppaca() (get_paca()->lppaca_ptr)
35 #define get_slb_shadow() (get_paca()->slb_shadow_ptr)
40 * Defines the layout of the paca.
42 * This structure is not directly accessed by firmware or the service
46 #ifdef CONFIG_PPC_BOOK3S
48 * Because hw_cpu_id, unlike other paca fields, is accessed
49 * routinely from other CPUs (from the IRQ code), we stick to
50 * read-only (after boot) fields in the first cacheline to
51 * avoid cacheline bouncing.
54 struct lppaca
*lppaca_ptr
; /* Pointer to LpPaca for PLIC */
55 #endif /* CONFIG_PPC_BOOK3S */
57 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
58 * load lock_token and paca_index with a single lwz
59 * instruction. They must travel together and be properly
62 u16 lock_token
; /* Constant 0x8000, used in locks */
63 u16 paca_index
; /* Logical processor number */
65 u64 kernel_toc
; /* Kernel TOC address */
66 u64 kernelbase
; /* Base address of kernel */
67 u64 kernel_msr
; /* MSR while running in kernel */
68 #ifdef CONFIG_PPC_STD_MMU_64
69 u64 stab_real
; /* Absolute address of segment table */
70 u64 stab_addr
; /* Virtual address of segment table */
71 #endif /* CONFIG_PPC_STD_MMU_64 */
72 void *emergency_sp
; /* pointer to emergency stack */
73 u64 data_offset
; /* per cpu data offset */
74 s16 hw_cpu_id
; /* Physical processor number */
75 u8 cpu_start
; /* At startup, processor spins until */
76 /* this becomes non-zero. */
77 #ifdef CONFIG_PPC_STD_MMU_64
78 struct slb_shadow
*slb_shadow_ptr
;
81 * Now, starting in cacheline 2, the exception save areas
83 /* used for most interrupts/exceptions */
84 u64 exgen
[10] __attribute__((aligned(0x80)));
85 u64 exmc
[10]; /* used for machine checks */
86 u64 exslb
[10]; /* used for SLB/segment table misses
87 * on the linear mapping */
88 /* SLB related definitions */
91 u16 slb_cache
[SLB_CACHE_ENTRIES
];
92 #endif /* CONFIG_PPC_STD_MMU_64 */
97 * then miscellaneous read-write fields
99 struct task_struct
*__current
; /* Pointer to current */
100 u64 kstack
; /* Saved Kernel stack addr */
101 u64 stab_rr
; /* stab/slb round-robin counter */
102 u64 saved_r1
; /* r1 save for RTAS calls */
103 u64 saved_msr
; /* MSR saved here by enter_rtas */
104 u16 trap_save
; /* Used when bad stack is encountered */
105 u8 soft_enabled
; /* irq soft-enable flag */
106 u8 hard_enabled
; /* set if irqs are enabled in MSR */
107 u8 io_sync
; /* writel() needs spin_unlock sync */
108 u8 perf_counter_pending
; /* PM interrupt while soft-disabled */
110 /* Stuff for accurate time accounting */
111 u64 user_time
; /* accumulated usermode TB ticks */
112 u64 system_time
; /* accumulated system TB ticks */
113 u64 startpurr
; /* PURR/TB value snapshot */
114 u64 startspurr
; /* SPURR value snapshot */
117 extern struct paca_struct paca
[];
118 extern void initialise_pacas(void);
120 #endif /* __KERNEL__ */
121 #endif /* _ASM_POWERPC_PACA_H */