arch/powerpc/platforms/85xx/xes_mpc85xx.c

   1 /*
   2  * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
   3  *
   4  * X-ES board-specific functionality
   5  *
   6  * Based on mpc85xx_ds code from Freescale Semiconductor, Inc.
   7  *
   8  * Author: Nate Case <ncase@xes-inc.com>
   9  *
  10  * This is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/stddef.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/kdev_t.h>
  19 #include <linux/delay.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/of_platform.h>
  23
  24 #include <asm/system.h>
  25 #include <asm/time.h>
  26 #include <asm/machdep.h>
  27 #include <asm/pci-bridge.h>
  28 #include <mm/mmu_decl.h>
  29 #include <asm/prom.h>
  30 #include <asm/udbg.h>
  31 #include <asm/mpic.h>
  32
  33 #include <sysdev/fsl_soc.h>
  34 #include <sysdev/fsl_pci.h>
  35 #include <linux/of_platform.h>
  36
  37 /* A few bit definitions needed for fixups on some boards */
  38 #define MPC85xx_L2CTL_L2E               0x80000000 /* L2 enable */
  39 #define MPC85xx_L2CTL_L2I               0x40000000 /* L2 flash invalidate */
  40 #define MPC85xx_L2CTL_L2SIZ_MASK        0x30000000 /* L2 SRAM size (R/O) */
  41
  42 void __init xes_mpc85xx_pic_init(void)
  43 {
  44         struct mpic *mpic;
  45         struct resource r;
  46         struct device_node *np;
  47
  48         np = of_find_node_by_type(NULL, "open-pic");
  49         if (np == NULL) {
  50                 printk(KERN_ERR "Could not find open-pic node\n");
  51                 return;
  52         }
  53
  54         if (of_address_to_resource(np, 0, &r)) {
  55                 printk(KERN_ERR "Failed to map mpic register space\n");
  56                 of_node_put(np);
  57                 return;
  58         }
  59
  60         mpic = mpic_alloc(np, r.start,
  61                           MPIC_PRIMARY | MPIC_WANTS_RESET |
  62                           MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
  63                         0, 256, " OpenPIC  ");
  64         BUG_ON(mpic == NULL);
  65         of_node_put(np);
  66
  67         mpic_init(mpic);
  68 }
  69
  70 static void xes_mpc85xx_configure_l2(void __iomem *l2_base)
  71 {
  72         volatile uint32_t ctl, tmp;
  73
  74         asm volatile("msync; isync");
  75         tmp = in_be32(l2_base);
  76
  77         /*
  78          * xMon may have enabled part of L2 as SRAM, so we need to set it
  79          * up for all cache mode just to be safe.
  80          */
  81         printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n");
  82
  83         ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I;
  84         if (machine_is_compatible("MPC8540") ||
  85             machine_is_compatible("MPC8560"))
  86                 /*
  87                  * Assume L2 SRAM is used fully for cache, so set
  88                  * L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3).
  89                  */
  90                 ctl |= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2;
  91
  92         asm volatile("msync; isync");
  93         out_be32(l2_base, ctl);
  94         asm volatile("msync; isync");
  95 }
  96
  97 static void xes_mpc85xx_fixups(void)
  98 {
  99         struct device_node *np;
 100         int err;
 101
 102         /*
 103          * Legacy xMon firmware on some X-ES boards does not enable L2
 104          * as cache.  We must ensure that they get enabled here.
 105          */
 106         for_each_node_by_name(np, "l2-cache-controller") {
 107                 struct resource r[2];
 108                 void __iomem *l2_base;
 109
 110                 /* Only MPC8548, MPC8540, and MPC8560 boards are affected */
 111                 if (!of_device_is_compatible(np,
 112                                     "fsl,mpc8548-l2-cache-controller") &&
 113                     !of_device_is_compatible(np,
 114                                     "fsl,mpc8540-l2-cache-controller") &&
 115                     !of_device_is_compatible(np,
 116                                     "fsl,mpc8560-l2-cache-controller"))
 117                         continue;
 118
 119                 err = of_address_to_resource(np, 0, &r[0]);
 120                 if (err) {
 121                         printk(KERN_WARNING "xes_mpc85xx: Could not get "
 122                                "resource for device tree node '%s'",
 123                                np->full_name);
 124                         continue;
 125                 }
 126
 127                 l2_base = ioremap(r[0].start, r[0].end - r[0].start + 1);
 128
 129                 xes_mpc85xx_configure_l2(l2_base);
 130         }
 131 }
 132
 133 #ifdef CONFIG_PCI
 134 static int primary_phb_addr;
 135 #endif
 136
 137 /*
 138  * Setup the architecture
 139  */
 140 #ifdef CONFIG_SMP
 141 extern void __init mpc85xx_smp_init(void);
 142 #endif
 143 static void __init xes_mpc85xx_setup_arch(void)
 144 {
 145 #ifdef CONFIG_PCI
 146         struct device_node *np;
 147 #endif
 148         struct device_node *root;
 149         const char *model = "Unknown";
 150
 151         root = of_find_node_by_path("/");
 152         if (root == NULL)
 153                 return;
 154
 155         model = of_get_property(root, "model", NULL);
 156
 157         printk(KERN_INFO "X-ES MPC85xx-based single-board computer: %s\n",
 158                model + strlen("xes,"));
 159
 160         xes_mpc85xx_fixups();
 161
 162 #ifdef CONFIG_PCI
 163         for_each_node_by_type(np, "pci") {
 164                 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
 165                     of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
 166                         struct resource rsrc;
 167                         of_address_to_resource(np, 0, &rsrc);
 168                         if ((rsrc.start & 0xfffff) == primary_phb_addr)
 169                                 fsl_add_bridge(np, 1);
 170                         else
 171                                 fsl_add_bridge(np, 0);
 172                 }
 173         }
 174 #endif
 175
 176 #ifdef CONFIG_SMP
 177         mpc85xx_smp_init();
 178 #endif
 179 }
 180
 181 static struct of_device_id __initdata xes_mpc85xx_ids[] = {
 182         { .type = "soc", },
 183         { .compatible = "soc", },
 184         { .compatible = "simple-bus", },
 185         { .compatible = "gianfar", },
 186         {},
 187 };
 188
 189 static int __init xes_mpc85xx_publish_devices(void)
 190 {
 191         return of_platform_bus_probe(NULL, xes_mpc85xx_ids, NULL);
 192 }
 193 machine_device_initcall(xes_mpc8572, xes_mpc85xx_publish_devices);
 194 machine_device_initcall(xes_mpc8548, xes_mpc85xx_publish_devices);
 195 machine_device_initcall(xes_mpc8540, xes_mpc85xx_publish_devices);
 196
 197 /*
 198  * Called very early, device-tree isn't unflattened
 199  */
 200 static int __init xes_mpc8572_probe(void)
 201 {
 202         unsigned long root = of_get_flat_dt_root();
 203
 204         if (of_flat_dt_is_compatible(root, "xes,MPC8572")) {
 205 #ifdef CONFIG_PCI
 206                 primary_phb_addr = 0x8000;
 207 #endif
 208                 return 1;
 209         } else {
 210                 return 0;
 211         }
 212 }
 213
 214 static int __init xes_mpc8548_probe(void)
 215 {
 216         unsigned long root = of_get_flat_dt_root();
 217
 218         if (of_flat_dt_is_compatible(root, "xes,MPC8548")) {
 219 #ifdef CONFIG_PCI
 220                 primary_phb_addr = 0xb000;
 221 #endif
 222                 return 1;
 223         } else {
 224                 return 0;
 225         }
 226 }
 227
 228 static int __init xes_mpc8540_probe(void)
 229 {
 230         unsigned long root = of_get_flat_dt_root();
 231
 232         if (of_flat_dt_is_compatible(root, "xes,MPC8540")) {
 233 #ifdef CONFIG_PCI
 234                 primary_phb_addr = 0xb000;
 235 #endif
 236                 return 1;
 237         } else {
 238                 return 0;
 239         }
 240 }
 241
 242 define_machine(xes_mpc8572) {
 243         .name                   = "X-ES MPC8572",
 244         .probe                  = xes_mpc8572_probe,
 245         .setup_arch             = xes_mpc85xx_setup_arch,
 246         .init_IRQ               = xes_mpc85xx_pic_init,
 247 #ifdef CONFIG_PCI
 248         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 249 #endif
 250         .get_irq                = mpic_get_irq,
 251         .restart                = fsl_rstcr_restart,
 252         .calibrate_decr         = generic_calibrate_decr,
 253         .progress               = udbg_progress,
 254 };
 255
 256 define_machine(xes_mpc8548) {
 257         .name                   = "X-ES MPC8548",
 258         .probe                  = xes_mpc8548_probe,
 259         .setup_arch             = xes_mpc85xx_setup_arch,
 260         .init_IRQ               = xes_mpc85xx_pic_init,
 261 #ifdef CONFIG_PCI
 262         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 263 #endif
 264         .get_irq                = mpic_get_irq,
 265         .restart                = fsl_rstcr_restart,
 266         .calibrate_decr         = generic_calibrate_decr,
 267         .progress               = udbg_progress,
 268 };
 269
 270 define_machine(xes_mpc8540) {
 271         .name                   = "X-ES MPC8540",
 272         .probe                  = xes_mpc8540_probe,
 273         .setup_arch             = xes_mpc85xx_setup_arch,
 274         .init_IRQ               = xes_mpc85xx_pic_init,
 275 #ifdef CONFIG_PCI
 276         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 277 #endif
 278         .get_irq                = mpic_get_irq,
 279         .restart                = fsl_rstcr_restart,
 280         .calibrate_decr         = generic_calibrate_decr,
 281         .progress               = udbg_progress,
 282 };