eeepc-laptop: Register as a pci-hotplug device
[linux-2.6/linux-acpi-2.6.git] / arch / x86 / pci / amd_bus.c
blobf893d6a6e803e266f3d36030f8744fecda130bf9
1 #include <linux/init.h>
2 #include <linux/pci.h>
3 #include <linux/topology.h>
4 #include <linux/cpu.h>
5 #include <asm/pci_x86.h>
7 #ifdef CONFIG_X86_64
8 #include <asm/pci-direct.h>
9 #include <asm/mpspec.h>
10 #include <linux/cpumask.h>
11 #endif
14 * This discovers the pcibus <-> node mapping on AMD K8.
15 * also get peer root bus resource for io,mmio
18 #ifdef CONFIG_NUMA
20 #define BUS_NR 256
22 #ifdef CONFIG_X86_64
24 static int mp_bus_to_node[BUS_NR];
26 void set_mp_bus_to_node(int busnum, int node)
28 if (busnum >= 0 && busnum < BUS_NR)
29 mp_bus_to_node[busnum] = node;
32 int get_mp_bus_to_node(int busnum)
34 int node = -1;
36 if (busnum < 0 || busnum > (BUS_NR - 1))
37 return node;
39 node = mp_bus_to_node[busnum];
42 * let numa_node_id to decide it later in dma_alloc_pages
43 * if there is no ram on that node
45 if (node != -1 && !node_online(node))
46 node = -1;
48 return node;
51 #else /* CONFIG_X86_32 */
53 static unsigned char mp_bus_to_node[BUS_NR];
55 void set_mp_bus_to_node(int busnum, int node)
57 if (busnum >= 0 && busnum < BUS_NR)
58 mp_bus_to_node[busnum] = (unsigned char) node;
61 int get_mp_bus_to_node(int busnum)
63 int node;
65 if (busnum < 0 || busnum > (BUS_NR - 1))
66 return 0;
67 node = mp_bus_to_node[busnum];
68 return node;
71 #endif /* CONFIG_X86_32 */
73 #endif /* CONFIG_NUMA */
75 #ifdef CONFIG_X86_64
78 * sub bus (transparent) will use entres from 3 to store extra from root,
79 * so need to make sure have enought slot there, increase PCI_BUS_NUM_RESOURCES?
81 #define RES_NUM 16
82 struct pci_root_info {
83 char name[12];
84 unsigned int res_num;
85 struct resource res[RES_NUM];
86 int bus_min;
87 int bus_max;
88 int node;
89 int link;
92 /* 4 at this time, it may become to 32 */
93 #define PCI_ROOT_NR 4
94 static int pci_root_num;
95 static struct pci_root_info pci_root_info[PCI_ROOT_NR];
97 void x86_pci_root_bus_res_quirks(struct pci_bus *b)
99 int i;
100 int j;
101 struct pci_root_info *info;
103 /* don't go for it if _CRS is used */
104 if (pci_probe & PCI_USE__CRS)
105 return;
107 /* if only one root bus, don't need to anything */
108 if (pci_root_num < 2)
109 return;
111 for (i = 0; i < pci_root_num; i++) {
112 if (pci_root_info[i].bus_min == b->number)
113 break;
116 if (i == pci_root_num)
117 return;
119 info = &pci_root_info[i];
120 for (j = 0; j < info->res_num; j++) {
121 struct resource *res;
122 struct resource *root;
124 res = &info->res[j];
125 b->resource[j] = res;
126 if (res->flags & IORESOURCE_IO)
127 root = &ioport_resource;
128 else
129 root = &iomem_resource;
130 insert_resource(root, res);
134 #define RANGE_NUM 16
136 struct res_range {
137 size_t start;
138 size_t end;
141 static void __init update_range(struct res_range *range, size_t start,
142 size_t end)
144 int i;
145 int j;
147 for (j = 0; j < RANGE_NUM; j++) {
148 if (!range[j].end)
149 continue;
151 if (start <= range[j].start && end >= range[j].end) {
152 range[j].start = 0;
153 range[j].end = 0;
154 continue;
157 if (start <= range[j].start && end < range[j].end && range[j].start < end + 1) {
158 range[j].start = end + 1;
159 continue;
163 if (start > range[j].start && end >= range[j].end && range[j].end > start - 1) {
164 range[j].end = start - 1;
165 continue;
168 if (start > range[j].start && end < range[j].end) {
169 /* find the new spare */
170 for (i = 0; i < RANGE_NUM; i++) {
171 if (range[i].end == 0)
172 break;
174 if (i < RANGE_NUM) {
175 range[i].end = range[j].end;
176 range[i].start = end + 1;
177 } else {
178 printk(KERN_ERR "run of slot in ranges\n");
180 range[j].end = start - 1;
181 continue;
186 static void __init update_res(struct pci_root_info *info, size_t start,
187 size_t end, unsigned long flags, int merge)
189 int i;
190 struct resource *res;
192 if (!merge)
193 goto addit;
195 /* try to merge it with old one */
196 for (i = 0; i < info->res_num; i++) {
197 size_t final_start, final_end;
198 size_t common_start, common_end;
200 res = &info->res[i];
201 if (res->flags != flags)
202 continue;
204 common_start = max((size_t)res->start, start);
205 common_end = min((size_t)res->end, end);
206 if (common_start > common_end + 1)
207 continue;
209 final_start = min((size_t)res->start, start);
210 final_end = max((size_t)res->end, end);
212 res->start = final_start;
213 res->end = final_end;
214 return;
217 addit:
219 /* need to add that */
220 if (info->res_num >= RES_NUM)
221 return;
223 res = &info->res[info->res_num];
224 res->name = info->name;
225 res->flags = flags;
226 res->start = start;
227 res->end = end;
228 res->child = NULL;
229 info->res_num++;
232 struct pci_hostbridge_probe {
233 u32 bus;
234 u32 slot;
235 u32 vendor;
236 u32 device;
239 static struct pci_hostbridge_probe pci_probes[] __initdata = {
240 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
241 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
242 { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
243 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
246 static u64 __initdata fam10h_mmconf_start;
247 static u64 __initdata fam10h_mmconf_end;
248 static void __init get_pci_mmcfg_amd_fam10h_range(void)
250 u32 address;
251 u64 base, msr;
252 unsigned segn_busn_bits;
254 /* assume all cpus from fam10h have mmconf */
255 if (boot_cpu_data.x86 < 0x10)
256 return;
258 address = MSR_FAM10H_MMIO_CONF_BASE;
259 rdmsrl(address, msr);
261 /* mmconfig is not enable */
262 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
263 return;
265 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
267 segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
268 FAM10H_MMIO_CONF_BUSRANGE_MASK;
270 fam10h_mmconf_start = base;
271 fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
275 * early_fill_mp_bus_to_node()
276 * called before pcibios_scan_root and pci_scan_bus
277 * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
278 * Registers found in the K8 northbridge
280 static int __init early_fill_mp_bus_info(void)
282 int i;
283 int j;
284 unsigned bus;
285 unsigned slot;
286 int found;
287 int node;
288 int link;
289 int def_node;
290 int def_link;
291 struct pci_root_info *info;
292 u32 reg;
293 struct resource *res;
294 size_t start;
295 size_t end;
296 struct res_range range[RANGE_NUM];
297 u64 val;
298 u32 address;
300 #ifdef CONFIG_NUMA
301 for (i = 0; i < BUS_NR; i++)
302 mp_bus_to_node[i] = -1;
303 #endif
305 if (!early_pci_allowed())
306 return -1;
308 found = 0;
309 for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
310 u32 id;
311 u16 device;
312 u16 vendor;
314 bus = pci_probes[i].bus;
315 slot = pci_probes[i].slot;
316 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
318 vendor = id & 0xffff;
319 device = (id>>16) & 0xffff;
320 if (pci_probes[i].vendor == vendor &&
321 pci_probes[i].device == device) {
322 found = 1;
323 break;
327 if (!found)
328 return 0;
330 pci_root_num = 0;
331 for (i = 0; i < 4; i++) {
332 int min_bus;
333 int max_bus;
334 reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
336 /* Check if that register is enabled for bus range */
337 if ((reg & 7) != 3)
338 continue;
340 min_bus = (reg >> 16) & 0xff;
341 max_bus = (reg >> 24) & 0xff;
342 node = (reg >> 4) & 0x07;
343 #ifdef CONFIG_NUMA
344 for (j = min_bus; j <= max_bus; j++)
345 mp_bus_to_node[j] = (unsigned char) node;
346 #endif
347 link = (reg >> 8) & 0x03;
349 info = &pci_root_info[pci_root_num];
350 info->bus_min = min_bus;
351 info->bus_max = max_bus;
352 info->node = node;
353 info->link = link;
354 sprintf(info->name, "PCI Bus #%02x", min_bus);
355 pci_root_num++;
358 /* get the default node and link for left over res */
359 reg = read_pci_config(bus, slot, 0, 0x60);
360 def_node = (reg >> 8) & 0x07;
361 reg = read_pci_config(bus, slot, 0, 0x64);
362 def_link = (reg >> 8) & 0x03;
364 memset(range, 0, sizeof(range));
365 range[0].end = 0xffff;
366 /* io port resource */
367 for (i = 0; i < 4; i++) {
368 reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
369 if (!(reg & 3))
370 continue;
372 start = reg & 0xfff000;
373 reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
374 node = reg & 0x07;
375 link = (reg >> 4) & 0x03;
376 end = (reg & 0xfff000) | 0xfff;
378 /* find the position */
379 for (j = 0; j < pci_root_num; j++) {
380 info = &pci_root_info[j];
381 if (info->node == node && info->link == link)
382 break;
384 if (j == pci_root_num)
385 continue; /* not found */
387 info = &pci_root_info[j];
388 printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
389 node, link, (u64)start, (u64)end);
391 /* kernel only handle 16 bit only */
392 if (end > 0xffff)
393 end = 0xffff;
394 update_res(info, start, end, IORESOURCE_IO, 1);
395 update_range(range, start, end);
397 /* add left over io port range to def node/link, [0, 0xffff] */
398 /* find the position */
399 for (j = 0; j < pci_root_num; j++) {
400 info = &pci_root_info[j];
401 if (info->node == def_node && info->link == def_link)
402 break;
404 if (j < pci_root_num) {
405 info = &pci_root_info[j];
406 for (i = 0; i < RANGE_NUM; i++) {
407 if (!range[i].end)
408 continue;
410 update_res(info, range[i].start, range[i].end,
411 IORESOURCE_IO, 1);
415 memset(range, 0, sizeof(range));
416 /* 0xfd00000000-0xffffffffff for HT */
417 range[0].end = (0xfdULL<<32) - 1;
419 /* need to take out [0, TOM) for RAM*/
420 address = MSR_K8_TOP_MEM1;
421 rdmsrl(address, val);
422 end = (val & 0xffffff800000ULL);
423 printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
424 if (end < (1ULL<<32))
425 update_range(range, 0, end - 1);
427 /* get mmconfig */
428 get_pci_mmcfg_amd_fam10h_range();
429 /* need to take out mmconf range */
430 if (fam10h_mmconf_end) {
431 printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
432 update_range(range, fam10h_mmconf_start, fam10h_mmconf_end);
435 /* mmio resource */
436 for (i = 0; i < 8; i++) {
437 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
438 if (!(reg & 3))
439 continue;
441 start = reg & 0xffffff00; /* 39:16 on 31:8*/
442 start <<= 8;
443 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
444 node = reg & 0x07;
445 link = (reg >> 4) & 0x03;
446 end = (reg & 0xffffff00);
447 end <<= 8;
448 end |= 0xffff;
450 /* find the position */
451 for (j = 0; j < pci_root_num; j++) {
452 info = &pci_root_info[j];
453 if (info->node == node && info->link == link)
454 break;
456 if (j == pci_root_num)
457 continue; /* not found */
459 info = &pci_root_info[j];
461 printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
462 node, link, (u64)start, (u64)end);
464 * some sick allocation would have range overlap with fam10h
465 * mmconf range, so need to update start and end.
467 if (fam10h_mmconf_end) {
468 int changed = 0;
469 u64 endx = 0;
470 if (start >= fam10h_mmconf_start &&
471 start <= fam10h_mmconf_end) {
472 start = fam10h_mmconf_end + 1;
473 changed = 1;
476 if (end >= fam10h_mmconf_start &&
477 end <= fam10h_mmconf_end) {
478 end = fam10h_mmconf_start - 1;
479 changed = 1;
482 if (start < fam10h_mmconf_start &&
483 end > fam10h_mmconf_end) {
484 /* we got a hole */
485 endx = fam10h_mmconf_start - 1;
486 update_res(info, start, endx, IORESOURCE_MEM, 0);
487 update_range(range, start, endx);
488 printk(KERN_CONT " ==> [%llx, %llx]", (u64)start, endx);
489 start = fam10h_mmconf_end + 1;
490 changed = 1;
492 if (changed) {
493 if (start <= end) {
494 printk(KERN_CONT " %s [%llx, %llx]", endx?"and":"==>", (u64)start, (u64)end);
495 } else {
496 printk(KERN_CONT "%s\n", endx?"":" ==> none");
497 continue;
502 update_res(info, start, end, IORESOURCE_MEM, 1);
503 update_range(range, start, end);
504 printk(KERN_CONT "\n");
507 /* need to take out [4G, TOM2) for RAM*/
508 /* SYS_CFG */
509 address = MSR_K8_SYSCFG;
510 rdmsrl(address, val);
511 /* TOP_MEM2 is enabled? */
512 if (val & (1<<21)) {
513 /* TOP_MEM2 */
514 address = MSR_K8_TOP_MEM2;
515 rdmsrl(address, val);
516 end = (val & 0xffffff800000ULL);
517 printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
518 update_range(range, 1ULL<<32, end - 1);
522 * add left over mmio range to def node/link ?
523 * that is tricky, just record range in from start_min to 4G
525 for (j = 0; j < pci_root_num; j++) {
526 info = &pci_root_info[j];
527 if (info->node == def_node && info->link == def_link)
528 break;
530 if (j < pci_root_num) {
531 info = &pci_root_info[j];
533 for (i = 0; i < RANGE_NUM; i++) {
534 if (!range[i].end)
535 continue;
537 update_res(info, range[i].start, range[i].end,
538 IORESOURCE_MEM, 1);
542 for (i = 0; i < pci_root_num; i++) {
543 int res_num;
544 int busnum;
546 info = &pci_root_info[i];
547 res_num = info->res_num;
548 busnum = info->bus_min;
549 printk(KERN_DEBUG "bus: [%02x,%02x] on node %x link %x\n",
550 info->bus_min, info->bus_max, info->node, info->link);
551 for (j = 0; j < res_num; j++) {
552 res = &info->res[j];
553 printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
554 busnum, j,
555 (res->flags & IORESOURCE_IO)?"io port":"mmio",
556 res->start, res->end);
560 return 0;
563 #else /* !CONFIG_X86_64 */
565 static int __init early_fill_mp_bus_info(void) { return 0; }
567 #endif /* !CONFIG_X86_64 */
569 /* common 32/64 bit code */
571 #define ENABLE_CF8_EXT_CFG (1ULL << 46)
573 static void enable_pci_io_ecs(void *unused)
575 u64 reg;
576 rdmsrl(MSR_AMD64_NB_CFG, reg);
577 if (!(reg & ENABLE_CF8_EXT_CFG)) {
578 reg |= ENABLE_CF8_EXT_CFG;
579 wrmsrl(MSR_AMD64_NB_CFG, reg);
583 static int __cpuinit amd_cpu_notify(struct notifier_block *self,
584 unsigned long action, void *hcpu)
586 int cpu = (long)hcpu;
587 switch (action) {
588 case CPU_ONLINE:
589 case CPU_ONLINE_FROZEN:
590 smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
591 break;
592 default:
593 break;
595 return NOTIFY_OK;
598 static struct notifier_block __cpuinitdata amd_cpu_notifier = {
599 .notifier_call = amd_cpu_notify,
602 static int __init pci_io_ecs_init(void)
604 int cpu;
606 /* assume all cpus from fam10h have IO ECS */
607 if (boot_cpu_data.x86 < 0x10)
608 return 0;
610 register_cpu_notifier(&amd_cpu_notifier);
611 for_each_online_cpu(cpu)
612 amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
613 (void *)(long)cpu);
614 pci_probe |= PCI_HAS_IO_ECS;
616 return 0;
619 static int __init amd_postcore_init(void)
621 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
622 return 0;
624 early_fill_mp_bus_info();
625 pci_io_ecs_init();
627 return 0;
630 postcore_initcall(amd_postcore_init);