ACPI: simplify acpi_pci_irq_add_prt() API
[linux-2.6/linux-acpi-2.6.git] / include / linux / sm501-regs.h
blobd53642d2d8992d33e234d4f24f7dbe366d86cab7
1 /* sm501-regs.h
3 * Copyright 2006 Simtec Electronics
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * Silicon Motion SM501 register definitions
12 /* System Configuration area */
13 /* System config base */
14 #define SM501_SYS_CONFIG (0x000000)
16 /* config 1 */
17 #define SM501_SYSTEM_CONTROL (0x000000)
19 #define SM501_SYSCTRL_PANEL_TRISTATE (1<<0)
20 #define SM501_SYSCTRL_MEM_TRISTATE (1<<1)
21 #define SM501_SYSCTRL_CRT_TRISTATE (1<<2)
23 #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4)
24 #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4)
25 #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4)
26 #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4)
27 #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4)
29 #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6)
30 #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7)
31 #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11)
32 #define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15)
34 /* miscellaneous control */
36 #define SM501_MISC_CONTROL (0x000004)
38 #define SM501_MISC_BUS_SH (0x0)
39 #define SM501_MISC_BUS_PCI (0x1)
40 #define SM501_MISC_BUS_XSCALE (0x2)
41 #define SM501_MISC_BUS_NEC (0x6)
42 #define SM501_MISC_BUS_MASK (0x7)
44 #define SM501_MISC_VR_62MB (1<<3)
45 #define SM501_MISC_CDR_RESET (1<<7)
46 #define SM501_MISC_USB_LB (1<<8)
47 #define SM501_MISC_USB_SLAVE (1<<9)
48 #define SM501_MISC_BL_1 (1<<10)
49 #define SM501_MISC_MC (1<<11)
50 #define SM501_MISC_DAC_POWER (1<<12)
51 #define SM501_MISC_IRQ_INVERT (1<<16)
52 #define SM501_MISC_SH (1<<17)
54 #define SM501_MISC_HOLD_EMPTY (0<<18)
55 #define SM501_MISC_HOLD_8 (1<<18)
56 #define SM501_MISC_HOLD_16 (2<<18)
57 #define SM501_MISC_HOLD_24 (3<<18)
58 #define SM501_MISC_HOLD_32 (4<<18)
59 #define SM501_MISC_HOLD_MASK (7<<18)
61 #define SM501_MISC_FREQ_12 (1<<24)
62 #define SM501_MISC_PNL_24BIT (1<<25)
63 #define SM501_MISC_8051_LE (1<<26)
67 #define SM501_GPIO31_0_CONTROL (0x000008)
68 #define SM501_GPIO63_32_CONTROL (0x00000C)
69 #define SM501_DRAM_CONTROL (0x000010)
71 /* command list */
72 #define SM501_ARBTRTN_CONTROL (0x000014)
74 /* command list */
75 #define SM501_COMMAND_LIST_STATUS (0x000024)
77 /* interrupt debug */
78 #define SM501_RAW_IRQ_STATUS (0x000028)
79 #define SM501_RAW_IRQ_CLEAR (0x000028)
80 #define SM501_IRQ_STATUS (0x00002C)
81 #define SM501_IRQ_MASK (0x000030)
82 #define SM501_DEBUG_CONTROL (0x000034)
84 /* power management */
85 #define SM501_POWERMODE_P2X_SRC (1<<29)
86 #define SM501_POWERMODE_V2X_SRC (1<<20)
87 #define SM501_POWERMODE_M_SRC (1<<12)
88 #define SM501_POWERMODE_M1_SRC (1<<4)
90 #define SM501_CURRENT_GATE (0x000038)
91 #define SM501_CURRENT_CLOCK (0x00003C)
92 #define SM501_POWER_MODE_0_GATE (0x000040)
93 #define SM501_POWER_MODE_0_CLOCK (0x000044)
94 #define SM501_POWER_MODE_1_GATE (0x000048)
95 #define SM501_POWER_MODE_1_CLOCK (0x00004C)
96 #define SM501_SLEEP_MODE_GATE (0x000050)
97 #define SM501_POWER_MODE_CONTROL (0x000054)
99 /* power gates for units within the 501 */
100 #define SM501_GATE_HOST (0)
101 #define SM501_GATE_MEMORY (1)
102 #define SM501_GATE_DISPLAY (2)
103 #define SM501_GATE_2D_ENGINE (3)
104 #define SM501_GATE_CSC (4)
105 #define SM501_GATE_ZVPORT (5)
106 #define SM501_GATE_GPIO (6)
107 #define SM501_GATE_UART0 (7)
108 #define SM501_GATE_UART1 (8)
109 #define SM501_GATE_SSP (10)
110 #define SM501_GATE_USB_HOST (11)
111 #define SM501_GATE_USB_GADGET (12)
112 #define SM501_GATE_UCONTROLLER (17)
113 #define SM501_GATE_AC97 (18)
115 /* panel clock */
116 #define SM501_CLOCK_P2XCLK (24)
117 /* crt clock */
118 #define SM501_CLOCK_V2XCLK (16)
119 /* main clock */
120 #define SM501_CLOCK_MCLK (8)
121 /* SDRAM controller clock */
122 #define SM501_CLOCK_M1XCLK (0)
124 /* config 2 */
125 #define SM501_PCI_MASTER_BASE (0x000058)
126 #define SM501_ENDIAN_CONTROL (0x00005C)
127 #define SM501_DEVICEID (0x000060)
128 /* 0x050100A0 */
130 #define SM501_DEVICEID_SM501 (0x05010000)
131 #define SM501_DEVICEID_IDMASK (0xffff0000)
132 #define SM501_DEVICEID_REVMASK (0x000000ff)
134 #define SM501_PLLCLOCK_COUNT (0x000064)
135 #define SM501_MISC_TIMING (0x000068)
136 #define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
138 #define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
140 /* GPIO base */
141 #define SM501_GPIO (0x010000)
142 #define SM501_GPIO_DATA_LOW (0x00)
143 #define SM501_GPIO_DATA_HIGH (0x04)
144 #define SM501_GPIO_DDR_LOW (0x08)
145 #define SM501_GPIO_DDR_HIGH (0x0C)
146 #define SM501_GPIO_IRQ_SETUP (0x10)
147 #define SM501_GPIO_IRQ_STATUS (0x14)
148 #define SM501_GPIO_IRQ_RESET (0x14)
150 /* I2C controller base */
151 #define SM501_I2C (0x010040)
152 #define SM501_I2C_BYTE_COUNT (0x00)
153 #define SM501_I2C_CONTROL (0x01)
154 #define SM501_I2C_STATUS (0x02)
155 #define SM501_I2C_RESET (0x02)
156 #define SM501_I2C_SLAVE_ADDRESS (0x03)
157 #define SM501_I2C_DATA (0x04)
159 /* SSP base */
160 #define SM501_SSP (0x020000)
162 /* Uart 0 base */
163 #define SM501_UART0 (0x030000)
165 /* Uart 1 base */
166 #define SM501_UART1 (0x030020)
168 /* USB host port base */
169 #define SM501_USB_HOST (0x040000)
171 /* USB slave/gadget base */
172 #define SM501_USB_GADGET (0x060000)
174 /* USB slave/gadget data port base */
175 #define SM501_USB_GADGET_DATA (0x070000)
177 /* Display controller/video engine base */
178 #define SM501_DC (0x080000)
180 /* common defines for the SM501 address registers */
181 #define SM501_ADDR_FLIP (1<<31)
182 #define SM501_ADDR_EXT (1<<27)
183 #define SM501_ADDR_CS1 (1<<26)
184 #define SM501_ADDR_MASK (0x3f << 26)
186 #define SM501_FIFO_MASK (0x3 << 16)
187 #define SM501_FIFO_1 (0x0 << 16)
188 #define SM501_FIFO_3 (0x1 << 16)
189 #define SM501_FIFO_7 (0x2 << 16)
190 #define SM501_FIFO_11 (0x3 << 16)
192 /* common registers for panel and the crt */
193 #define SM501_OFF_DC_H_TOT (0x000)
194 #define SM501_OFF_DC_V_TOT (0x008)
195 #define SM501_OFF_DC_H_SYNC (0x004)
196 #define SM501_OFF_DC_V_SYNC (0x00C)
198 #define SM501_DC_PANEL_CONTROL (0x000)
200 #define SM501_DC_PANEL_CONTROL_FPEN (1<<27)
201 #define SM501_DC_PANEL_CONTROL_BIAS (1<<26)
202 #define SM501_DC_PANEL_CONTROL_DATA (1<<25)
203 #define SM501_DC_PANEL_CONTROL_VDD (1<<24)
204 #define SM501_DC_PANEL_CONTROL_DP (1<<23)
206 #define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21)
207 #define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21)
208 #define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21)
210 #define SM501_DC_PANEL_CONTROL_DE (1<<20)
212 #define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18)
213 #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18)
214 #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18)
216 #define SM501_DC_PANEL_CONTROL_CP (1<<14)
217 #define SM501_DC_PANEL_CONTROL_VSP (1<<13)
218 #define SM501_DC_PANEL_CONTROL_HSP (1<<12)
219 #define SM501_DC_PANEL_CONTROL_CK (1<<9)
220 #define SM501_DC_PANEL_CONTROL_TE (1<<8)
221 #define SM501_DC_PANEL_CONTROL_VPD (1<<7)
222 #define SM501_DC_PANEL_CONTROL_VP (1<<6)
223 #define SM501_DC_PANEL_CONTROL_HPD (1<<5)
224 #define SM501_DC_PANEL_CONTROL_HP (1<<4)
225 #define SM501_DC_PANEL_CONTROL_GAMMA (1<<3)
226 #define SM501_DC_PANEL_CONTROL_EN (1<<2)
228 #define SM501_DC_PANEL_CONTROL_8BPP (0<<0)
229 #define SM501_DC_PANEL_CONTROL_16BPP (1<<0)
230 #define SM501_DC_PANEL_CONTROL_32BPP (2<<0)
233 #define SM501_DC_PANEL_PANNING_CONTROL (0x004)
234 #define SM501_DC_PANEL_COLOR_KEY (0x008)
235 #define SM501_DC_PANEL_FB_ADDR (0x00C)
236 #define SM501_DC_PANEL_FB_OFFSET (0x010)
237 #define SM501_DC_PANEL_FB_WIDTH (0x014)
238 #define SM501_DC_PANEL_FB_HEIGHT (0x018)
239 #define SM501_DC_PANEL_TL_LOC (0x01C)
240 #define SM501_DC_PANEL_BR_LOC (0x020)
241 #define SM501_DC_PANEL_H_TOT (0x024)
242 #define SM501_DC_PANEL_H_SYNC (0x028)
243 #define SM501_DC_PANEL_V_TOT (0x02C)
244 #define SM501_DC_PANEL_V_SYNC (0x030)
245 #define SM501_DC_PANEL_CUR_LINE (0x034)
247 #define SM501_DC_VIDEO_CONTROL (0x040)
248 #define SM501_DC_VIDEO_FB0_ADDR (0x044)
249 #define SM501_DC_VIDEO_FB_WIDTH (0x048)
250 #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
251 #define SM501_DC_VIDEO_TL_LOC (0x050)
252 #define SM501_DC_VIDEO_BR_LOC (0x054)
253 #define SM501_DC_VIDEO_SCALE (0x058)
254 #define SM501_DC_VIDEO_INIT_SCALE (0x05C)
255 #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
256 #define SM501_DC_VIDEO_FB1_ADDR (0x064)
257 #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
259 #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
260 #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
261 #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
262 #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
263 #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
264 #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
265 #define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
266 #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
267 #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
268 #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
270 #define SM501_DC_PANEL_HWC_BASE (0x0F0)
271 #define SM501_DC_PANEL_HWC_ADDR (0x0F0)
272 #define SM501_DC_PANEL_HWC_LOC (0x0F4)
273 #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
274 #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
276 #define SM501_HWC_EN (1<<31)
278 #define SM501_OFF_HWC_ADDR (0x00)
279 #define SM501_OFF_HWC_LOC (0x04)
280 #define SM501_OFF_HWC_COLOR_1_2 (0x08)
281 #define SM501_OFF_HWC_COLOR_3 (0x0C)
283 #define SM501_DC_ALPHA_CONTROL (0x100)
284 #define SM501_DC_ALPHA_FB_ADDR (0x104)
285 #define SM501_DC_ALPHA_FB_OFFSET (0x108)
286 #define SM501_DC_ALPHA_TL_LOC (0x10C)
287 #define SM501_DC_ALPHA_BR_LOC (0x110)
288 #define SM501_DC_ALPHA_CHROMA_KEY (0x114)
289 #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
291 #define SM501_DC_CRT_CONTROL (0x200)
293 #define SM501_DC_CRT_CONTROL_TVP (1<<15)
294 #define SM501_DC_CRT_CONTROL_CP (1<<14)
295 #define SM501_DC_CRT_CONTROL_VSP (1<<13)
296 #define SM501_DC_CRT_CONTROL_HSP (1<<12)
297 #define SM501_DC_CRT_CONTROL_VS (1<<11)
298 #define SM501_DC_CRT_CONTROL_BLANK (1<<10)
299 #define SM501_DC_CRT_CONTROL_SEL (1<<9)
300 #define SM501_DC_CRT_CONTROL_TE (1<<8)
301 #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
302 #define SM501_DC_CRT_CONTROL_GAMMA (1<<3)
303 #define SM501_DC_CRT_CONTROL_ENABLE (1<<2)
305 #define SM501_DC_CRT_CONTROL_8BPP (0<<0)
306 #define SM501_DC_CRT_CONTROL_16BPP (1<<0)
307 #define SM501_DC_CRT_CONTROL_32BPP (2<<0)
309 #define SM501_DC_CRT_FB_ADDR (0x204)
310 #define SM501_DC_CRT_FB_OFFSET (0x208)
311 #define SM501_DC_CRT_H_TOT (0x20C)
312 #define SM501_DC_CRT_H_SYNC (0x210)
313 #define SM501_DC_CRT_V_TOT (0x214)
314 #define SM501_DC_CRT_V_SYNC (0x218)
315 #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
316 #define SM501_DC_CRT_CUR_LINE (0x220)
317 #define SM501_DC_CRT_MONITOR_DETECT (0x224)
319 #define SM501_DC_CRT_HWC_BASE (0x230)
320 #define SM501_DC_CRT_HWC_ADDR (0x230)
321 #define SM501_DC_CRT_HWC_LOC (0x234)
322 #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
323 #define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
325 #define SM501_DC_PANEL_PALETTE (0x400)
327 #define SM501_DC_VIDEO_PALETTE (0x800)
329 #define SM501_DC_CRT_PALETTE (0xC00)
331 /* Zoom Video port base */
332 #define SM501_ZVPORT (0x090000)
334 /* AC97/I2S base */
335 #define SM501_AC97 (0x0A0000)
337 /* 8051 micro controller base */
338 #define SM501_UCONTROLLER (0x0B0000)
340 /* 8051 micro controller SRAM base */
341 #define SM501_UCONTROLLER_SRAM (0x0C0000)
343 /* DMA base */
344 #define SM501_DMA (0x0D0000)
346 /* 2d engine base */
347 #define SM501_2D_ENGINE (0x100000)
348 #define SM501_2D_SOURCE (0x00)
349 #define SM501_2D_DESTINATION (0x04)
350 #define SM501_2D_DIMENSION (0x08)
351 #define SM501_2D_CONTROL (0x0C)
352 #define SM501_2D_PITCH (0x10)
353 #define SM501_2D_FOREGROUND (0x14)
354 #define SM501_2D_BACKGROUND (0x18)
355 #define SM501_2D_STRETCH (0x1C)
356 #define SM501_2D_COLOR_COMPARE (0x20)
357 #define SM501_2D_COLOR_COMPARE_MASK (0x24)
358 #define SM501_2D_MASK (0x28)
359 #define SM501_2D_CLIP_TL (0x2C)
360 #define SM501_2D_CLIP_BR (0x30)
361 #define SM501_2D_MONO_PATTERN_LOW (0x34)
362 #define SM501_2D_MONO_PATTERN_HIGH (0x38)
363 #define SM501_2D_WINDOW_WIDTH (0x3C)
364 #define SM501_2D_SOURCE_BASE (0x40)
365 #define SM501_2D_DESTINATION_BASE (0x44)
366 #define SM501_2D_ALPHA (0x48)
367 #define SM501_2D_WRAP (0x4C)
368 #define SM501_2D_STATUS (0x50)
370 #define SM501_CSC_Y_SOURCE_BASE (0xC8)
371 #define SM501_CSC_CONSTANTS (0xCC)
372 #define SM501_CSC_Y_SOURCE_X (0xD0)
373 #define SM501_CSC_Y_SOURCE_Y (0xD4)
374 #define SM501_CSC_U_SOURCE_BASE (0xD8)
375 #define SM501_CSC_V_SOURCE_BASE (0xDC)
376 #define SM501_CSC_SOURCE_DIMENSION (0xE0)
377 #define SM501_CSC_SOURCE_PITCH (0xE4)
378 #define SM501_CSC_DESTINATION (0xE8)
379 #define SM501_CSC_DESTINATION_DIMENSION (0xEC)
380 #define SM501_CSC_DESTINATION_PITCH (0xF0)
381 #define SM501_CSC_SCALE_FACTOR (0xF4)
382 #define SM501_CSC_DESTINATION_BASE (0xF8)
383 #define SM501_CSC_CONTROL (0xFC)
385 /* 2d engine data port base */
386 #define SM501_2D_ENGINE_DATA (0x110000)